diff --git a/bsp/stm32/libraries/Kconfig b/bsp/stm32/libraries/Kconfig
index 1d7e8b590a..f08186c039 100644
--- a/bsp/stm32/libraries/Kconfig
+++ b/bsp/stm32/libraries/Kconfig
@@ -41,6 +41,7 @@ config SOC_SERIES_STM32L0
     bool
     select ARCH_ARM_CORTEX_M0
     select SOC_FAMILY_STM32
+    select PKG_USING_STM32L0_HAL_DRIVER
 
 config SOC_SERIES_STM32L1
     bool
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h
deleted file mode 100644
index adfcfd8fac..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h
+++ /dev/null
@@ -1,5806 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l010x4.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l010x4 devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l010x4
-  * @{
-  */
-    
-#ifndef __STM32L010x4_H
-#define __STM32L010x4_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             0U /*!< STM32L0xx  provides no MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l010x4 Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
-  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                          */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  LPUART1_IRQn                = 29,     /*!< LPUART1 Interrupt                                       */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1,                              Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x0808007FUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00000800UL) /*!< maximum SRAM size (up to 2KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP3_Pos          (10U)      
-#define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
-#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-/* Note: No specific macro feature on this device */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      ((INSTANCE) == TIM2)
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM21))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE)  ((INSTANCE) == USART2)
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (1 == 0)
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (1 == 0)
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                    ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (1==0)
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   ((INSTANCE) == LPUART1)
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE)    (1==0)
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE)    (1==0)
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define RNG_LPUART1_IRQn               LPUART1_IRQn
-#define AES_LPUART1_IRQn               LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           LPUART1_IRQn
-#define RCC_CRS_IRQn                   RCC_IRQn
-#define DMA1_Channel4_5_6_7_IRQn       DMA1_Channel4_5_IRQn
-#define ADC1_COMP_IRQn                 ADC1_IRQn
-
-/* Aliases for __IRQHandler */
-#define RNG_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     LPUART1_IRQHandler
-#define RCC_CRS_IRQHandler             RCC_IRQHandler
-#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
-#define ADC1_COMP_IRQHandler           ADC1_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L010x4_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h
deleted file mode 100644
index a50fb96847..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h
+++ /dev/null
@@ -1,5862 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l010x6.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l010x6 devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l010x6
-  * @{
-  */
-    
-#ifndef __STM32L010x6_H
-#define __STM32L010x6_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             0U /*!< STM32L0xx  provides no MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l010x6 Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                          */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  LPUART1_IRQn                = 29,     /*!< LPUART1 Interrupt                                       */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1,                              Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x080800FFUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos          (10U)      
-#define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
-#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      ((INSTANCE) == TIM2)
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM21))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE)  ((INSTANCE) == USART2)
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (1 == 0)
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (1 == 0)
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                    ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (1==0)
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   ((INSTANCE) == LPUART1)
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE)    (1==0)
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE)    (1==0)
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define RNG_LPUART1_IRQn               LPUART1_IRQn
-#define AES_LPUART1_IRQn               LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           LPUART1_IRQn
-#define RCC_CRS_IRQn                   RCC_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_COMP_IRQn                 ADC1_IRQn
-
-/* Aliases for __IRQHandler */
-#define RNG_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     LPUART1_IRQHandler
-#define RCC_CRS_IRQHandler             RCC_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_COMP_IRQHandler           ADC1_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L010x6_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h
deleted file mode 100644
index fa836aa5ff..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h
+++ /dev/null
@@ -1,5858 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l010x8.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l010x8 devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l010x8
-  * @{
-  */
-    
-#ifndef __STM32L010x8_H
-#define __STM32L010x8_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             0U /*!< STM32L0xx  provides no MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l010x8 Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                          */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  LPUART1_IRQn                = 29,     /*!< LPUART1 Interrupt                                       */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1,                              Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x080800FFUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      ((INSTANCE) == TIM2)
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM21))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE)  ((INSTANCE) == USART2)
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                    ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    ((INSTANCE) == USART2)
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE)    (1==0)
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define RNG_LPUART1_IRQn               LPUART1_IRQn
-#define AES_LPUART1_IRQn               LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           LPUART1_IRQn
-#define RCC_CRS_IRQn                   RCC_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_COMP_IRQn                 ADC1_IRQn
-
-/* Aliases for __IRQHandler */
-#define RNG_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     LPUART1_IRQHandler
-#define RCC_CRS_IRQHandler             RCC_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_COMP_IRQHandler           ADC1_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L010x8_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h
deleted file mode 100644
index 1acd24ebaa..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h
+++ /dev/null
@@ -1,5934 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l010xb.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l010xb devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l010xb
-  * @{
-  */
-    
-#ifndef __STM32L010xB_H
-#define __STM32L010xB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             0U /*!< STM32L0xx  provides no MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l010xb Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                          */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  LPUART1_IRQn                = 29,     /*!< LPUART1 Interrupt                                       */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1,                              Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x080801FFUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (IOPPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPERST_Pos          (4U) 
-#define RCC_IOPRSTR_IOPERST_Msk          (0x1UL << RCC_IOPRSTR_IOPERST_Pos)     /*!< 0x00000010 */
-#define RCC_IOPRSTR_IOPERST              RCC_IOPRSTR_IOPERST_Msk               /*!< GPIO port E reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOERST                RCC_IOPRSTR_IOPERST        /*!< GPIO port E reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPEEN_Pos            (4U) 
-#define RCC_IOPENR_IOPEEN_Msk            (0x1UL << RCC_IOPENR_IOPEEN_Pos)       /*!< 0x00000010 */
-#define RCC_IOPENR_IOPEEN                RCC_IOPENR_IOPEEN_Msk                 /*!< GPIO port E clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOEEN                  RCC_IOPENR_IOPEEN        /*!< GPIO port E clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPESMEN_Pos        (4U) 
-#define RCC_IOPSMENR_IOPESMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos)   /*!< 0x00000010 */
-#define RCC_IOPSMENR_IOPESMEN            RCC_IOPSMENR_IOPESMEN_Msk             /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOESMEN              RCC_IOPSMENR_IOPESMEN        /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      ((INSTANCE) == TIM2)
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM21)  || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE)  ((INSTANCE) == USART2)
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                    ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    ((INSTANCE) == USART2)
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define RNG_LPUART1_IRQn               LPUART1_IRQn
-#define AES_LPUART1_IRQn               LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           LPUART1_IRQn
-#define RCC_CRS_IRQn                   RCC_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_COMP_IRQn                 ADC1_IRQn
-
-/* Aliases for __IRQHandler */
-#define RNG_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     LPUART1_IRQHandler
-#define RCC_CRS_IRQHandler             RCC_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_COMP_IRQHandler           ADC1_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L010xB_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h
deleted file mode 100644
index 80ae3f0fb0..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h
+++ /dev/null
@@ -1,5948 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l011xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l011xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l011xx
-  * @{
-  */
-    
-#ifndef __STM32L011xx_H
-#define __STM32L011xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             0U /*!< STM32L0xx  provides no MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l011xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  LPUART1_IRQn                = 29,     /*!< LPUART1 Interrupt                                       */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1,                              Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x080801FFUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00000800UL) /*!< maximum SRAM size (up to 2KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-#define PWR_CR_LPDS_Pos            (16U)      
-#define PWR_CR_LPDS_Msk            (0x1UL << PWR_CR_LPDS_Pos)                   /*!< 0x00010000 */
-#define PWR_CR_LPDS                PWR_CR_LPDS_Msk                             /*!< regulator in low power deepsleep mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP3_Pos          (10U)      
-#define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
-#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-/* Note: No specific macro feature on this device */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI_SUPPORT	     /*!<Support remap HSI on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define USART_TCBGT_SUPPORT                       /*!< Transmission completed before guard time interrupt support */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-#define USART_CR3_TCBGTIE_Pos         (24U)   
-#define USART_CR3_TCBGTIE_Msk         (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
-#define USART_CR3_TCBGTIE             USART_CR3_TCBGTIE_Msk                    /*!< Transmission Complete Before Guard Time Interrupt Enable */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-#define USART_ISR_TCBGT_Pos           (25U)   
-#define USART_ISR_TCBGT_Msk           (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
-#define USART_ISR_TCBGT               USART_ISR_TCBGT_Msk                      /*!< Transmission Complete Before Guard Time Completion Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_TCBGTCF_Pos         (7U)    
-#define USART_ICR_TCBGTCF_Msk         (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
-#define USART_ICR_TCBGTCF             USART_ICR_TCBGTCF_Msk                    /*!< Transmission Complete Before Guard Time Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      ((INSTANCE) == TIM2)
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM21))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE)  ((INSTANCE) == USART2)
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (1 == 0)
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (1 == 0)
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                    ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (1==0)
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   ((INSTANCE) == LPUART1)
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define RNG_LPUART1_IRQn               LPUART1_IRQn
-#define AES_LPUART1_IRQn               LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           LPUART1_IRQn
-#define RCC_CRS_IRQn                   RCC_IRQn
-#define DMA1_Channel4_5_6_7_IRQn       DMA1_Channel4_5_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define RNG_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     LPUART1_IRQHandler
-#define RCC_CRS_IRQHandler             RCC_IRQHandler
-#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L011xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h
deleted file mode 100644
index 583b8ff3aa..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h
+++ /dev/null
@@ -1,6088 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l021xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l021xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l021xx
-  * @{
-  */
-    
-#ifndef __STM32L021xx_H
-#define __STM32L021xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             0U /*!< STM32L0xx  provides no MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l021xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  AES_LPUART1_IRQn            = 29,     /*!< AES and LPUART1 Interrupts                              */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;      /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;      /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;    /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;   /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;   /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;   /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;   /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;   /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;    /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;    /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;    /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;    /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1,                              Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x080801FFUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00000800UL) /*!< maximum SRAM size (up to 2KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define AES_BASE              (AHBPERIPH_BASE + 0x00006000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define AES                 ((AES_TypeDef *) AES_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos            (0U)         
-#define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                       /*!< 0x00000001 */
-#define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos      (1U)         
-#define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000006 */
-#define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
-#define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos          (3U)         
-#define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                     /*!< 0x00000018 */
-#define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                     /*!< 0x00000008 */
-#define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                     /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos         (5U)         
-#define AES_CR_CHMOD_Msk         (0x3UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000060 */
-#define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0           (0x1UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000020 */
-#define AES_CR_CHMOD_1           (0x2UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000040 */
-
-#define AES_CR_CCFC_Pos          (7U)         
-#define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                     /*!< 0x00000080 */
-#define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos          (8U)         
-#define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                     /*!< 0x00000100 */
-#define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
-#define AES_CR_CCIE_Pos          (9U)         
-#define AES_CR_CCIE_Msk          (0x1UL << AES_CR_CCIE_Pos)                     /*!< 0x00000200 */
-#define AES_CR_CCIE              AES_CR_CCIE_Msk                               /*!< Computation Complete Interrupt Enable */
-#define AES_CR_ERRIE_Pos         (10U)        
-#define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                    /*!< 0x00000400 */
-#define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos       (11U)        
-#define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                  /*!< 0x00000800 */
-#define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< DMA ENable managing the data input phase */
-#define AES_CR_DMAOUTEN_Pos      (12U)        
-#define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                 /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos           (0U)         
-#define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                      /*!< 0x00000001 */
-#define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos         (1U)         
-#define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                    /*!< 0x00000002 */
-#define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos         (2U)         
-#define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                    /*!< 0x00000004 */
-#define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos             (0U)         
-#define AES_DINR_Msk             (0xFFFFUL << AES_DINR_Pos)                     /*!< 0x0000FFFF */
-#define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos            (0U)         
-#define AES_DOUTR_Msk            (0xFFFFUL << AES_DOUTR_Pos)                    /*!< 0x0000FFFF */
-#define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos            (0U)         
-#define AES_KEYR0_Msk            (0xFFFFUL << AES_KEYR0_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos            (0U)         
-#define AES_KEYR1_Msk            (0xFFFFUL << AES_KEYR1_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos            (0U)         
-#define AES_KEYR2_Msk            (0xFFFFUL << AES_KEYR2_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos            (0U)         
-#define AES_KEYR3_Msk            (0xFFFFUL << AES_KEYR3_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define AES_IVR0_Pos             (0U)         
-#define AES_IVR0_Msk             (0xFFFFUL << AES_IVR0_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define AES_IVR1_Pos             (0U)         
-#define AES_IVR1_Msk             (0xFFFFUL << AES_IVR1_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define AES_IVR2_Pos             (0U)         
-#define AES_IVR2_Msk             (0xFFFFUL << AES_IVR2_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define AES_IVR3_Pos             (0U)         
-#define AES_IVR3_Msk             (0xFFFFUL << AES_IVR3_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-#define PWR_CR_LPDS_Pos            (16U)      
-#define PWR_CR_LPDS_Msk            (0x1UL << PWR_CR_LPDS_Pos)                   /*!< 0x00010000 */
-#define PWR_CR_LPDS                PWR_CR_LPDS_Msk                             /*!< regulator in low power deepsleep mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP3_Pos          (10U)      
-#define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
-#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-/* Note: No specific macro feature on this device */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_CRYPRST_Pos          (24U)
-#define RCC_AHBRSTR_CRYPRST_Msk          (0x1UL << RCC_AHBRSTR_CRYPRST_Pos)     /*!< 0x01000000 */
-#define RCC_AHBRSTR_CRYPRST              RCC_AHBRSTR_CRYPRST_Msk               /*!< Crypto reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_CRYPEN_Pos            (24U)
-#define RCC_AHBENR_CRYPEN_Msk            (0x1UL << RCC_AHBENR_CRYPEN_Pos)       /*!< 0x01000000 */
-#define RCC_AHBENR_CRYPEN                RCC_AHBENR_CRYPEN_Msk                 /*!< Crypto clock enable*/
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRYPSMEN_Pos        (24U)
-#define RCC_AHBSMENR_CRYPSMEN_Msk        (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos)   /*!< 0x01000000 */
-#define RCC_AHBSMENR_CRYPSMEN            RCC_AHBSMENR_CRYPSMEN_Msk             /*!< Crypto clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI_SUPPORT	     /*!<Support remap HSI on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define USART_TCBGT_SUPPORT                       /*!< Transmission completed before guard time interrupt support */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-#define USART_CR3_TCBGTIE_Pos         (24U)   
-#define USART_CR3_TCBGTIE_Msk         (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
-#define USART_CR3_TCBGTIE             USART_CR3_TCBGTIE_Msk                    /*!< Transmission Complete Before Guard Time Interrupt Enable */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-#define USART_ISR_TCBGT_Pos           (25U)   
-#define USART_ISR_TCBGT_Msk           (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
-#define USART_ISR_TCBGT               USART_ISR_TCBGT_Msk                      /*!< Transmission Complete Before Guard Time Completion Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_TCBGTCF_Pos         (7U)    
-#define USART_ICR_TCBGTCF_Msk         (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
-#define USART_ICR_TCBGTCF             USART_ICR_TCBGTCF_Msk                    /*!< Transmission Complete Before Guard Time Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* AES Instances ********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      ((INSTANCE) == TIM2)
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM21))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE)  ((INSTANCE) == USART2)
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (1 == 0)
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (1 == 0)
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                    ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (1==0)
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   ((INSTANCE) == LPUART1)
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define RNG_LPUART1_IRQn               AES_LPUART1_IRQn
-#define LPUART1_IRQn                   AES_LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           AES_LPUART1_IRQn
-#define RCC_CRS_IRQn                   RCC_IRQn
-#define DMA1_Channel4_5_6_7_IRQn       DMA1_Channel4_5_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             AES_LPUART1_IRQHandler
-#define RNG_LPUART1_IRQHandler         AES_LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     AES_LPUART1_IRQHandler
-#define RCC_CRS_IRQHandler             RCC_IRQHandler
-#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L021xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h
deleted file mode 100644
index f082418783..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h
+++ /dev/null
@@ -1,6094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l031xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l031xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l031xx
-  * @{
-  */
-    
-#ifndef __STM32L031xx_H
-#define __STM32L031xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             0U /*!< STM32L0xx  provides no MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l031xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  LPUART1_IRQn                = 29,     /*!< LPUART1 Interrupt                                       */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1,                              Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x080803FFUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos          (10U)      
-#define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
-#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-#define RCC_MCO3_SUPPORT            /*!<Support MCO3 */
-#define RCC_MCO3_AF2_SUPPORT        /*!<Support MCO3 on Alternate Function AF0 */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI_SUPPORT	     /*!<Support remap HSI on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      ((INSTANCE) == TIM2)
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM21)  || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE)  ((INSTANCE) == USART2)
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                    ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    ((INSTANCE) == USART2)
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define RNG_LPUART1_IRQn               LPUART1_IRQn
-#define AES_LPUART1_IRQn               LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           LPUART1_IRQn
-#define RCC_CRS_IRQn                   RCC_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define RNG_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     LPUART1_IRQHandler
-#define RCC_CRS_IRQHandler             RCC_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L031xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h
deleted file mode 100644
index 6028b519a1..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h
+++ /dev/null
@@ -1,6234 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l041xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l041xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l041xx
-  * @{
-  */
-    
-#ifndef __STM32L041xx_H
-#define __STM32L041xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             0U /*!< STM32L0xx  provides no MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l041xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  AES_LPUART1_IRQn            = 29,     /*!< AES and LPUART1 Interrupts                              */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;      /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;      /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;    /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;   /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;   /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;   /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;   /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;   /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;    /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;    /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;    /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;    /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1,                              Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x080803FFUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define AES_BASE              (AHBPERIPH_BASE + 0x00006000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define AES                 ((AES_TypeDef *) AES_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos            (0U)         
-#define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                       /*!< 0x00000001 */
-#define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos      (1U)         
-#define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000006 */
-#define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
-#define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos          (3U)         
-#define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                     /*!< 0x00000018 */
-#define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                     /*!< 0x00000008 */
-#define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                     /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos         (5U)         
-#define AES_CR_CHMOD_Msk         (0x3UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000060 */
-#define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0           (0x1UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000020 */
-#define AES_CR_CHMOD_1           (0x2UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000040 */
-
-#define AES_CR_CCFC_Pos          (7U)         
-#define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                     /*!< 0x00000080 */
-#define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos          (8U)         
-#define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                     /*!< 0x00000100 */
-#define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
-#define AES_CR_CCIE_Pos          (9U)         
-#define AES_CR_CCIE_Msk          (0x1UL << AES_CR_CCIE_Pos)                     /*!< 0x00000200 */
-#define AES_CR_CCIE              AES_CR_CCIE_Msk                               /*!< Computation Complete Interrupt Enable */
-#define AES_CR_ERRIE_Pos         (10U)        
-#define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                    /*!< 0x00000400 */
-#define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos       (11U)        
-#define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                  /*!< 0x00000800 */
-#define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< DMA ENable managing the data input phase */
-#define AES_CR_DMAOUTEN_Pos      (12U)        
-#define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                 /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos           (0U)         
-#define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                      /*!< 0x00000001 */
-#define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos         (1U)         
-#define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                    /*!< 0x00000002 */
-#define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos         (2U)         
-#define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                    /*!< 0x00000004 */
-#define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos             (0U)         
-#define AES_DINR_Msk             (0xFFFFUL << AES_DINR_Pos)                     /*!< 0x0000FFFF */
-#define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos            (0U)         
-#define AES_DOUTR_Msk            (0xFFFFUL << AES_DOUTR_Pos)                    /*!< 0x0000FFFF */
-#define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos            (0U)         
-#define AES_KEYR0_Msk            (0xFFFFUL << AES_KEYR0_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos            (0U)         
-#define AES_KEYR1_Msk            (0xFFFFUL << AES_KEYR1_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos            (0U)         
-#define AES_KEYR2_Msk            (0xFFFFUL << AES_KEYR2_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos            (0U)         
-#define AES_KEYR3_Msk            (0xFFFFUL << AES_KEYR3_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define AES_IVR0_Pos             (0U)         
-#define AES_IVR0_Msk             (0xFFFFUL << AES_IVR0_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define AES_IVR1_Pos             (0U)         
-#define AES_IVR1_Msk             (0xFFFFUL << AES_IVR1_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define AES_IVR2_Pos             (0U)         
-#define AES_IVR2_Msk             (0xFFFFUL << AES_IVR2_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define AES_IVR3_Pos             (0U)         
-#define AES_IVR3_Msk             (0xFFFFUL << AES_IVR3_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos          (10U)      
-#define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
-#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-#define RCC_MCO3_SUPPORT            /*!<Support MCO3 */
-#define RCC_MCO3_AF2_SUPPORT        /*!<Support MCO3 on Alternate Function AF0 */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_CRYPRST_Pos          (24U)
-#define RCC_AHBRSTR_CRYPRST_Msk          (0x1UL << RCC_AHBRSTR_CRYPRST_Pos)     /*!< 0x01000000 */
-#define RCC_AHBRSTR_CRYPRST              RCC_AHBRSTR_CRYPRST_Msk               /*!< Crypto reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_CRYPEN_Pos            (24U)
-#define RCC_AHBENR_CRYPEN_Msk            (0x1UL << RCC_AHBENR_CRYPEN_Pos)       /*!< 0x01000000 */
-#define RCC_AHBENR_CRYPEN                RCC_AHBENR_CRYPEN_Msk                 /*!< Crypto clock enable*/
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRYPSMEN_Pos        (24U)
-#define RCC_AHBSMENR_CRYPSMEN_Msk        (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos)   /*!< 0x01000000 */
-#define RCC_AHBSMENR_CRYPSMEN            RCC_AHBSMENR_CRYPSMEN_Msk             /*!< Crypto clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI_SUPPORT	     /*!<Support remap HSI on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* AES Instances ********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      ((INSTANCE) == TIM2)
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM21)  || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE)  ((INSTANCE) == USART2)
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                    ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    ((INSTANCE) == USART2)
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define RNG_LPUART1_IRQn               AES_LPUART1_IRQn
-#define LPUART1_IRQn                   AES_LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           AES_LPUART1_IRQn
-#define RCC_CRS_IRQn                   RCC_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             AES_LPUART1_IRQHandler
-#define RNG_LPUART1_IRQHandler         AES_LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     AES_LPUART1_IRQHandler
-#define RCC_CRS_IRQHandler             RCC_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L041xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h
deleted file mode 100644
index 852d26c263..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h
+++ /dev/null
@@ -1,6269 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l051xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l051xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l051xx
-  * @{
-  */
-    
-#ifndef __STM32L051xx_H
-#define __STM32L051xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1U /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l051xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM6_IRQn                   = 17,     /*!< TIM6  Interrupt                                         */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  LPUART1_IRQn                = 29,     /*!< LPUART1 Interrupt                                       */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x080807FFUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)             
-#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)             
-#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)             
-#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)             
-#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)             
-#define FW_VDSSA_ADD_Msk     (0x3FFUL << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)             
-#define FW_VDSL_LENG_Msk     (0x3FFUL << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)             
-#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)             
-#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)             
-#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-#define RCC_MCO3_SUPPORT            /*!<Support MCO3 */
-#define RCC_MCO3_AF0_SUPPORT        /*!<Support MCO3 on Alternate Function AF2 */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1UL << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)
-#define RCC_APB2ENR_USART1EN_Msk         (0x1UL << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U) 
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1UL << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1UL << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1UL << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U) 
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U) 
-#define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)      
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)      
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)      
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)      
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)      
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)      
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)     
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)     
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)      
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)      
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)      
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM6))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define RNG_LPUART1_IRQn               LPUART1_IRQn
-#define AES_LPUART1_IRQn               LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           LPUART1_IRQn
-#define TIM6_DAC_IRQn                  TIM6_IRQn
-#define RCC_CRS_IRQn                   RCC_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define RNG_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     LPUART1_IRQHandler
-#define TIM6_DAC_IRQHandler            TIM6_IRQHandler
-#define RCC_CRS_IRQHandler             RCC_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L051xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h
deleted file mode 100644
index cc5c806865..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h
+++ /dev/null
@@ -1,7351 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l052xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l052xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l052xx
-  * @{
-  */
-    
-#ifndef __STM32L052xx_H
-#define __STM32L052xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1U /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l052xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  RNG_LPUART1_IRQn            = 29,     /*!< RNG and LPUART1 Interrupts                              */
-  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Clock Recovery System 
-  */
-
-typedef struct 
-{
-__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
-__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
-__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
-__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
-} CRS_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  uint32_t      RESERVED0[6];  /*!<                                                                     0x14-0x28 */
-  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  uint32_t      RESERVED1;     /*!<                                                                          0x30 */
-  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Random numbers generator
-  */
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
-  __IO uint16_t RESERVEDD;       /*!< Reserved */       
-  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
-  __IO uint16_t RESERVEDE;       /*!< Reserved */       
-} USB_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x080807FFUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
-#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000UL)
-#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define CRS                 ((CRS_TypeDef *) CRS_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define USB                 ((USB_TypeDef *) USB_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRS Clock Recovery System                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRS_CR register  *********************/
-#define CRS_CR_SYNCOKIE_Pos       (0U)        
-#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
-#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
-#define CRS_CR_SYNCWARNIE_Pos     (1U)        
-#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
-#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
-#define CRS_CR_ERRIE_Pos          (2U)        
-#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
-#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
-#define CRS_CR_ESYNCIE_Pos        (3U)        
-#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
-#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN_Pos            (5U)        
-#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
-#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
-#define CRS_CR_AUTOTRIMEN_Pos     (6U)        
-#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
-#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
-#define CRS_CR_SWSYNC_Pos         (7U)        
-#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
-#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
-#define CRS_CR_TRIM_Pos           (8U)        
-#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
-#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
-
-/*******************  Bit definition for CRS_CFGR register  *********************/
-#define CRS_CFGR_RELOAD_Pos       (0U)        
-#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
-#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
-#define CRS_CFGR_FELIM_Pos        (16U)       
-#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
-#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
-
-#define CRS_CFGR_SYNCDIV_Pos      (24U)       
-#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
-#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
-#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
-#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
-#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
-
-#define CRS_CFGR_SYNCSRC_Pos      (28U)       
-#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
-#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
-#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
-#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
-
-#define CRS_CFGR_SYNCPOL_Pos      (31U)       
-#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
-#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
-  
-/*******************  Bit definition for CRS_ISR register  *********************/
-#define CRS_ISR_SYNCOKF_Pos       (0U)        
-#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
-#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
-#define CRS_ISR_SYNCWARNF_Pos     (1U)        
-#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
-#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
-#define CRS_ISR_ERRF_Pos          (2U)        
-#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
-#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
-#define CRS_ISR_ESYNCF_Pos        (3U)        
-#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
-#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
-#define CRS_ISR_SYNCERR_Pos       (8U)        
-#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
-#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
-#define CRS_ISR_SYNCMISS_Pos      (9U)        
-#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
-#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
-#define CRS_ISR_TRIMOVF_Pos       (10U)       
-#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
-#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR_Pos         (15U)       
-#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
-#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
-#define CRS_ISR_FECAP_Pos         (16U)       
-#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
-#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
-
-/*******************  Bit definition for CRS_ICR register  *********************/
-#define CRS_ICR_SYNCOKC_Pos       (0U)        
-#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
-#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
-#define CRS_ICR_SYNCWARNC_Pos     (1U)        
-#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
-#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
-#define CRS_ICR_ERRC_Pos          (2U)        
-#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
-#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag             */
-#define CRS_ICR_ESYNCC_Pos        (3U)        
-#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
-#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)      
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos            (1U)      
-#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos             (2U)      
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (3U)      
-#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)      
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)      
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)     
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)     
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)      
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)      
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)      
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)      
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)      
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)     
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)             
-#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)             
-#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)             
-#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)             
-#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)             
-#define FW_VDSSA_ADD_Msk     (0x3FFUL << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)             
-#define FW_VDSL_LENG_Msk     (0x3FFUL << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)             
-#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)             
-#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)             
-#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CRRCR register  *****************/
-#define RCC_CRRCR_HSI48ON_Pos            (0U) 
-#define RCC_CRRCR_HSI48ON_Msk            (0x1UL << RCC_CRRCR_HSI48ON_Pos)       /*!< 0x00000001 */
-#define RCC_CRRCR_HSI48ON                RCC_CRRCR_HSI48ON_Msk                 /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY_Pos           (1U) 
-#define RCC_CRRCR_HSI48RDY_Msk           (0x1UL << RCC_CRRCR_HSI48RDY_Pos)      /*!< 0x00000002 */
-#define RCC_CRRCR_HSI48RDY               RCC_CRRCR_HSI48RDY_Msk                /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48CAL_Pos           (8U) 
-#define RCC_CRRCR_HSI48CAL_Msk           (0xFFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF00 */
-#define RCC_CRRCR_HSI48CAL               RCC_CRRCR_HSI48CAL_Msk                /*!< HSI 48MHz clock Calibration */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-#define RCC_CFGR_MCOSEL_HSI48_Pos            (27U)                             
-#define RCC_CFGR_MCOSEL_HSI48_Msk            (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
-#define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCOSEL_HSI48_Msk         /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE_Pos          (6U) 
-#define RCC_CIER_HSI48RDYIE_Msk          (0x1UL << RCC_CIER_HSI48RDYIE_Pos)     /*!< 0x00000040 */
-#define RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE_Msk               /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF_Pos           (6U) 
-#define RCC_CIFR_HSI48RDYF_Msk           (0x1UL << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000040 */
-#define RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF_Msk                /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC_Pos           (6U) 
-#define RCC_CICR_HSI48RDYC_Msk           (0x1UL << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000040 */
-#define RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC_Msk                /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST_Pos           (16U)
-#define RCC_AHBRSTR_TSCRST_Msk           (0x1UL << RCC_AHBRSTR_TSCRST_Pos)      /*!< 0x00010000 */
-#define RCC_AHBRSTR_TSCRST               RCC_AHBRSTR_TSCRST_Msk                /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST_Pos           (20U)
-#define RCC_AHBRSTR_RNGRST_Msk           (0x1UL << RCC_AHBRSTR_RNGRST_Pos)      /*!< 0x00100000 */
-#define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk                /*!< RNG reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1UL << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos          (23U)
-#define RCC_APB1RSTR_USBRST_Msk          (0x1UL << RCC_APB1RSTR_USBRST_Pos)     /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST              RCC_APB1RSTR_USBRST_Msk               /*!< USB reset */
-#define RCC_APB1RSTR_CRSRST_Pos          (27U)
-#define RCC_APB1RSTR_CRSRST_Msk          (0x1UL << RCC_APB1RSTR_CRSRST_Pos)     /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST              RCC_APB1RSTR_CRSRST_Msk               /*!< CRS reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_DACRST_Pos          (29U)
-#define RCC_APB1RSTR_DACRST_Msk          (0x1UL << RCC_APB1RSTR_DACRST_Pos)     /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST              RCC_APB1RSTR_DACRST_Msk               /*!< DAC reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN_Pos             (16U)
-#define RCC_AHBENR_TSCEN_Msk             (0x1UL << RCC_AHBENR_TSCEN_Pos)        /*!< 0x00010000 */
-#define RCC_AHBENR_TSCEN                 RCC_AHBENR_TSCEN_Msk                  /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN_Pos             (20U)
-#define RCC_AHBENR_RNGEN_Msk             (0x1UL << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00100000 */
-#define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk                  /*!< RNG clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)
-#define RCC_APB2ENR_USART1EN_Msk         (0x1UL << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U) 
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1UL << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1UL << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1UL << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos            (23U)
-#define RCC_APB1ENR_USBEN_Msk            (0x1UL << RCC_APB1ENR_USBEN_Pos)       /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                RCC_APB1ENR_USBEN_Msk                 /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN_Pos            (27U)
-#define RCC_APB1ENR_CRSEN_Msk            (0x1UL << RCC_APB1ENR_CRSEN_Pos)       /*!< 0x08000000 */
-#define RCC_APB1ENR_CRSEN                RCC_APB1ENR_CRSEN_Msk                 /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN_Pos            (29U)
-#define RCC_APB1ENR_DACEN_Msk            (0x1UL << RCC_APB1ENR_DACEN_Pos)       /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                RCC_APB1ENR_DACEN_Msk                 /*!< DAC clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN_Pos         (16U)
-#define RCC_AHBSMENR_TSCSMEN_Msk         (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos)    /*!< 0x00010000 */
-#define RCC_AHBSMENR_TSCSMEN             RCC_AHBSMENR_TSCSMEN_Msk              /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN_Pos         (20U)
-#define RCC_AHBSMENR_RNGSMEN_Msk         (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00100000 */
-#define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk              /*!< RNG clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U) 
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN_Pos        (23U)
-#define RCC_APB1SMENR_USBSMEN_Msk        (0x1UL << RCC_APB1SMENR_USBSMEN_Pos)   /*!< 0x00800000 */
-#define RCC_APB1SMENR_USBSMEN            RCC_APB1SMENR_USBSMEN_Msk             /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN_Pos        (27U)
-#define RCC_APB1SMENR_CRSSMEN_Msk        (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos)   /*!< 0x08000000 */
-#define RCC_APB1SMENR_CRSSMEN            RCC_APB1SMENR_CRSSMEN_Msk             /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN_Pos        (29U)
-#define RCC_APB1SMENR_DACSMEN_Msk        (0x1UL << RCC_APB1SMENR_DACSMEN_Pos)   /*!< 0x20000000 */
-#define RCC_APB1SMENR_DACSMEN            RCC_APB1SMENR_DACSMEN_Msk             /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U) 
-#define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*!< HSI48 Clock source selection */ 
-#define RCC_CCIPR_HSI48SEL_Pos           (26U)
-#define RCC_CCIPR_HSI48SEL_Msk           (0x1UL << RCC_CCIPR_HSI48SEL_Pos)      /*!< 0x04000000 */
-#define RCC_CCIPR_HSI48SEL               RCC_CCIPR_HSI48SEL_Msk                /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Legacy defines */
-#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos    (2U)              
-#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
-#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
-#define RNG_CR_IE_Pos       (3U)              
-#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
-#define RNG_CR_IE           RNG_CR_IE_Msk                                      
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)              
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
-#define RNG_SR_CECS_Pos     (1U)              
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
-#define RNG_SR_SECS_Pos     (2U)              
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
-#define RNG_SR_CEIS_Pos     (5U)              
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
-#define RNG_SR_SEIS_Pos     (6U)              
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)      
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)      
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)      
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)      
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)      
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)      
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)     
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)     
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)      
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)      
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)      
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48_Pos             (13U)                         
-#define SYSCFG_CFGR3_ENREF_HSI48_Msk             (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR3_ENREF_HSI48                 SYSCFG_CFGR3_ENREF_HSI48_Msk  /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
-#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_REF_HSI48_RDYF           SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE_Pos          (0U)         
-#define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
-#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
-#define TSC_CR_START_Pos         (1U)         
-#define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
-#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
-#define TSC_CR_AM_Pos            (2U)         
-#define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
-#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL_Pos       (3U)         
-#define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
-#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF_Pos         (4U)         
-#define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
-#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
-
-#define TSC_CR_MCV_Pos           (5U)         
-#define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
-#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
-#define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
-#define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
-
-#define TSC_CR_PGPSC_Pos         (12U)        
-#define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
-#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
-#define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
-#define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
-
-#define TSC_CR_SSPSC_Pos         (15U)        
-#define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
-#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE_Pos           (16U)        
-#define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
-#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD_Pos           (17U)        
-#define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
-#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
-#define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
-#define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
-#define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
-#define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
-#define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
-#define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
-
-#define TSC_CR_CTPL_Pos          (24U)        
-#define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
-#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
-#define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
-#define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
-#define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
-
-#define TSC_CR_CTPH_Pos          (28U)        
-#define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
-#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
-#define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
-#define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
-#define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE_Pos        (0U)         
-#define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
-#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE_Pos        (1U)         
-#define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
-#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC_Pos        (0U)         
-#define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
-#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC_Pos        (1U)         
-#define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
-#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF_Pos         (0U)         
-#define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
-#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
-#define TSC_ISR_MCEF_Pos         (1U)         
-#define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
-#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1_Pos     (0U)         
-#define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2_Pos     (1U)         
-#define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3_Pos     (2U)         
-#define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4_Pos     (3U)         
-#define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1_Pos     (4U)         
-#define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2_Pos     (5U)         
-#define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3_Pos     (6U)         
-#define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4_Pos     (7U)         
-#define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1_Pos     (8U)         
-#define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2_Pos     (9U)         
-#define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3_Pos     (10U)        
-#define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4_Pos     (11U)        
-#define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1_Pos     (12U)        
-#define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2_Pos     (13U)        
-#define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3_Pos     (14U)        
-#define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4_Pos     (15U)        
-#define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1_Pos     (16U)        
-#define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2_Pos     (17U)        
-#define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3_Pos     (18U)        
-#define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4_Pos     (19U)        
-#define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1_Pos     (20U)        
-#define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2_Pos     (21U)        
-#define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3_Pos     (22U)        
-#define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4_Pos     (23U)        
-#define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1_Pos     (24U)        
-#define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2_Pos     (25U)        
-#define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3_Pos     (26U)        
-#define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4_Pos     (27U)        
-#define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1_Pos     (28U)        
-#define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2_Pos     (29U)        
-#define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3_Pos     (30U)        
-#define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4_Pos     (31U)        
-#define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1_Pos    (0U)         
-#define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
-#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2_Pos    (1U)         
-#define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
-#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3_Pos    (2U)         
-#define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
-#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4_Pos    (3U)         
-#define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
-#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1_Pos    (4U)         
-#define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
-#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2_Pos    (5U)         
-#define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
-#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3_Pos    (6U)         
-#define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
-#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4_Pos    (7U)         
-#define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
-#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1_Pos    (8U)         
-#define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
-#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2_Pos    (9U)         
-#define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
-#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3_Pos    (10U)        
-#define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
-#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4_Pos    (11U)        
-#define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
-#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1_Pos    (12U)        
-#define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
-#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2_Pos    (13U)        
-#define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
-#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3_Pos    (14U)        
-#define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
-#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4_Pos    (15U)        
-#define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
-#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1_Pos    (16U)        
-#define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
-#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2_Pos    (17U)        
-#define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
-#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3_Pos    (18U)        
-#define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
-#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4_Pos    (19U)        
-#define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
-#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1_Pos    (20U)        
-#define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
-#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2_Pos    (21U)        
-#define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
-#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3_Pos    (22U)        
-#define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
-#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4_Pos    (23U)        
-#define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
-#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1_Pos    (24U)        
-#define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
-#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2_Pos    (25U)        
-#define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
-#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3_Pos    (26U)        
-#define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
-#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4_Pos    (27U)        
-#define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
-#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1_Pos    (28U)        
-#define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
-#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2_Pos    (29U)        
-#define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
-#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3_Pos    (30U)        
-#define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
-#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4_Pos    (31U)        
-#define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
-#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1_Pos     (0U)         
-#define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2_Pos     (1U)         
-#define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3_Pos     (2U)         
-#define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4_Pos     (3U)         
-#define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1_Pos     (4U)         
-#define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2_Pos     (5U)         
-#define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3_Pos     (6U)         
-#define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4_Pos     (7U)         
-#define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1_Pos     (8U)         
-#define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2_Pos     (9U)         
-#define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3_Pos     (10U)        
-#define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4_Pos     (11U)        
-#define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1_Pos     (12U)        
-#define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2_Pos     (13U)        
-#define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3_Pos     (14U)        
-#define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4_Pos     (15U)        
-#define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1_Pos     (16U)        
-#define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2_Pos     (17U)        
-#define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3_Pos     (18U)        
-#define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4_Pos     (19U)        
-#define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1_Pos     (20U)        
-#define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2_Pos     (21U)        
-#define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3_Pos     (22U)        
-#define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4_Pos     (23U)        
-#define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1_Pos     (24U)        
-#define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2_Pos     (25U)        
-#define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3_Pos     (26U)        
-#define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4_Pos     (27U)        
-#define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1_Pos     (28U)        
-#define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2_Pos     (29U)        
-#define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3_Pos     (30U)        
-#define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4_Pos     (31U)        
-#define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1_Pos     (0U)         
-#define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2_Pos     (1U)         
-#define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3_Pos     (2U)         
-#define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4_Pos     (3U)         
-#define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1_Pos     (4U)         
-#define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2_Pos     (5U)         
-#define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3_Pos     (6U)         
-#define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4_Pos     (7U)         
-#define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1_Pos     (8U)         
-#define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2_Pos     (9U)         
-#define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3_Pos     (10U)        
-#define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4_Pos     (11U)        
-#define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1_Pos     (12U)        
-#define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2_Pos     (13U)        
-#define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3_Pos     (14U)        
-#define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4_Pos     (15U)        
-#define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1_Pos     (16U)        
-#define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2_Pos     (17U)        
-#define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3_Pos     (18U)        
-#define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4_Pos     (19U)        
-#define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1_Pos     (20U)        
-#define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2_Pos     (21U)        
-#define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3_Pos     (22U)        
-#define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4_Pos     (23U)        
-#define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1_Pos     (24U)        
-#define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2_Pos     (25U)        
-#define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3_Pos     (26U)        
-#define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4_Pos     (27U)        
-#define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1_Pos     (28U)        
-#define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2_Pos     (29U)        
-#define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3_Pos     (30U)        
-#define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4_Pos     (31U)        
-#define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E_Pos       (0U)         
-#define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
-#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E_Pos       (1U)         
-#define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
-#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E_Pos       (2U)         
-#define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
-#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E_Pos       (3U)         
-#define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
-#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E_Pos       (4U)         
-#define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
-#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E_Pos       (5U)         
-#define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
-#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E_Pos       (6U)         
-#define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
-#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E_Pos       (7U)         
-#define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
-#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S_Pos       (16U)        
-#define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
-#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S_Pos       (17U)        
-#define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
-#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S_Pos       (18U)        
-#define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
-#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S_Pos       (19U)        
-#define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
-#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S_Pos       (20U)        
-#define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
-#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S_Pos       (21U)        
-#define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
-#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S_Pos       (22U)        
-#define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
-#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S_Pos       (23U)        
-#define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
-#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT_Pos       (0U)         
-#define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
-#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         USB Device General registers                       */
-/*                                                                            */
-/******************************************************************************/
-#define USB_BASE                              (0x40005C00U)                    /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR_Pos           (13U)       
-#define USB_PMAADDR_Msk           (0x20003UL << USB_PMAADDR_Pos)                /*!< 0x40006000 */
-#define USB_PMAADDR               USB_PMAADDR_Msk                              /*!< USB_IP Packet Memory Area base address */
-                                             
-#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
-#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
-#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
-#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
-#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
-#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
-#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
-
-/****************************  ISTR interrupt events  *************************/
-#define USB_ISTR_CTR                          ((uint16_t)0x8000U)              /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR                       ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR                          ((uint16_t)0x2000U)              /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP                         ((uint16_t)0x1000U)              /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP                         ((uint16_t)0x0800U)              /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET                        ((uint16_t)0x0400U)              /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF                          ((uint16_t)0x0200U)              /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF                         ((uint16_t)0x0100U)              /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ                        ((uint16_t)0x0080U)              /*!< LPM L1 state request  */
-#define USB_ISTR_DIR                          ((uint16_t)0x0010U)              /*!< DIRection of transaction (read-only bit)  */
-#define USB_ISTR_EP_ID                        ((uint16_t)0x000FU)              /*!< EndPoint IDentifier (read-only bit)  */
-
-#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
-#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
-#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
-#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
-#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
-#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
-#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
-#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
-/*************************  CNTR control register bits definitions  ***********/
-#define USB_CNTR_CTRM                         ((uint16_t)0x8000U)              /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM                      ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM                         ((uint16_t)0x2000U)              /*!< ERRor Mask */
-#define USB_CNTR_WKUPM                        ((uint16_t)0x1000U)              /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM                        ((uint16_t)0x0800U)              /*!< SUSPend Mask */
-#define USB_CNTR_RESETM                       ((uint16_t)0x0400U)              /*!< RESET Mask   */
-#define USB_CNTR_SOFM                         ((uint16_t)0x0200U)              /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM                        ((uint16_t)0x0100U)              /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM                       ((uint16_t)0x0080U)              /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME                     ((uint16_t)0x0020U)              /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME                       ((uint16_t)0x0010U)              /*!< RESUME request */
-#define USB_CNTR_FSUSP                        ((uint16_t)0x0008U)              /*!< Force SUSPend */
-#define USB_CNTR_LPMODE                       ((uint16_t)0x0004U)              /*!< Low-power MODE */
-#define USB_CNTR_PDWN                         ((uint16_t)0x0002U)              /*!< Power DoWN */
-#define USB_CNTR_FRES                         ((uint16_t)0x0001U)              /*!< Force USB RESet */
-/*************************  BCDR control register bits definitions  ***********/
-#define USB_BCDR_DPPU                         ((uint16_t)0x8000U)              /*!< DP Pull-up Enable */  
-#define USB_BCDR_PS2DET                       ((uint16_t)0x0080U)              /*!< PS2 port or proprietary charger detected */  
-#define USB_BCDR_SDET                         ((uint16_t)0x0040U)              /*!< Secondary detection (SD) status */  
-#define USB_BCDR_PDET                         ((uint16_t)0x0020U)              /*!< Primary detection (PD) status */ 
-#define USB_BCDR_DCDET                        ((uint16_t)0x0010U)              /*!< Data contact detection (DCD) status */ 
-#define USB_BCDR_SDEN                         ((uint16_t)0x0008U)              /*!< Secondary detection (SD) mode enable */ 
-#define USB_BCDR_PDEN                         ((uint16_t)0x0004U)              /*!< Primary detection (PD) mode enable */  
-#define USB_BCDR_DCDEN                        ((uint16_t)0x0002U)              /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN                        ((uint16_t)0x0001U)              /*!< Battery charging detector (BCD) enable */
-/***************************  LPM register bits definitions  ******************/
-#define USB_LPMCSR_BESL                       ((uint16_t)0x00F0U)              /*!< BESL value received with last ACKed LPM Token  */ 
-#define USB_LPMCSR_REMWAKE                    ((uint16_t)0x0008U)              /*!< bRemoteWake value received with last ACKed LPM Token */ 
-#define USB_LPMCSR_LPMACK                     ((uint16_t)0x0002U)              /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN                      ((uint16_t)0x0001U)              /*!< LPM support enable  */
-/********************  FNR Frame Number Register bit definitions   ************/
-#define USB_FNR_RXDP                          ((uint16_t)0x8000U)              /*!< status of D+ data line */
-#define USB_FNR_RXDM                          ((uint16_t)0x4000U)              /*!< status of D- data line */
-#define USB_FNR_LCK                           ((uint16_t)0x2000U)              /*!< LoCKed */
-#define USB_FNR_LSOF                          ((uint16_t)0x1800U)              /*!< Lost SOF */
-#define USB_FNR_FN                            ((uint16_t)0x07FFU)              /*!< Frame Number */
-/********************  DADDR Device ADDRess bit definitions    ****************/
-#define USB_DADDR_EF                          ((uint8_t)0x80U)                 /*!< USB device address Enable Function */
-#define USB_DADDR_ADD                         ((uint8_t)0x7FU)                 /*!< USB device address */
-/******************************  Endpoint register    *************************/
-#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
-#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
-#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
-#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
-#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
-#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
-#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
-#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
-/* bit positions */ 
-#define USB_EP_CTR_RX                         ((uint16_t)0x8000U)              /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX                        ((uint16_t)0x4000U)              /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT                         ((uint16_t)0x3000U)              /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP                          ((uint16_t)0x0800U)              /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD                        ((uint16_t)0x0600U)              /*!<  EndPoint TYPE */
-#define USB_EP_KIND                           ((uint16_t)0x0100U)              /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX                         ((uint16_t)0x0080U)              /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX                        ((uint16_t)0x0040U)              /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT                         ((uint16_t)0x0030U)              /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD                      ((uint16_t)0x000FU)              /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK                      ((uint16_t)0x0600U)              /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           ((uint16_t)0x0000U)              /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        ((uint16_t)0x0200U)              /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    ((uint16_t)0x0400U)              /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      ((uint16_t)0x0600U)              /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
-                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       ((uint16_t)0x0010U)              /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         ((uint16_t)0x0020U)              /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       ((uint16_t)0x0030U)              /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        ((uint16_t)0x0010U)              /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        ((uint16_t)0x0020U)              /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       ((uint16_t)0x1000U)              /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         ((uint16_t)0x2000U)              /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       ((uint16_t)0x3000U)              /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        ((uint16_t)0x1000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        ((uint16_t)0x2000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM6))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************************** TSC Instances *********************************/
-#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/******************************* USB Instances *******************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define LPUART1_IRQn                   RNG_LPUART1_IRQn
-#define AES_LPUART1_IRQn               RNG_LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           RNG_LPUART1_IRQn
-#define TIM6_IRQn                      TIM6_DAC_IRQn
-#define RCC_IRQn                       RCC_CRS_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             RNG_LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         RNG_LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     RNG_LPUART1_IRQHandler
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
-#define RCC_IRQHandler                 RCC_CRS_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L052xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h
deleted file mode 100644
index 77052b9d04..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h
+++ /dev/null
@@ -1,7513 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l053xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l053xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l053xx
-  * @{
-  */
-    
-#ifndef __STM32L053xx_H
-#define __STM32L053xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1U /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l053xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  RNG_LPUART1_IRQn            = 29,     /*!< RNG and LPUART1 Interrupts                              */
-  LCD_IRQn                    = 30,     /*!< LCD Interrupt                                           */
-  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Clock Recovery System 
-  */
-
-typedef struct 
-{
-__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
-__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
-__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
-__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
-} CRS_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  uint32_t      RESERVED0[6];  /*!<                                                                     0x14-0x28 */
-  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  uint32_t      RESERVED1;     /*!<                                                                          0x30 */
-  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Random numbers generator
-  */
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
-  __IO uint16_t RESERVEDD;       /*!< Reserved */       
-  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
-  __IO uint16_t RESERVEDE;       /*!< Reserved */       
-} USB_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x080807FFUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
-#define LCD_BASE              (APBPERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
-#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000UL)
-#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define CRS                 ((CRS_TypeDef *) CRS_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define USB                 ((USB_TypeDef *) USB_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16_Pos     (16U)      
-#define ADC_CHSELR_CHSEL16_Msk     (0x1UL << ADC_CHSELR_CHSEL16_Pos)            /*!< 0x00010000 */
-#define ADC_CHSELR_CHSEL16         ADC_CHSELR_CHSEL16_Msk                      /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_VLCDEN_Pos         (24U)      
-#define ADC_CCR_VLCDEN_Msk         (0x1UL << ADC_CCR_VLCDEN_Pos)                /*!< 0x01000000 */
-#define ADC_CCR_VLCDEN             ADC_CCR_VLCDEN_Msk                          /*!< Voltage LCD enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRS Clock Recovery System                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRS_CR register  *********************/
-#define CRS_CR_SYNCOKIE_Pos       (0U)        
-#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
-#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
-#define CRS_CR_SYNCWARNIE_Pos     (1U)        
-#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
-#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
-#define CRS_CR_ERRIE_Pos          (2U)        
-#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
-#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
-#define CRS_CR_ESYNCIE_Pos        (3U)        
-#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
-#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN_Pos            (5U)        
-#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
-#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
-#define CRS_CR_AUTOTRIMEN_Pos     (6U)        
-#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
-#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
-#define CRS_CR_SWSYNC_Pos         (7U)        
-#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
-#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
-#define CRS_CR_TRIM_Pos           (8U)        
-#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
-#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
-
-/*******************  Bit definition for CRS_CFGR register  *********************/
-#define CRS_CFGR_RELOAD_Pos       (0U)        
-#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
-#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
-#define CRS_CFGR_FELIM_Pos        (16U)       
-#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
-#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
-
-#define CRS_CFGR_SYNCDIV_Pos      (24U)       
-#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
-#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
-#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
-#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
-#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
-
-#define CRS_CFGR_SYNCSRC_Pos      (28U)       
-#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
-#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
-#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
-#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
-
-#define CRS_CFGR_SYNCPOL_Pos      (31U)       
-#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
-#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
-  
-/*******************  Bit definition for CRS_ISR register  *********************/
-#define CRS_ISR_SYNCOKF_Pos       (0U)        
-#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
-#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
-#define CRS_ISR_SYNCWARNF_Pos     (1U)        
-#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
-#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
-#define CRS_ISR_ERRF_Pos          (2U)        
-#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
-#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
-#define CRS_ISR_ESYNCF_Pos        (3U)        
-#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
-#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
-#define CRS_ISR_SYNCERR_Pos       (8U)        
-#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
-#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
-#define CRS_ISR_SYNCMISS_Pos      (9U)        
-#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
-#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
-#define CRS_ISR_TRIMOVF_Pos       (10U)       
-#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
-#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR_Pos         (15U)       
-#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
-#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
-#define CRS_ISR_FECAP_Pos         (16U)       
-#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
-#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
-
-/*******************  Bit definition for CRS_ICR register  *********************/
-#define CRS_ICR_SYNCOKC_Pos       (0U)        
-#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
-#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
-#define CRS_ICR_SYNCWARNC_Pos     (1U)        
-#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
-#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
-#define CRS_ICR_ERRC_Pos          (2U)        
-#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
-#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag             */
-#define CRS_ICR_ESYNCC_Pos        (3U)        
-#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
-#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)      
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos            (1U)      
-#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos             (2U)      
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (3U)      
-#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)      
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)      
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)     
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)     
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)      
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)      
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)      
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)      
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)      
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)     
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos            (0U)      
-#define LCD_CR_LCDEN_Msk            (0x1UL << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
-#define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos             (1U)      
-#define LCD_CR_VSEL_Msk             (0x1UL << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
-#define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos             (2U)      
-#define LCD_CR_DUTY_Msk             (0x7UL << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
-#define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0               (0x1UL << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
-#define LCD_CR_DUTY_1               (0x2UL << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
-#define LCD_CR_DUTY_2               (0x4UL << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos             (5U)      
-#define LCD_CR_BIAS_Msk             (0x3UL << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
-#define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0               (0x1UL << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
-#define LCD_CR_BIAS_1               (0x2UL << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos          (7U)      
-#define LCD_CR_MUX_SEG_Msk          (0x1UL << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
-
-#define LCD_CR_BUFEN_Pos            (8U)
-#define LCD_CR_BUFEN_Msk            (0x1UL << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
-#define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos              (0U)      
-#define LCD_FCR_HD_Msk              (0x1UL << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
-#define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos           (1U)      
-#define LCD_FCR_SOFIE_Msk           (0x1UL << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
-#define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos           (3U)      
-#define LCD_FCR_UDDIE_Msk           (0x1UL << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
-#define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos             (4U)      
-#define LCD_FCR_PON_Msk             (0x7UL << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
-#define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0               (0x1UL << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
-#define LCD_FCR_PON_1               (0x2UL << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
-#define LCD_FCR_PON_2               (0x4UL << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos            (7U)      
-#define LCD_FCR_DEAD_Msk            (0x7UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
-#define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0              (0x1UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1              (0x2UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2              (0x4UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos              (10U)     
-#define LCD_FCR_CC_Msk              (0x7UL << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
-#define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0                (0x1UL << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
-#define LCD_FCR_CC_1                (0x2UL << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
-#define LCD_FCR_CC_2                (0x4UL << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos          (13U)     
-#define LCD_FCR_BLINKF_Msk          (0x7UL << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0            (0x1UL << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1            (0x2UL << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2            (0x4UL << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos           (16U)     
-#define LCD_FCR_BLINK_Msk           (0x3UL << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
-#define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0             (0x1UL << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1             (0x2UL << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos             (18U)     
-#define LCD_FCR_DIV_Msk             (0xFUL << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
-#define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos              (22U)     
-#define LCD_FCR_PS_Msk              (0xFUL << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
-#define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos              (0U)      
-#define LCD_SR_ENS_Msk              (0x1UL << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
-#define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos              (1U)      
-#define LCD_SR_SOF_Msk              (0x1UL << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
-#define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos              (2U)      
-#define LCD_SR_UDR_Msk              (0x1UL << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
-#define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos              (3U)      
-#define LCD_SR_UDD_Msk              (0x1UL << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
-#define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos              (4U)      
-#define LCD_SR_RDY_Msk              (0x1UL << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
-#define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos            (5U)      
-#define LCD_SR_FCRSR_Msk            (0x1UL << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
-#define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos            (1U)      
-#define LCD_CLR_SOFC_Msk            (0x1UL << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
-#define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos            (3U)      
-#define LCD_CLR_UDDC_Msk            (0x1UL << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
-#define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos    (0U)      
-#define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)             
-#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)             
-#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)             
-#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)             
-#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)             
-#define FW_VDSSA_ADD_Msk     (0x3FFUL << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)             
-#define FW_VDSL_LENG_Msk     (0x3FFUL << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)             
-#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)             
-#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)             
-#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-#define RCC_MCO3_SUPPORT            /*!<Support MCO3 */
-#define RCC_MCO3_AF0_SUPPORT        /*!<Support MCO3 on Alternate Function AF2 */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC/LCD prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CRRCR register  *****************/
-#define RCC_CRRCR_HSI48ON_Pos            (0U) 
-#define RCC_CRRCR_HSI48ON_Msk            (0x1UL << RCC_CRRCR_HSI48ON_Pos)       /*!< 0x00000001 */
-#define RCC_CRRCR_HSI48ON                RCC_CRRCR_HSI48ON_Msk                 /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY_Pos           (1U) 
-#define RCC_CRRCR_HSI48RDY_Msk           (0x1UL << RCC_CRRCR_HSI48RDY_Pos)      /*!< 0x00000002 */
-#define RCC_CRRCR_HSI48RDY               RCC_CRRCR_HSI48RDY_Msk                /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48CAL_Pos           (8U) 
-#define RCC_CRRCR_HSI48CAL_Msk           (0xFFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF00 */
-#define RCC_CRRCR_HSI48CAL               RCC_CRRCR_HSI48CAL_Msk                /*!< HSI 48MHz clock Calibration */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-#define RCC_CFGR_MCOSEL_HSI48_Pos            (27U)                             
-#define RCC_CFGR_MCOSEL_HSI48_Msk            (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
-#define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCOSEL_HSI48_Msk         /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE_Pos          (6U) 
-#define RCC_CIER_HSI48RDYIE_Msk          (0x1UL << RCC_CIER_HSI48RDYIE_Pos)     /*!< 0x00000040 */
-#define RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE_Msk               /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF_Pos           (6U) 
-#define RCC_CIFR_HSI48RDYF_Msk           (0x1UL << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000040 */
-#define RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF_Msk                /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC_Pos           (6U) 
-#define RCC_CICR_HSI48RDYC_Msk           (0x1UL << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000040 */
-#define RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC_Msk                /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST_Pos           (16U)
-#define RCC_AHBRSTR_TSCRST_Msk           (0x1UL << RCC_AHBRSTR_TSCRST_Pos)      /*!< 0x00010000 */
-#define RCC_AHBRSTR_TSCRST               RCC_AHBRSTR_TSCRST_Msk                /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST_Pos           (20U)
-#define RCC_AHBRSTR_RNGRST_Msk           (0x1UL << RCC_AHBRSTR_RNGRST_Pos)      /*!< 0x00100000 */
-#define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk                /*!< RNG reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1UL << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 reset */
-#define RCC_APB1RSTR_LCDRST_Pos          (9U)
-#define RCC_APB1RSTR_LCDRST_Msk          (0x1UL << RCC_APB1RSTR_LCDRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST              RCC_APB1RSTR_LCDRST_Msk               /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos          (23U)
-#define RCC_APB1RSTR_USBRST_Msk          (0x1UL << RCC_APB1RSTR_USBRST_Pos)     /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST              RCC_APB1RSTR_USBRST_Msk               /*!< USB reset */
-#define RCC_APB1RSTR_CRSRST_Pos          (27U)
-#define RCC_APB1RSTR_CRSRST_Msk          (0x1UL << RCC_APB1RSTR_CRSRST_Pos)     /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST              RCC_APB1RSTR_CRSRST_Msk               /*!< CRS reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_DACRST_Pos          (29U)
-#define RCC_APB1RSTR_DACRST_Msk          (0x1UL << RCC_APB1RSTR_DACRST_Pos)     /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST              RCC_APB1RSTR_DACRST_Msk               /*!< DAC reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN_Pos             (16U)
-#define RCC_AHBENR_TSCEN_Msk             (0x1UL << RCC_AHBENR_TSCEN_Pos)        /*!< 0x00010000 */
-#define RCC_AHBENR_TSCEN                 RCC_AHBENR_TSCEN_Msk                  /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN_Pos             (20U)
-#define RCC_AHBENR_RNGEN_Msk             (0x1UL << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00100000 */
-#define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk                  /*!< RNG clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)
-#define RCC_APB2ENR_USART1EN_Msk         (0x1UL << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U) 
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1UL << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos            (9U) 
-#define RCC_APB1ENR_LCDEN_Msk            (0x1UL << RCC_APB1ENR_LCDEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                RCC_APB1ENR_LCDEN_Msk                 /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1UL << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1UL << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos            (23U)
-#define RCC_APB1ENR_USBEN_Msk            (0x1UL << RCC_APB1ENR_USBEN_Pos)       /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                RCC_APB1ENR_USBEN_Msk                 /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN_Pos            (27U)
-#define RCC_APB1ENR_CRSEN_Msk            (0x1UL << RCC_APB1ENR_CRSEN_Pos)       /*!< 0x08000000 */
-#define RCC_APB1ENR_CRSEN                RCC_APB1ENR_CRSEN_Msk                 /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN_Pos            (29U)
-#define RCC_APB1ENR_DACEN_Msk            (0x1UL << RCC_APB1ENR_DACEN_Pos)       /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                RCC_APB1ENR_DACEN_Msk                 /*!< DAC clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN_Pos         (16U)
-#define RCC_AHBSMENR_TSCSMEN_Msk         (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos)    /*!< 0x00010000 */
-#define RCC_AHBSMENR_TSCSMEN             RCC_AHBSMENR_TSCSMEN_Msk              /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN_Pos         (20U)
-#define RCC_AHBSMENR_RNGSMEN_Msk         (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00100000 */
-#define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk              /*!< RNG clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U) 
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LCDSMEN_Pos        (9U) 
-#define RCC_APB1SMENR_LCDSMEN_Msk        (0x1UL << RCC_APB1SMENR_LCDSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB1SMENR_LCDSMEN            RCC_APB1SMENR_LCDSMEN_Msk             /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN_Pos        (23U)
-#define RCC_APB1SMENR_USBSMEN_Msk        (0x1UL << RCC_APB1SMENR_USBSMEN_Pos)   /*!< 0x00800000 */
-#define RCC_APB1SMENR_USBSMEN            RCC_APB1SMENR_USBSMEN_Msk             /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN_Pos        (27U)
-#define RCC_APB1SMENR_CRSSMEN_Msk        (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos)   /*!< 0x08000000 */
-#define RCC_APB1SMENR_CRSSMEN            RCC_APB1SMENR_CRSSMEN_Msk             /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN_Pos        (29U)
-#define RCC_APB1SMENR_DACSMEN_Msk        (0x1UL << RCC_APB1SMENR_DACSMEN_Pos)   /*!< 0x20000000 */
-#define RCC_APB1SMENR_DACSMEN            RCC_APB1SMENR_DACSMEN_Msk             /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U) 
-#define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*!< HSI48 Clock source selection */ 
-#define RCC_CCIPR_HSI48SEL_Pos           (26U)
-#define RCC_CCIPR_HSI48SEL_Msk           (0x1UL << RCC_CCIPR_HSI48SEL_Pos)      /*!< 0x04000000 */
-#define RCC_CCIPR_HSI48SEL               RCC_CCIPR_HSI48SEL_Msk                /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Legacy defines */
-#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos    (2U)              
-#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
-#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
-#define RNG_CR_IE_Pos       (3U)              
-#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
-#define RNG_CR_IE           RNG_CR_IE_Msk                                      
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)              
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
-#define RNG_SR_CECS_Pos     (1U)              
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
-#define RNG_SR_SECS_Pos     (2U)              
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
-#define RNG_SR_CEIS_Pos     (5U)              
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
-#define RNG_SR_SEIS_Pos     (6U)              
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)      
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)      
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)      
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)      
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)      
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)      
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)     
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)     
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)      
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)      
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)      
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_CAPA_Pos                    (1U)                          
-#define SYSCFG_CFGR2_CAPA_Msk                    (0x7UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x0000000E */
-#define SYSCFG_CFGR2_CAPA                        SYSCFG_CFGR2_CAPA_Msk         /*!< Connection of internal Vlcd rail to external capacitors */
-#define SYSCFG_CFGR2_CAPA_0                      (0x1UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR2_CAPA_1                      (0x2UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000004 */
-#define SYSCFG_CFGR2_CAPA_2                      (0x4UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000008 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48_Pos             (13U)                         
-#define SYSCFG_CFGR3_ENREF_HSI48_Msk             (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR3_ENREF_HSI48                 SYSCFG_CFGR3_ENREF_HSI48_Msk  /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
-#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_REF_HSI48_RDYF           SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE_Pos          (0U)         
-#define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
-#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
-#define TSC_CR_START_Pos         (1U)         
-#define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
-#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
-#define TSC_CR_AM_Pos            (2U)         
-#define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
-#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL_Pos       (3U)         
-#define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
-#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF_Pos         (4U)         
-#define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
-#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
-
-#define TSC_CR_MCV_Pos           (5U)         
-#define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
-#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
-#define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
-#define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
-
-#define TSC_CR_PGPSC_Pos         (12U)        
-#define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
-#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
-#define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
-#define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
-
-#define TSC_CR_SSPSC_Pos         (15U)        
-#define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
-#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE_Pos           (16U)        
-#define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
-#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD_Pos           (17U)        
-#define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
-#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
-#define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
-#define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
-#define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
-#define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
-#define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
-#define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
-
-#define TSC_CR_CTPL_Pos          (24U)        
-#define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
-#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
-#define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
-#define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
-#define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
-
-#define TSC_CR_CTPH_Pos          (28U)        
-#define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
-#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
-#define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
-#define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
-#define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE_Pos        (0U)         
-#define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
-#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE_Pos        (1U)         
-#define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
-#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC_Pos        (0U)         
-#define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
-#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC_Pos        (1U)         
-#define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
-#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF_Pos         (0U)         
-#define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
-#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
-#define TSC_ISR_MCEF_Pos         (1U)         
-#define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
-#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1_Pos     (0U)         
-#define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2_Pos     (1U)         
-#define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3_Pos     (2U)         
-#define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4_Pos     (3U)         
-#define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1_Pos     (4U)         
-#define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2_Pos     (5U)         
-#define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3_Pos     (6U)         
-#define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4_Pos     (7U)         
-#define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1_Pos     (8U)         
-#define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2_Pos     (9U)         
-#define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3_Pos     (10U)        
-#define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4_Pos     (11U)        
-#define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1_Pos     (12U)        
-#define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2_Pos     (13U)        
-#define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3_Pos     (14U)        
-#define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4_Pos     (15U)        
-#define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1_Pos     (16U)        
-#define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2_Pos     (17U)        
-#define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3_Pos     (18U)        
-#define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4_Pos     (19U)        
-#define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1_Pos     (20U)        
-#define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2_Pos     (21U)        
-#define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3_Pos     (22U)        
-#define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4_Pos     (23U)        
-#define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1_Pos     (24U)        
-#define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2_Pos     (25U)        
-#define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3_Pos     (26U)        
-#define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4_Pos     (27U)        
-#define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1_Pos     (28U)        
-#define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2_Pos     (29U)        
-#define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3_Pos     (30U)        
-#define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4_Pos     (31U)        
-#define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1_Pos    (0U)         
-#define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
-#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2_Pos    (1U)         
-#define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
-#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3_Pos    (2U)         
-#define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
-#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4_Pos    (3U)         
-#define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
-#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1_Pos    (4U)         
-#define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
-#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2_Pos    (5U)         
-#define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
-#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3_Pos    (6U)         
-#define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
-#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4_Pos    (7U)         
-#define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
-#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1_Pos    (8U)         
-#define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
-#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2_Pos    (9U)         
-#define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
-#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3_Pos    (10U)        
-#define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
-#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4_Pos    (11U)        
-#define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
-#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1_Pos    (12U)        
-#define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
-#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2_Pos    (13U)        
-#define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
-#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3_Pos    (14U)        
-#define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
-#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4_Pos    (15U)        
-#define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
-#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1_Pos    (16U)        
-#define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
-#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2_Pos    (17U)        
-#define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
-#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3_Pos    (18U)        
-#define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
-#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4_Pos    (19U)        
-#define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
-#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1_Pos    (20U)        
-#define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
-#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2_Pos    (21U)        
-#define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
-#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3_Pos    (22U)        
-#define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
-#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4_Pos    (23U)        
-#define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
-#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1_Pos    (24U)        
-#define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
-#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2_Pos    (25U)        
-#define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
-#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3_Pos    (26U)        
-#define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
-#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4_Pos    (27U)        
-#define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
-#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1_Pos    (28U)        
-#define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
-#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2_Pos    (29U)        
-#define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
-#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3_Pos    (30U)        
-#define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
-#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4_Pos    (31U)        
-#define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
-#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1_Pos     (0U)         
-#define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2_Pos     (1U)         
-#define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3_Pos     (2U)         
-#define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4_Pos     (3U)         
-#define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1_Pos     (4U)         
-#define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2_Pos     (5U)         
-#define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3_Pos     (6U)         
-#define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4_Pos     (7U)         
-#define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1_Pos     (8U)         
-#define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2_Pos     (9U)         
-#define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3_Pos     (10U)        
-#define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4_Pos     (11U)        
-#define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1_Pos     (12U)        
-#define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2_Pos     (13U)        
-#define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3_Pos     (14U)        
-#define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4_Pos     (15U)        
-#define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1_Pos     (16U)        
-#define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2_Pos     (17U)        
-#define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3_Pos     (18U)        
-#define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4_Pos     (19U)        
-#define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1_Pos     (20U)        
-#define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2_Pos     (21U)        
-#define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3_Pos     (22U)        
-#define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4_Pos     (23U)        
-#define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1_Pos     (24U)        
-#define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2_Pos     (25U)        
-#define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3_Pos     (26U)        
-#define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4_Pos     (27U)        
-#define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1_Pos     (28U)        
-#define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2_Pos     (29U)        
-#define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3_Pos     (30U)        
-#define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4_Pos     (31U)        
-#define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1_Pos     (0U)         
-#define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2_Pos     (1U)         
-#define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3_Pos     (2U)         
-#define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4_Pos     (3U)         
-#define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1_Pos     (4U)         
-#define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2_Pos     (5U)         
-#define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3_Pos     (6U)         
-#define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4_Pos     (7U)         
-#define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1_Pos     (8U)         
-#define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2_Pos     (9U)         
-#define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3_Pos     (10U)        
-#define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4_Pos     (11U)        
-#define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1_Pos     (12U)        
-#define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2_Pos     (13U)        
-#define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3_Pos     (14U)        
-#define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4_Pos     (15U)        
-#define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1_Pos     (16U)        
-#define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2_Pos     (17U)        
-#define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3_Pos     (18U)        
-#define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4_Pos     (19U)        
-#define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1_Pos     (20U)        
-#define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2_Pos     (21U)        
-#define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3_Pos     (22U)        
-#define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4_Pos     (23U)        
-#define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1_Pos     (24U)        
-#define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2_Pos     (25U)        
-#define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3_Pos     (26U)        
-#define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4_Pos     (27U)        
-#define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1_Pos     (28U)        
-#define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2_Pos     (29U)        
-#define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3_Pos     (30U)        
-#define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4_Pos     (31U)        
-#define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E_Pos       (0U)         
-#define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
-#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E_Pos       (1U)         
-#define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
-#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E_Pos       (2U)         
-#define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
-#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E_Pos       (3U)         
-#define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
-#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E_Pos       (4U)         
-#define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
-#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E_Pos       (5U)         
-#define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
-#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E_Pos       (6U)         
-#define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
-#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E_Pos       (7U)         
-#define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
-#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S_Pos       (16U)        
-#define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
-#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S_Pos       (17U)        
-#define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
-#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S_Pos       (18U)        
-#define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
-#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S_Pos       (19U)        
-#define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
-#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S_Pos       (20U)        
-#define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
-#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S_Pos       (21U)        
-#define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
-#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S_Pos       (22U)        
-#define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
-#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S_Pos       (23U)        
-#define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
-#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT_Pos       (0U)         
-#define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
-#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         USB Device General registers                       */
-/*                                                                            */
-/******************************************************************************/
-#define USB_BASE                              (0x40005C00U)                    /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR_Pos           (13U)       
-#define USB_PMAADDR_Msk           (0x20003UL << USB_PMAADDR_Pos)                /*!< 0x40006000 */
-#define USB_PMAADDR               USB_PMAADDR_Msk                              /*!< USB_IP Packet Memory Area base address */
-                                             
-#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
-#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
-#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
-#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
-#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
-#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
-#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
-
-/****************************  ISTR interrupt events  *************************/
-#define USB_ISTR_CTR                          ((uint16_t)0x8000U)              /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR                       ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR                          ((uint16_t)0x2000U)              /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP                         ((uint16_t)0x1000U)              /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP                         ((uint16_t)0x0800U)              /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET                        ((uint16_t)0x0400U)              /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF                          ((uint16_t)0x0200U)              /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF                         ((uint16_t)0x0100U)              /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ                        ((uint16_t)0x0080U)              /*!< LPM L1 state request  */
-#define USB_ISTR_DIR                          ((uint16_t)0x0010U)              /*!< DIRection of transaction (read-only bit)  */
-#define USB_ISTR_EP_ID                        ((uint16_t)0x000FU)              /*!< EndPoint IDentifier (read-only bit)  */
-
-#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
-#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
-#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
-#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
-#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
-#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
-#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
-#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
-/*************************  CNTR control register bits definitions  ***********/
-#define USB_CNTR_CTRM                         ((uint16_t)0x8000U)              /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM                      ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM                         ((uint16_t)0x2000U)              /*!< ERRor Mask */
-#define USB_CNTR_WKUPM                        ((uint16_t)0x1000U)              /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM                        ((uint16_t)0x0800U)              /*!< SUSPend Mask */
-#define USB_CNTR_RESETM                       ((uint16_t)0x0400U)              /*!< RESET Mask   */
-#define USB_CNTR_SOFM                         ((uint16_t)0x0200U)              /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM                        ((uint16_t)0x0100U)              /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM                       ((uint16_t)0x0080U)              /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME                     ((uint16_t)0x0020U)              /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME                       ((uint16_t)0x0010U)              /*!< RESUME request */
-#define USB_CNTR_FSUSP                        ((uint16_t)0x0008U)              /*!< Force SUSPend */
-#define USB_CNTR_LPMODE                       ((uint16_t)0x0004U)              /*!< Low-power MODE */
-#define USB_CNTR_PDWN                         ((uint16_t)0x0002U)              /*!< Power DoWN */
-#define USB_CNTR_FRES                         ((uint16_t)0x0001U)              /*!< Force USB RESet */
-/*************************  BCDR control register bits definitions  ***********/
-#define USB_BCDR_DPPU                         ((uint16_t)0x8000U)              /*!< DP Pull-up Enable */  
-#define USB_BCDR_PS2DET                       ((uint16_t)0x0080U)              /*!< PS2 port or proprietary charger detected */  
-#define USB_BCDR_SDET                         ((uint16_t)0x0040U)              /*!< Secondary detection (SD) status */  
-#define USB_BCDR_PDET                         ((uint16_t)0x0020U)              /*!< Primary detection (PD) status */ 
-#define USB_BCDR_DCDET                        ((uint16_t)0x0010U)              /*!< Data contact detection (DCD) status */ 
-#define USB_BCDR_SDEN                         ((uint16_t)0x0008U)              /*!< Secondary detection (SD) mode enable */ 
-#define USB_BCDR_PDEN                         ((uint16_t)0x0004U)              /*!< Primary detection (PD) mode enable */  
-#define USB_BCDR_DCDEN                        ((uint16_t)0x0002U)              /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN                        ((uint16_t)0x0001U)              /*!< Battery charging detector (BCD) enable */
-/***************************  LPM register bits definitions  ******************/
-#define USB_LPMCSR_BESL                       ((uint16_t)0x00F0U)              /*!< BESL value received with last ACKed LPM Token  */ 
-#define USB_LPMCSR_REMWAKE                    ((uint16_t)0x0008U)              /*!< bRemoteWake value received with last ACKed LPM Token */ 
-#define USB_LPMCSR_LPMACK                     ((uint16_t)0x0002U)              /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN                      ((uint16_t)0x0001U)              /*!< LPM support enable  */
-/********************  FNR Frame Number Register bit definitions   ************/
-#define USB_FNR_RXDP                          ((uint16_t)0x8000U)              /*!< status of D+ data line */
-#define USB_FNR_RXDM                          ((uint16_t)0x4000U)              /*!< status of D- data line */
-#define USB_FNR_LCK                           ((uint16_t)0x2000U)              /*!< LoCKed */
-#define USB_FNR_LSOF                          ((uint16_t)0x1800U)              /*!< Lost SOF */
-#define USB_FNR_FN                            ((uint16_t)0x07FFU)              /*!< Frame Number */
-/********************  DADDR Device ADDRess bit definitions    ****************/
-#define USB_DADDR_EF                          ((uint8_t)0x80U)                 /*!< USB device address Enable Function */
-#define USB_DADDR_ADD                         ((uint8_t)0x7FU)                 /*!< USB device address */
-/******************************  Endpoint register    *************************/
-#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
-#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
-#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
-#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
-#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
-#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
-#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
-#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
-/* bit positions */ 
-#define USB_EP_CTR_RX                         ((uint16_t)0x8000U)              /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX                        ((uint16_t)0x4000U)              /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT                         ((uint16_t)0x3000U)              /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP                          ((uint16_t)0x0800U)              /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD                        ((uint16_t)0x0600U)              /*!<  EndPoint TYPE */
-#define USB_EP_KIND                           ((uint16_t)0x0100U)              /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX                         ((uint16_t)0x0080U)              /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX                        ((uint16_t)0x0040U)              /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT                         ((uint16_t)0x0030U)              /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD                      ((uint16_t)0x000FU)              /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK                      ((uint16_t)0x0600U)              /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           ((uint16_t)0x0000U)              /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        ((uint16_t)0x0200U)              /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    ((uint16_t)0x0400U)              /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      ((uint16_t)0x0600U)              /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
-                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       ((uint16_t)0x0010U)              /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         ((uint16_t)0x0020U)              /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       ((uint16_t)0x0030U)              /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        ((uint16_t)0x0010U)              /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        ((uint16_t)0x0020U)              /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       ((uint16_t)0x1000U)              /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         ((uint16_t)0x2000U)              /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       ((uint16_t)0x3000U)              /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        ((uint16_t)0x1000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        ((uint16_t)0x2000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM6))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************************** TSC Instances *********************************/
-#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/******************************* USB Instances *******************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define LPUART1_IRQn                   RNG_LPUART1_IRQn
-#define AES_LPUART1_IRQn               RNG_LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           RNG_LPUART1_IRQn
-#define TIM6_IRQn                      TIM6_DAC_IRQn
-#define RCC_IRQn                       RCC_CRS_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             RNG_LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         RNG_LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     RNG_LPUART1_IRQHandler
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
-#define RCC_IRQHandler                 RCC_CRS_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L053xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h
deleted file mode 100644
index 351d1b62d8..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h
+++ /dev/null
@@ -1,7491 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l062xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l062xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l062xx
-  * @{
-  */
-    
-#ifndef __STM32L062xx_H
-#define __STM32L062xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1U /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l062xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  AES_RNG_LPUART1_IRQn        = 29,     /*!< AES and RNG and LPUART1 Interrupts                      */
-  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;      /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;      /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;    /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;   /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;   /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;   /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;   /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;   /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;    /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;    /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;    /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;    /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Clock Recovery System 
-  */
-
-typedef struct 
-{
-__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
-__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
-__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
-__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
-} CRS_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  uint32_t      RESERVED0[6];  /*!<                                                                     0x14-0x28 */
-  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  uint32_t      RESERVED1;     /*!<                                                                          0x30 */
-  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Random numbers generator
-  */
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
-  __IO uint16_t RESERVEDD;       /*!< Reserved */       
-  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
-  __IO uint16_t RESERVEDE;       /*!< Reserved */       
-} USB_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x080807FFUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
-#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000UL)
-#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000UL)
-#define AES_BASE              (AHBPERIPH_BASE + 0x00006000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define CRS                 ((CRS_TypeDef *) CRS_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define AES                 ((AES_TypeDef *) AES_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define USB                 ((USB_TypeDef *) USB_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos            (0U)         
-#define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                       /*!< 0x00000001 */
-#define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos      (1U)         
-#define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000006 */
-#define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
-#define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos          (3U)         
-#define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                     /*!< 0x00000018 */
-#define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                     /*!< 0x00000008 */
-#define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                     /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos         (5U)         
-#define AES_CR_CHMOD_Msk         (0x3UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000060 */
-#define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0           (0x1UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000020 */
-#define AES_CR_CHMOD_1           (0x2UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000040 */
-
-#define AES_CR_CCFC_Pos          (7U)         
-#define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                     /*!< 0x00000080 */
-#define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos          (8U)         
-#define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                     /*!< 0x00000100 */
-#define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
-#define AES_CR_CCIE_Pos          (9U)         
-#define AES_CR_CCIE_Msk          (0x1UL << AES_CR_CCIE_Pos)                     /*!< 0x00000200 */
-#define AES_CR_CCIE              AES_CR_CCIE_Msk                               /*!< Computation Complete Interrupt Enable */
-#define AES_CR_ERRIE_Pos         (10U)        
-#define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                    /*!< 0x00000400 */
-#define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos       (11U)        
-#define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                  /*!< 0x00000800 */
-#define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< DMA ENable managing the data input phase */
-#define AES_CR_DMAOUTEN_Pos      (12U)        
-#define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                 /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos           (0U)         
-#define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                      /*!< 0x00000001 */
-#define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos         (1U)         
-#define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                    /*!< 0x00000002 */
-#define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos         (2U)         
-#define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                    /*!< 0x00000004 */
-#define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos             (0U)         
-#define AES_DINR_Msk             (0xFFFFUL << AES_DINR_Pos)                     /*!< 0x0000FFFF */
-#define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos            (0U)         
-#define AES_DOUTR_Msk            (0xFFFFUL << AES_DOUTR_Pos)                    /*!< 0x0000FFFF */
-#define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos            (0U)         
-#define AES_KEYR0_Msk            (0xFFFFUL << AES_KEYR0_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos            (0U)         
-#define AES_KEYR1_Msk            (0xFFFFUL << AES_KEYR1_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos            (0U)         
-#define AES_KEYR2_Msk            (0xFFFFUL << AES_KEYR2_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos            (0U)         
-#define AES_KEYR3_Msk            (0xFFFFUL << AES_KEYR3_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define AES_IVR0_Pos             (0U)         
-#define AES_IVR0_Msk             (0xFFFFUL << AES_IVR0_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define AES_IVR1_Pos             (0U)         
-#define AES_IVR1_Msk             (0xFFFFUL << AES_IVR1_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define AES_IVR2_Pos             (0U)         
-#define AES_IVR2_Msk             (0xFFFFUL << AES_IVR2_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define AES_IVR3_Pos             (0U)         
-#define AES_IVR3_Msk             (0xFFFFUL << AES_IVR3_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRS Clock Recovery System                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRS_CR register  *********************/
-#define CRS_CR_SYNCOKIE_Pos       (0U)        
-#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
-#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
-#define CRS_CR_SYNCWARNIE_Pos     (1U)        
-#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
-#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
-#define CRS_CR_ERRIE_Pos          (2U)        
-#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
-#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
-#define CRS_CR_ESYNCIE_Pos        (3U)        
-#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
-#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN_Pos            (5U)        
-#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
-#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
-#define CRS_CR_AUTOTRIMEN_Pos     (6U)        
-#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
-#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
-#define CRS_CR_SWSYNC_Pos         (7U)        
-#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
-#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
-#define CRS_CR_TRIM_Pos           (8U)        
-#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
-#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
-
-/*******************  Bit definition for CRS_CFGR register  *********************/
-#define CRS_CFGR_RELOAD_Pos       (0U)        
-#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
-#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
-#define CRS_CFGR_FELIM_Pos        (16U)       
-#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
-#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
-
-#define CRS_CFGR_SYNCDIV_Pos      (24U)       
-#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
-#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
-#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
-#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
-#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
-
-#define CRS_CFGR_SYNCSRC_Pos      (28U)       
-#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
-#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
-#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
-#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
-
-#define CRS_CFGR_SYNCPOL_Pos      (31U)       
-#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
-#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
-  
-/*******************  Bit definition for CRS_ISR register  *********************/
-#define CRS_ISR_SYNCOKF_Pos       (0U)        
-#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
-#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
-#define CRS_ISR_SYNCWARNF_Pos     (1U)        
-#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
-#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
-#define CRS_ISR_ERRF_Pos          (2U)        
-#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
-#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
-#define CRS_ISR_ESYNCF_Pos        (3U)        
-#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
-#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
-#define CRS_ISR_SYNCERR_Pos       (8U)        
-#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
-#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
-#define CRS_ISR_SYNCMISS_Pos      (9U)        
-#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
-#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
-#define CRS_ISR_TRIMOVF_Pos       (10U)       
-#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
-#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR_Pos         (15U)       
-#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
-#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
-#define CRS_ISR_FECAP_Pos         (16U)       
-#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
-#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
-
-/*******************  Bit definition for CRS_ICR register  *********************/
-#define CRS_ICR_SYNCOKC_Pos       (0U)        
-#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
-#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
-#define CRS_ICR_SYNCWARNC_Pos     (1U)        
-#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
-#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
-#define CRS_ICR_ERRC_Pos          (2U)        
-#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
-#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag             */
-#define CRS_ICR_ESYNCC_Pos        (3U)        
-#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
-#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)      
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos            (1U)      
-#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos             (2U)      
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (3U)      
-#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)      
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)      
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)     
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)     
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)      
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)      
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)      
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)      
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)      
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)     
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)             
-#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)             
-#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)             
-#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)             
-#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)             
-#define FW_VDSSA_ADD_Msk     (0x3FFUL << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)             
-#define FW_VDSL_LENG_Msk     (0x3FFUL << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)             
-#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)             
-#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)             
-#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CRRCR register  *****************/
-#define RCC_CRRCR_HSI48ON_Pos            (0U) 
-#define RCC_CRRCR_HSI48ON_Msk            (0x1UL << RCC_CRRCR_HSI48ON_Pos)       /*!< 0x00000001 */
-#define RCC_CRRCR_HSI48ON                RCC_CRRCR_HSI48ON_Msk                 /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY_Pos           (1U) 
-#define RCC_CRRCR_HSI48RDY_Msk           (0x1UL << RCC_CRRCR_HSI48RDY_Pos)      /*!< 0x00000002 */
-#define RCC_CRRCR_HSI48RDY               RCC_CRRCR_HSI48RDY_Msk                /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48CAL_Pos           (8U) 
-#define RCC_CRRCR_HSI48CAL_Msk           (0xFFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF00 */
-#define RCC_CRRCR_HSI48CAL               RCC_CRRCR_HSI48CAL_Msk                /*!< HSI 48MHz clock Calibration */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-#define RCC_CFGR_MCOSEL_HSI48_Pos            (27U)                             
-#define RCC_CFGR_MCOSEL_HSI48_Msk            (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
-#define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCOSEL_HSI48_Msk         /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE_Pos          (6U) 
-#define RCC_CIER_HSI48RDYIE_Msk          (0x1UL << RCC_CIER_HSI48RDYIE_Pos)     /*!< 0x00000040 */
-#define RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE_Msk               /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF_Pos           (6U) 
-#define RCC_CIFR_HSI48RDYF_Msk           (0x1UL << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000040 */
-#define RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF_Msk                /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC_Pos           (6U) 
-#define RCC_CICR_HSI48RDYC_Msk           (0x1UL << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000040 */
-#define RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC_Msk                /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST_Pos           (16U)
-#define RCC_AHBRSTR_TSCRST_Msk           (0x1UL << RCC_AHBRSTR_TSCRST_Pos)      /*!< 0x00010000 */
-#define RCC_AHBRSTR_TSCRST               RCC_AHBRSTR_TSCRST_Msk                /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST_Pos           (20U)
-#define RCC_AHBRSTR_RNGRST_Msk           (0x1UL << RCC_AHBRSTR_RNGRST_Pos)      /*!< 0x00100000 */
-#define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk                /*!< RNG reset */
-#define RCC_AHBRSTR_CRYPRST_Pos          (24U)
-#define RCC_AHBRSTR_CRYPRST_Msk          (0x1UL << RCC_AHBRSTR_CRYPRST_Pos)     /*!< 0x01000000 */
-#define RCC_AHBRSTR_CRYPRST              RCC_AHBRSTR_CRYPRST_Msk               /*!< Crypto reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1UL << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos          (23U)
-#define RCC_APB1RSTR_USBRST_Msk          (0x1UL << RCC_APB1RSTR_USBRST_Pos)     /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST              RCC_APB1RSTR_USBRST_Msk               /*!< USB reset */
-#define RCC_APB1RSTR_CRSRST_Pos          (27U)
-#define RCC_APB1RSTR_CRSRST_Msk          (0x1UL << RCC_APB1RSTR_CRSRST_Pos)     /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST              RCC_APB1RSTR_CRSRST_Msk               /*!< CRS reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_DACRST_Pos          (29U)
-#define RCC_APB1RSTR_DACRST_Msk          (0x1UL << RCC_APB1RSTR_DACRST_Pos)     /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST              RCC_APB1RSTR_DACRST_Msk               /*!< DAC reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN_Pos             (16U)
-#define RCC_AHBENR_TSCEN_Msk             (0x1UL << RCC_AHBENR_TSCEN_Pos)        /*!< 0x00010000 */
-#define RCC_AHBENR_TSCEN                 RCC_AHBENR_TSCEN_Msk                  /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN_Pos             (20U)
-#define RCC_AHBENR_RNGEN_Msk             (0x1UL << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00100000 */
-#define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk                  /*!< RNG clock enable */
-#define RCC_AHBENR_CRYPEN_Pos            (24U)
-#define RCC_AHBENR_CRYPEN_Msk            (0x1UL << RCC_AHBENR_CRYPEN_Pos)       /*!< 0x01000000 */
-#define RCC_AHBENR_CRYPEN                RCC_AHBENR_CRYPEN_Msk                 /*!< Crypto clock enable*/
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)
-#define RCC_APB2ENR_USART1EN_Msk         (0x1UL << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U) 
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1UL << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1UL << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1UL << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos            (23U)
-#define RCC_APB1ENR_USBEN_Msk            (0x1UL << RCC_APB1ENR_USBEN_Pos)       /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                RCC_APB1ENR_USBEN_Msk                 /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN_Pos            (27U)
-#define RCC_APB1ENR_CRSEN_Msk            (0x1UL << RCC_APB1ENR_CRSEN_Pos)       /*!< 0x08000000 */
-#define RCC_APB1ENR_CRSEN                RCC_APB1ENR_CRSEN_Msk                 /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN_Pos            (29U)
-#define RCC_APB1ENR_DACEN_Msk            (0x1UL << RCC_APB1ENR_DACEN_Pos)       /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                RCC_APB1ENR_DACEN_Msk                 /*!< DAC clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN_Pos         (16U)
-#define RCC_AHBSMENR_TSCSMEN_Msk         (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos)    /*!< 0x00010000 */
-#define RCC_AHBSMENR_TSCSMEN             RCC_AHBSMENR_TSCSMEN_Msk              /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN_Pos         (20U)
-#define RCC_AHBSMENR_RNGSMEN_Msk         (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00100000 */
-#define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk              /*!< RNG clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRYPSMEN_Pos        (24U)
-#define RCC_AHBSMENR_CRYPSMEN_Msk        (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos)   /*!< 0x01000000 */
-#define RCC_AHBSMENR_CRYPSMEN            RCC_AHBSMENR_CRYPSMEN_Msk             /*!< Crypto clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U) 
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN_Pos        (23U)
-#define RCC_APB1SMENR_USBSMEN_Msk        (0x1UL << RCC_APB1SMENR_USBSMEN_Pos)   /*!< 0x00800000 */
-#define RCC_APB1SMENR_USBSMEN            RCC_APB1SMENR_USBSMEN_Msk             /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN_Pos        (27U)
-#define RCC_APB1SMENR_CRSSMEN_Msk        (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos)   /*!< 0x08000000 */
-#define RCC_APB1SMENR_CRSSMEN            RCC_APB1SMENR_CRSSMEN_Msk             /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN_Pos        (29U)
-#define RCC_APB1SMENR_DACSMEN_Msk        (0x1UL << RCC_APB1SMENR_DACSMEN_Pos)   /*!< 0x20000000 */
-#define RCC_APB1SMENR_DACSMEN            RCC_APB1SMENR_DACSMEN_Msk             /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U) 
-#define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*!< HSI48 Clock source selection */ 
-#define RCC_CCIPR_HSI48SEL_Pos           (26U)
-#define RCC_CCIPR_HSI48SEL_Msk           (0x1UL << RCC_CCIPR_HSI48SEL_Pos)      /*!< 0x04000000 */
-#define RCC_CCIPR_HSI48SEL               RCC_CCIPR_HSI48SEL_Msk                /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Legacy defines */
-#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos    (2U)              
-#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
-#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
-#define RNG_CR_IE_Pos       (3U)              
-#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
-#define RNG_CR_IE           RNG_CR_IE_Msk                                      
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)              
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
-#define RNG_SR_CECS_Pos     (1U)              
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
-#define RNG_SR_SECS_Pos     (2U)              
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
-#define RNG_SR_CEIS_Pos     (5U)              
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
-#define RNG_SR_SEIS_Pos     (6U)              
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)      
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)      
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)      
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)      
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)      
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)      
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)     
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)     
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)      
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)      
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)      
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48_Pos             (13U)                         
-#define SYSCFG_CFGR3_ENREF_HSI48_Msk             (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR3_ENREF_HSI48                 SYSCFG_CFGR3_ENREF_HSI48_Msk  /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
-#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_REF_HSI48_RDYF           SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE_Pos          (0U)         
-#define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
-#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
-#define TSC_CR_START_Pos         (1U)         
-#define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
-#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
-#define TSC_CR_AM_Pos            (2U)         
-#define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
-#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL_Pos       (3U)         
-#define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
-#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF_Pos         (4U)         
-#define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
-#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
-
-#define TSC_CR_MCV_Pos           (5U)         
-#define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
-#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
-#define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
-#define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
-
-#define TSC_CR_PGPSC_Pos         (12U)        
-#define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
-#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
-#define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
-#define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
-
-#define TSC_CR_SSPSC_Pos         (15U)        
-#define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
-#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE_Pos           (16U)        
-#define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
-#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD_Pos           (17U)        
-#define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
-#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
-#define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
-#define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
-#define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
-#define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
-#define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
-#define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
-
-#define TSC_CR_CTPL_Pos          (24U)        
-#define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
-#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
-#define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
-#define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
-#define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
-
-#define TSC_CR_CTPH_Pos          (28U)        
-#define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
-#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
-#define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
-#define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
-#define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE_Pos        (0U)         
-#define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
-#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE_Pos        (1U)         
-#define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
-#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC_Pos        (0U)         
-#define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
-#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC_Pos        (1U)         
-#define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
-#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF_Pos         (0U)         
-#define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
-#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
-#define TSC_ISR_MCEF_Pos         (1U)         
-#define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
-#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1_Pos     (0U)         
-#define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2_Pos     (1U)         
-#define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3_Pos     (2U)         
-#define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4_Pos     (3U)         
-#define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1_Pos     (4U)         
-#define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2_Pos     (5U)         
-#define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3_Pos     (6U)         
-#define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4_Pos     (7U)         
-#define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1_Pos     (8U)         
-#define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2_Pos     (9U)         
-#define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3_Pos     (10U)        
-#define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4_Pos     (11U)        
-#define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1_Pos     (12U)        
-#define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2_Pos     (13U)        
-#define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3_Pos     (14U)        
-#define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4_Pos     (15U)        
-#define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1_Pos     (16U)        
-#define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2_Pos     (17U)        
-#define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3_Pos     (18U)        
-#define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4_Pos     (19U)        
-#define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1_Pos     (20U)        
-#define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2_Pos     (21U)        
-#define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3_Pos     (22U)        
-#define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4_Pos     (23U)        
-#define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1_Pos     (24U)        
-#define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2_Pos     (25U)        
-#define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3_Pos     (26U)        
-#define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4_Pos     (27U)        
-#define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1_Pos     (28U)        
-#define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2_Pos     (29U)        
-#define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3_Pos     (30U)        
-#define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4_Pos     (31U)        
-#define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1_Pos    (0U)         
-#define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
-#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2_Pos    (1U)         
-#define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
-#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3_Pos    (2U)         
-#define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
-#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4_Pos    (3U)         
-#define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
-#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1_Pos    (4U)         
-#define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
-#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2_Pos    (5U)         
-#define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
-#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3_Pos    (6U)         
-#define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
-#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4_Pos    (7U)         
-#define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
-#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1_Pos    (8U)         
-#define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
-#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2_Pos    (9U)         
-#define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
-#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3_Pos    (10U)        
-#define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
-#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4_Pos    (11U)        
-#define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
-#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1_Pos    (12U)        
-#define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
-#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2_Pos    (13U)        
-#define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
-#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3_Pos    (14U)        
-#define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
-#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4_Pos    (15U)        
-#define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
-#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1_Pos    (16U)        
-#define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
-#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2_Pos    (17U)        
-#define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
-#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3_Pos    (18U)        
-#define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
-#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4_Pos    (19U)        
-#define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
-#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1_Pos    (20U)        
-#define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
-#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2_Pos    (21U)        
-#define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
-#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3_Pos    (22U)        
-#define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
-#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4_Pos    (23U)        
-#define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
-#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1_Pos    (24U)        
-#define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
-#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2_Pos    (25U)        
-#define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
-#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3_Pos    (26U)        
-#define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
-#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4_Pos    (27U)        
-#define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
-#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1_Pos    (28U)        
-#define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
-#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2_Pos    (29U)        
-#define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
-#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3_Pos    (30U)        
-#define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
-#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4_Pos    (31U)        
-#define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
-#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1_Pos     (0U)         
-#define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2_Pos     (1U)         
-#define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3_Pos     (2U)         
-#define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4_Pos     (3U)         
-#define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1_Pos     (4U)         
-#define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2_Pos     (5U)         
-#define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3_Pos     (6U)         
-#define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4_Pos     (7U)         
-#define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1_Pos     (8U)         
-#define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2_Pos     (9U)         
-#define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3_Pos     (10U)        
-#define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4_Pos     (11U)        
-#define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1_Pos     (12U)        
-#define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2_Pos     (13U)        
-#define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3_Pos     (14U)        
-#define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4_Pos     (15U)        
-#define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1_Pos     (16U)        
-#define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2_Pos     (17U)        
-#define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3_Pos     (18U)        
-#define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4_Pos     (19U)        
-#define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1_Pos     (20U)        
-#define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2_Pos     (21U)        
-#define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3_Pos     (22U)        
-#define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4_Pos     (23U)        
-#define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1_Pos     (24U)        
-#define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2_Pos     (25U)        
-#define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3_Pos     (26U)        
-#define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4_Pos     (27U)        
-#define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1_Pos     (28U)        
-#define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2_Pos     (29U)        
-#define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3_Pos     (30U)        
-#define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4_Pos     (31U)        
-#define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1_Pos     (0U)         
-#define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2_Pos     (1U)         
-#define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3_Pos     (2U)         
-#define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4_Pos     (3U)         
-#define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1_Pos     (4U)         
-#define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2_Pos     (5U)         
-#define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3_Pos     (6U)         
-#define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4_Pos     (7U)         
-#define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1_Pos     (8U)         
-#define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2_Pos     (9U)         
-#define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3_Pos     (10U)        
-#define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4_Pos     (11U)        
-#define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1_Pos     (12U)        
-#define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2_Pos     (13U)        
-#define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3_Pos     (14U)        
-#define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4_Pos     (15U)        
-#define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1_Pos     (16U)        
-#define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2_Pos     (17U)        
-#define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3_Pos     (18U)        
-#define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4_Pos     (19U)        
-#define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1_Pos     (20U)        
-#define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2_Pos     (21U)        
-#define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3_Pos     (22U)        
-#define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4_Pos     (23U)        
-#define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1_Pos     (24U)        
-#define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2_Pos     (25U)        
-#define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3_Pos     (26U)        
-#define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4_Pos     (27U)        
-#define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1_Pos     (28U)        
-#define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2_Pos     (29U)        
-#define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3_Pos     (30U)        
-#define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4_Pos     (31U)        
-#define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E_Pos       (0U)         
-#define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
-#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E_Pos       (1U)         
-#define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
-#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E_Pos       (2U)         
-#define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
-#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E_Pos       (3U)         
-#define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
-#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E_Pos       (4U)         
-#define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
-#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E_Pos       (5U)         
-#define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
-#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E_Pos       (6U)         
-#define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
-#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E_Pos       (7U)         
-#define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
-#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S_Pos       (16U)        
-#define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
-#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S_Pos       (17U)        
-#define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
-#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S_Pos       (18U)        
-#define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
-#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S_Pos       (19U)        
-#define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
-#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S_Pos       (20U)        
-#define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
-#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S_Pos       (21U)        
-#define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
-#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S_Pos       (22U)        
-#define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
-#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S_Pos       (23U)        
-#define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
-#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT_Pos       (0U)         
-#define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
-#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         USB Device General registers                       */
-/*                                                                            */
-/******************************************************************************/
-#define USB_BASE                              (0x40005C00U)                    /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR_Pos           (13U)       
-#define USB_PMAADDR_Msk           (0x20003UL << USB_PMAADDR_Pos)                /*!< 0x40006000 */
-#define USB_PMAADDR               USB_PMAADDR_Msk                              /*!< USB_IP Packet Memory Area base address */
-                                             
-#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
-#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
-#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
-#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
-#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
-#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
-#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
-
-/****************************  ISTR interrupt events  *************************/
-#define USB_ISTR_CTR                          ((uint16_t)0x8000U)              /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR                       ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR                          ((uint16_t)0x2000U)              /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP                         ((uint16_t)0x1000U)              /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP                         ((uint16_t)0x0800U)              /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET                        ((uint16_t)0x0400U)              /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF                          ((uint16_t)0x0200U)              /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF                         ((uint16_t)0x0100U)              /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ                        ((uint16_t)0x0080U)              /*!< LPM L1 state request  */
-#define USB_ISTR_DIR                          ((uint16_t)0x0010U)              /*!< DIRection of transaction (read-only bit)  */
-#define USB_ISTR_EP_ID                        ((uint16_t)0x000FU)              /*!< EndPoint IDentifier (read-only bit)  */
-
-#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
-#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
-#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
-#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
-#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
-#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
-#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
-#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
-/*************************  CNTR control register bits definitions  ***********/
-#define USB_CNTR_CTRM                         ((uint16_t)0x8000U)              /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM                      ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM                         ((uint16_t)0x2000U)              /*!< ERRor Mask */
-#define USB_CNTR_WKUPM                        ((uint16_t)0x1000U)              /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM                        ((uint16_t)0x0800U)              /*!< SUSPend Mask */
-#define USB_CNTR_RESETM                       ((uint16_t)0x0400U)              /*!< RESET Mask   */
-#define USB_CNTR_SOFM                         ((uint16_t)0x0200U)              /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM                        ((uint16_t)0x0100U)              /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM                       ((uint16_t)0x0080U)              /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME                     ((uint16_t)0x0020U)              /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME                       ((uint16_t)0x0010U)              /*!< RESUME request */
-#define USB_CNTR_FSUSP                        ((uint16_t)0x0008U)              /*!< Force SUSPend */
-#define USB_CNTR_LPMODE                       ((uint16_t)0x0004U)              /*!< Low-power MODE */
-#define USB_CNTR_PDWN                         ((uint16_t)0x0002U)              /*!< Power DoWN */
-#define USB_CNTR_FRES                         ((uint16_t)0x0001U)              /*!< Force USB RESet */
-/*************************  BCDR control register bits definitions  ***********/
-#define USB_BCDR_DPPU                         ((uint16_t)0x8000U)              /*!< DP Pull-up Enable */  
-#define USB_BCDR_PS2DET                       ((uint16_t)0x0080U)              /*!< PS2 port or proprietary charger detected */  
-#define USB_BCDR_SDET                         ((uint16_t)0x0040U)              /*!< Secondary detection (SD) status */  
-#define USB_BCDR_PDET                         ((uint16_t)0x0020U)              /*!< Primary detection (PD) status */ 
-#define USB_BCDR_DCDET                        ((uint16_t)0x0010U)              /*!< Data contact detection (DCD) status */ 
-#define USB_BCDR_SDEN                         ((uint16_t)0x0008U)              /*!< Secondary detection (SD) mode enable */ 
-#define USB_BCDR_PDEN                         ((uint16_t)0x0004U)              /*!< Primary detection (PD) mode enable */  
-#define USB_BCDR_DCDEN                        ((uint16_t)0x0002U)              /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN                        ((uint16_t)0x0001U)              /*!< Battery charging detector (BCD) enable */
-/***************************  LPM register bits definitions  ******************/
-#define USB_LPMCSR_BESL                       ((uint16_t)0x00F0U)              /*!< BESL value received with last ACKed LPM Token  */ 
-#define USB_LPMCSR_REMWAKE                    ((uint16_t)0x0008U)              /*!< bRemoteWake value received with last ACKed LPM Token */ 
-#define USB_LPMCSR_LPMACK                     ((uint16_t)0x0002U)              /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN                      ((uint16_t)0x0001U)              /*!< LPM support enable  */
-/********************  FNR Frame Number Register bit definitions   ************/
-#define USB_FNR_RXDP                          ((uint16_t)0x8000U)              /*!< status of D+ data line */
-#define USB_FNR_RXDM                          ((uint16_t)0x4000U)              /*!< status of D- data line */
-#define USB_FNR_LCK                           ((uint16_t)0x2000U)              /*!< LoCKed */
-#define USB_FNR_LSOF                          ((uint16_t)0x1800U)              /*!< Lost SOF */
-#define USB_FNR_FN                            ((uint16_t)0x07FFU)              /*!< Frame Number */
-/********************  DADDR Device ADDRess bit definitions    ****************/
-#define USB_DADDR_EF                          ((uint8_t)0x80U)                 /*!< USB device address Enable Function */
-#define USB_DADDR_ADD                         ((uint8_t)0x7FU)                 /*!< USB device address */
-/******************************  Endpoint register    *************************/
-#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
-#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
-#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
-#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
-#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
-#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
-#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
-#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
-/* bit positions */ 
-#define USB_EP_CTR_RX                         ((uint16_t)0x8000U)              /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX                        ((uint16_t)0x4000U)              /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT                         ((uint16_t)0x3000U)              /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP                          ((uint16_t)0x0800U)              /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD                        ((uint16_t)0x0600U)              /*!<  EndPoint TYPE */
-#define USB_EP_KIND                           ((uint16_t)0x0100U)              /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX                         ((uint16_t)0x0080U)              /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX                        ((uint16_t)0x0040U)              /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT                         ((uint16_t)0x0030U)              /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD                      ((uint16_t)0x000FU)              /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK                      ((uint16_t)0x0600U)              /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           ((uint16_t)0x0000U)              /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        ((uint16_t)0x0200U)              /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    ((uint16_t)0x0400U)              /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      ((uint16_t)0x0600U)              /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
-                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       ((uint16_t)0x0010U)              /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         ((uint16_t)0x0020U)              /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       ((uint16_t)0x0030U)              /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        ((uint16_t)0x0010U)              /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        ((uint16_t)0x0020U)              /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       ((uint16_t)0x1000U)              /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         ((uint16_t)0x2000U)              /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       ((uint16_t)0x3000U)              /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        ((uint16_t)0x1000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        ((uint16_t)0x2000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* AES Instances ********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM6))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************************** TSC Instances *********************************/
-#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/******************************* USB Instances *******************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define LPUART1_IRQn                   AES_RNG_LPUART1_IRQn
-#define AES_LPUART1_IRQn               AES_RNG_LPUART1_IRQn
-#define RNG_LPUART1_IRQn               AES_RNG_LPUART1_IRQn
-#define TIM6_IRQn                      TIM6_DAC_IRQn
-#define RCC_IRQn                       RCC_CRS_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             AES_RNG_LPUART1_IRQHandler
-#define RNG_LPUART1_IRQHandler         AES_RNG_LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         AES_RNG_LPUART1_IRQHandler
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
-#define RCC_IRQHandler                 RCC_CRS_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L062xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h
deleted file mode 100644
index 5c5a9c1277..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h
+++ /dev/null
@@ -1,7651 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l063xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l063xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l063xx
-  * @{
-  */
-    
-#ifndef __STM32L063xx_H
-#define __STM32L063xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1U /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l063xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  AES_RNG_LPUART1_IRQn        = 29,     /*!< AES and RNG and LPUART1 Interrupts                      */
-  LCD_IRQn                    = 30,     /*!< LCD Interrupt                                           */
-  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;      /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;      /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;    /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;   /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;   /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;   /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;   /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;   /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;    /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;    /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;    /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;    /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Clock Recovery System 
-  */
-
-typedef struct 
-{
-__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
-__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
-__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
-__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
-} CRS_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  uint32_t      RESERVED0[6];  /*!<                                                                     0x14-0x28 */
-  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  uint32_t      RESERVED1;     /*!<                                                                          0x30 */
-  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Random numbers generator
-  */
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
-  __IO uint16_t RESERVEDD;       /*!< Reserved */       
-  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
-  __IO uint16_t RESERVEDE;       /*!< Reserved */       
-} USB_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        (0x080807FFUL) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
-#define LCD_BASE              (APBPERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
-#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000UL)
-#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000UL)
-#define AES_BASE              (AHBPERIPH_BASE + 0x00006000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define CRS                 ((CRS_TypeDef *) CRS_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define AES                 ((AES_TypeDef *) AES_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define USB                 ((USB_TypeDef *) USB_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16_Pos     (16U)      
-#define ADC_CHSELR_CHSEL16_Msk     (0x1UL << ADC_CHSELR_CHSEL16_Pos)            /*!< 0x00010000 */
-#define ADC_CHSELR_CHSEL16         ADC_CHSELR_CHSEL16_Msk                      /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_VLCDEN_Pos         (24U)      
-#define ADC_CCR_VLCDEN_Msk         (0x1UL << ADC_CCR_VLCDEN_Pos)                /*!< 0x01000000 */
-#define ADC_CCR_VLCDEN             ADC_CCR_VLCDEN_Msk                          /*!< Voltage LCD enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos            (0U)         
-#define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                       /*!< 0x00000001 */
-#define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos      (1U)         
-#define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000006 */
-#define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
-#define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos          (3U)         
-#define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                     /*!< 0x00000018 */
-#define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                     /*!< 0x00000008 */
-#define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                     /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos         (5U)         
-#define AES_CR_CHMOD_Msk         (0x3UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000060 */
-#define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0           (0x1UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000020 */
-#define AES_CR_CHMOD_1           (0x2UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000040 */
-
-#define AES_CR_CCFC_Pos          (7U)         
-#define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                     /*!< 0x00000080 */
-#define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos          (8U)         
-#define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                     /*!< 0x00000100 */
-#define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
-#define AES_CR_CCIE_Pos          (9U)         
-#define AES_CR_CCIE_Msk          (0x1UL << AES_CR_CCIE_Pos)                     /*!< 0x00000200 */
-#define AES_CR_CCIE              AES_CR_CCIE_Msk                               /*!< Computation Complete Interrupt Enable */
-#define AES_CR_ERRIE_Pos         (10U)        
-#define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                    /*!< 0x00000400 */
-#define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos       (11U)        
-#define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                  /*!< 0x00000800 */
-#define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< DMA ENable managing the data input phase */
-#define AES_CR_DMAOUTEN_Pos      (12U)        
-#define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                 /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos           (0U)         
-#define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                      /*!< 0x00000001 */
-#define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos         (1U)         
-#define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                    /*!< 0x00000002 */
-#define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos         (2U)         
-#define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                    /*!< 0x00000004 */
-#define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos             (0U)         
-#define AES_DINR_Msk             (0xFFFFUL << AES_DINR_Pos)                     /*!< 0x0000FFFF */
-#define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos            (0U)         
-#define AES_DOUTR_Msk            (0xFFFFUL << AES_DOUTR_Pos)                    /*!< 0x0000FFFF */
-#define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos            (0U)         
-#define AES_KEYR0_Msk            (0xFFFFUL << AES_KEYR0_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos            (0U)         
-#define AES_KEYR1_Msk            (0xFFFFUL << AES_KEYR1_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos            (0U)         
-#define AES_KEYR2_Msk            (0xFFFFUL << AES_KEYR2_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos            (0U)         
-#define AES_KEYR3_Msk            (0xFFFFUL << AES_KEYR3_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define AES_IVR0_Pos             (0U)         
-#define AES_IVR0_Msk             (0xFFFFUL << AES_IVR0_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define AES_IVR1_Pos             (0U)         
-#define AES_IVR1_Msk             (0xFFFFUL << AES_IVR1_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define AES_IVR2_Pos             (0U)         
-#define AES_IVR2_Msk             (0xFFFFUL << AES_IVR2_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define AES_IVR3_Pos             (0U)         
-#define AES_IVR3_Msk             (0xFFFFUL << AES_IVR3_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRS Clock Recovery System                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRS_CR register  *********************/
-#define CRS_CR_SYNCOKIE_Pos       (0U)        
-#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
-#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
-#define CRS_CR_SYNCWARNIE_Pos     (1U)        
-#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
-#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
-#define CRS_CR_ERRIE_Pos          (2U)        
-#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
-#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
-#define CRS_CR_ESYNCIE_Pos        (3U)        
-#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
-#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN_Pos            (5U)        
-#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
-#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
-#define CRS_CR_AUTOTRIMEN_Pos     (6U)        
-#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
-#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
-#define CRS_CR_SWSYNC_Pos         (7U)        
-#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
-#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
-#define CRS_CR_TRIM_Pos           (8U)        
-#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
-#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
-
-/*******************  Bit definition for CRS_CFGR register  *********************/
-#define CRS_CFGR_RELOAD_Pos       (0U)        
-#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
-#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
-#define CRS_CFGR_FELIM_Pos        (16U)       
-#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
-#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
-
-#define CRS_CFGR_SYNCDIV_Pos      (24U)       
-#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
-#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
-#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
-#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
-#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
-
-#define CRS_CFGR_SYNCSRC_Pos      (28U)       
-#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
-#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
-#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
-#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
-
-#define CRS_CFGR_SYNCPOL_Pos      (31U)       
-#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
-#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
-  
-/*******************  Bit definition for CRS_ISR register  *********************/
-#define CRS_ISR_SYNCOKF_Pos       (0U)        
-#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
-#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
-#define CRS_ISR_SYNCWARNF_Pos     (1U)        
-#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
-#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
-#define CRS_ISR_ERRF_Pos          (2U)        
-#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
-#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
-#define CRS_ISR_ESYNCF_Pos        (3U)        
-#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
-#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
-#define CRS_ISR_SYNCERR_Pos       (8U)        
-#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
-#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
-#define CRS_ISR_SYNCMISS_Pos      (9U)        
-#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
-#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
-#define CRS_ISR_TRIMOVF_Pos       (10U)       
-#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
-#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR_Pos         (15U)       
-#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
-#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
-#define CRS_ISR_FECAP_Pos         (16U)       
-#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
-#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
-
-/*******************  Bit definition for CRS_ICR register  *********************/
-#define CRS_ICR_SYNCOKC_Pos       (0U)        
-#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
-#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
-#define CRS_ICR_SYNCWARNC_Pos     (1U)        
-#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
-#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
-#define CRS_ICR_ERRC_Pos          (2U)        
-#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
-#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag             */
-#define CRS_ICR_ESYNCC_Pos        (3U)        
-#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
-#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)      
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos            (1U)      
-#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos             (2U)      
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (3U)      
-#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)      
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)      
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)     
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)     
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)      
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)      
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)      
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)      
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)      
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)     
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos            (0U)      
-#define LCD_CR_LCDEN_Msk            (0x1UL << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
-#define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos             (1U)      
-#define LCD_CR_VSEL_Msk             (0x1UL << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
-#define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos             (2U)      
-#define LCD_CR_DUTY_Msk             (0x7UL << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
-#define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0               (0x1UL << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
-#define LCD_CR_DUTY_1               (0x2UL << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
-#define LCD_CR_DUTY_2               (0x4UL << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos             (5U)      
-#define LCD_CR_BIAS_Msk             (0x3UL << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
-#define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0               (0x1UL << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
-#define LCD_CR_BIAS_1               (0x2UL << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos          (7U)      
-#define LCD_CR_MUX_SEG_Msk          (0x1UL << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
-
-#define LCD_CR_BUFEN_Pos            (8U)
-#define LCD_CR_BUFEN_Msk            (0x1UL << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
-#define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos              (0U)      
-#define LCD_FCR_HD_Msk              (0x1UL << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
-#define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos           (1U)      
-#define LCD_FCR_SOFIE_Msk           (0x1UL << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
-#define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos           (3U)      
-#define LCD_FCR_UDDIE_Msk           (0x1UL << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
-#define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos             (4U)      
-#define LCD_FCR_PON_Msk             (0x7UL << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
-#define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0               (0x1UL << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
-#define LCD_FCR_PON_1               (0x2UL << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
-#define LCD_FCR_PON_2               (0x4UL << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos            (7U)      
-#define LCD_FCR_DEAD_Msk            (0x7UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
-#define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0              (0x1UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1              (0x2UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2              (0x4UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos              (10U)     
-#define LCD_FCR_CC_Msk              (0x7UL << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
-#define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0                (0x1UL << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
-#define LCD_FCR_CC_1                (0x2UL << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
-#define LCD_FCR_CC_2                (0x4UL << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos          (13U)     
-#define LCD_FCR_BLINKF_Msk          (0x7UL << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0            (0x1UL << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1            (0x2UL << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2            (0x4UL << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos           (16U)     
-#define LCD_FCR_BLINK_Msk           (0x3UL << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
-#define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0             (0x1UL << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1             (0x2UL << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos             (18U)     
-#define LCD_FCR_DIV_Msk             (0xFUL << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
-#define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos              (22U)     
-#define LCD_FCR_PS_Msk              (0xFUL << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
-#define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos              (0U)      
-#define LCD_SR_ENS_Msk              (0x1UL << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
-#define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos              (1U)      
-#define LCD_SR_SOF_Msk              (0x1UL << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
-#define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos              (2U)      
-#define LCD_SR_UDR_Msk              (0x1UL << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
-#define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos              (3U)      
-#define LCD_SR_UDD_Msk              (0x1UL << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
-#define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos              (4U)      
-#define LCD_SR_RDY_Msk              (0x1UL << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
-#define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos            (5U)      
-#define LCD_SR_FCRSR_Msk            (0x1UL << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
-#define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos            (1U)      
-#define LCD_CLR_SOFC_Msk            (0x1UL << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
-#define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos            (3U)      
-#define LCD_CLR_UDDC_Msk            (0x1UL << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
-#define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos    (0U)      
-#define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)             
-#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)             
-#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)             
-#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)             
-#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)             
-#define FW_VDSSA_ADD_Msk     (0x3FFUL << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)             
-#define FW_VDSL_LENG_Msk     (0x3FFUL << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)             
-#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)             
-#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)             
-#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC/LCD prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CRRCR register  *****************/
-#define RCC_CRRCR_HSI48ON_Pos            (0U) 
-#define RCC_CRRCR_HSI48ON_Msk            (0x1UL << RCC_CRRCR_HSI48ON_Pos)       /*!< 0x00000001 */
-#define RCC_CRRCR_HSI48ON                RCC_CRRCR_HSI48ON_Msk                 /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY_Pos           (1U) 
-#define RCC_CRRCR_HSI48RDY_Msk           (0x1UL << RCC_CRRCR_HSI48RDY_Pos)      /*!< 0x00000002 */
-#define RCC_CRRCR_HSI48RDY               RCC_CRRCR_HSI48RDY_Msk                /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48CAL_Pos           (8U) 
-#define RCC_CRRCR_HSI48CAL_Msk           (0xFFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF00 */
-#define RCC_CRRCR_HSI48CAL               RCC_CRRCR_HSI48CAL_Msk                /*!< HSI 48MHz clock Calibration */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-#define RCC_CFGR_MCOSEL_HSI48_Pos            (27U)                             
-#define RCC_CFGR_MCOSEL_HSI48_Msk            (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
-#define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCOSEL_HSI48_Msk         /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE_Pos          (6U) 
-#define RCC_CIER_HSI48RDYIE_Msk          (0x1UL << RCC_CIER_HSI48RDYIE_Pos)     /*!< 0x00000040 */
-#define RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE_Msk               /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF_Pos           (6U) 
-#define RCC_CIFR_HSI48RDYF_Msk           (0x1UL << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000040 */
-#define RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF_Msk                /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC_Pos           (6U) 
-#define RCC_CICR_HSI48RDYC_Msk           (0x1UL << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000040 */
-#define RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC_Msk                /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST_Pos           (16U)
-#define RCC_AHBRSTR_TSCRST_Msk           (0x1UL << RCC_AHBRSTR_TSCRST_Pos)      /*!< 0x00010000 */
-#define RCC_AHBRSTR_TSCRST               RCC_AHBRSTR_TSCRST_Msk                /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST_Pos           (20U)
-#define RCC_AHBRSTR_RNGRST_Msk           (0x1UL << RCC_AHBRSTR_RNGRST_Pos)      /*!< 0x00100000 */
-#define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk                /*!< RNG reset */
-#define RCC_AHBRSTR_CRYPRST_Pos          (24U)
-#define RCC_AHBRSTR_CRYPRST_Msk          (0x1UL << RCC_AHBRSTR_CRYPRST_Pos)     /*!< 0x01000000 */
-#define RCC_AHBRSTR_CRYPRST              RCC_AHBRSTR_CRYPRST_Msk               /*!< Crypto reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1UL << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 reset */
-#define RCC_APB1RSTR_LCDRST_Pos          (9U)
-#define RCC_APB1RSTR_LCDRST_Msk          (0x1UL << RCC_APB1RSTR_LCDRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST              RCC_APB1RSTR_LCDRST_Msk               /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos          (23U)
-#define RCC_APB1RSTR_USBRST_Msk          (0x1UL << RCC_APB1RSTR_USBRST_Pos)     /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST              RCC_APB1RSTR_USBRST_Msk               /*!< USB reset */
-#define RCC_APB1RSTR_CRSRST_Pos          (27U)
-#define RCC_APB1RSTR_CRSRST_Msk          (0x1UL << RCC_APB1RSTR_CRSRST_Pos)     /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST              RCC_APB1RSTR_CRSRST_Msk               /*!< CRS reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_DACRST_Pos          (29U)
-#define RCC_APB1RSTR_DACRST_Msk          (0x1UL << RCC_APB1RSTR_DACRST_Pos)     /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST              RCC_APB1RSTR_DACRST_Msk               /*!< DAC reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN_Pos             (16U)
-#define RCC_AHBENR_TSCEN_Msk             (0x1UL << RCC_AHBENR_TSCEN_Pos)        /*!< 0x00010000 */
-#define RCC_AHBENR_TSCEN                 RCC_AHBENR_TSCEN_Msk                  /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN_Pos             (20U)
-#define RCC_AHBENR_RNGEN_Msk             (0x1UL << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00100000 */
-#define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk                  /*!< RNG clock enable */
-#define RCC_AHBENR_CRYPEN_Pos            (24U)
-#define RCC_AHBENR_CRYPEN_Msk            (0x1UL << RCC_AHBENR_CRYPEN_Pos)       /*!< 0x01000000 */
-#define RCC_AHBENR_CRYPEN                RCC_AHBENR_CRYPEN_Msk                 /*!< Crypto clock enable*/
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)
-#define RCC_APB2ENR_USART1EN_Msk         (0x1UL << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U) 
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1UL << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos            (9U) 
-#define RCC_APB1ENR_LCDEN_Msk            (0x1UL << RCC_APB1ENR_LCDEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                RCC_APB1ENR_LCDEN_Msk                 /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1UL << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1UL << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos            (23U)
-#define RCC_APB1ENR_USBEN_Msk            (0x1UL << RCC_APB1ENR_USBEN_Pos)       /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                RCC_APB1ENR_USBEN_Msk                 /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN_Pos            (27U)
-#define RCC_APB1ENR_CRSEN_Msk            (0x1UL << RCC_APB1ENR_CRSEN_Pos)       /*!< 0x08000000 */
-#define RCC_APB1ENR_CRSEN                RCC_APB1ENR_CRSEN_Msk                 /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN_Pos            (29U)
-#define RCC_APB1ENR_DACEN_Msk            (0x1UL << RCC_APB1ENR_DACEN_Pos)       /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                RCC_APB1ENR_DACEN_Msk                 /*!< DAC clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN_Pos         (16U)
-#define RCC_AHBSMENR_TSCSMEN_Msk         (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos)    /*!< 0x00010000 */
-#define RCC_AHBSMENR_TSCSMEN             RCC_AHBSMENR_TSCSMEN_Msk              /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN_Pos         (20U)
-#define RCC_AHBSMENR_RNGSMEN_Msk         (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00100000 */
-#define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk              /*!< RNG clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRYPSMEN_Pos        (24U)
-#define RCC_AHBSMENR_CRYPSMEN_Msk        (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos)   /*!< 0x01000000 */
-#define RCC_AHBSMENR_CRYPSMEN            RCC_AHBSMENR_CRYPSMEN_Msk             /*!< Crypto clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U) 
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LCDSMEN_Pos        (9U) 
-#define RCC_APB1SMENR_LCDSMEN_Msk        (0x1UL << RCC_APB1SMENR_LCDSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB1SMENR_LCDSMEN            RCC_APB1SMENR_LCDSMEN_Msk             /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN_Pos        (23U)
-#define RCC_APB1SMENR_USBSMEN_Msk        (0x1UL << RCC_APB1SMENR_USBSMEN_Pos)   /*!< 0x00800000 */
-#define RCC_APB1SMENR_USBSMEN            RCC_APB1SMENR_USBSMEN_Msk             /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN_Pos        (27U)
-#define RCC_APB1SMENR_CRSSMEN_Msk        (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos)   /*!< 0x08000000 */
-#define RCC_APB1SMENR_CRSSMEN            RCC_APB1SMENR_CRSSMEN_Msk             /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN_Pos        (29U)
-#define RCC_APB1SMENR_DACSMEN_Msk        (0x1UL << RCC_APB1SMENR_DACSMEN_Pos)   /*!< 0x20000000 */
-#define RCC_APB1SMENR_DACSMEN            RCC_APB1SMENR_DACSMEN_Msk             /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U) 
-#define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*!< HSI48 Clock source selection */ 
-#define RCC_CCIPR_HSI48SEL_Pos           (26U)
-#define RCC_CCIPR_HSI48SEL_Msk           (0x1UL << RCC_CCIPR_HSI48SEL_Pos)      /*!< 0x04000000 */
-#define RCC_CCIPR_HSI48SEL               RCC_CCIPR_HSI48SEL_Msk                /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Legacy defines */
-#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos    (2U)              
-#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
-#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
-#define RNG_CR_IE_Pos       (3U)              
-#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
-#define RNG_CR_IE           RNG_CR_IE_Msk                                      
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)              
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
-#define RNG_SR_CECS_Pos     (1U)              
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
-#define RNG_SR_SECS_Pos     (2U)              
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
-#define RNG_SR_CEIS_Pos     (5U)              
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
-#define RNG_SR_SEIS_Pos     (6U)              
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)      
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)      
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)      
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)      
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)      
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)      
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)     
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)     
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)      
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)      
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)      
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_CAPA_Pos                    (1U)                          
-#define SYSCFG_CFGR2_CAPA_Msk                    (0x7UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x0000000E */
-#define SYSCFG_CFGR2_CAPA                        SYSCFG_CFGR2_CAPA_Msk         /*!< Connection of internal Vlcd rail to external capacitors */
-#define SYSCFG_CFGR2_CAPA_0                      (0x1UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR2_CAPA_1                      (0x2UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000004 */
-#define SYSCFG_CFGR2_CAPA_2                      (0x4UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000008 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48_Pos             (13U)                         
-#define SYSCFG_CFGR3_ENREF_HSI48_Msk             (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR3_ENREF_HSI48                 SYSCFG_CFGR3_ENREF_HSI48_Msk  /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
-#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_REF_HSI48_RDYF           SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE_Pos          (0U)         
-#define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
-#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
-#define TSC_CR_START_Pos         (1U)         
-#define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
-#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
-#define TSC_CR_AM_Pos            (2U)         
-#define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
-#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL_Pos       (3U)         
-#define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
-#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF_Pos         (4U)         
-#define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
-#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
-
-#define TSC_CR_MCV_Pos           (5U)         
-#define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
-#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
-#define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
-#define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
-
-#define TSC_CR_PGPSC_Pos         (12U)        
-#define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
-#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
-#define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
-#define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
-
-#define TSC_CR_SSPSC_Pos         (15U)        
-#define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
-#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE_Pos           (16U)        
-#define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
-#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD_Pos           (17U)        
-#define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
-#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
-#define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
-#define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
-#define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
-#define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
-#define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
-#define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
-
-#define TSC_CR_CTPL_Pos          (24U)        
-#define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
-#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
-#define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
-#define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
-#define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
-
-#define TSC_CR_CTPH_Pos          (28U)        
-#define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
-#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
-#define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
-#define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
-#define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE_Pos        (0U)         
-#define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
-#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE_Pos        (1U)         
-#define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
-#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC_Pos        (0U)         
-#define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
-#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC_Pos        (1U)         
-#define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
-#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF_Pos         (0U)         
-#define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
-#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
-#define TSC_ISR_MCEF_Pos         (1U)         
-#define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
-#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1_Pos     (0U)         
-#define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2_Pos     (1U)         
-#define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3_Pos     (2U)         
-#define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4_Pos     (3U)         
-#define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1_Pos     (4U)         
-#define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2_Pos     (5U)         
-#define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3_Pos     (6U)         
-#define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4_Pos     (7U)         
-#define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1_Pos     (8U)         
-#define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2_Pos     (9U)         
-#define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3_Pos     (10U)        
-#define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4_Pos     (11U)        
-#define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1_Pos     (12U)        
-#define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2_Pos     (13U)        
-#define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3_Pos     (14U)        
-#define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4_Pos     (15U)        
-#define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1_Pos     (16U)        
-#define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2_Pos     (17U)        
-#define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3_Pos     (18U)        
-#define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4_Pos     (19U)        
-#define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1_Pos     (20U)        
-#define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2_Pos     (21U)        
-#define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3_Pos     (22U)        
-#define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4_Pos     (23U)        
-#define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1_Pos     (24U)        
-#define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2_Pos     (25U)        
-#define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3_Pos     (26U)        
-#define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4_Pos     (27U)        
-#define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1_Pos     (28U)        
-#define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2_Pos     (29U)        
-#define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3_Pos     (30U)        
-#define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4_Pos     (31U)        
-#define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1_Pos    (0U)         
-#define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
-#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2_Pos    (1U)         
-#define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
-#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3_Pos    (2U)         
-#define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
-#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4_Pos    (3U)         
-#define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
-#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1_Pos    (4U)         
-#define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
-#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2_Pos    (5U)         
-#define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
-#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3_Pos    (6U)         
-#define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
-#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4_Pos    (7U)         
-#define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
-#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1_Pos    (8U)         
-#define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
-#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2_Pos    (9U)         
-#define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
-#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3_Pos    (10U)        
-#define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
-#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4_Pos    (11U)        
-#define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
-#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1_Pos    (12U)        
-#define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
-#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2_Pos    (13U)        
-#define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
-#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3_Pos    (14U)        
-#define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
-#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4_Pos    (15U)        
-#define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
-#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1_Pos    (16U)        
-#define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
-#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2_Pos    (17U)        
-#define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
-#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3_Pos    (18U)        
-#define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
-#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4_Pos    (19U)        
-#define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
-#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1_Pos    (20U)        
-#define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
-#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2_Pos    (21U)        
-#define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
-#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3_Pos    (22U)        
-#define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
-#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4_Pos    (23U)        
-#define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
-#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1_Pos    (24U)        
-#define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
-#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2_Pos    (25U)        
-#define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
-#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3_Pos    (26U)        
-#define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
-#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4_Pos    (27U)        
-#define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
-#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1_Pos    (28U)        
-#define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
-#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2_Pos    (29U)        
-#define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
-#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3_Pos    (30U)        
-#define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
-#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4_Pos    (31U)        
-#define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
-#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1_Pos     (0U)         
-#define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2_Pos     (1U)         
-#define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3_Pos     (2U)         
-#define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4_Pos     (3U)         
-#define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1_Pos     (4U)         
-#define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2_Pos     (5U)         
-#define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3_Pos     (6U)         
-#define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4_Pos     (7U)         
-#define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1_Pos     (8U)         
-#define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2_Pos     (9U)         
-#define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3_Pos     (10U)        
-#define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4_Pos     (11U)        
-#define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1_Pos     (12U)        
-#define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2_Pos     (13U)        
-#define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3_Pos     (14U)        
-#define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4_Pos     (15U)        
-#define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1_Pos     (16U)        
-#define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2_Pos     (17U)        
-#define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3_Pos     (18U)        
-#define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4_Pos     (19U)        
-#define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1_Pos     (20U)        
-#define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2_Pos     (21U)        
-#define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3_Pos     (22U)        
-#define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4_Pos     (23U)        
-#define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1_Pos     (24U)        
-#define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2_Pos     (25U)        
-#define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3_Pos     (26U)        
-#define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4_Pos     (27U)        
-#define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1_Pos     (28U)        
-#define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2_Pos     (29U)        
-#define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3_Pos     (30U)        
-#define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4_Pos     (31U)        
-#define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1_Pos     (0U)         
-#define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2_Pos     (1U)         
-#define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3_Pos     (2U)         
-#define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4_Pos     (3U)         
-#define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1_Pos     (4U)         
-#define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2_Pos     (5U)         
-#define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3_Pos     (6U)         
-#define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4_Pos     (7U)         
-#define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1_Pos     (8U)         
-#define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2_Pos     (9U)         
-#define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3_Pos     (10U)        
-#define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4_Pos     (11U)        
-#define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1_Pos     (12U)        
-#define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2_Pos     (13U)        
-#define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3_Pos     (14U)        
-#define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4_Pos     (15U)        
-#define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1_Pos     (16U)        
-#define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2_Pos     (17U)        
-#define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3_Pos     (18U)        
-#define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4_Pos     (19U)        
-#define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1_Pos     (20U)        
-#define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2_Pos     (21U)        
-#define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3_Pos     (22U)        
-#define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4_Pos     (23U)        
-#define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1_Pos     (24U)        
-#define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2_Pos     (25U)        
-#define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3_Pos     (26U)        
-#define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4_Pos     (27U)        
-#define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1_Pos     (28U)        
-#define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2_Pos     (29U)        
-#define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3_Pos     (30U)        
-#define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4_Pos     (31U)        
-#define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E_Pos       (0U)         
-#define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
-#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E_Pos       (1U)         
-#define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
-#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E_Pos       (2U)         
-#define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
-#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E_Pos       (3U)         
-#define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
-#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E_Pos       (4U)         
-#define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
-#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E_Pos       (5U)         
-#define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
-#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E_Pos       (6U)         
-#define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
-#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E_Pos       (7U)         
-#define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
-#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S_Pos       (16U)        
-#define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
-#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S_Pos       (17U)        
-#define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
-#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S_Pos       (18U)        
-#define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
-#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S_Pos       (19U)        
-#define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
-#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S_Pos       (20U)        
-#define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
-#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S_Pos       (21U)        
-#define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
-#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S_Pos       (22U)        
-#define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
-#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S_Pos       (23U)        
-#define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
-#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT_Pos       (0U)         
-#define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
-#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         USB Device General registers                       */
-/*                                                                            */
-/******************************************************************************/
-#define USB_BASE                              (0x40005C00U)                    /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR_Pos           (13U)       
-#define USB_PMAADDR_Msk           (0x20003UL << USB_PMAADDR_Pos)                /*!< 0x40006000 */
-#define USB_PMAADDR               USB_PMAADDR_Msk                              /*!< USB_IP Packet Memory Area base address */
-                                             
-#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
-#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
-#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
-#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
-#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
-#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
-#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
-
-/****************************  ISTR interrupt events  *************************/
-#define USB_ISTR_CTR                          ((uint16_t)0x8000U)              /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR                       ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR                          ((uint16_t)0x2000U)              /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP                         ((uint16_t)0x1000U)              /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP                         ((uint16_t)0x0800U)              /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET                        ((uint16_t)0x0400U)              /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF                          ((uint16_t)0x0200U)              /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF                         ((uint16_t)0x0100U)              /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ                        ((uint16_t)0x0080U)              /*!< LPM L1 state request  */
-#define USB_ISTR_DIR                          ((uint16_t)0x0010U)              /*!< DIRection of transaction (read-only bit)  */
-#define USB_ISTR_EP_ID                        ((uint16_t)0x000FU)              /*!< EndPoint IDentifier (read-only bit)  */
-
-#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
-#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
-#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
-#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
-#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
-#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
-#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
-#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
-/*************************  CNTR control register bits definitions  ***********/
-#define USB_CNTR_CTRM                         ((uint16_t)0x8000U)              /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM                      ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM                         ((uint16_t)0x2000U)              /*!< ERRor Mask */
-#define USB_CNTR_WKUPM                        ((uint16_t)0x1000U)              /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM                        ((uint16_t)0x0800U)              /*!< SUSPend Mask */
-#define USB_CNTR_RESETM                       ((uint16_t)0x0400U)              /*!< RESET Mask   */
-#define USB_CNTR_SOFM                         ((uint16_t)0x0200U)              /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM                        ((uint16_t)0x0100U)              /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM                       ((uint16_t)0x0080U)              /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME                     ((uint16_t)0x0020U)              /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME                       ((uint16_t)0x0010U)              /*!< RESUME request */
-#define USB_CNTR_FSUSP                        ((uint16_t)0x0008U)              /*!< Force SUSPend */
-#define USB_CNTR_LPMODE                       ((uint16_t)0x0004U)              /*!< Low-power MODE */
-#define USB_CNTR_PDWN                         ((uint16_t)0x0002U)              /*!< Power DoWN */
-#define USB_CNTR_FRES                         ((uint16_t)0x0001U)              /*!< Force USB RESet */
-/*************************  BCDR control register bits definitions  ***********/
-#define USB_BCDR_DPPU                         ((uint16_t)0x8000U)              /*!< DP Pull-up Enable */  
-#define USB_BCDR_PS2DET                       ((uint16_t)0x0080U)              /*!< PS2 port or proprietary charger detected */  
-#define USB_BCDR_SDET                         ((uint16_t)0x0040U)              /*!< Secondary detection (SD) status */  
-#define USB_BCDR_PDET                         ((uint16_t)0x0020U)              /*!< Primary detection (PD) status */ 
-#define USB_BCDR_DCDET                        ((uint16_t)0x0010U)              /*!< Data contact detection (DCD) status */ 
-#define USB_BCDR_SDEN                         ((uint16_t)0x0008U)              /*!< Secondary detection (SD) mode enable */ 
-#define USB_BCDR_PDEN                         ((uint16_t)0x0004U)              /*!< Primary detection (PD) mode enable */  
-#define USB_BCDR_DCDEN                        ((uint16_t)0x0002U)              /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN                        ((uint16_t)0x0001U)              /*!< Battery charging detector (BCD) enable */
-/***************************  LPM register bits definitions  ******************/
-#define USB_LPMCSR_BESL                       ((uint16_t)0x00F0U)              /*!< BESL value received with last ACKed LPM Token  */ 
-#define USB_LPMCSR_REMWAKE                    ((uint16_t)0x0008U)              /*!< bRemoteWake value received with last ACKed LPM Token */ 
-#define USB_LPMCSR_LPMACK                     ((uint16_t)0x0002U)              /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN                      ((uint16_t)0x0001U)              /*!< LPM support enable  */
-/********************  FNR Frame Number Register bit definitions   ************/
-#define USB_FNR_RXDP                          ((uint16_t)0x8000U)              /*!< status of D+ data line */
-#define USB_FNR_RXDM                          ((uint16_t)0x4000U)              /*!< status of D- data line */
-#define USB_FNR_LCK                           ((uint16_t)0x2000U)              /*!< LoCKed */
-#define USB_FNR_LSOF                          ((uint16_t)0x1800U)              /*!< Lost SOF */
-#define USB_FNR_FN                            ((uint16_t)0x07FFU)              /*!< Frame Number */
-/********************  DADDR Device ADDRess bit definitions    ****************/
-#define USB_DADDR_EF                          ((uint8_t)0x80U)                 /*!< USB device address Enable Function */
-#define USB_DADDR_ADD                         ((uint8_t)0x7FU)                 /*!< USB device address */
-/******************************  Endpoint register    *************************/
-#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
-#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
-#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
-#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
-#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
-#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
-#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
-#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
-/* bit positions */ 
-#define USB_EP_CTR_RX                         ((uint16_t)0x8000U)              /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX                        ((uint16_t)0x4000U)              /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT                         ((uint16_t)0x3000U)              /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP                          ((uint16_t)0x0800U)              /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD                        ((uint16_t)0x0600U)              /*!<  EndPoint TYPE */
-#define USB_EP_KIND                           ((uint16_t)0x0100U)              /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX                         ((uint16_t)0x0080U)              /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX                        ((uint16_t)0x0040U)              /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT                         ((uint16_t)0x0030U)              /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD                      ((uint16_t)0x000FU)              /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK                      ((uint16_t)0x0600U)              /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           ((uint16_t)0x0000U)              /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        ((uint16_t)0x0200U)              /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    ((uint16_t)0x0400U)              /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      ((uint16_t)0x0600U)              /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
-                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       ((uint16_t)0x0010U)              /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         ((uint16_t)0x0020U)              /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       ((uint16_t)0x0030U)              /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        ((uint16_t)0x0010U)              /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        ((uint16_t)0x0020U)              /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       ((uint16_t)0x1000U)              /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         ((uint16_t)0x2000U)              /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       ((uint16_t)0x3000U)              /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        ((uint16_t)0x1000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        ((uint16_t)0x2000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* AES Instances ********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM6))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************************** TSC Instances *********************************/
-#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/******************************* USB Instances *******************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define LPUART1_IRQn                   AES_RNG_LPUART1_IRQn
-#define AES_LPUART1_IRQn               AES_RNG_LPUART1_IRQn
-#define RNG_LPUART1_IRQn               AES_RNG_LPUART1_IRQn
-#define TIM6_IRQn                      TIM6_DAC_IRQn
-#define RCC_IRQn                       RCC_CRS_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             AES_RNG_LPUART1_IRQHandler
-#define RNG_LPUART1_IRQHandler         AES_RNG_LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         AES_RNG_LPUART1_IRQHandler
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
-#define RCC_IRQHandler                 RCC_CRS_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L063xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h
deleted file mode 100644
index a880da97a3..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h
+++ /dev/null
@@ -1,6502 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l071xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l071xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l071xx
-  * @{
-  */
-    
-#ifndef __STM32L071xx_H
-#define __STM32L071xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1U /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l071xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  USART4_5_IRQn               = 14,     /*!< USART4 and USART5 Interrupt                             */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
-  TIM6_IRQn                   = 17,     /*!< TIM6  Interrupt                                         */
-  TIM7_IRQn                   = 18,     /*!< TIM7 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  I2C3_IRQn                   = 21,     /*!< I2C3 Interrupt                                          */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  LPUART1_IRQn                = 29,     /*!< LPUART1 Interrupt                                       */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-  __IO uint32_t RESERVED1[23]; /*!< Reserved1,                                   Address offset: 0x24 */
-  __IO uint32_t WRPR2;         /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-  __IO uint32_t WRP23;             /*!< write protection Bytes 2 and 3          Address offset: 0x0C */
-  __IO uint32_t WRP45;             /*!< write protection Bytes 4 and 5          Address offset: 0x10 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_BANK2_BASE (0x08080C00UL) /*!< DATA EEPROM BANK2 base address in the alias region */
-#define DATA_EEPROM_BANK1_END  (0x08080BFFUL) /*!< Program end DATA EEPROM BANK1 address */
-#define DATA_EEPROM_BANK2_END  (0x080817FFUL) /*!< Program end DATA EEPROM BANK2 address */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400UL)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define USART4_BASE           (APBPERIPH_BASE + 0x00004C00UL)
-#define USART5_BASE           (APBPERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-#define I2C3_BASE             (APBPERIPH_BASE + 0x00007800UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (IOPPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define USART4              ((USART_TypeDef *) USART4_BASE)
-#define USART5              ((USART_TypeDef *) USART5_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos       (1U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP           DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos       (5U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP           DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos       (23U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP           DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM24_Pos       (24U)         
-#define EXTI_IMR_IM24_Msk       (0x1UL << EXTI_IMR_IM24_Pos)                    /*!< 0x01000000 */
-#define EXTI_IMR_IM24           EXTI_IMR_IM24_Msk                              /*!< Interrupt Mask on line 24 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x37FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x37FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM24_Pos       (24U)         
-#define EXTI_EMR_EM24_Msk       (0x1UL << EXTI_EMR_EM24_Pos)                    /*!< 0x01000000 */
-#define EXTI_EMR_EM24           EXTI_EMR_EM24_Msk                              /*!< Event Mask on line 24 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos    (15U)    
-#define FLASH_PECR_PARALLBANK_Msk    (0x1UL << FLASH_PECR_PARALLBANK_Pos)       /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK        FLASH_PECR_PARALLBANK_Msk                 /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-#define FLASH_PECR_NZDISABLE_Pos     (22U)    
-#define FLASH_PECR_NZDISABLE_Msk     (0x1UL << FLASH_PECR_NZDISABLE_Pos)        /*!< 0x00400000 */
-#define FLASH_PECR_NZDISABLE         FLASH_PECR_NZDISABLE_Msk                  /*!< Non-Zero check disable */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_BFB2_Pos          (23U)    
-#define FLASH_OPTR_BFB2_Msk          (0x1UL << FLASH_OPTR_BFB2_Pos)             /*!< 0x00800000 */
-#define FLASH_OPTR_BFB2              FLASH_OPTR_BFB2_Msk                       /*!< BFB2 */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)             
-#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)             
-#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)             
-#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)             
-#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)             
-#define FW_VDSSA_ADD_Msk     (0x3FFUL << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)             
-#define FW_VDSL_LENG_Msk     (0x3FFUL << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)             
-#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)             
-#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)             
-#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos          (10U)      
-#define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
-#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-#define RCC_MCO3_SUPPORT            /*!<Support MCO3 */
-#define RCC_MCO3_AF2_SUPPORT        /*!<Support MCO3 on Alternate Function AF0 */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPERST_Pos          (4U) 
-#define RCC_IOPRSTR_IOPERST_Msk          (0x1UL << RCC_IOPRSTR_IOPERST_Pos)     /*!< 0x00000010 */
-#define RCC_IOPRSTR_IOPERST              RCC_IOPRSTR_IOPERST_Msk               /*!< GPIO port E reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOERST                RCC_IOPRSTR_IOPERST        /*!< GPIO port E reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1UL << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos         (1U)
-#define RCC_APB1RSTR_TIM3RST_Msk         (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)    /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST             RCC_APB1RSTR_TIM3RST_Msk              /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos         (5U)
-#define RCC_APB1RSTR_TIM7RST_Msk         (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)    /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST             RCC_APB1RSTR_TIM7RST_Msk              /*!< Timer 7 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_USART4RST_Pos       (19U)
-#define RCC_APB1RSTR_USART4RST_Msk       (0x1UL << RCC_APB1RSTR_USART4RST_Pos)  /*!< 0x00080000 */
-#define RCC_APB1RSTR_USART4RST           RCC_APB1RSTR_USART4RST_Msk            /*!< USART4 reset */
-#define RCC_APB1RSTR_USART5RST_Pos       (20U)
-#define RCC_APB1RSTR_USART5RST_Msk       (0x1UL << RCC_APB1RSTR_USART5RST_Pos)  /*!< 0x00100000 */
-#define RCC_APB1RSTR_USART5RST           RCC_APB1RSTR_USART5RST_Msk            /*!< USART5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_I2C3RST_Pos         (30U)
-#define RCC_APB1RSTR_I2C3RST_Msk         (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)    /*!< 0x40000000 */
-#define RCC_APB1RSTR_I2C3RST             RCC_APB1RSTR_I2C3RST_Msk              /*!< I2C3  reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPEEN_Pos            (4U) 
-#define RCC_IOPENR_IOPEEN_Msk            (0x1UL << RCC_IOPENR_IOPEEN_Pos)       /*!< 0x00000010 */
-#define RCC_IOPENR_IOPEEN                RCC_IOPENR_IOPEEN_Msk                 /*!< GPIO port E clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOEEN                  RCC_IOPENR_IOPEEN        /*!< GPIO port E clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)
-#define RCC_APB2ENR_USART1EN_Msk         (0x1UL << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM3EN_Pos           (1U) 
-#define RCC_APB1ENR_TIM3EN_Msk           (0x1UL << RCC_APB1ENR_TIM3EN_Pos)      /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN               RCC_APB1ENR_TIM3EN_Msk                /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U) 
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1UL << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos           (5U) 
-#define RCC_APB1ENR_TIM7EN_Msk           (0x1UL << RCC_APB1ENR_TIM7EN_Pos)      /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN               RCC_APB1ENR_TIM7EN_Msk                /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1UL << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_USART4EN_Pos         (19U)
-#define RCC_APB1ENR_USART4EN_Msk         (0x1UL << RCC_APB1ENR_USART4EN_Pos)    /*!< 0x00080000 */
-#define RCC_APB1ENR_USART4EN             RCC_APB1ENR_USART4EN_Msk              /*!< USART4 clock enable */
-#define RCC_APB1ENR_USART5EN_Pos         (20U)
-#define RCC_APB1ENR_USART5EN_Msk         (0x1UL << RCC_APB1ENR_USART5EN_Pos)    /*!< 0x00100000 */
-#define RCC_APB1ENR_USART5EN             RCC_APB1ENR_USART5EN_Msk              /*!< USART5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1UL << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_I2C3EN_Pos           (30U)
-#define RCC_APB1ENR_I2C3EN_Msk           (0x1UL << RCC_APB1ENR_I2C3EN_Pos)      /*!< 0x40000000 */
-#define RCC_APB1ENR_I2C3EN               RCC_APB1ENR_I2C3EN_Msk                /*!< I2C3 clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPESMEN_Pos        (4U) 
-#define RCC_IOPSMENR_IOPESMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos)   /*!< 0x00000010 */
-#define RCC_IOPSMENR_IOPESMEN            RCC_IOPSMENR_IOPESMEN_Msk             /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOESMEN              RCC_IOPSMENR_IOPESMEN        /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM3SMEN_Pos       (1U) 
-#define RCC_APB1SMENR_TIM3SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM3SMEN_Pos)  /*!< 0x00000002 */
-#define RCC_APB1SMENR_TIM3SMEN           RCC_APB1SMENR_TIM3SMEN_Msk            /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U) 
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM7SMEN_Pos       (5U) 
-#define RCC_APB1SMENR_TIM7SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM7SMEN_Pos)  /*!< 0x00000020 */
-#define RCC_APB1SMENR_TIM7SMEN           RCC_APB1SMENR_TIM7SMEN_Msk            /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART4SMEN_Pos     (19U)
-#define RCC_APB1SMENR_USART4SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1SMENR_USART4SMEN         RCC_APB1SMENR_USART4SMEN_Msk          /*!< USART4 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART5SMEN_Pos     (20U)
-#define RCC_APB1SMENR_USART5SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1SMENR_USART5SMEN         RCC_APB1SMENR_USART5SMEN_Msk          /*!< USART5 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C3SMEN_Pos       (30U)
-#define RCC_APB1SMENR_I2C3SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C3SMEN_Pos)  /*!< 0x40000000 */
-#define RCC_APB1SMENR_I2C3SMEN           RCC_APB1SMENR_I2C3SMEN_Msk            /*!< I2C3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U) 
-#define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-/*!< I2C3 Clock source selection */
-#define RCC_CCIPR_I2C3SEL_Pos            (16U)
-#define RCC_CCIPR_I2C3SEL_Msk            (0x3UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00030000 */
-#define RCC_CCIPR_I2C3SEL                RCC_CCIPR_I2C3SEL_Msk                 /*!< I2C3SEL [1:0] bits */
-#define RCC_CCIPR_I2C3SEL_0              (0x1UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00010000 */
-#define RCC_CCIPR_I2C3SEL_1              (0x2UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00020000 */
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)      
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)      
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)      
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)      
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)      
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)      
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)     
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)     
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)     
-#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */
-#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)      
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)      
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)      
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_UFB_Pos                     (3U)                          
-#define SYSCFG_CFGR1_UFB_Msk                     (0x1UL << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */
-#define SYSCFG_CFGR1_UFB                         SYSCFG_CFGR1_UFB_Msk          /*!< User bank swapping */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-#define SYSCFG_CFGR2_I2C3_FMP_Pos                (14U)                         
-#define SYSCFG_CFGR2_I2C3_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */
-#define SYSCFG_CFGR2_I2C3_FMP                    SYSCFG_CFGR2_I2C3_FMP_Msk     /*!< I2C3 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD                  (0x00000003U)                 /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE                  (0x00000004U)                 /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD                  (0x00000030U)                 /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE                  (0x00000040U)                 /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE                  (0x00000400U)                 /*!< PE[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD                  (0x00003000U)                 /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE                  (0x00004000U)                 /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD                  (0x00000003U)                 /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE                  (0x00000004U)                 /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD                  (0x00000030U)                 /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE                  (0x00000040U)                 /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD                  (0x00000300U)                 /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE                  (0x00000400U)                 /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD                  (0x00003000U)                 /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE                  (0x00004000U)                 /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD                  (0x00000003U)                 /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE                  (0x00000004U)                 /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD                  (0x00000030U)                 /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE                  (0x00000040U)                 /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH                  (0x00000050U)                 /*!< PH[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD                 (0x00000300U)                 /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE                 (0x00000400U)                 /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH                 (0x00000500U)                 /*!< PH[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD                 (0x00003000U)                 /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE                 (0x00004000U)                 /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD                 (0x00000003U)                 /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE                 (0x00000004U)                 /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD                 (0x00000030U)                 /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE                 (0x00000040U)                 /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD                 (0x00000300U)                 /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE                 (0x00000400U)                 /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD                 (0x00003000U)                 /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE                 (0x00004000U)                 /*!< PE[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI_SUPPORT       /*!<Support remap HSI on TIM2 */
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-#define TIM3_OR_ETR_RMP_Pos      (0U)         
-#define TIM3_OR_ETR_RMP_Msk      (0x3UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000003 */
-#define TIM3_OR_ETR_RMP          TIM3_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
-#define TIM3_OR_ETR_RMP_0        (0x1UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM3_OR_ETR_RMP_1        (0x2UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM3_OR_TI1_RMP_Pos      (2U)         
-#define TIM3_OR_TI1_RMP_Msk      (0x1UL << TIM3_OR_TI1_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM3_OR_TI1_RMP          TIM3_OR_TI1_RMP_Msk                           /*!<TI1_RMP[2] bit                      */
-#define TIM3_OR_TI2_RMP_Pos      (3U)         
-#define TIM3_OR_TI2_RMP_Msk      (0x1UL << TIM3_OR_TI2_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM3_OR_TI2_RMP          TIM3_OR_TI2_RMP_Msk                           /*!<TI2_RMP[3] bit                      */
-#define TIM3_OR_TI4_RMP_Pos      (4U)         
-#define TIM3_OR_TI4_RMP_Msk      (0x1UL << TIM3_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-#define TIM3_OR_TI4_RMP          TIM3_OR_TI4_RMP_Msk                           /*!<TI4_RMP[4] bit                      */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                                   ((INSTANCE) == I2C3))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                     ((INSTANCE) == I2C3))
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM7)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM3)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3) || \
-                                            ((INSTANCE) == TIM6) || \
-                                            ((INSTANCE) == TIM7))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                           ((INSTANCE) == TIM3))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-   (((((INSTANCE) == TIM2) ||                  \
-      ((INSTANCE) == TIM3))                    \
-     &&                                        \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM3)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM3)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM3)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM7)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                                ((INSTANCE) == TIM3))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART4) || \
-                                    ((INSTANCE) == USART5))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART4) || \
-                                     ((INSTANCE) == USART5))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART4) || \
-                                           ((INSTANCE) == USART5) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define RNG_LPUART1_IRQn               LPUART1_IRQn
-#define AES_LPUART1_IRQn               LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           LPUART1_IRQn
-#define TIM6_DAC_IRQn                  TIM6_IRQn
-#define RCC_CRS_IRQn                   RCC_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define RNG_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     LPUART1_IRQHandler
-#define TIM6_DAC_IRQHandler            TIM6_IRQHandler
-#define RCC_CRS_IRQHandler             RCC_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L071xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h
deleted file mode 100644
index 649749114b..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h
+++ /dev/null
@@ -1,7688 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l072xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l072xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l072xx
-  * @{
-  */
-    
-#ifndef __STM32L072xx_H
-#define __STM32L072xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1U /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l072xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  USART4_5_IRQn               = 14,     /*!< USART4 and USART5 Interrupt                             */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM7_IRQn                   = 18,     /*!< TIM7 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  I2C3_IRQn                   = 21,     /*!< I2C3 Interrupt                                          */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  RNG_LPUART1_IRQn            = 29,     /*!< RNG and LPUART1 Interrupts                              */
-  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Clock Recovery System 
-  */
-
-typedef struct 
-{
-__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
-__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
-__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
-__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
-} CRS_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;       /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;       /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;        /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;       /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;       /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;        /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;          /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-  __IO uint32_t RESERVED1[23]; /*!< Reserved1,                                   Address offset: 0x24 */
-  __IO uint32_t WRPR2;         /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-  __IO uint32_t WRP23;             /*!< write protection Bytes 2 and 3          Address offset: 0x0C */
-  __IO uint32_t WRP45;             /*!< write protection Bytes 4 and 5          Address offset: 0x10 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Random numbers generator
-  */
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
-  __IO uint16_t RESERVEDD;       /*!< Reserved */       
-  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
-  __IO uint16_t RESERVEDE;       /*!< Reserved */       
-} USB_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_BANK2_BASE (0x08080C00UL) /*!< DATA EEPROM BANK2 base address in the alias region */
-#define DATA_EEPROM_BANK1_END  (0x08080BFFUL) /*!< Program end DATA EEPROM BANK1 address */
-#define DATA_EEPROM_BANK2_END  (0x080817FFUL) /*!< Program end DATA EEPROM BANK2 address */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400UL)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define USART4_BASE           (APBPERIPH_BASE + 0x00004C00UL)
-#define USART5_BASE           (APBPERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
-#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-#define I2C3_BASE             (APBPERIPH_BASE + 0x00007800UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000UL)
-#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (IOPPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CRS                 ((CRS_TypeDef *) CRS_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define USART4              ((USART_TypeDef *) USART4_BASE)
-#define USART5              ((USART_TypeDef *) USART5_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define USB                 ((USB_TypeDef *) USB_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRS Clock Recovery System                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRS_CR register  *********************/
-#define CRS_CR_SYNCOKIE_Pos       (0U)        
-#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
-#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
-#define CRS_CR_SYNCWARNIE_Pos     (1U)        
-#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
-#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
-#define CRS_CR_ERRIE_Pos          (2U)        
-#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
-#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
-#define CRS_CR_ESYNCIE_Pos        (3U)        
-#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
-#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN_Pos            (5U)        
-#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
-#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
-#define CRS_CR_AUTOTRIMEN_Pos     (6U)        
-#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
-#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
-#define CRS_CR_SWSYNC_Pos         (7U)        
-#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
-#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
-#define CRS_CR_TRIM_Pos           (8U)        
-#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
-#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
-
-/*******************  Bit definition for CRS_CFGR register  *********************/
-#define CRS_CFGR_RELOAD_Pos       (0U)        
-#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
-#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
-#define CRS_CFGR_FELIM_Pos        (16U)       
-#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
-#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
-
-#define CRS_CFGR_SYNCDIV_Pos      (24U)       
-#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
-#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
-#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
-#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
-#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
-
-#define CRS_CFGR_SYNCSRC_Pos      (28U)       
-#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
-#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
-#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
-#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
-
-#define CRS_CFGR_SYNCPOL_Pos      (31U)       
-#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
-#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
-  
-/*******************  Bit definition for CRS_ISR register  *********************/
-#define CRS_ISR_SYNCOKF_Pos       (0U)        
-#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
-#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
-#define CRS_ISR_SYNCWARNF_Pos     (1U)        
-#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
-#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
-#define CRS_ISR_ERRF_Pos          (2U)        
-#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
-#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
-#define CRS_ISR_ESYNCF_Pos        (3U)        
-#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
-#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
-#define CRS_ISR_SYNCERR_Pos       (8U)        
-#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
-#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
-#define CRS_ISR_SYNCMISS_Pos      (9U)        
-#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
-#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
-#define CRS_ISR_TRIMOVF_Pos       (10U)       
-#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
-#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR_Pos         (15U)       
-#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
-#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
-#define CRS_ISR_FECAP_Pos         (16U)       
-#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
-#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
-
-/*******************  Bit definition for CRS_ICR register  *********************/
-#define CRS_ICR_SYNCOKC_Pos       (0U)        
-#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
-#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
-#define CRS_ICR_SYNCWARNC_Pos     (1U)        
-#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
-#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
-#define CRS_ICR_ERRC_Pos          (2U)        
-#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
-#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag             */
-#define CRS_ICR_ESYNCC_Pos        (3U)        
-#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
-#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define DAC_CHANNEL2_SUPPORT                       /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)      
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos            (1U)      
-#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos             (2U)      
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (3U)      
-#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)      
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)      
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)     
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)     
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun interrupt enable */
-
-#define DAC_CR_EN2_Pos              (16U)     
-#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
-#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos            (17U)     
-#define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
-#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!< DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos             (18U)     
-#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
-#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!< DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos            (19U)     
-#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
-#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos            (22U)     
-#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos            (24U)     
-#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos           (28U)     
-#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
-#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!< DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos        (29U)     
-#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!< DAC channel12DMA Underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)      
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)      
-#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!< DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)      
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)      
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)      
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos    (0U)      
-#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos    (4U)      
-#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos     (0U)      
-#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos    (0U)      
-#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos    (16U)     
-#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos    (4U)      
-#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos    (20U)     
-#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos     (0U)      
-#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos     (8U)      
-#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)      
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos       (0U)      
-#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!< DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)     
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos          (29U)     
-#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!< DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_DIV_ID_Pos               (12U)                           
-#define DBGMCU_IDCODE_DIV_ID_Msk               (0xFUL << DBGMCU_IDCODE_DIV_ID_Pos) /*!< 0x0000F000 */
-#define DBGMCU_IDCODE_DIV_ID                   DBGMCU_IDCODE_DIV_ID_Msk        /*!< Division Identifier */
-#define DBGMCU_IDCODE_MCD_DIV_ID_Pos           (13U)                           
-#define DBGMCU_IDCODE_MCD_DIV_ID_Msk           (0x3UL << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */
-#define DBGMCU_IDCODE_MCD_DIV_ID               DBGMCU_IDCODE_MCD_DIV_ID_Msk    /*!< MCD divsion ID is 6 */
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos       (1U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP           DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos       (5U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP           DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos       (23U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP           DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM24_Pos       (24U)         
-#define EXTI_IMR_IM24_Msk       (0x1UL << EXTI_IMR_IM24_Pos)                    /*!< 0x01000000 */
-#define EXTI_IMR_IM24           EXTI_IMR_IM24_Msk                              /*!< Interrupt Mask on line 24 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x37FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x37FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM24_Pos       (24U)         
-#define EXTI_EMR_EM24_Msk       (0x1UL << EXTI_EMR_EM24_Pos)                    /*!< 0x01000000 */
-#define EXTI_EMR_EM24           EXTI_EMR_EM24_Msk                              /*!< Event Mask on line 24 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos    (15U)    
-#define FLASH_PECR_PARALLBANK_Msk    (0x1UL << FLASH_PECR_PARALLBANK_Pos)       /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK        FLASH_PECR_PARALLBANK_Msk                 /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-#define FLASH_PECR_NZDISABLE_Pos     (22U)    
-#define FLASH_PECR_NZDISABLE_Msk     (0x1UL << FLASH_PECR_NZDISABLE_Pos)        /*!< 0x00400000 */
-#define FLASH_PECR_NZDISABLE         FLASH_PECR_NZDISABLE_Msk                  /*!< Non-Zero check disable */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_BFB2_Pos          (23U)    
-#define FLASH_OPTR_BFB2_Msk          (0x1UL << FLASH_OPTR_BFB2_Pos)             /*!< 0x00800000 */
-#define FLASH_OPTR_BFB2              FLASH_OPTR_BFB2_Msk                       /*!< BFB2 */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)             
-#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)             
-#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)             
-#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)             
-#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)             
-#define FW_VDSSA_ADD_Msk     (0x3FFUL << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)             
-#define FW_VDSL_LENG_Msk     (0x3FFUL << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)             
-#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)             
-#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)             
-#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos          (10U)      
-#define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
-#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-#define RCC_MCO3_SUPPORT            /*!<Support MCO3 */
-#define RCC_MCO3_AF2_SUPPORT        /*!<Support MCO3 on Alternate Function AF0 */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CRRCR register  *****************/
-#define RCC_CRRCR_HSI48ON_Pos            (0U) 
-#define RCC_CRRCR_HSI48ON_Msk            (0x1UL << RCC_CRRCR_HSI48ON_Pos)       /*!< 0x00000001 */
-#define RCC_CRRCR_HSI48ON                RCC_CRRCR_HSI48ON_Msk                 /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY_Pos           (1U) 
-#define RCC_CRRCR_HSI48RDY_Msk           (0x1UL << RCC_CRRCR_HSI48RDY_Pos)      /*!< 0x00000002 */
-#define RCC_CRRCR_HSI48RDY               RCC_CRRCR_HSI48RDY_Msk                /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48DIV6OUTEN_Pos     (2U) 
-#define RCC_CRRCR_HSI48DIV6OUTEN_Msk     (0x1UL << RCC_CRRCR_HSI48DIV6OUTEN_Pos) /*!< 0x00000004 */
-#define RCC_CRRCR_HSI48DIV6OUTEN         RCC_CRRCR_HSI48DIV6OUTEN_Msk          /*!< HSI 48MHz DIV6 out enable */
-#define RCC_CRRCR_HSI48CAL_Pos           (8U) 
-#define RCC_CRRCR_HSI48CAL_Msk           (0xFFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF00 */
-#define RCC_CRRCR_HSI48CAL               RCC_CRRCR_HSI48CAL_Msk                /*!< HSI 48MHz clock Calibration */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-#define RCC_CFGR_MCOSEL_HSI48_Pos            (27U)                             
-#define RCC_CFGR_MCOSEL_HSI48_Msk            (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
-#define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCOSEL_HSI48_Msk         /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE_Pos          (6U) 
-#define RCC_CIER_HSI48RDYIE_Msk          (0x1UL << RCC_CIER_HSI48RDYIE_Pos)     /*!< 0x00000040 */
-#define RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE_Msk               /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF_Pos           (6U) 
-#define RCC_CIFR_HSI48RDYF_Msk           (0x1UL << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000040 */
-#define RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF_Msk                /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC_Pos           (6U) 
-#define RCC_CICR_HSI48RDYC_Msk           (0x1UL << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000040 */
-#define RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC_Msk                /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPERST_Pos          (4U) 
-#define RCC_IOPRSTR_IOPERST_Msk          (0x1UL << RCC_IOPRSTR_IOPERST_Pos)     /*!< 0x00000010 */
-#define RCC_IOPRSTR_IOPERST              RCC_IOPRSTR_IOPERST_Msk               /*!< GPIO port E reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOERST                RCC_IOPRSTR_IOPERST        /*!< GPIO port E reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST_Pos           (16U)
-#define RCC_AHBRSTR_TSCRST_Msk           (0x1UL << RCC_AHBRSTR_TSCRST_Pos)      /*!< 0x00010000 */
-#define RCC_AHBRSTR_TSCRST               RCC_AHBRSTR_TSCRST_Msk                /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST_Pos           (20U)
-#define RCC_AHBRSTR_RNGRST_Msk           (0x1UL << RCC_AHBRSTR_RNGRST_Pos)      /*!< 0x00100000 */
-#define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk                /*!< RNG reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1UL << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos         (1U)
-#define RCC_APB1RSTR_TIM3RST_Msk         (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)    /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST             RCC_APB1RSTR_TIM3RST_Msk              /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos         (5U)
-#define RCC_APB1RSTR_TIM7RST_Msk         (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)    /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST             RCC_APB1RSTR_TIM7RST_Msk              /*!< Timer 7 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_USART4RST_Pos       (19U)
-#define RCC_APB1RSTR_USART4RST_Msk       (0x1UL << RCC_APB1RSTR_USART4RST_Pos)  /*!< 0x00080000 */
-#define RCC_APB1RSTR_USART4RST           RCC_APB1RSTR_USART4RST_Msk            /*!< USART4 reset */
-#define RCC_APB1RSTR_USART5RST_Pos       (20U)
-#define RCC_APB1RSTR_USART5RST_Msk       (0x1UL << RCC_APB1RSTR_USART5RST_Pos)  /*!< 0x00100000 */
-#define RCC_APB1RSTR_USART5RST           RCC_APB1RSTR_USART5RST_Msk            /*!< USART5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos          (23U)
-#define RCC_APB1RSTR_USBRST_Msk          (0x1UL << RCC_APB1RSTR_USBRST_Pos)     /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST              RCC_APB1RSTR_USBRST_Msk               /*!< USB reset */
-#define RCC_APB1RSTR_CRSRST_Pos          (27U)
-#define RCC_APB1RSTR_CRSRST_Msk          (0x1UL << RCC_APB1RSTR_CRSRST_Pos)     /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST              RCC_APB1RSTR_CRSRST_Msk               /*!< CRS reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_DACRST_Pos          (29U)
-#define RCC_APB1RSTR_DACRST_Msk          (0x1UL << RCC_APB1RSTR_DACRST_Pos)     /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST              RCC_APB1RSTR_DACRST_Msk               /*!< DAC reset */
-#define RCC_APB1RSTR_I2C3RST_Pos         (30U)
-#define RCC_APB1RSTR_I2C3RST_Msk         (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)    /*!< 0x40000000 */
-#define RCC_APB1RSTR_I2C3RST             RCC_APB1RSTR_I2C3RST_Msk              /*!< I2C3  reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPEEN_Pos            (4U) 
-#define RCC_IOPENR_IOPEEN_Msk            (0x1UL << RCC_IOPENR_IOPEEN_Pos)       /*!< 0x00000010 */
-#define RCC_IOPENR_IOPEEN                RCC_IOPENR_IOPEEN_Msk                 /*!< GPIO port E clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOEEN                  RCC_IOPENR_IOPEEN        /*!< GPIO port E clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN_Pos             (16U)
-#define RCC_AHBENR_TSCEN_Msk             (0x1UL << RCC_AHBENR_TSCEN_Pos)        /*!< 0x00010000 */
-#define RCC_AHBENR_TSCEN                 RCC_AHBENR_TSCEN_Msk                  /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN_Pos             (20U)
-#define RCC_AHBENR_RNGEN_Msk             (0x1UL << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00100000 */
-#define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk                  /*!< RNG clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)
-#define RCC_APB2ENR_USART1EN_Msk         (0x1UL << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM3EN_Pos           (1U) 
-#define RCC_APB1ENR_TIM3EN_Msk           (0x1UL << RCC_APB1ENR_TIM3EN_Pos)      /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN               RCC_APB1ENR_TIM3EN_Msk                /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U) 
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1UL << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos           (5U) 
-#define RCC_APB1ENR_TIM7EN_Msk           (0x1UL << RCC_APB1ENR_TIM7EN_Pos)      /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN               RCC_APB1ENR_TIM7EN_Msk                /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1UL << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_USART4EN_Pos         (19U)
-#define RCC_APB1ENR_USART4EN_Msk         (0x1UL << RCC_APB1ENR_USART4EN_Pos)    /*!< 0x00080000 */
-#define RCC_APB1ENR_USART4EN             RCC_APB1ENR_USART4EN_Msk              /*!< USART4 clock enable */
-#define RCC_APB1ENR_USART5EN_Pos         (20U)
-#define RCC_APB1ENR_USART5EN_Msk         (0x1UL << RCC_APB1ENR_USART5EN_Pos)    /*!< 0x00100000 */
-#define RCC_APB1ENR_USART5EN             RCC_APB1ENR_USART5EN_Msk              /*!< USART5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1UL << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos            (23U)
-#define RCC_APB1ENR_USBEN_Msk            (0x1UL << RCC_APB1ENR_USBEN_Pos)       /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                RCC_APB1ENR_USBEN_Msk                 /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN_Pos            (27U)
-#define RCC_APB1ENR_CRSEN_Msk            (0x1UL << RCC_APB1ENR_CRSEN_Pos)       /*!< 0x08000000 */
-#define RCC_APB1ENR_CRSEN                RCC_APB1ENR_CRSEN_Msk                 /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN_Pos            (29U)
-#define RCC_APB1ENR_DACEN_Msk            (0x1UL << RCC_APB1ENR_DACEN_Pos)       /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                RCC_APB1ENR_DACEN_Msk                 /*!< DAC clock enable */
-#define RCC_APB1ENR_I2C3EN_Pos           (30U)
-#define RCC_APB1ENR_I2C3EN_Msk           (0x1UL << RCC_APB1ENR_I2C3EN_Pos)      /*!< 0x40000000 */
-#define RCC_APB1ENR_I2C3EN               RCC_APB1ENR_I2C3EN_Msk                /*!< I2C3 clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPESMEN_Pos        (4U) 
-#define RCC_IOPSMENR_IOPESMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos)   /*!< 0x00000010 */
-#define RCC_IOPSMENR_IOPESMEN            RCC_IOPSMENR_IOPESMEN_Msk             /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOESMEN              RCC_IOPSMENR_IOPESMEN        /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN_Pos         (16U)
-#define RCC_AHBSMENR_TSCSMEN_Msk         (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos)    /*!< 0x00010000 */
-#define RCC_AHBSMENR_TSCSMEN             RCC_AHBSMENR_TSCSMEN_Msk              /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN_Pos         (20U)
-#define RCC_AHBSMENR_RNGSMEN_Msk         (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00100000 */
-#define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk              /*!< RNG clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM3SMEN_Pos       (1U) 
-#define RCC_APB1SMENR_TIM3SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM3SMEN_Pos)  /*!< 0x00000002 */
-#define RCC_APB1SMENR_TIM3SMEN           RCC_APB1SMENR_TIM3SMEN_Msk            /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U) 
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM7SMEN_Pos       (5U) 
-#define RCC_APB1SMENR_TIM7SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM7SMEN_Pos)  /*!< 0x00000020 */
-#define RCC_APB1SMENR_TIM7SMEN           RCC_APB1SMENR_TIM7SMEN_Msk            /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART4SMEN_Pos     (19U)
-#define RCC_APB1SMENR_USART4SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1SMENR_USART4SMEN         RCC_APB1SMENR_USART4SMEN_Msk          /*!< USART4 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART5SMEN_Pos     (20U)
-#define RCC_APB1SMENR_USART5SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1SMENR_USART5SMEN         RCC_APB1SMENR_USART5SMEN_Msk          /*!< USART5 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN_Pos        (23U)
-#define RCC_APB1SMENR_USBSMEN_Msk        (0x1UL << RCC_APB1SMENR_USBSMEN_Pos)   /*!< 0x00800000 */
-#define RCC_APB1SMENR_USBSMEN            RCC_APB1SMENR_USBSMEN_Msk             /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN_Pos        (27U)
-#define RCC_APB1SMENR_CRSSMEN_Msk        (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos)   /*!< 0x08000000 */
-#define RCC_APB1SMENR_CRSSMEN            RCC_APB1SMENR_CRSSMEN_Msk             /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN_Pos        (29U)
-#define RCC_APB1SMENR_DACSMEN_Msk        (0x1UL << RCC_APB1SMENR_DACSMEN_Pos)   /*!< 0x20000000 */
-#define RCC_APB1SMENR_DACSMEN            RCC_APB1SMENR_DACSMEN_Msk             /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C3SMEN_Pos       (30U)
-#define RCC_APB1SMENR_I2C3SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C3SMEN_Pos)  /*!< 0x40000000 */
-#define RCC_APB1SMENR_I2C3SMEN           RCC_APB1SMENR_I2C3SMEN_Msk            /*!< I2C3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U) 
-#define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-/*!< I2C3 Clock source selection */
-#define RCC_CCIPR_I2C3SEL_Pos            (16U)
-#define RCC_CCIPR_I2C3SEL_Msk            (0x3UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00030000 */
-#define RCC_CCIPR_I2C3SEL                RCC_CCIPR_I2C3SEL_Msk                 /*!< I2C3SEL [1:0] bits */
-#define RCC_CCIPR_I2C3SEL_0              (0x1UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00010000 */
-#define RCC_CCIPR_I2C3SEL_1              (0x2UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00020000 */
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*!< HSI48 Clock source selection */ 
-#define RCC_CCIPR_HSI48SEL_Pos           (26U)
-#define RCC_CCIPR_HSI48SEL_Msk           (0x1UL << RCC_CCIPR_HSI48SEL_Pos)      /*!< 0x04000000 */
-#define RCC_CCIPR_HSI48SEL               RCC_CCIPR_HSI48SEL_Msk                /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Legacy defines */
-#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos    (2U)              
-#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
-#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
-#define RNG_CR_IE_Pos       (3U)              
-#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
-#define RNG_CR_IE           RNG_CR_IE_Msk                                      
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)              
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
-#define RNG_SR_CECS_Pos     (1U)              
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
-#define RNG_SR_SECS_Pos     (2U)              
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
-#define RNG_SR_CEIS_Pos     (5U)              
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
-#define RNG_SR_SEIS_Pos     (6U)              
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)      
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)      
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)      
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)      
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)      
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)      
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)     
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)     
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)     
-#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */
-#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)      
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)      
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)      
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_UFB_Pos                     (3U)                          
-#define SYSCFG_CFGR1_UFB_Msk                     (0x1UL << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */
-#define SYSCFG_CFGR1_UFB                         SYSCFG_CFGR1_UFB_Msk          /*!< User bank swapping */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-#define SYSCFG_CFGR2_I2C3_FMP_Pos                (14U)                         
-#define SYSCFG_CFGR2_I2C3_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */
-#define SYSCFG_CFGR2_I2C3_FMP                    SYSCFG_CFGR2_I2C3_FMP_Msk     /*!< I2C3 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD                  (0x00000003U)                 /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE                  (0x00000004U)                 /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD                  (0x00000030U)                 /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE                  (0x00000040U)                 /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE                  (0x00000400U)                 /*!< PE[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD                  (0x00003000U)                 /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE                  (0x00004000U)                 /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD                  (0x00000003U)                 /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE                  (0x00000004U)                 /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD                  (0x00000030U)                 /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE                  (0x00000040U)                 /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD                  (0x00000300U)                 /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE                  (0x00000400U)                 /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD                  (0x00003000U)                 /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE                  (0x00004000U)                 /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD                  (0x00000003U)                 /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE                  (0x00000004U)                 /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD                  (0x00000030U)                 /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE                  (0x00000040U)                 /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH                  (0x00000050U)                 /*!< PH[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD                 (0x00000300U)                 /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE                 (0x00000400U)                 /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH                 (0x00000500U)                 /*!< PH[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD                 (0x00003000U)                 /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE                 (0x00004000U)                 /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD                 (0x00000003U)                 /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE                 (0x00000004U)                 /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD                 (0x00000030U)                 /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE                 (0x00000040U)                 /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD                 (0x00000300U)                 /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE                 (0x00000400U)                 /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD                 (0x00003000U)                 /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE                 (0x00004000U)                 /*!< PE[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48_Pos             (13U)                         
-#define SYSCFG_CFGR3_ENREF_HSI48_Msk             (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR3_ENREF_HSI48                 SYSCFG_CFGR3_ENREF_HSI48_Msk  /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
-#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_REF_HSI48_RDYF           SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI_SUPPORT       /*!<Support remap HSI on TIM2 */
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-#define TIM3_OR_ETR_RMP_Pos      (0U)         
-#define TIM3_OR_ETR_RMP_Msk      (0x3UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000003 */
-#define TIM3_OR_ETR_RMP          TIM3_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
-#define TIM3_OR_ETR_RMP_0        (0x1UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM3_OR_ETR_RMP_1        (0x2UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM3_OR_TI1_RMP_Pos      (2U)         
-#define TIM3_OR_TI1_RMP_Msk      (0x1UL << TIM3_OR_TI1_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM3_OR_TI1_RMP          TIM3_OR_TI1_RMP_Msk                           /*!<TI1_RMP[2] bit                      */
-#define TIM3_OR_TI2_RMP_Pos      (3U)         
-#define TIM3_OR_TI2_RMP_Msk      (0x1UL << TIM3_OR_TI2_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM3_OR_TI2_RMP          TIM3_OR_TI2_RMP_Msk                           /*!<TI2_RMP[3] bit                      */
-#define TIM3_OR_TI4_RMP_Pos      (4U)         
-#define TIM3_OR_TI4_RMP_Msk      (0x1UL << TIM3_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-#define TIM3_OR_TI4_RMP          TIM3_OR_TI4_RMP_Msk                           /*!<TI4_RMP[4] bit                      */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE_Pos          (0U)         
-#define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
-#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
-#define TSC_CR_START_Pos         (1U)         
-#define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
-#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
-#define TSC_CR_AM_Pos            (2U)         
-#define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
-#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL_Pos       (3U)         
-#define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
-#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF_Pos         (4U)         
-#define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
-#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
-
-#define TSC_CR_MCV_Pos           (5U)         
-#define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
-#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
-#define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
-#define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
-
-#define TSC_CR_PGPSC_Pos         (12U)        
-#define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
-#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
-#define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
-#define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
-
-#define TSC_CR_SSPSC_Pos         (15U)        
-#define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
-#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE_Pos           (16U)        
-#define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
-#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD_Pos           (17U)        
-#define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
-#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
-#define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
-#define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
-#define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
-#define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
-#define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
-#define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
-
-#define TSC_CR_CTPL_Pos          (24U)        
-#define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
-#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
-#define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
-#define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
-#define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
-
-#define TSC_CR_CTPH_Pos          (28U)        
-#define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
-#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
-#define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
-#define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
-#define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE_Pos        (0U)         
-#define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
-#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE_Pos        (1U)         
-#define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
-#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC_Pos        (0U)         
-#define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
-#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC_Pos        (1U)         
-#define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
-#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF_Pos         (0U)         
-#define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
-#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
-#define TSC_ISR_MCEF_Pos         (1U)         
-#define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
-#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1_Pos     (0U)         
-#define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2_Pos     (1U)         
-#define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3_Pos     (2U)         
-#define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4_Pos     (3U)         
-#define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1_Pos     (4U)         
-#define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2_Pos     (5U)         
-#define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3_Pos     (6U)         
-#define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4_Pos     (7U)         
-#define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1_Pos     (8U)         
-#define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2_Pos     (9U)         
-#define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3_Pos     (10U)        
-#define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4_Pos     (11U)        
-#define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1_Pos     (12U)        
-#define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2_Pos     (13U)        
-#define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3_Pos     (14U)        
-#define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4_Pos     (15U)        
-#define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1_Pos     (16U)        
-#define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2_Pos     (17U)        
-#define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3_Pos     (18U)        
-#define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4_Pos     (19U)        
-#define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1_Pos     (20U)        
-#define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2_Pos     (21U)        
-#define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3_Pos     (22U)        
-#define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4_Pos     (23U)        
-#define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1_Pos     (24U)        
-#define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2_Pos     (25U)        
-#define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3_Pos     (26U)        
-#define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4_Pos     (27U)        
-#define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1_Pos     (28U)        
-#define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2_Pos     (29U)        
-#define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3_Pos     (30U)        
-#define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4_Pos     (31U)        
-#define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1_Pos    (0U)         
-#define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
-#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2_Pos    (1U)         
-#define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
-#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3_Pos    (2U)         
-#define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
-#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4_Pos    (3U)         
-#define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
-#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1_Pos    (4U)         
-#define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
-#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2_Pos    (5U)         
-#define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
-#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3_Pos    (6U)         
-#define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
-#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4_Pos    (7U)         
-#define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
-#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1_Pos    (8U)         
-#define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
-#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2_Pos    (9U)         
-#define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
-#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3_Pos    (10U)        
-#define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
-#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4_Pos    (11U)        
-#define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
-#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1_Pos    (12U)        
-#define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
-#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2_Pos    (13U)        
-#define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
-#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3_Pos    (14U)        
-#define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
-#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4_Pos    (15U)        
-#define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
-#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1_Pos    (16U)        
-#define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
-#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2_Pos    (17U)        
-#define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
-#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3_Pos    (18U)        
-#define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
-#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4_Pos    (19U)        
-#define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
-#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1_Pos    (20U)        
-#define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
-#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2_Pos    (21U)        
-#define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
-#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3_Pos    (22U)        
-#define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
-#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4_Pos    (23U)        
-#define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
-#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1_Pos    (24U)        
-#define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
-#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2_Pos    (25U)        
-#define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
-#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3_Pos    (26U)        
-#define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
-#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4_Pos    (27U)        
-#define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
-#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1_Pos    (28U)        
-#define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
-#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2_Pos    (29U)        
-#define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
-#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3_Pos    (30U)        
-#define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
-#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4_Pos    (31U)        
-#define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
-#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1_Pos     (0U)         
-#define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2_Pos     (1U)         
-#define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3_Pos     (2U)         
-#define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4_Pos     (3U)         
-#define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1_Pos     (4U)         
-#define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2_Pos     (5U)         
-#define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3_Pos     (6U)         
-#define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4_Pos     (7U)         
-#define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1_Pos     (8U)         
-#define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2_Pos     (9U)         
-#define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3_Pos     (10U)        
-#define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4_Pos     (11U)        
-#define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1_Pos     (12U)        
-#define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2_Pos     (13U)        
-#define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3_Pos     (14U)        
-#define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4_Pos     (15U)        
-#define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1_Pos     (16U)        
-#define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2_Pos     (17U)        
-#define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3_Pos     (18U)        
-#define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4_Pos     (19U)        
-#define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1_Pos     (20U)        
-#define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2_Pos     (21U)        
-#define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3_Pos     (22U)        
-#define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4_Pos     (23U)        
-#define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1_Pos     (24U)        
-#define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2_Pos     (25U)        
-#define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3_Pos     (26U)        
-#define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4_Pos     (27U)        
-#define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1_Pos     (28U)        
-#define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2_Pos     (29U)        
-#define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3_Pos     (30U)        
-#define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4_Pos     (31U)        
-#define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1_Pos     (0U)         
-#define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2_Pos     (1U)         
-#define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3_Pos     (2U)         
-#define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4_Pos     (3U)         
-#define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1_Pos     (4U)         
-#define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2_Pos     (5U)         
-#define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3_Pos     (6U)         
-#define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4_Pos     (7U)         
-#define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1_Pos     (8U)         
-#define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2_Pos     (9U)         
-#define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3_Pos     (10U)        
-#define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4_Pos     (11U)        
-#define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1_Pos     (12U)        
-#define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2_Pos     (13U)        
-#define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3_Pos     (14U)        
-#define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4_Pos     (15U)        
-#define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1_Pos     (16U)        
-#define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2_Pos     (17U)        
-#define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3_Pos     (18U)        
-#define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4_Pos     (19U)        
-#define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1_Pos     (20U)        
-#define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2_Pos     (21U)        
-#define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3_Pos     (22U)        
-#define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4_Pos     (23U)        
-#define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1_Pos     (24U)        
-#define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2_Pos     (25U)        
-#define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3_Pos     (26U)        
-#define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4_Pos     (27U)        
-#define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1_Pos     (28U)        
-#define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2_Pos     (29U)        
-#define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3_Pos     (30U)        
-#define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4_Pos     (31U)        
-#define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E_Pos       (0U)         
-#define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
-#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E_Pos       (1U)         
-#define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
-#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E_Pos       (2U)         
-#define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
-#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E_Pos       (3U)         
-#define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
-#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E_Pos       (4U)         
-#define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
-#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E_Pos       (5U)         
-#define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
-#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E_Pos       (6U)         
-#define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
-#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E_Pos       (7U)         
-#define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
-#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S_Pos       (16U)        
-#define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
-#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S_Pos       (17U)        
-#define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
-#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S_Pos       (18U)        
-#define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
-#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S_Pos       (19U)        
-#define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
-#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S_Pos       (20U)        
-#define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
-#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S_Pos       (21U)        
-#define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
-#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S_Pos       (22U)        
-#define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
-#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S_Pos       (23U)        
-#define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
-#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT_Pos       (0U)         
-#define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
-#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         USB Device General registers                       */
-/*                                                                            */
-/******************************************************************************/
-#define USB_BASE                              (0x40005C00U)                    /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR_Pos           (13U)       
-#define USB_PMAADDR_Msk           (0x20003UL << USB_PMAADDR_Pos)                /*!< 0x40006000 */
-#define USB_PMAADDR               USB_PMAADDR_Msk                              /*!< USB_IP Packet Memory Area base address */
-                                             
-#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
-#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
-#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
-#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
-#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
-#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
-#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
-
-/****************************  ISTR interrupt events  *************************/
-#define USB_ISTR_CTR                          ((uint16_t)0x8000U)              /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR                       ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR                          ((uint16_t)0x2000U)              /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP                         ((uint16_t)0x1000U)              /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP                         ((uint16_t)0x0800U)              /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET                        ((uint16_t)0x0400U)              /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF                          ((uint16_t)0x0200U)              /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF                         ((uint16_t)0x0100U)              /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ                        ((uint16_t)0x0080U)              /*!< LPM L1 state request  */
-#define USB_ISTR_DIR                          ((uint16_t)0x0010U)              /*!< DIRection of transaction (read-only bit)  */
-#define USB_ISTR_EP_ID                        ((uint16_t)0x000FU)              /*!< EndPoint IDentifier (read-only bit)  */
-
-#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
-#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
-#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
-#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
-#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
-#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
-#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
-#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
-/*************************  CNTR control register bits definitions  ***********/
-#define USB_CNTR_CTRM                         ((uint16_t)0x8000U)              /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM                      ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM                         ((uint16_t)0x2000U)              /*!< ERRor Mask */
-#define USB_CNTR_WKUPM                        ((uint16_t)0x1000U)              /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM                        ((uint16_t)0x0800U)              /*!< SUSPend Mask */
-#define USB_CNTR_RESETM                       ((uint16_t)0x0400U)              /*!< RESET Mask   */
-#define USB_CNTR_SOFM                         ((uint16_t)0x0200U)              /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM                        ((uint16_t)0x0100U)              /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM                       ((uint16_t)0x0080U)              /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME                     ((uint16_t)0x0020U)              /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME                       ((uint16_t)0x0010U)              /*!< RESUME request */
-#define USB_CNTR_FSUSP                        ((uint16_t)0x0008U)              /*!< Force SUSPend */
-#define USB_CNTR_LPMODE                       ((uint16_t)0x0004U)              /*!< Low-power MODE */
-#define USB_CNTR_PDWN                         ((uint16_t)0x0002U)              /*!< Power DoWN */
-#define USB_CNTR_FRES                         ((uint16_t)0x0001U)              /*!< Force USB RESet */
-/*************************  BCDR control register bits definitions  ***********/
-#define USB_BCDR_DPPU                         ((uint16_t)0x8000U)              /*!< DP Pull-up Enable */  
-#define USB_BCDR_PS2DET                       ((uint16_t)0x0080U)              /*!< PS2 port or proprietary charger detected */  
-#define USB_BCDR_SDET                         ((uint16_t)0x0040U)              /*!< Secondary detection (SD) status */  
-#define USB_BCDR_PDET                         ((uint16_t)0x0020U)              /*!< Primary detection (PD) status */ 
-#define USB_BCDR_DCDET                        ((uint16_t)0x0010U)              /*!< Data contact detection (DCD) status */ 
-#define USB_BCDR_SDEN                         ((uint16_t)0x0008U)              /*!< Secondary detection (SD) mode enable */ 
-#define USB_BCDR_PDEN                         ((uint16_t)0x0004U)              /*!< Primary detection (PD) mode enable */  
-#define USB_BCDR_DCDEN                        ((uint16_t)0x0002U)              /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN                        ((uint16_t)0x0001U)              /*!< Battery charging detector (BCD) enable */
-/***************************  LPM register bits definitions  ******************/
-#define USB_LPMCSR_BESL                       ((uint16_t)0x00F0U)              /*!< BESL value received with last ACKed LPM Token  */ 
-#define USB_LPMCSR_REMWAKE                    ((uint16_t)0x0008U)              /*!< bRemoteWake value received with last ACKed LPM Token */ 
-#define USB_LPMCSR_LPMACK                     ((uint16_t)0x0002U)              /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN                      ((uint16_t)0x0001U)              /*!< LPM support enable  */
-/********************  FNR Frame Number Register bit definitions   ************/
-#define USB_FNR_RXDP                          ((uint16_t)0x8000U)              /*!< status of D+ data line */
-#define USB_FNR_RXDM                          ((uint16_t)0x4000U)              /*!< status of D- data line */
-#define USB_FNR_LCK                           ((uint16_t)0x2000U)              /*!< LoCKed */
-#define USB_FNR_LSOF                          ((uint16_t)0x1800U)              /*!< Lost SOF */
-#define USB_FNR_FN                            ((uint16_t)0x07FFU)              /*!< Frame Number */
-/********************  DADDR Device ADDRess bit definitions    ****************/
-#define USB_DADDR_EF                          ((uint8_t)0x80U)                 /*!< USB device address Enable Function */
-#define USB_DADDR_ADD                         ((uint8_t)0x7FU)                 /*!< USB device address */
-/******************************  Endpoint register    *************************/
-#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
-#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
-#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
-#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
-#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
-#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
-#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
-#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
-/* bit positions */ 
-#define USB_EP_CTR_RX                         ((uint16_t)0x8000U)              /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX                        ((uint16_t)0x4000U)              /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT                         ((uint16_t)0x3000U)              /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP                          ((uint16_t)0x0800U)              /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD                        ((uint16_t)0x0600U)              /*!<  EndPoint TYPE */
-#define USB_EP_KIND                           ((uint16_t)0x0100U)              /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX                         ((uint16_t)0x0080U)              /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX                        ((uint16_t)0x0040U)              /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT                         ((uint16_t)0x0030U)              /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD                      ((uint16_t)0x000FU)              /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK                      ((uint16_t)0x0600U)              /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           ((uint16_t)0x0000U)              /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        ((uint16_t)0x0200U)              /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    ((uint16_t)0x0400U)              /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      ((uint16_t)0x0600U)              /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
-                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       ((uint16_t)0x0010U)              /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         ((uint16_t)0x0020U)              /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       ((uint16_t)0x0030U)              /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        ((uint16_t)0x0010U)              /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        ((uint16_t)0x0020U)              /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       ((uint16_t)0x1000U)              /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         ((uint16_t)0x2000U)              /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       ((uint16_t)0x3000U)              /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        ((uint16_t)0x1000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        ((uint16_t)0x2000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                                   ((INSTANCE) == I2C3))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                     ((INSTANCE) == I2C3))
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM7)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM3)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3) || \
-                                            ((INSTANCE) == TIM6) || \
-                                            ((INSTANCE) == TIM7))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                           ((INSTANCE) == TIM3))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-   (((((INSTANCE) == TIM2) ||                  \
-      ((INSTANCE) == TIM3))                    \
-     &&                                        \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM3)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM3)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM3)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM7)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                                ((INSTANCE) == TIM3))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/****************************** TSC Instances *********************************/
-#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART4) || \
-                                    ((INSTANCE) == USART5))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART4) || \
-                                     ((INSTANCE) == USART5))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART4) || \
-                                           ((INSTANCE) == USART5) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/******************************* USB Instances *******************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define LPUART1_IRQn                   RNG_LPUART1_IRQn
-#define AES_LPUART1_IRQn               RNG_LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           RNG_LPUART1_IRQn
-#define TIM6_IRQn                      TIM6_DAC_IRQn
-#define RCC_IRQn                       RCC_CRS_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             RNG_LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         RNG_LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     RNG_LPUART1_IRQHandler
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
-#define RCC_IRQHandler                 RCC_CRS_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L072xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h
deleted file mode 100644
index a66f1b0af4..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h
+++ /dev/null
@@ -1,7850 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l073xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l073xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l073xx
-  * @{
-  */
-    
-#ifndef __STM32L073xx_H
-#define __STM32L073xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1U /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l073xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  USART4_5_IRQn               = 14,     /*!< USART4 and USART5 Interrupt                             */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM7_IRQn                   = 18,     /*!< TIM7 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  I2C3_IRQn                   = 21,     /*!< I2C3 Interrupt                                          */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  RNG_LPUART1_IRQn            = 29,     /*!< RNG and LPUART1 Interrupts                              */
-  LCD_IRQn                    = 30,     /*!< LCD Interrupt                                           */
-  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Clock Recovery System 
-  */
-
-typedef struct 
-{
-__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
-__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
-__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
-__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
-} CRS_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;       /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;       /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;        /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;       /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;       /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;        /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;          /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-  __IO uint32_t RESERVED1[23]; /*!< Reserved1,                                   Address offset: 0x24 */
-  __IO uint32_t WRPR2;         /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-  __IO uint32_t WRP23;             /*!< write protection Bytes 2 and 3          Address offset: 0x0C */
-  __IO uint32_t WRP45;             /*!< write protection Bytes 4 and 5          Address offset: 0x10 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Random numbers generator
-  */
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
-  __IO uint16_t RESERVEDD;       /*!< Reserved */       
-  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
-  __IO uint16_t RESERVEDE;       /*!< Reserved */       
-} USB_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_BANK2_BASE (0x08080C00UL) /*!< DATA EEPROM BANK2 base address in the alias region */
-#define DATA_EEPROM_BANK1_END  (0x08080BFFUL) /*!< Program end DATA EEPROM BANK1 address */
-#define DATA_EEPROM_BANK2_END  (0x080817FFUL) /*!< Program end DATA EEPROM BANK2 address */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400UL)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APBPERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define USART4_BASE           (APBPERIPH_BASE + 0x00004C00UL)
-#define USART5_BASE           (APBPERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
-#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-#define I2C3_BASE             (APBPERIPH_BASE + 0x00007800UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000UL)
-#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (IOPPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CRS                 ((CRS_TypeDef *) CRS_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define USART4              ((USART_TypeDef *) USART4_BASE)
-#define USART5              ((USART_TypeDef *) USART5_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define USB                 ((USB_TypeDef *) USB_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16_Pos     (16U)      
-#define ADC_CHSELR_CHSEL16_Msk     (0x1UL << ADC_CHSELR_CHSEL16_Pos)            /*!< 0x00010000 */
-#define ADC_CHSELR_CHSEL16         ADC_CHSELR_CHSEL16_Msk                      /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_VLCDEN_Pos         (24U)      
-#define ADC_CCR_VLCDEN_Msk         (0x1UL << ADC_CCR_VLCDEN_Pos)                /*!< 0x01000000 */
-#define ADC_CCR_VLCDEN             ADC_CCR_VLCDEN_Msk                          /*!< Voltage LCD enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRS Clock Recovery System                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRS_CR register  *********************/
-#define CRS_CR_SYNCOKIE_Pos       (0U)        
-#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
-#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
-#define CRS_CR_SYNCWARNIE_Pos     (1U)        
-#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
-#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
-#define CRS_CR_ERRIE_Pos          (2U)        
-#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
-#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
-#define CRS_CR_ESYNCIE_Pos        (3U)        
-#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
-#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN_Pos            (5U)        
-#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
-#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
-#define CRS_CR_AUTOTRIMEN_Pos     (6U)        
-#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
-#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
-#define CRS_CR_SWSYNC_Pos         (7U)        
-#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
-#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
-#define CRS_CR_TRIM_Pos           (8U)        
-#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
-#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
-
-/*******************  Bit definition for CRS_CFGR register  *********************/
-#define CRS_CFGR_RELOAD_Pos       (0U)        
-#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
-#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
-#define CRS_CFGR_FELIM_Pos        (16U)       
-#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
-#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
-
-#define CRS_CFGR_SYNCDIV_Pos      (24U)       
-#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
-#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
-#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
-#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
-#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
-
-#define CRS_CFGR_SYNCSRC_Pos      (28U)       
-#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
-#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
-#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
-#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
-
-#define CRS_CFGR_SYNCPOL_Pos      (31U)       
-#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
-#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
-  
-/*******************  Bit definition for CRS_ISR register  *********************/
-#define CRS_ISR_SYNCOKF_Pos       (0U)        
-#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
-#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
-#define CRS_ISR_SYNCWARNF_Pos     (1U)        
-#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
-#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
-#define CRS_ISR_ERRF_Pos          (2U)        
-#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
-#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
-#define CRS_ISR_ESYNCF_Pos        (3U)        
-#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
-#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
-#define CRS_ISR_SYNCERR_Pos       (8U)        
-#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
-#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
-#define CRS_ISR_SYNCMISS_Pos      (9U)        
-#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
-#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
-#define CRS_ISR_TRIMOVF_Pos       (10U)       
-#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
-#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR_Pos         (15U)       
-#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
-#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
-#define CRS_ISR_FECAP_Pos         (16U)       
-#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
-#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
-
-/*******************  Bit definition for CRS_ICR register  *********************/
-#define CRS_ICR_SYNCOKC_Pos       (0U)        
-#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
-#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
-#define CRS_ICR_SYNCWARNC_Pos     (1U)        
-#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
-#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
-#define CRS_ICR_ERRC_Pos          (2U)        
-#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
-#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag             */
-#define CRS_ICR_ESYNCC_Pos        (3U)        
-#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
-#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define DAC_CHANNEL2_SUPPORT                       /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)      
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos            (1U)      
-#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos             (2U)      
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (3U)      
-#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)      
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)      
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)     
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)     
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun interrupt enable */
-
-#define DAC_CR_EN2_Pos              (16U)     
-#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
-#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos            (17U)     
-#define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
-#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!< DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos             (18U)     
-#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
-#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!< DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos            (19U)     
-#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
-#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos            (22U)     
-#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos            (24U)     
-#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos           (28U)     
-#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
-#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!< DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos        (29U)     
-#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!< DAC channel12DMA Underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)      
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)      
-#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!< DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)      
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)      
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)      
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos    (0U)      
-#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos    (4U)      
-#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos     (0U)      
-#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos    (0U)      
-#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos    (16U)     
-#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos    (4U)      
-#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos    (20U)     
-#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos     (0U)      
-#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos     (8U)      
-#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)      
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos       (0U)      
-#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!< DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)     
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos          (29U)     
-#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!< DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_DIV_ID_Pos               (12U)                           
-#define DBGMCU_IDCODE_DIV_ID_Msk               (0xFUL << DBGMCU_IDCODE_DIV_ID_Pos) /*!< 0x0000F000 */
-#define DBGMCU_IDCODE_DIV_ID                   DBGMCU_IDCODE_DIV_ID_Msk        /*!< Division Identifier */
-#define DBGMCU_IDCODE_MCD_DIV_ID_Pos           (13U)                           
-#define DBGMCU_IDCODE_MCD_DIV_ID_Msk           (0x3UL << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */
-#define DBGMCU_IDCODE_MCD_DIV_ID               DBGMCU_IDCODE_MCD_DIV_ID_Msk    /*!< MCD divsion ID is 6 */
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos       (1U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP           DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos       (5U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP           DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos       (23U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP           DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM24_Pos       (24U)         
-#define EXTI_IMR_IM24_Msk       (0x1UL << EXTI_IMR_IM24_Pos)                    /*!< 0x01000000 */
-#define EXTI_IMR_IM24           EXTI_IMR_IM24_Msk                              /*!< Interrupt Mask on line 24 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x37FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x37FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM24_Pos       (24U)         
-#define EXTI_EMR_EM24_Msk       (0x1UL << EXTI_EMR_EM24_Pos)                    /*!< 0x01000000 */
-#define EXTI_EMR_EM24           EXTI_EMR_EM24_Msk                              /*!< Event Mask on line 24 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos    (15U)    
-#define FLASH_PECR_PARALLBANK_Msk    (0x1UL << FLASH_PECR_PARALLBANK_Pos)       /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK        FLASH_PECR_PARALLBANK_Msk                 /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-#define FLASH_PECR_NZDISABLE_Pos     (22U)    
-#define FLASH_PECR_NZDISABLE_Msk     (0x1UL << FLASH_PECR_NZDISABLE_Pos)        /*!< 0x00400000 */
-#define FLASH_PECR_NZDISABLE         FLASH_PECR_NZDISABLE_Msk                  /*!< Non-Zero check disable */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_BFB2_Pos          (23U)    
-#define FLASH_OPTR_BFB2_Msk          (0x1UL << FLASH_OPTR_BFB2_Pos)             /*!< 0x00800000 */
-#define FLASH_OPTR_BFB2              FLASH_OPTR_BFB2_Msk                       /*!< BFB2 */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos            (0U)      
-#define LCD_CR_LCDEN_Msk            (0x1UL << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
-#define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos             (1U)      
-#define LCD_CR_VSEL_Msk             (0x1UL << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
-#define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos             (2U)      
-#define LCD_CR_DUTY_Msk             (0x7UL << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
-#define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0               (0x1UL << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
-#define LCD_CR_DUTY_1               (0x2UL << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
-#define LCD_CR_DUTY_2               (0x4UL << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos             (5U)      
-#define LCD_CR_BIAS_Msk             (0x3UL << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
-#define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0               (0x1UL << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
-#define LCD_CR_BIAS_1               (0x2UL << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos          (7U)      
-#define LCD_CR_MUX_SEG_Msk          (0x1UL << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
-
-#define LCD_CR_BUFEN_Pos            (8U)
-#define LCD_CR_BUFEN_Msk            (0x1UL << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
-#define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos              (0U)      
-#define LCD_FCR_HD_Msk              (0x1UL << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
-#define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos           (1U)      
-#define LCD_FCR_SOFIE_Msk           (0x1UL << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
-#define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos           (3U)      
-#define LCD_FCR_UDDIE_Msk           (0x1UL << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
-#define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos             (4U)      
-#define LCD_FCR_PON_Msk             (0x7UL << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
-#define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0               (0x1UL << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
-#define LCD_FCR_PON_1               (0x2UL << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
-#define LCD_FCR_PON_2               (0x4UL << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos            (7U)      
-#define LCD_FCR_DEAD_Msk            (0x7UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
-#define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0              (0x1UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1              (0x2UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2              (0x4UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos              (10U)     
-#define LCD_FCR_CC_Msk              (0x7UL << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
-#define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0                (0x1UL << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
-#define LCD_FCR_CC_1                (0x2UL << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
-#define LCD_FCR_CC_2                (0x4UL << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos          (13U)     
-#define LCD_FCR_BLINKF_Msk          (0x7UL << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0            (0x1UL << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1            (0x2UL << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2            (0x4UL << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos           (16U)     
-#define LCD_FCR_BLINK_Msk           (0x3UL << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
-#define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0             (0x1UL << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1             (0x2UL << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos             (18U)     
-#define LCD_FCR_DIV_Msk             (0xFUL << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
-#define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos              (22U)     
-#define LCD_FCR_PS_Msk              (0xFUL << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
-#define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos              (0U)      
-#define LCD_SR_ENS_Msk              (0x1UL << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
-#define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos              (1U)      
-#define LCD_SR_SOF_Msk              (0x1UL << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
-#define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos              (2U)      
-#define LCD_SR_UDR_Msk              (0x1UL << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
-#define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos              (3U)      
-#define LCD_SR_UDD_Msk              (0x1UL << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
-#define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos              (4U)      
-#define LCD_SR_RDY_Msk              (0x1UL << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
-#define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos            (5U)      
-#define LCD_SR_FCRSR_Msk            (0x1UL << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
-#define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos            (1U)      
-#define LCD_CLR_SOFC_Msk            (0x1UL << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
-#define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos            (3U)      
-#define LCD_CLR_UDDC_Msk            (0x1UL << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
-#define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos    (0U)      
-#define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)             
-#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)             
-#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)             
-#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)             
-#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)             
-#define FW_VDSSA_ADD_Msk     (0x3FFUL << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)             
-#define FW_VDSL_LENG_Msk     (0x3FFUL << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)             
-#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)             
-#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)             
-#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos          (10U)      
-#define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
-#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-#define RCC_MCO3_SUPPORT            /*!<Support MCO3 */
-#define RCC_MCO3_AF2_SUPPORT        /*!<Support MCO3 on Alternate Function AF0 */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC/LCD prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CRRCR register  *****************/
-#define RCC_CRRCR_HSI48ON_Pos            (0U) 
-#define RCC_CRRCR_HSI48ON_Msk            (0x1UL << RCC_CRRCR_HSI48ON_Pos)       /*!< 0x00000001 */
-#define RCC_CRRCR_HSI48ON                RCC_CRRCR_HSI48ON_Msk                 /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY_Pos           (1U) 
-#define RCC_CRRCR_HSI48RDY_Msk           (0x1UL << RCC_CRRCR_HSI48RDY_Pos)      /*!< 0x00000002 */
-#define RCC_CRRCR_HSI48RDY               RCC_CRRCR_HSI48RDY_Msk                /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48DIV6OUTEN_Pos     (2U) 
-#define RCC_CRRCR_HSI48DIV6OUTEN_Msk     (0x1UL << RCC_CRRCR_HSI48DIV6OUTEN_Pos) /*!< 0x00000004 */
-#define RCC_CRRCR_HSI48DIV6OUTEN         RCC_CRRCR_HSI48DIV6OUTEN_Msk          /*!< HSI 48MHz DIV6 out enable */
-#define RCC_CRRCR_HSI48CAL_Pos           (8U) 
-#define RCC_CRRCR_HSI48CAL_Msk           (0xFFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF00 */
-#define RCC_CRRCR_HSI48CAL               RCC_CRRCR_HSI48CAL_Msk                /*!< HSI 48MHz clock Calibration */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-#define RCC_CFGR_MCOSEL_HSI48_Pos            (27U)                             
-#define RCC_CFGR_MCOSEL_HSI48_Msk            (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
-#define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCOSEL_HSI48_Msk         /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE_Pos          (6U) 
-#define RCC_CIER_HSI48RDYIE_Msk          (0x1UL << RCC_CIER_HSI48RDYIE_Pos)     /*!< 0x00000040 */
-#define RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE_Msk               /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF_Pos           (6U) 
-#define RCC_CIFR_HSI48RDYF_Msk           (0x1UL << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000040 */
-#define RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF_Msk                /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC_Pos           (6U) 
-#define RCC_CICR_HSI48RDYC_Msk           (0x1UL << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000040 */
-#define RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC_Msk                /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPERST_Pos          (4U) 
-#define RCC_IOPRSTR_IOPERST_Msk          (0x1UL << RCC_IOPRSTR_IOPERST_Pos)     /*!< 0x00000010 */
-#define RCC_IOPRSTR_IOPERST              RCC_IOPRSTR_IOPERST_Msk               /*!< GPIO port E reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOERST                RCC_IOPRSTR_IOPERST        /*!< GPIO port E reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST_Pos           (16U)
-#define RCC_AHBRSTR_TSCRST_Msk           (0x1UL << RCC_AHBRSTR_TSCRST_Pos)      /*!< 0x00010000 */
-#define RCC_AHBRSTR_TSCRST               RCC_AHBRSTR_TSCRST_Msk                /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST_Pos           (20U)
-#define RCC_AHBRSTR_RNGRST_Msk           (0x1UL << RCC_AHBRSTR_RNGRST_Pos)      /*!< 0x00100000 */
-#define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk                /*!< RNG reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1UL << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos         (1U)
-#define RCC_APB1RSTR_TIM3RST_Msk         (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)    /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST             RCC_APB1RSTR_TIM3RST_Msk              /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos         (5U)
-#define RCC_APB1RSTR_TIM7RST_Msk         (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)    /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST             RCC_APB1RSTR_TIM7RST_Msk              /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos          (9U)
-#define RCC_APB1RSTR_LCDRST_Msk          (0x1UL << RCC_APB1RSTR_LCDRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST              RCC_APB1RSTR_LCDRST_Msk               /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_USART4RST_Pos       (19U)
-#define RCC_APB1RSTR_USART4RST_Msk       (0x1UL << RCC_APB1RSTR_USART4RST_Pos)  /*!< 0x00080000 */
-#define RCC_APB1RSTR_USART4RST           RCC_APB1RSTR_USART4RST_Msk            /*!< USART4 reset */
-#define RCC_APB1RSTR_USART5RST_Pos       (20U)
-#define RCC_APB1RSTR_USART5RST_Msk       (0x1UL << RCC_APB1RSTR_USART5RST_Pos)  /*!< 0x00100000 */
-#define RCC_APB1RSTR_USART5RST           RCC_APB1RSTR_USART5RST_Msk            /*!< USART5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos          (23U)
-#define RCC_APB1RSTR_USBRST_Msk          (0x1UL << RCC_APB1RSTR_USBRST_Pos)     /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST              RCC_APB1RSTR_USBRST_Msk               /*!< USB reset */
-#define RCC_APB1RSTR_CRSRST_Pos          (27U)
-#define RCC_APB1RSTR_CRSRST_Msk          (0x1UL << RCC_APB1RSTR_CRSRST_Pos)     /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST              RCC_APB1RSTR_CRSRST_Msk               /*!< CRS reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_DACRST_Pos          (29U)
-#define RCC_APB1RSTR_DACRST_Msk          (0x1UL << RCC_APB1RSTR_DACRST_Pos)     /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST              RCC_APB1RSTR_DACRST_Msk               /*!< DAC reset */
-#define RCC_APB1RSTR_I2C3RST_Pos         (30U)
-#define RCC_APB1RSTR_I2C3RST_Msk         (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)    /*!< 0x40000000 */
-#define RCC_APB1RSTR_I2C3RST             RCC_APB1RSTR_I2C3RST_Msk              /*!< I2C3  reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPEEN_Pos            (4U) 
-#define RCC_IOPENR_IOPEEN_Msk            (0x1UL << RCC_IOPENR_IOPEEN_Pos)       /*!< 0x00000010 */
-#define RCC_IOPENR_IOPEEN                RCC_IOPENR_IOPEEN_Msk                 /*!< GPIO port E clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOEEN                  RCC_IOPENR_IOPEEN        /*!< GPIO port E clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN_Pos             (16U)
-#define RCC_AHBENR_TSCEN_Msk             (0x1UL << RCC_AHBENR_TSCEN_Pos)        /*!< 0x00010000 */
-#define RCC_AHBENR_TSCEN                 RCC_AHBENR_TSCEN_Msk                  /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN_Pos             (20U)
-#define RCC_AHBENR_RNGEN_Msk             (0x1UL << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00100000 */
-#define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk                  /*!< RNG clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)
-#define RCC_APB2ENR_USART1EN_Msk         (0x1UL << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM3EN_Pos           (1U) 
-#define RCC_APB1ENR_TIM3EN_Msk           (0x1UL << RCC_APB1ENR_TIM3EN_Pos)      /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN               RCC_APB1ENR_TIM3EN_Msk                /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U) 
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1UL << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos           (5U) 
-#define RCC_APB1ENR_TIM7EN_Msk           (0x1UL << RCC_APB1ENR_TIM7EN_Pos)      /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN               RCC_APB1ENR_TIM7EN_Msk                /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos            (9U) 
-#define RCC_APB1ENR_LCDEN_Msk            (0x1UL << RCC_APB1ENR_LCDEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                RCC_APB1ENR_LCDEN_Msk                 /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1UL << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_USART4EN_Pos         (19U)
-#define RCC_APB1ENR_USART4EN_Msk         (0x1UL << RCC_APB1ENR_USART4EN_Pos)    /*!< 0x00080000 */
-#define RCC_APB1ENR_USART4EN             RCC_APB1ENR_USART4EN_Msk              /*!< USART4 clock enable */
-#define RCC_APB1ENR_USART5EN_Pos         (20U)
-#define RCC_APB1ENR_USART5EN_Msk         (0x1UL << RCC_APB1ENR_USART5EN_Pos)    /*!< 0x00100000 */
-#define RCC_APB1ENR_USART5EN             RCC_APB1ENR_USART5EN_Msk              /*!< USART5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1UL << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos            (23U)
-#define RCC_APB1ENR_USBEN_Msk            (0x1UL << RCC_APB1ENR_USBEN_Pos)       /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                RCC_APB1ENR_USBEN_Msk                 /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN_Pos            (27U)
-#define RCC_APB1ENR_CRSEN_Msk            (0x1UL << RCC_APB1ENR_CRSEN_Pos)       /*!< 0x08000000 */
-#define RCC_APB1ENR_CRSEN                RCC_APB1ENR_CRSEN_Msk                 /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN_Pos            (29U)
-#define RCC_APB1ENR_DACEN_Msk            (0x1UL << RCC_APB1ENR_DACEN_Pos)       /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                RCC_APB1ENR_DACEN_Msk                 /*!< DAC clock enable */
-#define RCC_APB1ENR_I2C3EN_Pos           (30U)
-#define RCC_APB1ENR_I2C3EN_Msk           (0x1UL << RCC_APB1ENR_I2C3EN_Pos)      /*!< 0x40000000 */
-#define RCC_APB1ENR_I2C3EN               RCC_APB1ENR_I2C3EN_Msk                /*!< I2C3 clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPESMEN_Pos        (4U) 
-#define RCC_IOPSMENR_IOPESMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos)   /*!< 0x00000010 */
-#define RCC_IOPSMENR_IOPESMEN            RCC_IOPSMENR_IOPESMEN_Msk             /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOESMEN              RCC_IOPSMENR_IOPESMEN        /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN_Pos         (16U)
-#define RCC_AHBSMENR_TSCSMEN_Msk         (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos)    /*!< 0x00010000 */
-#define RCC_AHBSMENR_TSCSMEN             RCC_AHBSMENR_TSCSMEN_Msk              /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN_Pos         (20U)
-#define RCC_AHBSMENR_RNGSMEN_Msk         (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00100000 */
-#define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk              /*!< RNG clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM3SMEN_Pos       (1U) 
-#define RCC_APB1SMENR_TIM3SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM3SMEN_Pos)  /*!< 0x00000002 */
-#define RCC_APB1SMENR_TIM3SMEN           RCC_APB1SMENR_TIM3SMEN_Msk            /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U) 
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM7SMEN_Pos       (5U) 
-#define RCC_APB1SMENR_TIM7SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM7SMEN_Pos)  /*!< 0x00000020 */
-#define RCC_APB1SMENR_TIM7SMEN           RCC_APB1SMENR_TIM7SMEN_Msk            /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LCDSMEN_Pos        (9U) 
-#define RCC_APB1SMENR_LCDSMEN_Msk        (0x1UL << RCC_APB1SMENR_LCDSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB1SMENR_LCDSMEN            RCC_APB1SMENR_LCDSMEN_Msk             /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART4SMEN_Pos     (19U)
-#define RCC_APB1SMENR_USART4SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1SMENR_USART4SMEN         RCC_APB1SMENR_USART4SMEN_Msk          /*!< USART4 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART5SMEN_Pos     (20U)
-#define RCC_APB1SMENR_USART5SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1SMENR_USART5SMEN         RCC_APB1SMENR_USART5SMEN_Msk          /*!< USART5 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN_Pos        (23U)
-#define RCC_APB1SMENR_USBSMEN_Msk        (0x1UL << RCC_APB1SMENR_USBSMEN_Pos)   /*!< 0x00800000 */
-#define RCC_APB1SMENR_USBSMEN            RCC_APB1SMENR_USBSMEN_Msk             /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN_Pos        (27U)
-#define RCC_APB1SMENR_CRSSMEN_Msk        (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos)   /*!< 0x08000000 */
-#define RCC_APB1SMENR_CRSSMEN            RCC_APB1SMENR_CRSSMEN_Msk             /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN_Pos        (29U)
-#define RCC_APB1SMENR_DACSMEN_Msk        (0x1UL << RCC_APB1SMENR_DACSMEN_Pos)   /*!< 0x20000000 */
-#define RCC_APB1SMENR_DACSMEN            RCC_APB1SMENR_DACSMEN_Msk             /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C3SMEN_Pos       (30U)
-#define RCC_APB1SMENR_I2C3SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C3SMEN_Pos)  /*!< 0x40000000 */
-#define RCC_APB1SMENR_I2C3SMEN           RCC_APB1SMENR_I2C3SMEN_Msk            /*!< I2C3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U) 
-#define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-/*!< I2C3 Clock source selection */
-#define RCC_CCIPR_I2C3SEL_Pos            (16U)
-#define RCC_CCIPR_I2C3SEL_Msk            (0x3UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00030000 */
-#define RCC_CCIPR_I2C3SEL                RCC_CCIPR_I2C3SEL_Msk                 /*!< I2C3SEL [1:0] bits */
-#define RCC_CCIPR_I2C3SEL_0              (0x1UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00010000 */
-#define RCC_CCIPR_I2C3SEL_1              (0x2UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00020000 */
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*!< HSI48 Clock source selection */ 
-#define RCC_CCIPR_HSI48SEL_Pos           (26U)
-#define RCC_CCIPR_HSI48SEL_Msk           (0x1UL << RCC_CCIPR_HSI48SEL_Pos)      /*!< 0x04000000 */
-#define RCC_CCIPR_HSI48SEL               RCC_CCIPR_HSI48SEL_Msk                /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Legacy defines */
-#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos    (2U)              
-#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
-#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
-#define RNG_CR_IE_Pos       (3U)              
-#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
-#define RNG_CR_IE           RNG_CR_IE_Msk                                      
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)              
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
-#define RNG_SR_CECS_Pos     (1U)              
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
-#define RNG_SR_SECS_Pos     (2U)              
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
-#define RNG_SR_CEIS_Pos     (5U)              
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
-#define RNG_SR_SEIS_Pos     (6U)              
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)      
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)      
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)      
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)      
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)      
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)      
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)     
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)     
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)     
-#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */
-#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)      
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)      
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)      
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_UFB_Pos                     (3U)                          
-#define SYSCFG_CFGR1_UFB_Msk                     (0x1UL << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */
-#define SYSCFG_CFGR1_UFB                         SYSCFG_CFGR1_UFB_Msk          /*!< User bank swapping */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_CAPA_Pos                    (1U)                          
-#define SYSCFG_CFGR2_CAPA_Msk                    (0x1FUL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x0000003E */
-#define SYSCFG_CFGR2_CAPA                        SYSCFG_CFGR2_CAPA_Msk         /*!< Connection of internal Vlcd rail to external capacitors */
-#define SYSCFG_CFGR2_CAPA_0                      (0x01UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR2_CAPA_1                      (0x02UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000004 */
-#define SYSCFG_CFGR2_CAPA_2                      (0x04UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000008 */
-#define SYSCFG_CFGR2_CAPA_3                      (0x08UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR2_CAPA_4                      (0x10UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-#define SYSCFG_CFGR2_I2C3_FMP_Pos                (14U)                         
-#define SYSCFG_CFGR2_I2C3_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */
-#define SYSCFG_CFGR2_I2C3_FMP                    SYSCFG_CFGR2_I2C3_FMP_Msk     /*!< I2C3 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD                  (0x00000003U)                 /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE                  (0x00000004U)                 /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD                  (0x00000030U)                 /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE                  (0x00000040U)                 /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE                  (0x00000400U)                 /*!< PE[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD                  (0x00003000U)                 /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE                  (0x00004000U)                 /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD                  (0x00000003U)                 /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE                  (0x00000004U)                 /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD                  (0x00000030U)                 /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE                  (0x00000040U)                 /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD                  (0x00000300U)                 /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE                  (0x00000400U)                 /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD                  (0x00003000U)                 /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE                  (0x00004000U)                 /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD                  (0x00000003U)                 /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE                  (0x00000004U)                 /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD                  (0x00000030U)                 /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE                  (0x00000040U)                 /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH                  (0x00000050U)                 /*!< PH[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD                 (0x00000300U)                 /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE                 (0x00000400U)                 /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH                 (0x00000500U)                 /*!< PH[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD                 (0x00003000U)                 /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE                 (0x00004000U)                 /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD                 (0x00000003U)                 /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE                 (0x00000004U)                 /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD                 (0x00000030U)                 /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE                 (0x00000040U)                 /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD                 (0x00000300U)                 /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE                 (0x00000400U)                 /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD                 (0x00003000U)                 /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE                 (0x00004000U)                 /*!< PE[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48_Pos             (13U)                         
-#define SYSCFG_CFGR3_ENREF_HSI48_Msk             (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR3_ENREF_HSI48                 SYSCFG_CFGR3_ENREF_HSI48_Msk  /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
-#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_REF_HSI48_RDYF           SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI_SUPPORT       /*!<Support remap HSI on TIM2 */
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-#define TIM3_OR_ETR_RMP_Pos      (0U)         
-#define TIM3_OR_ETR_RMP_Msk      (0x3UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000003 */
-#define TIM3_OR_ETR_RMP          TIM3_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
-#define TIM3_OR_ETR_RMP_0        (0x1UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM3_OR_ETR_RMP_1        (0x2UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM3_OR_TI1_RMP_Pos      (2U)         
-#define TIM3_OR_TI1_RMP_Msk      (0x1UL << TIM3_OR_TI1_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM3_OR_TI1_RMP          TIM3_OR_TI1_RMP_Msk                           /*!<TI1_RMP[2] bit                      */
-#define TIM3_OR_TI2_RMP_Pos      (3U)         
-#define TIM3_OR_TI2_RMP_Msk      (0x1UL << TIM3_OR_TI2_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM3_OR_TI2_RMP          TIM3_OR_TI2_RMP_Msk                           /*!<TI2_RMP[3] bit                      */
-#define TIM3_OR_TI4_RMP_Pos      (4U)         
-#define TIM3_OR_TI4_RMP_Msk      (0x1UL << TIM3_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-#define TIM3_OR_TI4_RMP          TIM3_OR_TI4_RMP_Msk                           /*!<TI4_RMP[4] bit                      */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE_Pos          (0U)         
-#define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
-#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
-#define TSC_CR_START_Pos         (1U)         
-#define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
-#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
-#define TSC_CR_AM_Pos            (2U)         
-#define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
-#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL_Pos       (3U)         
-#define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
-#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF_Pos         (4U)         
-#define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
-#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
-
-#define TSC_CR_MCV_Pos           (5U)         
-#define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
-#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
-#define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
-#define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
-
-#define TSC_CR_PGPSC_Pos         (12U)        
-#define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
-#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
-#define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
-#define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
-
-#define TSC_CR_SSPSC_Pos         (15U)        
-#define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
-#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE_Pos           (16U)        
-#define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
-#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD_Pos           (17U)        
-#define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
-#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
-#define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
-#define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
-#define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
-#define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
-#define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
-#define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
-
-#define TSC_CR_CTPL_Pos          (24U)        
-#define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
-#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
-#define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
-#define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
-#define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
-
-#define TSC_CR_CTPH_Pos          (28U)        
-#define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
-#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
-#define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
-#define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
-#define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE_Pos        (0U)         
-#define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
-#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE_Pos        (1U)         
-#define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
-#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC_Pos        (0U)         
-#define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
-#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC_Pos        (1U)         
-#define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
-#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF_Pos         (0U)         
-#define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
-#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
-#define TSC_ISR_MCEF_Pos         (1U)         
-#define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
-#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1_Pos     (0U)         
-#define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2_Pos     (1U)         
-#define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3_Pos     (2U)         
-#define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4_Pos     (3U)         
-#define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1_Pos     (4U)         
-#define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2_Pos     (5U)         
-#define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3_Pos     (6U)         
-#define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4_Pos     (7U)         
-#define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1_Pos     (8U)         
-#define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2_Pos     (9U)         
-#define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3_Pos     (10U)        
-#define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4_Pos     (11U)        
-#define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1_Pos     (12U)        
-#define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2_Pos     (13U)        
-#define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3_Pos     (14U)        
-#define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4_Pos     (15U)        
-#define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1_Pos     (16U)        
-#define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2_Pos     (17U)        
-#define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3_Pos     (18U)        
-#define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4_Pos     (19U)        
-#define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1_Pos     (20U)        
-#define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2_Pos     (21U)        
-#define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3_Pos     (22U)        
-#define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4_Pos     (23U)        
-#define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1_Pos     (24U)        
-#define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2_Pos     (25U)        
-#define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3_Pos     (26U)        
-#define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4_Pos     (27U)        
-#define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1_Pos     (28U)        
-#define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2_Pos     (29U)        
-#define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3_Pos     (30U)        
-#define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4_Pos     (31U)        
-#define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1_Pos    (0U)         
-#define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
-#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2_Pos    (1U)         
-#define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
-#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3_Pos    (2U)         
-#define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
-#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4_Pos    (3U)         
-#define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
-#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1_Pos    (4U)         
-#define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
-#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2_Pos    (5U)         
-#define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
-#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3_Pos    (6U)         
-#define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
-#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4_Pos    (7U)         
-#define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
-#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1_Pos    (8U)         
-#define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
-#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2_Pos    (9U)         
-#define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
-#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3_Pos    (10U)        
-#define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
-#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4_Pos    (11U)        
-#define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
-#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1_Pos    (12U)        
-#define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
-#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2_Pos    (13U)        
-#define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
-#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3_Pos    (14U)        
-#define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
-#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4_Pos    (15U)        
-#define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
-#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1_Pos    (16U)        
-#define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
-#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2_Pos    (17U)        
-#define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
-#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3_Pos    (18U)        
-#define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
-#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4_Pos    (19U)        
-#define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
-#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1_Pos    (20U)        
-#define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
-#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2_Pos    (21U)        
-#define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
-#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3_Pos    (22U)        
-#define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
-#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4_Pos    (23U)        
-#define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
-#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1_Pos    (24U)        
-#define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
-#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2_Pos    (25U)        
-#define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
-#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3_Pos    (26U)        
-#define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
-#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4_Pos    (27U)        
-#define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
-#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1_Pos    (28U)        
-#define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
-#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2_Pos    (29U)        
-#define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
-#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3_Pos    (30U)        
-#define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
-#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4_Pos    (31U)        
-#define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
-#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1_Pos     (0U)         
-#define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2_Pos     (1U)         
-#define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3_Pos     (2U)         
-#define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4_Pos     (3U)         
-#define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1_Pos     (4U)         
-#define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2_Pos     (5U)         
-#define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3_Pos     (6U)         
-#define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4_Pos     (7U)         
-#define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1_Pos     (8U)         
-#define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2_Pos     (9U)         
-#define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3_Pos     (10U)        
-#define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4_Pos     (11U)        
-#define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1_Pos     (12U)        
-#define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2_Pos     (13U)        
-#define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3_Pos     (14U)        
-#define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4_Pos     (15U)        
-#define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1_Pos     (16U)        
-#define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2_Pos     (17U)        
-#define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3_Pos     (18U)        
-#define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4_Pos     (19U)        
-#define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1_Pos     (20U)        
-#define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2_Pos     (21U)        
-#define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3_Pos     (22U)        
-#define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4_Pos     (23U)        
-#define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1_Pos     (24U)        
-#define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2_Pos     (25U)        
-#define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3_Pos     (26U)        
-#define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4_Pos     (27U)        
-#define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1_Pos     (28U)        
-#define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2_Pos     (29U)        
-#define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3_Pos     (30U)        
-#define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4_Pos     (31U)        
-#define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1_Pos     (0U)         
-#define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2_Pos     (1U)         
-#define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3_Pos     (2U)         
-#define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4_Pos     (3U)         
-#define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1_Pos     (4U)         
-#define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2_Pos     (5U)         
-#define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3_Pos     (6U)         
-#define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4_Pos     (7U)         
-#define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1_Pos     (8U)         
-#define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2_Pos     (9U)         
-#define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3_Pos     (10U)        
-#define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4_Pos     (11U)        
-#define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1_Pos     (12U)        
-#define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2_Pos     (13U)        
-#define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3_Pos     (14U)        
-#define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4_Pos     (15U)        
-#define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1_Pos     (16U)        
-#define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2_Pos     (17U)        
-#define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3_Pos     (18U)        
-#define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4_Pos     (19U)        
-#define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1_Pos     (20U)        
-#define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2_Pos     (21U)        
-#define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3_Pos     (22U)        
-#define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4_Pos     (23U)        
-#define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1_Pos     (24U)        
-#define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2_Pos     (25U)        
-#define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3_Pos     (26U)        
-#define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4_Pos     (27U)        
-#define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1_Pos     (28U)        
-#define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2_Pos     (29U)        
-#define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3_Pos     (30U)        
-#define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4_Pos     (31U)        
-#define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E_Pos       (0U)         
-#define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
-#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E_Pos       (1U)         
-#define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
-#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E_Pos       (2U)         
-#define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
-#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E_Pos       (3U)         
-#define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
-#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E_Pos       (4U)         
-#define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
-#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E_Pos       (5U)         
-#define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
-#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E_Pos       (6U)         
-#define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
-#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E_Pos       (7U)         
-#define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
-#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S_Pos       (16U)        
-#define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
-#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S_Pos       (17U)        
-#define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
-#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S_Pos       (18U)        
-#define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
-#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S_Pos       (19U)        
-#define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
-#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S_Pos       (20U)        
-#define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
-#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S_Pos       (21U)        
-#define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
-#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S_Pos       (22U)        
-#define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
-#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S_Pos       (23U)        
-#define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
-#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT_Pos       (0U)         
-#define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
-#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         USB Device General registers                       */
-/*                                                                            */
-/******************************************************************************/
-#define USB_BASE                              (0x40005C00U)                    /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR_Pos           (13U)       
-#define USB_PMAADDR_Msk           (0x20003UL << USB_PMAADDR_Pos)                /*!< 0x40006000 */
-#define USB_PMAADDR               USB_PMAADDR_Msk                              /*!< USB_IP Packet Memory Area base address */
-                                             
-#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
-#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
-#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
-#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
-#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
-#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
-#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
-
-/****************************  ISTR interrupt events  *************************/
-#define USB_ISTR_CTR                          ((uint16_t)0x8000U)              /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR                       ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR                          ((uint16_t)0x2000U)              /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP                         ((uint16_t)0x1000U)              /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP                         ((uint16_t)0x0800U)              /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET                        ((uint16_t)0x0400U)              /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF                          ((uint16_t)0x0200U)              /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF                         ((uint16_t)0x0100U)              /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ                        ((uint16_t)0x0080U)              /*!< LPM L1 state request  */
-#define USB_ISTR_DIR                          ((uint16_t)0x0010U)              /*!< DIRection of transaction (read-only bit)  */
-#define USB_ISTR_EP_ID                        ((uint16_t)0x000FU)              /*!< EndPoint IDentifier (read-only bit)  */
-
-#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
-#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
-#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
-#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
-#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
-#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
-#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
-#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
-/*************************  CNTR control register bits definitions  ***********/
-#define USB_CNTR_CTRM                         ((uint16_t)0x8000U)              /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM                      ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM                         ((uint16_t)0x2000U)              /*!< ERRor Mask */
-#define USB_CNTR_WKUPM                        ((uint16_t)0x1000U)              /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM                        ((uint16_t)0x0800U)              /*!< SUSPend Mask */
-#define USB_CNTR_RESETM                       ((uint16_t)0x0400U)              /*!< RESET Mask   */
-#define USB_CNTR_SOFM                         ((uint16_t)0x0200U)              /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM                        ((uint16_t)0x0100U)              /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM                       ((uint16_t)0x0080U)              /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME                     ((uint16_t)0x0020U)              /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME                       ((uint16_t)0x0010U)              /*!< RESUME request */
-#define USB_CNTR_FSUSP                        ((uint16_t)0x0008U)              /*!< Force SUSPend */
-#define USB_CNTR_LPMODE                       ((uint16_t)0x0004U)              /*!< Low-power MODE */
-#define USB_CNTR_PDWN                         ((uint16_t)0x0002U)              /*!< Power DoWN */
-#define USB_CNTR_FRES                         ((uint16_t)0x0001U)              /*!< Force USB RESet */
-/*************************  BCDR control register bits definitions  ***********/
-#define USB_BCDR_DPPU                         ((uint16_t)0x8000U)              /*!< DP Pull-up Enable */  
-#define USB_BCDR_PS2DET                       ((uint16_t)0x0080U)              /*!< PS2 port or proprietary charger detected */  
-#define USB_BCDR_SDET                         ((uint16_t)0x0040U)              /*!< Secondary detection (SD) status */  
-#define USB_BCDR_PDET                         ((uint16_t)0x0020U)              /*!< Primary detection (PD) status */ 
-#define USB_BCDR_DCDET                        ((uint16_t)0x0010U)              /*!< Data contact detection (DCD) status */ 
-#define USB_BCDR_SDEN                         ((uint16_t)0x0008U)              /*!< Secondary detection (SD) mode enable */ 
-#define USB_BCDR_PDEN                         ((uint16_t)0x0004U)              /*!< Primary detection (PD) mode enable */  
-#define USB_BCDR_DCDEN                        ((uint16_t)0x0002U)              /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN                        ((uint16_t)0x0001U)              /*!< Battery charging detector (BCD) enable */
-/***************************  LPM register bits definitions  ******************/
-#define USB_LPMCSR_BESL                       ((uint16_t)0x00F0U)              /*!< BESL value received with last ACKed LPM Token  */ 
-#define USB_LPMCSR_REMWAKE                    ((uint16_t)0x0008U)              /*!< bRemoteWake value received with last ACKed LPM Token */ 
-#define USB_LPMCSR_LPMACK                     ((uint16_t)0x0002U)              /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN                      ((uint16_t)0x0001U)              /*!< LPM support enable  */
-/********************  FNR Frame Number Register bit definitions   ************/
-#define USB_FNR_RXDP                          ((uint16_t)0x8000U)              /*!< status of D+ data line */
-#define USB_FNR_RXDM                          ((uint16_t)0x4000U)              /*!< status of D- data line */
-#define USB_FNR_LCK                           ((uint16_t)0x2000U)              /*!< LoCKed */
-#define USB_FNR_LSOF                          ((uint16_t)0x1800U)              /*!< Lost SOF */
-#define USB_FNR_FN                            ((uint16_t)0x07FFU)              /*!< Frame Number */
-/********************  DADDR Device ADDRess bit definitions    ****************/
-#define USB_DADDR_EF                          ((uint8_t)0x80U)                 /*!< USB device address Enable Function */
-#define USB_DADDR_ADD                         ((uint8_t)0x7FU)                 /*!< USB device address */
-/******************************  Endpoint register    *************************/
-#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
-#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
-#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
-#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
-#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
-#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
-#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
-#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
-/* bit positions */ 
-#define USB_EP_CTR_RX                         ((uint16_t)0x8000U)              /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX                        ((uint16_t)0x4000U)              /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT                         ((uint16_t)0x3000U)              /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP                          ((uint16_t)0x0800U)              /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD                        ((uint16_t)0x0600U)              /*!<  EndPoint TYPE */
-#define USB_EP_KIND                           ((uint16_t)0x0100U)              /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX                         ((uint16_t)0x0080U)              /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX                        ((uint16_t)0x0040U)              /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT                         ((uint16_t)0x0030U)              /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD                      ((uint16_t)0x000FU)              /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK                      ((uint16_t)0x0600U)              /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           ((uint16_t)0x0000U)              /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        ((uint16_t)0x0200U)              /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    ((uint16_t)0x0400U)              /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      ((uint16_t)0x0600U)              /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
-                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       ((uint16_t)0x0010U)              /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         ((uint16_t)0x0020U)              /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       ((uint16_t)0x0030U)              /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        ((uint16_t)0x0010U)              /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        ((uint16_t)0x0020U)              /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       ((uint16_t)0x1000U)              /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         ((uint16_t)0x2000U)              /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       ((uint16_t)0x3000U)              /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        ((uint16_t)0x1000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        ((uint16_t)0x2000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                                   ((INSTANCE) == I2C3))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                     ((INSTANCE) == I2C3))
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM7)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM3)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3) || \
-                                            ((INSTANCE) == TIM6) || \
-                                            ((INSTANCE) == TIM7))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                           ((INSTANCE) == TIM3))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-   (((((INSTANCE) == TIM2) ||                  \
-      ((INSTANCE) == TIM3))                    \
-     &&                                        \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM3)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM3)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM3)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM7)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                                ((INSTANCE) == TIM3))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/****************************** TSC Instances *********************************/
-#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART4) || \
-                                    ((INSTANCE) == USART5))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART4) || \
-                                     ((INSTANCE) == USART5))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART4) || \
-                                           ((INSTANCE) == USART5) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/******************************* USB Instances *******************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define LPUART1_IRQn                   RNG_LPUART1_IRQn
-#define AES_LPUART1_IRQn               RNG_LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           RNG_LPUART1_IRQn
-#define TIM6_IRQn                      TIM6_DAC_IRQn
-#define RCC_IRQn                       RCC_CRS_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             RNG_LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         RNG_LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     RNG_LPUART1_IRQHandler
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
-#define RCC_IRQHandler                 RCC_CRS_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L073xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h
deleted file mode 100644
index 376a1cd629..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h
+++ /dev/null
@@ -1,6642 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l081xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l081xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l081xx
-  * @{
-  */
-    
-#ifndef __STM32L081xx_H
-#define __STM32L081xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1U /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l081xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  USART4_5_IRQn               = 14,     /*!< USART4 and USART5 Interrupt                             */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
-  TIM6_IRQn                   = 17,     /*!< TIM6  Interrupt                                         */
-  TIM7_IRQn                   = 18,     /*!< TIM7 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  I2C3_IRQn                   = 21,     /*!< I2C3 Interrupt                                          */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  AES_LPUART1_IRQn            = 29,     /*!< AES and LPUART1 Interrupts                              */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;      /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;      /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;    /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;   /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;   /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;   /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;   /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;   /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;    /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;    /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;    /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;    /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-  __IO uint32_t RESERVED1[23]; /*!< Reserved1,                                   Address offset: 0x24 */
-  __IO uint32_t WRPR2;         /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-  __IO uint32_t WRP23;             /*!< write protection Bytes 2 and 3          Address offset: 0x0C */
-  __IO uint32_t WRP45;             /*!< write protection Bytes 4 and 5          Address offset: 0x10 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_BANK2_BASE (0x08080C00UL) /*!< DATA EEPROM BANK2 base address in the alias region */
-#define DATA_EEPROM_BANK1_END  (0x08080BFFUL) /*!< Program end DATA EEPROM BANK1 address */
-#define DATA_EEPROM_BANK2_END  (0x080817FFUL) /*!< Program end DATA EEPROM BANK2 address */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400UL)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define USART4_BASE           (APBPERIPH_BASE + 0x00004C00UL)
-#define USART5_BASE           (APBPERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-#define I2C3_BASE             (APBPERIPH_BASE + 0x00007800UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define AES_BASE              (AHBPERIPH_BASE + 0x00006000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (IOPPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define USART4              ((USART_TypeDef *) USART4_BASE)
-#define USART5              ((USART_TypeDef *) USART5_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define AES                 ((AES_TypeDef *) AES_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos            (0U)         
-#define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                       /*!< 0x00000001 */
-#define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos      (1U)         
-#define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000006 */
-#define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
-#define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos          (3U)         
-#define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                     /*!< 0x00000018 */
-#define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                     /*!< 0x00000008 */
-#define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                     /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos         (5U)         
-#define AES_CR_CHMOD_Msk         (0x3UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000060 */
-#define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0           (0x1UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000020 */
-#define AES_CR_CHMOD_1           (0x2UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000040 */
-
-#define AES_CR_CCFC_Pos          (7U)         
-#define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                     /*!< 0x00000080 */
-#define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos          (8U)         
-#define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                     /*!< 0x00000100 */
-#define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
-#define AES_CR_CCIE_Pos          (9U)         
-#define AES_CR_CCIE_Msk          (0x1UL << AES_CR_CCIE_Pos)                     /*!< 0x00000200 */
-#define AES_CR_CCIE              AES_CR_CCIE_Msk                               /*!< Computation Complete Interrupt Enable */
-#define AES_CR_ERRIE_Pos         (10U)        
-#define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                    /*!< 0x00000400 */
-#define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos       (11U)        
-#define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                  /*!< 0x00000800 */
-#define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< DMA ENable managing the data input phase */
-#define AES_CR_DMAOUTEN_Pos      (12U)        
-#define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                 /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos           (0U)         
-#define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                      /*!< 0x00000001 */
-#define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos         (1U)         
-#define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                    /*!< 0x00000002 */
-#define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos         (2U)         
-#define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                    /*!< 0x00000004 */
-#define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos             (0U)         
-#define AES_DINR_Msk             (0xFFFFUL << AES_DINR_Pos)                     /*!< 0x0000FFFF */
-#define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos            (0U)         
-#define AES_DOUTR_Msk            (0xFFFFUL << AES_DOUTR_Pos)                    /*!< 0x0000FFFF */
-#define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos            (0U)         
-#define AES_KEYR0_Msk            (0xFFFFUL << AES_KEYR0_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos            (0U)         
-#define AES_KEYR1_Msk            (0xFFFFUL << AES_KEYR1_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos            (0U)         
-#define AES_KEYR2_Msk            (0xFFFFUL << AES_KEYR2_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos            (0U)         
-#define AES_KEYR3_Msk            (0xFFFFUL << AES_KEYR3_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define AES_IVR0_Pos             (0U)         
-#define AES_IVR0_Msk             (0xFFFFUL << AES_IVR0_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define AES_IVR1_Pos             (0U)         
-#define AES_IVR1_Msk             (0xFFFFUL << AES_IVR1_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define AES_IVR2_Pos             (0U)         
-#define AES_IVR2_Msk             (0xFFFFUL << AES_IVR2_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define AES_IVR3_Pos             (0U)         
-#define AES_IVR3_Msk             (0xFFFFUL << AES_IVR3_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos       (1U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP           DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos       (5U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP           DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos       (23U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP           DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM24_Pos       (24U)         
-#define EXTI_IMR_IM24_Msk       (0x1UL << EXTI_IMR_IM24_Pos)                    /*!< 0x01000000 */
-#define EXTI_IMR_IM24           EXTI_IMR_IM24_Msk                              /*!< Interrupt Mask on line 24 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x37FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x37FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM24_Pos       (24U)         
-#define EXTI_EMR_EM24_Msk       (0x1UL << EXTI_EMR_EM24_Pos)                    /*!< 0x01000000 */
-#define EXTI_EMR_EM24           EXTI_EMR_EM24_Msk                              /*!< Event Mask on line 24 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos    (15U)    
-#define FLASH_PECR_PARALLBANK_Msk    (0x1UL << FLASH_PECR_PARALLBANK_Pos)       /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK        FLASH_PECR_PARALLBANK_Msk                 /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-#define FLASH_PECR_NZDISABLE_Pos     (22U)    
-#define FLASH_PECR_NZDISABLE_Msk     (0x1UL << FLASH_PECR_NZDISABLE_Pos)        /*!< 0x00400000 */
-#define FLASH_PECR_NZDISABLE         FLASH_PECR_NZDISABLE_Msk                  /*!< Non-Zero check disable */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_BFB2_Pos          (23U)    
-#define FLASH_OPTR_BFB2_Msk          (0x1UL << FLASH_OPTR_BFB2_Pos)             /*!< 0x00800000 */
-#define FLASH_OPTR_BFB2              FLASH_OPTR_BFB2_Msk                       /*!< BFB2 */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)             
-#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)             
-#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)             
-#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)             
-#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)             
-#define FW_VDSSA_ADD_Msk     (0x3FFUL << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)             
-#define FW_VDSL_LENG_Msk     (0x3FFUL << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)             
-#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)             
-#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)             
-#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos          (10U)      
-#define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
-#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-#define RCC_MCO3_SUPPORT            /*!<Support MCO3 */
-#define RCC_MCO3_AF2_SUPPORT        /*!<Support MCO3 on Alternate Function AF0 */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPERST_Pos          (4U) 
-#define RCC_IOPRSTR_IOPERST_Msk          (0x1UL << RCC_IOPRSTR_IOPERST_Pos)     /*!< 0x00000010 */
-#define RCC_IOPRSTR_IOPERST              RCC_IOPRSTR_IOPERST_Msk               /*!< GPIO port E reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOERST                RCC_IOPRSTR_IOPERST        /*!< GPIO port E reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_CRYPRST_Pos          (24U)
-#define RCC_AHBRSTR_CRYPRST_Msk          (0x1UL << RCC_AHBRSTR_CRYPRST_Pos)     /*!< 0x01000000 */
-#define RCC_AHBRSTR_CRYPRST              RCC_AHBRSTR_CRYPRST_Msk               /*!< Crypto reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1UL << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos         (1U)
-#define RCC_APB1RSTR_TIM3RST_Msk         (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)    /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST             RCC_APB1RSTR_TIM3RST_Msk              /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos         (5U)
-#define RCC_APB1RSTR_TIM7RST_Msk         (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)    /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST             RCC_APB1RSTR_TIM7RST_Msk              /*!< Timer 7 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_USART4RST_Pos       (19U)
-#define RCC_APB1RSTR_USART4RST_Msk       (0x1UL << RCC_APB1RSTR_USART4RST_Pos)  /*!< 0x00080000 */
-#define RCC_APB1RSTR_USART4RST           RCC_APB1RSTR_USART4RST_Msk            /*!< USART4 reset */
-#define RCC_APB1RSTR_USART5RST_Pos       (20U)
-#define RCC_APB1RSTR_USART5RST_Msk       (0x1UL << RCC_APB1RSTR_USART5RST_Pos)  /*!< 0x00100000 */
-#define RCC_APB1RSTR_USART5RST           RCC_APB1RSTR_USART5RST_Msk            /*!< USART5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_I2C3RST_Pos         (30U)
-#define RCC_APB1RSTR_I2C3RST_Msk         (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)    /*!< 0x40000000 */
-#define RCC_APB1RSTR_I2C3RST             RCC_APB1RSTR_I2C3RST_Msk              /*!< I2C3  reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPEEN_Pos            (4U) 
-#define RCC_IOPENR_IOPEEN_Msk            (0x1UL << RCC_IOPENR_IOPEEN_Pos)       /*!< 0x00000010 */
-#define RCC_IOPENR_IOPEEN                RCC_IOPENR_IOPEEN_Msk                 /*!< GPIO port E clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOEEN                  RCC_IOPENR_IOPEEN        /*!< GPIO port E clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_CRYPEN_Pos            (24U)
-#define RCC_AHBENR_CRYPEN_Msk            (0x1UL << RCC_AHBENR_CRYPEN_Pos)       /*!< 0x01000000 */
-#define RCC_AHBENR_CRYPEN                RCC_AHBENR_CRYPEN_Msk                 /*!< Crypto clock enable*/
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)
-#define RCC_APB2ENR_USART1EN_Msk         (0x1UL << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM3EN_Pos           (1U) 
-#define RCC_APB1ENR_TIM3EN_Msk           (0x1UL << RCC_APB1ENR_TIM3EN_Pos)      /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN               RCC_APB1ENR_TIM3EN_Msk                /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U) 
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1UL << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos           (5U) 
-#define RCC_APB1ENR_TIM7EN_Msk           (0x1UL << RCC_APB1ENR_TIM7EN_Pos)      /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN               RCC_APB1ENR_TIM7EN_Msk                /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1UL << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_USART4EN_Pos         (19U)
-#define RCC_APB1ENR_USART4EN_Msk         (0x1UL << RCC_APB1ENR_USART4EN_Pos)    /*!< 0x00080000 */
-#define RCC_APB1ENR_USART4EN             RCC_APB1ENR_USART4EN_Msk              /*!< USART4 clock enable */
-#define RCC_APB1ENR_USART5EN_Pos         (20U)
-#define RCC_APB1ENR_USART5EN_Msk         (0x1UL << RCC_APB1ENR_USART5EN_Pos)    /*!< 0x00100000 */
-#define RCC_APB1ENR_USART5EN             RCC_APB1ENR_USART5EN_Msk              /*!< USART5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1UL << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_I2C3EN_Pos           (30U)
-#define RCC_APB1ENR_I2C3EN_Msk           (0x1UL << RCC_APB1ENR_I2C3EN_Pos)      /*!< 0x40000000 */
-#define RCC_APB1ENR_I2C3EN               RCC_APB1ENR_I2C3EN_Msk                /*!< I2C3 clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPESMEN_Pos        (4U) 
-#define RCC_IOPSMENR_IOPESMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos)   /*!< 0x00000010 */
-#define RCC_IOPSMENR_IOPESMEN            RCC_IOPSMENR_IOPESMEN_Msk             /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOESMEN              RCC_IOPSMENR_IOPESMEN        /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRYPSMEN_Pos        (24U)
-#define RCC_AHBSMENR_CRYPSMEN_Msk        (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos)   /*!< 0x01000000 */
-#define RCC_AHBSMENR_CRYPSMEN            RCC_AHBSMENR_CRYPSMEN_Msk             /*!< Crypto clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM3SMEN_Pos       (1U) 
-#define RCC_APB1SMENR_TIM3SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM3SMEN_Pos)  /*!< 0x00000002 */
-#define RCC_APB1SMENR_TIM3SMEN           RCC_APB1SMENR_TIM3SMEN_Msk            /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U) 
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM7SMEN_Pos       (5U) 
-#define RCC_APB1SMENR_TIM7SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM7SMEN_Pos)  /*!< 0x00000020 */
-#define RCC_APB1SMENR_TIM7SMEN           RCC_APB1SMENR_TIM7SMEN_Msk            /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART4SMEN_Pos     (19U)
-#define RCC_APB1SMENR_USART4SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1SMENR_USART4SMEN         RCC_APB1SMENR_USART4SMEN_Msk          /*!< USART4 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART5SMEN_Pos     (20U)
-#define RCC_APB1SMENR_USART5SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1SMENR_USART5SMEN         RCC_APB1SMENR_USART5SMEN_Msk          /*!< USART5 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C3SMEN_Pos       (30U)
-#define RCC_APB1SMENR_I2C3SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C3SMEN_Pos)  /*!< 0x40000000 */
-#define RCC_APB1SMENR_I2C3SMEN           RCC_APB1SMENR_I2C3SMEN_Msk            /*!< I2C3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U) 
-#define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-/*!< I2C3 Clock source selection */
-#define RCC_CCIPR_I2C3SEL_Pos            (16U)
-#define RCC_CCIPR_I2C3SEL_Msk            (0x3UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00030000 */
-#define RCC_CCIPR_I2C3SEL                RCC_CCIPR_I2C3SEL_Msk                 /*!< I2C3SEL [1:0] bits */
-#define RCC_CCIPR_I2C3SEL_0              (0x1UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00010000 */
-#define RCC_CCIPR_I2C3SEL_1              (0x2UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00020000 */
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)      
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)      
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)      
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)      
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)      
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)      
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)     
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)     
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)     
-#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */
-#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)      
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)      
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)      
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_UFB_Pos                     (3U)                          
-#define SYSCFG_CFGR1_UFB_Msk                     (0x1UL << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */
-#define SYSCFG_CFGR1_UFB                         SYSCFG_CFGR1_UFB_Msk          /*!< User bank swapping */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-#define SYSCFG_CFGR2_I2C3_FMP_Pos                (14U)                         
-#define SYSCFG_CFGR2_I2C3_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */
-#define SYSCFG_CFGR2_I2C3_FMP                    SYSCFG_CFGR2_I2C3_FMP_Msk     /*!< I2C3 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD                  (0x00000003U)                 /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE                  (0x00000004U)                 /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD                  (0x00000030U)                 /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE                  (0x00000040U)                 /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE                  (0x00000400U)                 /*!< PE[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD                  (0x00003000U)                 /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE                  (0x00004000U)                 /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD                  (0x00000003U)                 /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE                  (0x00000004U)                 /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD                  (0x00000030U)                 /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE                  (0x00000040U)                 /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD                  (0x00000300U)                 /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE                  (0x00000400U)                 /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD                  (0x00003000U)                 /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE                  (0x00004000U)                 /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD                  (0x00000003U)                 /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE                  (0x00000004U)                 /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD                  (0x00000030U)                 /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE                  (0x00000040U)                 /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH                  (0x00000050U)                 /*!< PH[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD                 (0x00000300U)                 /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE                 (0x00000400U)                 /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH                 (0x00000500U)                 /*!< PH[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD                 (0x00003000U)                 /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE                 (0x00004000U)                 /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD                 (0x00000003U)                 /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE                 (0x00000004U)                 /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD                 (0x00000030U)                 /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE                 (0x00000040U)                 /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD                 (0x00000300U)                 /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE                 (0x00000400U)                 /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD                 (0x00003000U)                 /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE                 (0x00004000U)                 /*!< PE[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI_SUPPORT       /*!<Support remap HSI on TIM2 */
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-#define TIM3_OR_ETR_RMP_Pos      (0U)         
-#define TIM3_OR_ETR_RMP_Msk      (0x3UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000003 */
-#define TIM3_OR_ETR_RMP          TIM3_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
-#define TIM3_OR_ETR_RMP_0        (0x1UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM3_OR_ETR_RMP_1        (0x2UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM3_OR_TI1_RMP_Pos      (2U)         
-#define TIM3_OR_TI1_RMP_Msk      (0x1UL << TIM3_OR_TI1_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM3_OR_TI1_RMP          TIM3_OR_TI1_RMP_Msk                           /*!<TI1_RMP[2] bit                      */
-#define TIM3_OR_TI2_RMP_Pos      (3U)         
-#define TIM3_OR_TI2_RMP_Msk      (0x1UL << TIM3_OR_TI2_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM3_OR_TI2_RMP          TIM3_OR_TI2_RMP_Msk                           /*!<TI2_RMP[3] bit                      */
-#define TIM3_OR_TI4_RMP_Pos      (4U)         
-#define TIM3_OR_TI4_RMP_Msk      (0x1UL << TIM3_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-#define TIM3_OR_TI4_RMP          TIM3_OR_TI4_RMP_Msk                           /*!<TI4_RMP[4] bit                      */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* AES Instances ********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                                   ((INSTANCE) == I2C3))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                     ((INSTANCE) == I2C3))
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM7)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM3)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3) || \
-                                            ((INSTANCE) == TIM6) || \
-                                            ((INSTANCE) == TIM7))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                           ((INSTANCE) == TIM3))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-   (((((INSTANCE) == TIM2) ||                  \
-      ((INSTANCE) == TIM3))                    \
-     &&                                        \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM3)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM3)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM3)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM7)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                                ((INSTANCE) == TIM3))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART4) || \
-                                    ((INSTANCE) == USART5))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART4) || \
-                                     ((INSTANCE) == USART5))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART4) || \
-                                           ((INSTANCE) == USART5) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define RNG_LPUART1_IRQn               AES_LPUART1_IRQn
-#define LPUART1_IRQn                   AES_LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           AES_LPUART1_IRQn
-#define TIM6_DAC_IRQn                  TIM6_IRQn
-#define RCC_CRS_IRQn                   RCC_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             AES_LPUART1_IRQHandler
-#define RNG_LPUART1_IRQHandler         AES_LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     AES_LPUART1_IRQHandler
-#define TIM6_DAC_IRQHandler            TIM6_IRQHandler
-#define RCC_CRS_IRQHandler             RCC_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L081xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h
deleted file mode 100644
index 4df3fe4b48..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h
+++ /dev/null
@@ -1,7828 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l082xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l082xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l082xx
-  * @{
-  */
-    
-#ifndef __STM32L082xx_H
-#define __STM32L082xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1U /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l082xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  USART4_5_IRQn               = 14,     /*!< USART4 and USART5 Interrupt                             */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM7_IRQn                   = 18,     /*!< TIM7 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  I2C3_IRQn                   = 21,     /*!< I2C3 Interrupt                                          */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  AES_RNG_LPUART1_IRQn        = 29,     /*!< AES and RNG and LPUART1 Interrupts                      */
-  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;      /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;      /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;    /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;   /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;   /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;   /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;   /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;   /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;    /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;    /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;    /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;    /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Clock Recovery System 
-  */
-
-typedef struct 
-{
-__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
-__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
-__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
-__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
-} CRS_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;       /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;       /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;        /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;       /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;       /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;        /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;          /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-  __IO uint32_t RESERVED1[23]; /*!< Reserved1,                                   Address offset: 0x24 */
-  __IO uint32_t WRPR2;         /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-  __IO uint32_t WRP23;             /*!< write protection Bytes 2 and 3          Address offset: 0x0C */
-  __IO uint32_t WRP45;             /*!< write protection Bytes 4 and 5          Address offset: 0x10 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Random numbers generator
-  */
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
-  __IO uint16_t RESERVEDD;       /*!< Reserved */       
-  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
-  __IO uint16_t RESERVEDE;       /*!< Reserved */       
-} USB_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_BANK2_BASE (0x08080C00UL) /*!< DATA EEPROM BANK2 base address in the alias region */
-#define DATA_EEPROM_BANK1_END  (0x08080BFFUL) /*!< Program end DATA EEPROM BANK1 address */
-#define DATA_EEPROM_BANK2_END  (0x080817FFUL) /*!< Program end DATA EEPROM BANK2 address */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400UL)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define USART4_BASE           (APBPERIPH_BASE + 0x00004C00UL)
-#define USART5_BASE           (APBPERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
-#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-#define I2C3_BASE             (APBPERIPH_BASE + 0x00007800UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000UL)
-#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000UL)
-#define AES_BASE              (AHBPERIPH_BASE + 0x00006000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (IOPPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CRS                 ((CRS_TypeDef *) CRS_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define USART4              ((USART_TypeDef *) USART4_BASE)
-#define USART5              ((USART_TypeDef *) USART5_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define AES                 ((AES_TypeDef *) AES_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define USB                 ((USB_TypeDef *) USB_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos            (0U)         
-#define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                       /*!< 0x00000001 */
-#define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos      (1U)         
-#define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000006 */
-#define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
-#define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos          (3U)         
-#define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                     /*!< 0x00000018 */
-#define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                     /*!< 0x00000008 */
-#define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                     /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos         (5U)         
-#define AES_CR_CHMOD_Msk         (0x3UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000060 */
-#define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0           (0x1UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000020 */
-#define AES_CR_CHMOD_1           (0x2UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000040 */
-
-#define AES_CR_CCFC_Pos          (7U)         
-#define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                     /*!< 0x00000080 */
-#define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos          (8U)         
-#define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                     /*!< 0x00000100 */
-#define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
-#define AES_CR_CCIE_Pos          (9U)         
-#define AES_CR_CCIE_Msk          (0x1UL << AES_CR_CCIE_Pos)                     /*!< 0x00000200 */
-#define AES_CR_CCIE              AES_CR_CCIE_Msk                               /*!< Computation Complete Interrupt Enable */
-#define AES_CR_ERRIE_Pos         (10U)        
-#define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                    /*!< 0x00000400 */
-#define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos       (11U)        
-#define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                  /*!< 0x00000800 */
-#define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< DMA ENable managing the data input phase */
-#define AES_CR_DMAOUTEN_Pos      (12U)        
-#define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                 /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos           (0U)         
-#define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                      /*!< 0x00000001 */
-#define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos         (1U)         
-#define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                    /*!< 0x00000002 */
-#define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos         (2U)         
-#define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                    /*!< 0x00000004 */
-#define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos             (0U)         
-#define AES_DINR_Msk             (0xFFFFUL << AES_DINR_Pos)                     /*!< 0x0000FFFF */
-#define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos            (0U)         
-#define AES_DOUTR_Msk            (0xFFFFUL << AES_DOUTR_Pos)                    /*!< 0x0000FFFF */
-#define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos            (0U)         
-#define AES_KEYR0_Msk            (0xFFFFUL << AES_KEYR0_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos            (0U)         
-#define AES_KEYR1_Msk            (0xFFFFUL << AES_KEYR1_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos            (0U)         
-#define AES_KEYR2_Msk            (0xFFFFUL << AES_KEYR2_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos            (0U)         
-#define AES_KEYR3_Msk            (0xFFFFUL << AES_KEYR3_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define AES_IVR0_Pos             (0U)         
-#define AES_IVR0_Msk             (0xFFFFUL << AES_IVR0_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define AES_IVR1_Pos             (0U)         
-#define AES_IVR1_Msk             (0xFFFFUL << AES_IVR1_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define AES_IVR2_Pos             (0U)         
-#define AES_IVR2_Msk             (0xFFFFUL << AES_IVR2_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define AES_IVR3_Pos             (0U)         
-#define AES_IVR3_Msk             (0xFFFFUL << AES_IVR3_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRS Clock Recovery System                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRS_CR register  *********************/
-#define CRS_CR_SYNCOKIE_Pos       (0U)        
-#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
-#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
-#define CRS_CR_SYNCWARNIE_Pos     (1U)        
-#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
-#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
-#define CRS_CR_ERRIE_Pos          (2U)        
-#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
-#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
-#define CRS_CR_ESYNCIE_Pos        (3U)        
-#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
-#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN_Pos            (5U)        
-#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
-#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
-#define CRS_CR_AUTOTRIMEN_Pos     (6U)        
-#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
-#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
-#define CRS_CR_SWSYNC_Pos         (7U)        
-#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
-#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
-#define CRS_CR_TRIM_Pos           (8U)        
-#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
-#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
-
-/*******************  Bit definition for CRS_CFGR register  *********************/
-#define CRS_CFGR_RELOAD_Pos       (0U)        
-#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
-#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
-#define CRS_CFGR_FELIM_Pos        (16U)       
-#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
-#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
-
-#define CRS_CFGR_SYNCDIV_Pos      (24U)       
-#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
-#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
-#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
-#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
-#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
-
-#define CRS_CFGR_SYNCSRC_Pos      (28U)       
-#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
-#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
-#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
-#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
-
-#define CRS_CFGR_SYNCPOL_Pos      (31U)       
-#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
-#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
-  
-/*******************  Bit definition for CRS_ISR register  *********************/
-#define CRS_ISR_SYNCOKF_Pos       (0U)        
-#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
-#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
-#define CRS_ISR_SYNCWARNF_Pos     (1U)        
-#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
-#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
-#define CRS_ISR_ERRF_Pos          (2U)        
-#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
-#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
-#define CRS_ISR_ESYNCF_Pos        (3U)        
-#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
-#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
-#define CRS_ISR_SYNCERR_Pos       (8U)        
-#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
-#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
-#define CRS_ISR_SYNCMISS_Pos      (9U)        
-#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
-#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
-#define CRS_ISR_TRIMOVF_Pos       (10U)       
-#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
-#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR_Pos         (15U)       
-#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
-#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
-#define CRS_ISR_FECAP_Pos         (16U)       
-#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
-#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
-
-/*******************  Bit definition for CRS_ICR register  *********************/
-#define CRS_ICR_SYNCOKC_Pos       (0U)        
-#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
-#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
-#define CRS_ICR_SYNCWARNC_Pos     (1U)        
-#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
-#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
-#define CRS_ICR_ERRC_Pos          (2U)        
-#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
-#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag             */
-#define CRS_ICR_ESYNCC_Pos        (3U)        
-#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
-#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define DAC_CHANNEL2_SUPPORT                       /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)      
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos            (1U)      
-#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos             (2U)      
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (3U)      
-#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)      
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)      
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)     
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)     
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun interrupt enable */
-
-#define DAC_CR_EN2_Pos              (16U)     
-#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
-#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos            (17U)     
-#define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
-#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!< DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos             (18U)     
-#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
-#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!< DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos            (19U)     
-#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
-#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos            (22U)     
-#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos            (24U)     
-#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos           (28U)     
-#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
-#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!< DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos        (29U)     
-#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!< DAC channel12DMA Underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)      
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)      
-#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!< DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)      
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)      
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)      
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos    (0U)      
-#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos    (4U)      
-#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos     (0U)      
-#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos    (0U)      
-#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos    (16U)     
-#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos    (4U)      
-#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos    (20U)     
-#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos     (0U)      
-#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos     (8U)      
-#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)      
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos       (0U)      
-#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!< DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)     
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos          (29U)     
-#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!< DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_DIV_ID_Pos               (12U)                           
-#define DBGMCU_IDCODE_DIV_ID_Msk               (0xFUL << DBGMCU_IDCODE_DIV_ID_Pos) /*!< 0x0000F000 */
-#define DBGMCU_IDCODE_DIV_ID                   DBGMCU_IDCODE_DIV_ID_Msk        /*!< Division Identifier */
-#define DBGMCU_IDCODE_MCD_DIV_ID_Pos           (13U)                           
-#define DBGMCU_IDCODE_MCD_DIV_ID_Msk           (0x3UL << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */
-#define DBGMCU_IDCODE_MCD_DIV_ID               DBGMCU_IDCODE_MCD_DIV_ID_Msk    /*!< MCD divsion ID is 6 */
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos       (1U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP           DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos       (5U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP           DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos       (23U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP           DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM24_Pos       (24U)         
-#define EXTI_IMR_IM24_Msk       (0x1UL << EXTI_IMR_IM24_Pos)                    /*!< 0x01000000 */
-#define EXTI_IMR_IM24           EXTI_IMR_IM24_Msk                              /*!< Interrupt Mask on line 24 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x37FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x37FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM24_Pos       (24U)         
-#define EXTI_EMR_EM24_Msk       (0x1UL << EXTI_EMR_EM24_Pos)                    /*!< 0x01000000 */
-#define EXTI_EMR_EM24           EXTI_EMR_EM24_Msk                              /*!< Event Mask on line 24 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos    (15U)    
-#define FLASH_PECR_PARALLBANK_Msk    (0x1UL << FLASH_PECR_PARALLBANK_Pos)       /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK        FLASH_PECR_PARALLBANK_Msk                 /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-#define FLASH_PECR_NZDISABLE_Pos     (22U)    
-#define FLASH_PECR_NZDISABLE_Msk     (0x1UL << FLASH_PECR_NZDISABLE_Pos)        /*!< 0x00400000 */
-#define FLASH_PECR_NZDISABLE         FLASH_PECR_NZDISABLE_Msk                  /*!< Non-Zero check disable */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_BFB2_Pos          (23U)    
-#define FLASH_OPTR_BFB2_Msk          (0x1UL << FLASH_OPTR_BFB2_Pos)             /*!< 0x00800000 */
-#define FLASH_OPTR_BFB2              FLASH_OPTR_BFB2_Msk                       /*!< BFB2 */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)             
-#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)             
-#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)             
-#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)             
-#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)             
-#define FW_VDSSA_ADD_Msk     (0x3FFUL << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)             
-#define FW_VDSL_LENG_Msk     (0x3FFUL << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)             
-#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)             
-#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)             
-#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos          (10U)      
-#define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
-#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-#define RCC_MCO3_SUPPORT            /*!<Support MCO3 */
-#define RCC_MCO3_AF2_SUPPORT        /*!<Support MCO3 on Alternate Function AF0 */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CRRCR register  *****************/
-#define RCC_CRRCR_HSI48ON_Pos            (0U) 
-#define RCC_CRRCR_HSI48ON_Msk            (0x1UL << RCC_CRRCR_HSI48ON_Pos)       /*!< 0x00000001 */
-#define RCC_CRRCR_HSI48ON                RCC_CRRCR_HSI48ON_Msk                 /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY_Pos           (1U) 
-#define RCC_CRRCR_HSI48RDY_Msk           (0x1UL << RCC_CRRCR_HSI48RDY_Pos)      /*!< 0x00000002 */
-#define RCC_CRRCR_HSI48RDY               RCC_CRRCR_HSI48RDY_Msk                /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48DIV6OUTEN_Pos     (2U) 
-#define RCC_CRRCR_HSI48DIV6OUTEN_Msk     (0x1UL << RCC_CRRCR_HSI48DIV6OUTEN_Pos) /*!< 0x00000004 */
-#define RCC_CRRCR_HSI48DIV6OUTEN         RCC_CRRCR_HSI48DIV6OUTEN_Msk          /*!< HSI 48MHz DIV6 out enable */
-#define RCC_CRRCR_HSI48CAL_Pos           (8U) 
-#define RCC_CRRCR_HSI48CAL_Msk           (0xFFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF00 */
-#define RCC_CRRCR_HSI48CAL               RCC_CRRCR_HSI48CAL_Msk                /*!< HSI 48MHz clock Calibration */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-#define RCC_CFGR_MCOSEL_HSI48_Pos            (27U)                             
-#define RCC_CFGR_MCOSEL_HSI48_Msk            (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
-#define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCOSEL_HSI48_Msk         /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE_Pos          (6U) 
-#define RCC_CIER_HSI48RDYIE_Msk          (0x1UL << RCC_CIER_HSI48RDYIE_Pos)     /*!< 0x00000040 */
-#define RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE_Msk               /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF_Pos           (6U) 
-#define RCC_CIFR_HSI48RDYF_Msk           (0x1UL << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000040 */
-#define RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF_Msk                /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC_Pos           (6U) 
-#define RCC_CICR_HSI48RDYC_Msk           (0x1UL << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000040 */
-#define RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC_Msk                /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPERST_Pos          (4U) 
-#define RCC_IOPRSTR_IOPERST_Msk          (0x1UL << RCC_IOPRSTR_IOPERST_Pos)     /*!< 0x00000010 */
-#define RCC_IOPRSTR_IOPERST              RCC_IOPRSTR_IOPERST_Msk               /*!< GPIO port E reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOERST                RCC_IOPRSTR_IOPERST        /*!< GPIO port E reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST_Pos           (16U)
-#define RCC_AHBRSTR_TSCRST_Msk           (0x1UL << RCC_AHBRSTR_TSCRST_Pos)      /*!< 0x00010000 */
-#define RCC_AHBRSTR_TSCRST               RCC_AHBRSTR_TSCRST_Msk                /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST_Pos           (20U)
-#define RCC_AHBRSTR_RNGRST_Msk           (0x1UL << RCC_AHBRSTR_RNGRST_Pos)      /*!< 0x00100000 */
-#define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk                /*!< RNG reset */
-#define RCC_AHBRSTR_CRYPRST_Pos          (24U)
-#define RCC_AHBRSTR_CRYPRST_Msk          (0x1UL << RCC_AHBRSTR_CRYPRST_Pos)     /*!< 0x01000000 */
-#define RCC_AHBRSTR_CRYPRST              RCC_AHBRSTR_CRYPRST_Msk               /*!< Crypto reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1UL << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos         (1U)
-#define RCC_APB1RSTR_TIM3RST_Msk         (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)    /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST             RCC_APB1RSTR_TIM3RST_Msk              /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos         (5U)
-#define RCC_APB1RSTR_TIM7RST_Msk         (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)    /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST             RCC_APB1RSTR_TIM7RST_Msk              /*!< Timer 7 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_USART4RST_Pos       (19U)
-#define RCC_APB1RSTR_USART4RST_Msk       (0x1UL << RCC_APB1RSTR_USART4RST_Pos)  /*!< 0x00080000 */
-#define RCC_APB1RSTR_USART4RST           RCC_APB1RSTR_USART4RST_Msk            /*!< USART4 reset */
-#define RCC_APB1RSTR_USART5RST_Pos       (20U)
-#define RCC_APB1RSTR_USART5RST_Msk       (0x1UL << RCC_APB1RSTR_USART5RST_Pos)  /*!< 0x00100000 */
-#define RCC_APB1RSTR_USART5RST           RCC_APB1RSTR_USART5RST_Msk            /*!< USART5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos          (23U)
-#define RCC_APB1RSTR_USBRST_Msk          (0x1UL << RCC_APB1RSTR_USBRST_Pos)     /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST              RCC_APB1RSTR_USBRST_Msk               /*!< USB reset */
-#define RCC_APB1RSTR_CRSRST_Pos          (27U)
-#define RCC_APB1RSTR_CRSRST_Msk          (0x1UL << RCC_APB1RSTR_CRSRST_Pos)     /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST              RCC_APB1RSTR_CRSRST_Msk               /*!< CRS reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_DACRST_Pos          (29U)
-#define RCC_APB1RSTR_DACRST_Msk          (0x1UL << RCC_APB1RSTR_DACRST_Pos)     /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST              RCC_APB1RSTR_DACRST_Msk               /*!< DAC reset */
-#define RCC_APB1RSTR_I2C3RST_Pos         (30U)
-#define RCC_APB1RSTR_I2C3RST_Msk         (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)    /*!< 0x40000000 */
-#define RCC_APB1RSTR_I2C3RST             RCC_APB1RSTR_I2C3RST_Msk              /*!< I2C3  reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPEEN_Pos            (4U) 
-#define RCC_IOPENR_IOPEEN_Msk            (0x1UL << RCC_IOPENR_IOPEEN_Pos)       /*!< 0x00000010 */
-#define RCC_IOPENR_IOPEEN                RCC_IOPENR_IOPEEN_Msk                 /*!< GPIO port E clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOEEN                  RCC_IOPENR_IOPEEN        /*!< GPIO port E clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN_Pos             (16U)
-#define RCC_AHBENR_TSCEN_Msk             (0x1UL << RCC_AHBENR_TSCEN_Pos)        /*!< 0x00010000 */
-#define RCC_AHBENR_TSCEN                 RCC_AHBENR_TSCEN_Msk                  /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN_Pos             (20U)
-#define RCC_AHBENR_RNGEN_Msk             (0x1UL << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00100000 */
-#define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk                  /*!< RNG clock enable */
-#define RCC_AHBENR_CRYPEN_Pos            (24U)
-#define RCC_AHBENR_CRYPEN_Msk            (0x1UL << RCC_AHBENR_CRYPEN_Pos)       /*!< 0x01000000 */
-#define RCC_AHBENR_CRYPEN                RCC_AHBENR_CRYPEN_Msk                 /*!< Crypto clock enable*/
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)
-#define RCC_APB2ENR_USART1EN_Msk         (0x1UL << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM3EN_Pos           (1U) 
-#define RCC_APB1ENR_TIM3EN_Msk           (0x1UL << RCC_APB1ENR_TIM3EN_Pos)      /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN               RCC_APB1ENR_TIM3EN_Msk                /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U) 
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1UL << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos           (5U) 
-#define RCC_APB1ENR_TIM7EN_Msk           (0x1UL << RCC_APB1ENR_TIM7EN_Pos)      /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN               RCC_APB1ENR_TIM7EN_Msk                /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1UL << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_USART4EN_Pos         (19U)
-#define RCC_APB1ENR_USART4EN_Msk         (0x1UL << RCC_APB1ENR_USART4EN_Pos)    /*!< 0x00080000 */
-#define RCC_APB1ENR_USART4EN             RCC_APB1ENR_USART4EN_Msk              /*!< USART4 clock enable */
-#define RCC_APB1ENR_USART5EN_Pos         (20U)
-#define RCC_APB1ENR_USART5EN_Msk         (0x1UL << RCC_APB1ENR_USART5EN_Pos)    /*!< 0x00100000 */
-#define RCC_APB1ENR_USART5EN             RCC_APB1ENR_USART5EN_Msk              /*!< USART5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1UL << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos            (23U)
-#define RCC_APB1ENR_USBEN_Msk            (0x1UL << RCC_APB1ENR_USBEN_Pos)       /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                RCC_APB1ENR_USBEN_Msk                 /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN_Pos            (27U)
-#define RCC_APB1ENR_CRSEN_Msk            (0x1UL << RCC_APB1ENR_CRSEN_Pos)       /*!< 0x08000000 */
-#define RCC_APB1ENR_CRSEN                RCC_APB1ENR_CRSEN_Msk                 /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN_Pos            (29U)
-#define RCC_APB1ENR_DACEN_Msk            (0x1UL << RCC_APB1ENR_DACEN_Pos)       /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                RCC_APB1ENR_DACEN_Msk                 /*!< DAC clock enable */
-#define RCC_APB1ENR_I2C3EN_Pos           (30U)
-#define RCC_APB1ENR_I2C3EN_Msk           (0x1UL << RCC_APB1ENR_I2C3EN_Pos)      /*!< 0x40000000 */
-#define RCC_APB1ENR_I2C3EN               RCC_APB1ENR_I2C3EN_Msk                /*!< I2C3 clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPESMEN_Pos        (4U) 
-#define RCC_IOPSMENR_IOPESMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos)   /*!< 0x00000010 */
-#define RCC_IOPSMENR_IOPESMEN            RCC_IOPSMENR_IOPESMEN_Msk             /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOESMEN              RCC_IOPSMENR_IOPESMEN        /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN_Pos         (16U)
-#define RCC_AHBSMENR_TSCSMEN_Msk         (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos)    /*!< 0x00010000 */
-#define RCC_AHBSMENR_TSCSMEN             RCC_AHBSMENR_TSCSMEN_Msk              /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN_Pos         (20U)
-#define RCC_AHBSMENR_RNGSMEN_Msk         (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00100000 */
-#define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk              /*!< RNG clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRYPSMEN_Pos        (24U)
-#define RCC_AHBSMENR_CRYPSMEN_Msk        (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos)   /*!< 0x01000000 */
-#define RCC_AHBSMENR_CRYPSMEN            RCC_AHBSMENR_CRYPSMEN_Msk             /*!< Crypto clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM3SMEN_Pos       (1U) 
-#define RCC_APB1SMENR_TIM3SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM3SMEN_Pos)  /*!< 0x00000002 */
-#define RCC_APB1SMENR_TIM3SMEN           RCC_APB1SMENR_TIM3SMEN_Msk            /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U) 
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM7SMEN_Pos       (5U) 
-#define RCC_APB1SMENR_TIM7SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM7SMEN_Pos)  /*!< 0x00000020 */
-#define RCC_APB1SMENR_TIM7SMEN           RCC_APB1SMENR_TIM7SMEN_Msk            /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART4SMEN_Pos     (19U)
-#define RCC_APB1SMENR_USART4SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1SMENR_USART4SMEN         RCC_APB1SMENR_USART4SMEN_Msk          /*!< USART4 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART5SMEN_Pos     (20U)
-#define RCC_APB1SMENR_USART5SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1SMENR_USART5SMEN         RCC_APB1SMENR_USART5SMEN_Msk          /*!< USART5 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN_Pos        (23U)
-#define RCC_APB1SMENR_USBSMEN_Msk        (0x1UL << RCC_APB1SMENR_USBSMEN_Pos)   /*!< 0x00800000 */
-#define RCC_APB1SMENR_USBSMEN            RCC_APB1SMENR_USBSMEN_Msk             /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN_Pos        (27U)
-#define RCC_APB1SMENR_CRSSMEN_Msk        (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos)   /*!< 0x08000000 */
-#define RCC_APB1SMENR_CRSSMEN            RCC_APB1SMENR_CRSSMEN_Msk             /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN_Pos        (29U)
-#define RCC_APB1SMENR_DACSMEN_Msk        (0x1UL << RCC_APB1SMENR_DACSMEN_Pos)   /*!< 0x20000000 */
-#define RCC_APB1SMENR_DACSMEN            RCC_APB1SMENR_DACSMEN_Msk             /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C3SMEN_Pos       (30U)
-#define RCC_APB1SMENR_I2C3SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C3SMEN_Pos)  /*!< 0x40000000 */
-#define RCC_APB1SMENR_I2C3SMEN           RCC_APB1SMENR_I2C3SMEN_Msk            /*!< I2C3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U) 
-#define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-/*!< I2C3 Clock source selection */
-#define RCC_CCIPR_I2C3SEL_Pos            (16U)
-#define RCC_CCIPR_I2C3SEL_Msk            (0x3UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00030000 */
-#define RCC_CCIPR_I2C3SEL                RCC_CCIPR_I2C3SEL_Msk                 /*!< I2C3SEL [1:0] bits */
-#define RCC_CCIPR_I2C3SEL_0              (0x1UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00010000 */
-#define RCC_CCIPR_I2C3SEL_1              (0x2UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00020000 */
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*!< HSI48 Clock source selection */ 
-#define RCC_CCIPR_HSI48SEL_Pos           (26U)
-#define RCC_CCIPR_HSI48SEL_Msk           (0x1UL << RCC_CCIPR_HSI48SEL_Pos)      /*!< 0x04000000 */
-#define RCC_CCIPR_HSI48SEL               RCC_CCIPR_HSI48SEL_Msk                /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Legacy defines */
-#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos    (2U)              
-#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
-#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
-#define RNG_CR_IE_Pos       (3U)              
-#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
-#define RNG_CR_IE           RNG_CR_IE_Msk                                      
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)              
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
-#define RNG_SR_CECS_Pos     (1U)              
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
-#define RNG_SR_SECS_Pos     (2U)              
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
-#define RNG_SR_CEIS_Pos     (5U)              
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
-#define RNG_SR_SEIS_Pos     (6U)              
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)      
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)      
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)      
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)      
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)      
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)      
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)     
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)     
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)     
-#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */
-#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)      
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)      
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)      
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_UFB_Pos                     (3U)                          
-#define SYSCFG_CFGR1_UFB_Msk                     (0x1UL << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */
-#define SYSCFG_CFGR1_UFB                         SYSCFG_CFGR1_UFB_Msk          /*!< User bank swapping */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-#define SYSCFG_CFGR2_I2C3_FMP_Pos                (14U)                         
-#define SYSCFG_CFGR2_I2C3_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */
-#define SYSCFG_CFGR2_I2C3_FMP                    SYSCFG_CFGR2_I2C3_FMP_Msk     /*!< I2C3 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD                  (0x00000003U)                 /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE                  (0x00000004U)                 /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD                  (0x00000030U)                 /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE                  (0x00000040U)                 /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE                  (0x00000400U)                 /*!< PE[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD                  (0x00003000U)                 /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE                  (0x00004000U)                 /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD                  (0x00000003U)                 /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE                  (0x00000004U)                 /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD                  (0x00000030U)                 /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE                  (0x00000040U)                 /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD                  (0x00000300U)                 /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE                  (0x00000400U)                 /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD                  (0x00003000U)                 /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE                  (0x00004000U)                 /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD                  (0x00000003U)                 /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE                  (0x00000004U)                 /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD                  (0x00000030U)                 /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE                  (0x00000040U)                 /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH                  (0x00000050U)                 /*!< PH[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD                 (0x00000300U)                 /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE                 (0x00000400U)                 /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH                 (0x00000500U)                 /*!< PH[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD                 (0x00003000U)                 /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE                 (0x00004000U)                 /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD                 (0x00000003U)                 /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE                 (0x00000004U)                 /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD                 (0x00000030U)                 /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE                 (0x00000040U)                 /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD                 (0x00000300U)                 /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE                 (0x00000400U)                 /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD                 (0x00003000U)                 /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE                 (0x00004000U)                 /*!< PE[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48_Pos             (13U)                         
-#define SYSCFG_CFGR3_ENREF_HSI48_Msk             (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR3_ENREF_HSI48                 SYSCFG_CFGR3_ENREF_HSI48_Msk  /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
-#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_REF_HSI48_RDYF           SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI_SUPPORT       /*!<Support remap HSI on TIM2 */
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-#define TIM3_OR_ETR_RMP_Pos      (0U)         
-#define TIM3_OR_ETR_RMP_Msk      (0x3UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000003 */
-#define TIM3_OR_ETR_RMP          TIM3_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
-#define TIM3_OR_ETR_RMP_0        (0x1UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM3_OR_ETR_RMP_1        (0x2UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM3_OR_TI1_RMP_Pos      (2U)         
-#define TIM3_OR_TI1_RMP_Msk      (0x1UL << TIM3_OR_TI1_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM3_OR_TI1_RMP          TIM3_OR_TI1_RMP_Msk                           /*!<TI1_RMP[2] bit                      */
-#define TIM3_OR_TI2_RMP_Pos      (3U)         
-#define TIM3_OR_TI2_RMP_Msk      (0x1UL << TIM3_OR_TI2_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM3_OR_TI2_RMP          TIM3_OR_TI2_RMP_Msk                           /*!<TI2_RMP[3] bit                      */
-#define TIM3_OR_TI4_RMP_Pos      (4U)         
-#define TIM3_OR_TI4_RMP_Msk      (0x1UL << TIM3_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-#define TIM3_OR_TI4_RMP          TIM3_OR_TI4_RMP_Msk                           /*!<TI4_RMP[4] bit                      */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE_Pos          (0U)         
-#define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
-#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
-#define TSC_CR_START_Pos         (1U)         
-#define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
-#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
-#define TSC_CR_AM_Pos            (2U)         
-#define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
-#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL_Pos       (3U)         
-#define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
-#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF_Pos         (4U)         
-#define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
-#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
-
-#define TSC_CR_MCV_Pos           (5U)         
-#define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
-#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
-#define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
-#define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
-
-#define TSC_CR_PGPSC_Pos         (12U)        
-#define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
-#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
-#define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
-#define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
-
-#define TSC_CR_SSPSC_Pos         (15U)        
-#define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
-#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE_Pos           (16U)        
-#define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
-#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD_Pos           (17U)        
-#define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
-#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
-#define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
-#define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
-#define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
-#define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
-#define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
-#define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
-
-#define TSC_CR_CTPL_Pos          (24U)        
-#define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
-#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
-#define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
-#define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
-#define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
-
-#define TSC_CR_CTPH_Pos          (28U)        
-#define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
-#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
-#define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
-#define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
-#define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE_Pos        (0U)         
-#define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
-#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE_Pos        (1U)         
-#define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
-#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC_Pos        (0U)         
-#define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
-#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC_Pos        (1U)         
-#define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
-#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF_Pos         (0U)         
-#define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
-#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
-#define TSC_ISR_MCEF_Pos         (1U)         
-#define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
-#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1_Pos     (0U)         
-#define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2_Pos     (1U)         
-#define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3_Pos     (2U)         
-#define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4_Pos     (3U)         
-#define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1_Pos     (4U)         
-#define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2_Pos     (5U)         
-#define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3_Pos     (6U)         
-#define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4_Pos     (7U)         
-#define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1_Pos     (8U)         
-#define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2_Pos     (9U)         
-#define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3_Pos     (10U)        
-#define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4_Pos     (11U)        
-#define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1_Pos     (12U)        
-#define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2_Pos     (13U)        
-#define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3_Pos     (14U)        
-#define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4_Pos     (15U)        
-#define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1_Pos     (16U)        
-#define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2_Pos     (17U)        
-#define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3_Pos     (18U)        
-#define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4_Pos     (19U)        
-#define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1_Pos     (20U)        
-#define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2_Pos     (21U)        
-#define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3_Pos     (22U)        
-#define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4_Pos     (23U)        
-#define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1_Pos     (24U)        
-#define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2_Pos     (25U)        
-#define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3_Pos     (26U)        
-#define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4_Pos     (27U)        
-#define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1_Pos     (28U)        
-#define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2_Pos     (29U)        
-#define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3_Pos     (30U)        
-#define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4_Pos     (31U)        
-#define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1_Pos    (0U)         
-#define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
-#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2_Pos    (1U)         
-#define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
-#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3_Pos    (2U)         
-#define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
-#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4_Pos    (3U)         
-#define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
-#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1_Pos    (4U)         
-#define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
-#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2_Pos    (5U)         
-#define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
-#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3_Pos    (6U)         
-#define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
-#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4_Pos    (7U)         
-#define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
-#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1_Pos    (8U)         
-#define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
-#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2_Pos    (9U)         
-#define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
-#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3_Pos    (10U)        
-#define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
-#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4_Pos    (11U)        
-#define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
-#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1_Pos    (12U)        
-#define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
-#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2_Pos    (13U)        
-#define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
-#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3_Pos    (14U)        
-#define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
-#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4_Pos    (15U)        
-#define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
-#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1_Pos    (16U)        
-#define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
-#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2_Pos    (17U)        
-#define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
-#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3_Pos    (18U)        
-#define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
-#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4_Pos    (19U)        
-#define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
-#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1_Pos    (20U)        
-#define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
-#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2_Pos    (21U)        
-#define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
-#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3_Pos    (22U)        
-#define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
-#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4_Pos    (23U)        
-#define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
-#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1_Pos    (24U)        
-#define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
-#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2_Pos    (25U)        
-#define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
-#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3_Pos    (26U)        
-#define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
-#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4_Pos    (27U)        
-#define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
-#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1_Pos    (28U)        
-#define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
-#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2_Pos    (29U)        
-#define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
-#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3_Pos    (30U)        
-#define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
-#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4_Pos    (31U)        
-#define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
-#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1_Pos     (0U)         
-#define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2_Pos     (1U)         
-#define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3_Pos     (2U)         
-#define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4_Pos     (3U)         
-#define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1_Pos     (4U)         
-#define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2_Pos     (5U)         
-#define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3_Pos     (6U)         
-#define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4_Pos     (7U)         
-#define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1_Pos     (8U)         
-#define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2_Pos     (9U)         
-#define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3_Pos     (10U)        
-#define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4_Pos     (11U)        
-#define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1_Pos     (12U)        
-#define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2_Pos     (13U)        
-#define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3_Pos     (14U)        
-#define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4_Pos     (15U)        
-#define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1_Pos     (16U)        
-#define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2_Pos     (17U)        
-#define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3_Pos     (18U)        
-#define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4_Pos     (19U)        
-#define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1_Pos     (20U)        
-#define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2_Pos     (21U)        
-#define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3_Pos     (22U)        
-#define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4_Pos     (23U)        
-#define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1_Pos     (24U)        
-#define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2_Pos     (25U)        
-#define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3_Pos     (26U)        
-#define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4_Pos     (27U)        
-#define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1_Pos     (28U)        
-#define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2_Pos     (29U)        
-#define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3_Pos     (30U)        
-#define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4_Pos     (31U)        
-#define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1_Pos     (0U)         
-#define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2_Pos     (1U)         
-#define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3_Pos     (2U)         
-#define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4_Pos     (3U)         
-#define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1_Pos     (4U)         
-#define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2_Pos     (5U)         
-#define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3_Pos     (6U)         
-#define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4_Pos     (7U)         
-#define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1_Pos     (8U)         
-#define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2_Pos     (9U)         
-#define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3_Pos     (10U)        
-#define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4_Pos     (11U)        
-#define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1_Pos     (12U)        
-#define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2_Pos     (13U)        
-#define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3_Pos     (14U)        
-#define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4_Pos     (15U)        
-#define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1_Pos     (16U)        
-#define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2_Pos     (17U)        
-#define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3_Pos     (18U)        
-#define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4_Pos     (19U)        
-#define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1_Pos     (20U)        
-#define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2_Pos     (21U)        
-#define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3_Pos     (22U)        
-#define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4_Pos     (23U)        
-#define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1_Pos     (24U)        
-#define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2_Pos     (25U)        
-#define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3_Pos     (26U)        
-#define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4_Pos     (27U)        
-#define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1_Pos     (28U)        
-#define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2_Pos     (29U)        
-#define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3_Pos     (30U)        
-#define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4_Pos     (31U)        
-#define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E_Pos       (0U)         
-#define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
-#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E_Pos       (1U)         
-#define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
-#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E_Pos       (2U)         
-#define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
-#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E_Pos       (3U)         
-#define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
-#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E_Pos       (4U)         
-#define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
-#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E_Pos       (5U)         
-#define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
-#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E_Pos       (6U)         
-#define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
-#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E_Pos       (7U)         
-#define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
-#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S_Pos       (16U)        
-#define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
-#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S_Pos       (17U)        
-#define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
-#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S_Pos       (18U)        
-#define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
-#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S_Pos       (19U)        
-#define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
-#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S_Pos       (20U)        
-#define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
-#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S_Pos       (21U)        
-#define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
-#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S_Pos       (22U)        
-#define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
-#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S_Pos       (23U)        
-#define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
-#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT_Pos       (0U)         
-#define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
-#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         USB Device General registers                       */
-/*                                                                            */
-/******************************************************************************/
-#define USB_BASE                              (0x40005C00U)                    /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR_Pos           (13U)       
-#define USB_PMAADDR_Msk           (0x20003UL << USB_PMAADDR_Pos)                /*!< 0x40006000 */
-#define USB_PMAADDR               USB_PMAADDR_Msk                              /*!< USB_IP Packet Memory Area base address */
-                                             
-#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
-#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
-#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
-#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
-#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
-#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
-#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
-
-/****************************  ISTR interrupt events  *************************/
-#define USB_ISTR_CTR                          ((uint16_t)0x8000U)              /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR                       ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR                          ((uint16_t)0x2000U)              /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP                         ((uint16_t)0x1000U)              /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP                         ((uint16_t)0x0800U)              /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET                        ((uint16_t)0x0400U)              /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF                          ((uint16_t)0x0200U)              /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF                         ((uint16_t)0x0100U)              /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ                        ((uint16_t)0x0080U)              /*!< LPM L1 state request  */
-#define USB_ISTR_DIR                          ((uint16_t)0x0010U)              /*!< DIRection of transaction (read-only bit)  */
-#define USB_ISTR_EP_ID                        ((uint16_t)0x000FU)              /*!< EndPoint IDentifier (read-only bit)  */
-
-#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
-#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
-#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
-#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
-#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
-#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
-#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
-#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
-/*************************  CNTR control register bits definitions  ***********/
-#define USB_CNTR_CTRM                         ((uint16_t)0x8000U)              /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM                      ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM                         ((uint16_t)0x2000U)              /*!< ERRor Mask */
-#define USB_CNTR_WKUPM                        ((uint16_t)0x1000U)              /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM                        ((uint16_t)0x0800U)              /*!< SUSPend Mask */
-#define USB_CNTR_RESETM                       ((uint16_t)0x0400U)              /*!< RESET Mask   */
-#define USB_CNTR_SOFM                         ((uint16_t)0x0200U)              /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM                        ((uint16_t)0x0100U)              /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM                       ((uint16_t)0x0080U)              /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME                     ((uint16_t)0x0020U)              /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME                       ((uint16_t)0x0010U)              /*!< RESUME request */
-#define USB_CNTR_FSUSP                        ((uint16_t)0x0008U)              /*!< Force SUSPend */
-#define USB_CNTR_LPMODE                       ((uint16_t)0x0004U)              /*!< Low-power MODE */
-#define USB_CNTR_PDWN                         ((uint16_t)0x0002U)              /*!< Power DoWN */
-#define USB_CNTR_FRES                         ((uint16_t)0x0001U)              /*!< Force USB RESet */
-/*************************  BCDR control register bits definitions  ***********/
-#define USB_BCDR_DPPU                         ((uint16_t)0x8000U)              /*!< DP Pull-up Enable */  
-#define USB_BCDR_PS2DET                       ((uint16_t)0x0080U)              /*!< PS2 port or proprietary charger detected */  
-#define USB_BCDR_SDET                         ((uint16_t)0x0040U)              /*!< Secondary detection (SD) status */  
-#define USB_BCDR_PDET                         ((uint16_t)0x0020U)              /*!< Primary detection (PD) status */ 
-#define USB_BCDR_DCDET                        ((uint16_t)0x0010U)              /*!< Data contact detection (DCD) status */ 
-#define USB_BCDR_SDEN                         ((uint16_t)0x0008U)              /*!< Secondary detection (SD) mode enable */ 
-#define USB_BCDR_PDEN                         ((uint16_t)0x0004U)              /*!< Primary detection (PD) mode enable */  
-#define USB_BCDR_DCDEN                        ((uint16_t)0x0002U)              /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN                        ((uint16_t)0x0001U)              /*!< Battery charging detector (BCD) enable */
-/***************************  LPM register bits definitions  ******************/
-#define USB_LPMCSR_BESL                       ((uint16_t)0x00F0U)              /*!< BESL value received with last ACKed LPM Token  */ 
-#define USB_LPMCSR_REMWAKE                    ((uint16_t)0x0008U)              /*!< bRemoteWake value received with last ACKed LPM Token */ 
-#define USB_LPMCSR_LPMACK                     ((uint16_t)0x0002U)              /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN                      ((uint16_t)0x0001U)              /*!< LPM support enable  */
-/********************  FNR Frame Number Register bit definitions   ************/
-#define USB_FNR_RXDP                          ((uint16_t)0x8000U)              /*!< status of D+ data line */
-#define USB_FNR_RXDM                          ((uint16_t)0x4000U)              /*!< status of D- data line */
-#define USB_FNR_LCK                           ((uint16_t)0x2000U)              /*!< LoCKed */
-#define USB_FNR_LSOF                          ((uint16_t)0x1800U)              /*!< Lost SOF */
-#define USB_FNR_FN                            ((uint16_t)0x07FFU)              /*!< Frame Number */
-/********************  DADDR Device ADDRess bit definitions    ****************/
-#define USB_DADDR_EF                          ((uint8_t)0x80U)                 /*!< USB device address Enable Function */
-#define USB_DADDR_ADD                         ((uint8_t)0x7FU)                 /*!< USB device address */
-/******************************  Endpoint register    *************************/
-#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
-#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
-#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
-#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
-#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
-#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
-#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
-#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
-/* bit positions */ 
-#define USB_EP_CTR_RX                         ((uint16_t)0x8000U)              /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX                        ((uint16_t)0x4000U)              /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT                         ((uint16_t)0x3000U)              /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP                          ((uint16_t)0x0800U)              /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD                        ((uint16_t)0x0600U)              /*!<  EndPoint TYPE */
-#define USB_EP_KIND                           ((uint16_t)0x0100U)              /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX                         ((uint16_t)0x0080U)              /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX                        ((uint16_t)0x0040U)              /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT                         ((uint16_t)0x0030U)              /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD                      ((uint16_t)0x000FU)              /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK                      ((uint16_t)0x0600U)              /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           ((uint16_t)0x0000U)              /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        ((uint16_t)0x0200U)              /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    ((uint16_t)0x0400U)              /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      ((uint16_t)0x0600U)              /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
-                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       ((uint16_t)0x0010U)              /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         ((uint16_t)0x0020U)              /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       ((uint16_t)0x0030U)              /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        ((uint16_t)0x0010U)              /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        ((uint16_t)0x0020U)              /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       ((uint16_t)0x1000U)              /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         ((uint16_t)0x2000U)              /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       ((uint16_t)0x3000U)              /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        ((uint16_t)0x1000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        ((uint16_t)0x2000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* AES Instances ********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                                   ((INSTANCE) == I2C3))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                     ((INSTANCE) == I2C3))
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM7)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM3)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3) || \
-                                            ((INSTANCE) == TIM6) || \
-                                            ((INSTANCE) == TIM7))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                           ((INSTANCE) == TIM3))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-   (((((INSTANCE) == TIM2) ||                  \
-      ((INSTANCE) == TIM3))                    \
-     &&                                        \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM3)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM3)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM3)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM7)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                                ((INSTANCE) == TIM3))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/****************************** TSC Instances *********************************/
-#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART4) || \
-                                    ((INSTANCE) == USART5))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART4) || \
-                                     ((INSTANCE) == USART5))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART4) || \
-                                           ((INSTANCE) == USART5) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/******************************* USB Instances *******************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define LPUART1_IRQn                   AES_RNG_LPUART1_IRQn
-#define AES_LPUART1_IRQn               AES_RNG_LPUART1_IRQn
-#define RNG_LPUART1_IRQn               AES_RNG_LPUART1_IRQn
-#define TIM6_IRQn                      TIM6_DAC_IRQn
-#define RCC_IRQn                       RCC_CRS_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             AES_RNG_LPUART1_IRQHandler
-#define RNG_LPUART1_IRQHandler         AES_RNG_LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         AES_RNG_LPUART1_IRQHandler
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
-#define RCC_IRQHandler                 RCC_CRS_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L082xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h
deleted file mode 100644
index a549a9b9d1..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h
+++ /dev/null
@@ -1,7990 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l083xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l083xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l083xx
-  * @{
-  */
-    
-#ifndef __STM32L083xx_H
-#define __STM32L083xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1U /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l083xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  USART4_5_IRQn               = 14,     /*!< USART4 and USART5 Interrupt                             */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM7_IRQn                   = 18,     /*!< TIM7 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  I2C3_IRQn                   = 21,     /*!< I2C3 Interrupt                                          */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  AES_RNG_LPUART1_IRQn        = 29,     /*!< AES and RNG and LPUART1 Interrupts                      */
-  LCD_IRQn                    = 30,     /*!< LCD Interrupt                                           */
-  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;      /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;      /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;    /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;   /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;   /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;   /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;   /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;   /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;    /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;    /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;    /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;    /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Clock Recovery System 
-  */
-
-typedef struct 
-{
-__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
-__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
-__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
-__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
-} CRS_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;       /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;       /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;        /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;       /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;       /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;        /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;          /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-  __IO uint32_t RESERVED1[23]; /*!< Reserved1,                                   Address offset: 0x24 */
-  __IO uint32_t WRPR2;         /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-  __IO uint32_t WRP23;             /*!< write protection Bytes 2 and 3          Address offset: 0x0C */
-  __IO uint32_t WRP45;             /*!< write protection Bytes 4 and 5          Address offset: 0x10 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Random numbers generator
-  */
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
-  __IO uint16_t RESERVEDD;       /*!< Reserved */       
-  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
-  __IO uint16_t RESERVEDE;       /*!< Reserved */       
-} USB_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
-
-#define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_BANK2_BASE (0x08080C00UL) /*!< DATA EEPROM BANK2 base address in the alias region */
-#define DATA_EEPROM_BANK1_END  (0x08080BFFUL) /*!< Program end DATA EEPROM BANK1 address */
-#define DATA_EEPROM_BANK2_END  (0x080817FFUL) /*!< Program end DATA EEPROM BANK2 address */
-#define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */
-
-#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400UL)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APBPERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
-#define USART4_BASE           (APBPERIPH_BASE + 0x00004C00UL)
-#define USART5_BASE           (APBPERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
-#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00UL)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
-#define I2C3_BASE             (APBPERIPH_BASE + 0x00007800UL)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
-#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000UL)
-#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000UL)
-#define AES_BASE              (AHBPERIPH_BASE + 0x00006000UL)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (IOPPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CRS                 ((CRS_TypeDef *) CRS_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define USART4              ((USART_TypeDef *) USART4_BASE)
-#define USART5              ((USART_TypeDef *) USART5_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define AES                 ((AES_TypeDef *) AES_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define USB                 ((USB_TypeDef *) USB_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)      
-#define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)       
-#define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)       
-#define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)       
-#define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)       
-#define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)       
-#define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)       
-#define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)      
-#define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)       
-#define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)       
-#define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)       
-#define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)       
-#define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)       
-#define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)       
-#define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)      
-#define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)      
-#define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)       
-#define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)       
-#define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)       
-#define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)       
-#define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)      
-#define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)      
-#define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)      
-#define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)      
-#define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)      
-#define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)      
-#define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)      
-#define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)      
-#define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)      
-#define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)       
-#define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)       
-#define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)       
-#define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)       
-#define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)       
-#define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)       
-#define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)       
-#define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)       
-#define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)       
-#define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)       
-#define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)      
-#define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)       
-#define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)      
-#define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)       
-#define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)       
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)      
-#define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)      
-#define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16_Pos     (16U)      
-#define ADC_CHSELR_CHSEL16_Msk     (0x1UL << ADC_CHSELR_CHSEL16_Pos)            /*!< 0x00010000 */
-#define ADC_CHSELR_CHSEL16         ADC_CHSELR_CHSEL16_Msk                      /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)      
-#define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)      
-#define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)      
-#define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)      
-#define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)      
-#define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)      
-#define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)       
-#define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)       
-#define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)       
-#define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)       
-#define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)       
-#define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)       
-#define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)       
-#define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)       
-#define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)       
-#define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)       
-#define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)       
-#define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)       
-#define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)      
-#define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_VLCDEN_Pos         (24U)      
-#define ADC_CCR_VLCDEN_Msk         (0x1UL << ADC_CCR_VLCDEN_Pos)                /*!< 0x01000000 */
-#define ADC_CCR_VLCDEN             ADC_CCR_VLCDEN_Msk                          /*!< Voltage LCD enable */
-#define ADC_CCR_TSEN_Pos           (23U)      
-#define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)      
-#define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)      
-#define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos            (0U)         
-#define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                       /*!< 0x00000001 */
-#define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos      (1U)         
-#define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000006 */
-#define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
-#define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos          (3U)         
-#define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                     /*!< 0x00000018 */
-#define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                     /*!< 0x00000008 */
-#define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                     /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos         (5U)         
-#define AES_CR_CHMOD_Msk         (0x3UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000060 */
-#define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0           (0x1UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000020 */
-#define AES_CR_CHMOD_1           (0x2UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000040 */
-
-#define AES_CR_CCFC_Pos          (7U)         
-#define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                     /*!< 0x00000080 */
-#define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos          (8U)         
-#define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                     /*!< 0x00000100 */
-#define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
-#define AES_CR_CCIE_Pos          (9U)         
-#define AES_CR_CCIE_Msk          (0x1UL << AES_CR_CCIE_Pos)                     /*!< 0x00000200 */
-#define AES_CR_CCIE              AES_CR_CCIE_Msk                               /*!< Computation Complete Interrupt Enable */
-#define AES_CR_ERRIE_Pos         (10U)        
-#define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                    /*!< 0x00000400 */
-#define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos       (11U)        
-#define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                  /*!< 0x00000800 */
-#define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< DMA ENable managing the data input phase */
-#define AES_CR_DMAOUTEN_Pos      (12U)        
-#define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                 /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos           (0U)         
-#define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                      /*!< 0x00000001 */
-#define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos         (1U)         
-#define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                    /*!< 0x00000002 */
-#define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos         (2U)         
-#define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                    /*!< 0x00000004 */
-#define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos             (0U)         
-#define AES_DINR_Msk             (0xFFFFUL << AES_DINR_Pos)                     /*!< 0x0000FFFF */
-#define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos            (0U)         
-#define AES_DOUTR_Msk            (0xFFFFUL << AES_DOUTR_Pos)                    /*!< 0x0000FFFF */
-#define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos            (0U)         
-#define AES_KEYR0_Msk            (0xFFFFUL << AES_KEYR0_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos            (0U)         
-#define AES_KEYR1_Msk            (0xFFFFUL << AES_KEYR1_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos            (0U)         
-#define AES_KEYR2_Msk            (0xFFFFUL << AES_KEYR2_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos            (0U)         
-#define AES_KEYR3_Msk            (0xFFFFUL << AES_KEYR3_Pos)                    /*!< 0x0000FFFF */
-#define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define AES_IVR0_Pos             (0U)         
-#define AES_IVR0_Msk             (0xFFFFUL << AES_IVR0_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define AES_IVR1_Pos             (0U)         
-#define AES_IVR1_Msk             (0xFFFFUL << AES_IVR1_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define AES_IVR2_Pos             (0U)         
-#define AES_IVR2_Msk             (0xFFFFUL << AES_IVR2_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define AES_IVR3_Pos             (0U)         
-#define AES_IVR3_Msk             (0xFFFFUL << AES_IVR3_Pos)                     /*!< 0x0000FFFF */
-#define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)   
-#define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)   
-#define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)  
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)  
-#define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)  
-#define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)   
-#define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)   
-#define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)   
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)   
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)  
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)  
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)  
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)  
-#define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)  
-#define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)   
-#define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)  
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)  
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)  
-#define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)         
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)         
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)         
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)         
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)         
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)         
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)         
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRS Clock Recovery System                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRS_CR register  *********************/
-#define CRS_CR_SYNCOKIE_Pos       (0U)        
-#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
-#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
-#define CRS_CR_SYNCWARNIE_Pos     (1U)        
-#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
-#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
-#define CRS_CR_ERRIE_Pos          (2U)        
-#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
-#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
-#define CRS_CR_ESYNCIE_Pos        (3U)        
-#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
-#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN_Pos            (5U)        
-#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
-#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
-#define CRS_CR_AUTOTRIMEN_Pos     (6U)        
-#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
-#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
-#define CRS_CR_SWSYNC_Pos         (7U)        
-#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
-#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
-#define CRS_CR_TRIM_Pos           (8U)        
-#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
-#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
-
-/*******************  Bit definition for CRS_CFGR register  *********************/
-#define CRS_CFGR_RELOAD_Pos       (0U)        
-#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
-#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
-#define CRS_CFGR_FELIM_Pos        (16U)       
-#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
-#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
-
-#define CRS_CFGR_SYNCDIV_Pos      (24U)       
-#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
-#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
-#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
-#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
-#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
-
-#define CRS_CFGR_SYNCSRC_Pos      (28U)       
-#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
-#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
-#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
-#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
-
-#define CRS_CFGR_SYNCPOL_Pos      (31U)       
-#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
-#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
-  
-/*******************  Bit definition for CRS_ISR register  *********************/
-#define CRS_ISR_SYNCOKF_Pos       (0U)        
-#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
-#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
-#define CRS_ISR_SYNCWARNF_Pos     (1U)        
-#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
-#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
-#define CRS_ISR_ERRF_Pos          (2U)        
-#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
-#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
-#define CRS_ISR_ESYNCF_Pos        (3U)        
-#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
-#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
-#define CRS_ISR_SYNCERR_Pos       (8U)        
-#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
-#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
-#define CRS_ISR_SYNCMISS_Pos      (9U)        
-#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
-#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
-#define CRS_ISR_TRIMOVF_Pos       (10U)       
-#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
-#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR_Pos         (15U)       
-#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
-#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
-#define CRS_ISR_FECAP_Pos         (16U)       
-#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
-#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
-
-/*******************  Bit definition for CRS_ICR register  *********************/
-#define CRS_ICR_SYNCOKC_Pos       (0U)        
-#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
-#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
-#define CRS_ICR_SYNCWARNC_Pos     (1U)        
-#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
-#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
-#define CRS_ICR_ERRC_Pos          (2U)        
-#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
-#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag             */
-#define CRS_ICR_ESYNCC_Pos        (3U)        
-#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
-#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define DAC_CHANNEL2_SUPPORT                       /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)      
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos            (1U)      
-#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos             (2U)      
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (3U)      
-#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)      
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)      
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)     
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)     
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun interrupt enable */
-
-#define DAC_CR_EN2_Pos              (16U)     
-#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
-#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos            (17U)     
-#define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
-#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!< DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos             (18U)     
-#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
-#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!< DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos            (19U)     
-#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
-#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos            (22U)     
-#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos            (24U)     
-#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos           (28U)     
-#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
-#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!< DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos        (29U)     
-#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!< DAC channel12DMA Underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)      
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)      
-#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!< DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)      
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)      
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)      
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos    (0U)      
-#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos    (4U)      
-#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos     (0U)      
-#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos    (0U)      
-#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos    (16U)     
-#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos    (4U)      
-#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos    (20U)     
-#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos     (0U)      
-#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos     (8U)      
-#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)      
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos       (0U)      
-#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!< DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)     
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos          (29U)     
-#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!< DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_DIV_ID_Pos               (12U)                           
-#define DBGMCU_IDCODE_DIV_ID_Msk               (0xFUL << DBGMCU_IDCODE_DIV_ID_Pos) /*!< 0x0000F000 */
-#define DBGMCU_IDCODE_DIV_ID                   DBGMCU_IDCODE_DIV_ID_Msk        /*!< Division Identifier */
-#define DBGMCU_IDCODE_MCD_DIV_ID_Pos           (13U)                           
-#define DBGMCU_IDCODE_MCD_DIV_ID_Msk           (0x3UL << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */
-#define DBGMCU_IDCODE_MCD_DIV_ID               DBGMCU_IDCODE_MCD_DIV_ID_Msk    /*!< MCD divsion ID is 6 */
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos       (1U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP           DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos       (5U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP           DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos       (23U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP           DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)           
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)           
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)           
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)           
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)           
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)           
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)           
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)           
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)           
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)           
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)          
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)          
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)          
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)          
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)          
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)          
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)          
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)          
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)          
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)          
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)          
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)          
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)          
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)          
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)          
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)          
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)          
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)          
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)           
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)           
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)           
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)           
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)           
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)           
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)           
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)           
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)           
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)           
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)          
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)          
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)          
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)          
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)          
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)          
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)          
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)          
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)          
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)          
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)          
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)          
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)          
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)          
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)          
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)          
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)          
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)          
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)           
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)           
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)           
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)           
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)           
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)           
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)           
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)           
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)           
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)          
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)          
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)          
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)           
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)           
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)           
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)           
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)           
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)           
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)          
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)          
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)          
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)          
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)          
-#define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)          
-#define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)          
-#define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)          
-#define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)          
-#define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)          
-#define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)          
-#define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)          
-#define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)          
-#define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)          
-#define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)         
-#define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)         
-#define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)         
-#define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)         
-#define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)         
-#define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)         
-#define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)         
-#define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)         
-#define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)         
-#define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)         
-#define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)         
-#define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)         
-#define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)         
-#define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)         
-#define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM24_Pos       (24U)         
-#define EXTI_IMR_IM24_Msk       (0x1UL << EXTI_IMR_IM24_Pos)                    /*!< 0x01000000 */
-#define EXTI_IMR_IM24           EXTI_IMR_IM24_Msk                              /*!< Interrupt Mask on line 24 */
-#define EXTI_IMR_IM25_Pos       (25U)         
-#define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)         
-#define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)         
-#define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)         
-#define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)          
-#define EXTI_IMR_IM_Msk         (0x37FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x37FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)          
-#define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)          
-#define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)          
-#define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)          
-#define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)          
-#define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)          
-#define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)          
-#define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)          
-#define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)          
-#define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)          
-#define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)         
-#define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)         
-#define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)         
-#define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)         
-#define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)         
-#define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)         
-#define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)         
-#define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)         
-#define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)         
-#define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)         
-#define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)         
-#define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)         
-#define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)         
-#define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)         
-#define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM24_Pos       (24U)         
-#define EXTI_EMR_EM24_Msk       (0x1UL << EXTI_EMR_EM24_Pos)                    /*!< 0x01000000 */
-#define EXTI_EMR_EM24           EXTI_EMR_EM24_Msk                              /*!< Event Mask on line 24 */
-#define EXTI_EMR_EM25_Pos       (25U)         
-#define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)         
-#define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)         
-#define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)         
-#define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)          
-#define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)          
-#define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)          
-#define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)          
-#define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)          
-#define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)          
-#define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)          
-#define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)          
-#define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)          
-#define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)          
-#define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)         
-#define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)         
-#define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)         
-#define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)         
-#define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)         
-#define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)         
-#define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)         
-#define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)         
-#define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)         
-#define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)         
-#define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)         
-#define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)         
-#define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)          
-#define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)          
-#define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)          
-#define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)          
-#define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)          
-#define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)          
-#define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)          
-#define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)          
-#define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)          
-#define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)          
-#define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)         
-#define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)         
-#define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)         
-#define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)         
-#define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)         
-#define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)         
-#define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)         
-#define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)         
-#define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)         
-#define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)         
-#define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)         
-#define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)         
-#define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)          
-#define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)          
-#define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)          
-#define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)          
-#define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)          
-#define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)          
-#define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)          
-#define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)          
-#define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)          
-#define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)          
-#define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)         
-#define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)         
-#define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)         
-#define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)         
-#define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)         
-#define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)         
-#define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)         
-#define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)         
-#define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)         
-#define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)         
-#define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)         
-#define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)         
-#define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)          
-#define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)          
-#define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)          
-#define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)          
-#define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)          
-#define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)          
-#define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)          
-#define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)          
-#define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)          
-#define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)          
-#define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)         
-#define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)         
-#define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)         
-#define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)         
-#define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)         
-#define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)         
-#define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)         
-#define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)         
-#define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)         
-#define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)         
-#define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)         
-#define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)         
-#define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)     
-#define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)     
-#define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)     
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)     
-#define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)     
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)     
-#define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)     
-#define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)     
-#define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)     
-#define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)     
-#define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)     
-#define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)     
-#define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)     
-#define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)    
-#define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos    (15U)    
-#define FLASH_PECR_PARALLBANK_Msk    (0x1UL << FLASH_PECR_PARALLBANK_Pos)       /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK        FLASH_PECR_PARALLBANK_Msk                 /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)    
-#define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)    
-#define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)    
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)    
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-#define FLASH_PECR_NZDISABLE_Pos     (22U)    
-#define FLASH_PECR_NZDISABLE_Msk     (0x1UL << FLASH_PECR_NZDISABLE_Pos)        /*!< 0x00400000 */
-#define FLASH_PECR_NZDISABLE         FLASH_PECR_NZDISABLE_Msk                  /*!< Non-Zero check disable */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)     
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)     
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)     
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)     
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)     
-#define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)     
-#define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)     
-#define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)     
-#define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)     
-#define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)     
-#define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)    
-#define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)    
-#define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)    
-#define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)    
-#define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)    
-#define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)     
-#define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)     
-#define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)    
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)    
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)    
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)    
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_BFB2_Pos          (23U)    
-#define FLASH_OPTR_BFB2_Msk          (0x1UL << FLASH_OPTR_BFB2_Pos)             /*!< 0x00800000 */
-#define FLASH_OPTR_BFB2              FLASH_OPTR_BFB2_Msk                       /*!< BFB2 */
-#define FLASH_OPTR_USER_Pos          (20U)    
-#define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)    
-#define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)     
-#define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)  
-#define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)  
-#define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)  
-#define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)  
-#define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)  
-#define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U) 
-#define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U) 
-#define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U) 
-#define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U) 
-#define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U) 
-#define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U) 
-#define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U) 
-#define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U) 
-#define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U) 
-#define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U) 
-#define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U) 
-#define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)  
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)  
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)  
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)  
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)  
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U) 
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U) 
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U) 
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U) 
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U) 
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U) 
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U) 
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U) 
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U) 
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U) 
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U) 
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)  
-#define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)  
-#define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)  
-#define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)  
-#define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)  
-#define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U) 
-#define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U) 
-#define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U) 
-#define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U) 
-#define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U) 
-#define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U) 
-#define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U) 
-#define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U) 
-#define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U) 
-#define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U) 
-#define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U) 
-#define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)  
-#define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)  
-#define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)  
-#define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)  
-#define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)  
-#define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)  
-#define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)  
-#define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)  
-#define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)  
-#define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)  
-#define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U) 
-#define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U) 
-#define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U) 
-#define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U) 
-#define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U) 
-#define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U) 
-#define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)  
-#define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)  
-#define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)  
-#define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)  
-#define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)  
-#define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)  
-#define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)  
-#define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)  
-#define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)  
-#define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)  
-#define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U) 
-#define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U) 
-#define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U) 
-#define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U) 
-#define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U) 
-#define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U) 
-#define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)  
-#define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)  
-#define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)  
-#define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)  
-#define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)  
-#define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)  
-#define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)  
-#define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)  
-#define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)  
-#define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)  
-#define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U) 
-#define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U) 
-#define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U) 
-#define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U) 
-#define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U) 
-#define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U) 
-#define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U) 
-#define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                    
-#define GPIO_AFRL_AFSEL1_Pos             (4U)  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                    
-#define GPIO_AFRL_AFSEL2_Pos             (8U)  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                    
-#define GPIO_AFRL_AFSEL3_Pos             (12U) 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                    
-#define GPIO_AFRL_AFSEL4_Pos             (16U) 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                    
-#define GPIO_AFRL_AFSEL5_Pos             (20U) 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                    
-#define GPIO_AFRL_AFSEL6_Pos             (24U) 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                    
-#define GPIO_AFRL_AFSEL7_Pos             (28U) 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                    
-#define GPIO_AFRH_AFSEL9_Pos             (4U)  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                    
-#define GPIO_AFRH_AFSEL10_Pos             (8U)  
-#define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk                    
-#define GPIO_AFRH_AFSEL11_Pos             (12U) 
-#define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk                    
-#define GPIO_AFRH_AFSEL12_Pos             (16U) 
-#define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk                    
-#define GPIO_AFRH_AFSEL13_Pos             (20U) 
-#define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk                    
-#define GPIO_AFRH_AFSEL14_Pos             (24U) 
-#define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk                    
-#define GPIO_AFRH_AFSEL15_Pos             (28U) 
-#define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)     
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)     
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)     
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)     
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)     
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)     
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)     
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)     
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)     
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)    
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)    
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)    
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)    
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)    
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)    
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)    
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)    
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)    
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)    
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)    
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)     
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)    
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)    
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)    
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)    
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)    
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)    
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)    
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)    
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)    
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)    
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)     
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)    
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)    
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)     
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)     
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)     
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)     
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)     
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)    
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)     
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)     
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)     
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)    
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)     
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)     
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)    
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)    
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)    
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)     
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)    
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)    
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)    
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)    
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)     
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)     
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)     
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)     
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)     
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)     
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)     
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)     
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)     
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)     
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)    
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)    
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)    
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)    
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)    
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)    
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)    
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)     
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)     
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)     
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)     
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)     
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)    
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)    
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)    
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)    
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)     
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)     
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)     
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)             
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)             
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)             
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)             
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)             
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)             
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)             
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos            (0U)      
-#define LCD_CR_LCDEN_Msk            (0x1UL << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
-#define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos             (1U)      
-#define LCD_CR_VSEL_Msk             (0x1UL << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
-#define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos             (2U)      
-#define LCD_CR_DUTY_Msk             (0x7UL << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
-#define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0               (0x1UL << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
-#define LCD_CR_DUTY_1               (0x2UL << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
-#define LCD_CR_DUTY_2               (0x4UL << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos             (5U)      
-#define LCD_CR_BIAS_Msk             (0x3UL << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
-#define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0               (0x1UL << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
-#define LCD_CR_BIAS_1               (0x2UL << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos          (7U)      
-#define LCD_CR_MUX_SEG_Msk          (0x1UL << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
-
-#define LCD_CR_BUFEN_Pos            (8U)
-#define LCD_CR_BUFEN_Msk            (0x1UL << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
-#define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos              (0U)      
-#define LCD_FCR_HD_Msk              (0x1UL << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
-#define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos           (1U)      
-#define LCD_FCR_SOFIE_Msk           (0x1UL << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
-#define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos           (3U)      
-#define LCD_FCR_UDDIE_Msk           (0x1UL << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
-#define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos             (4U)      
-#define LCD_FCR_PON_Msk             (0x7UL << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
-#define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0               (0x1UL << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
-#define LCD_FCR_PON_1               (0x2UL << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
-#define LCD_FCR_PON_2               (0x4UL << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos            (7U)      
-#define LCD_FCR_DEAD_Msk            (0x7UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
-#define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0              (0x1UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1              (0x2UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2              (0x4UL << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos              (10U)     
-#define LCD_FCR_CC_Msk              (0x7UL << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
-#define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0                (0x1UL << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
-#define LCD_FCR_CC_1                (0x2UL << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
-#define LCD_FCR_CC_2                (0x4UL << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos          (13U)     
-#define LCD_FCR_BLINKF_Msk          (0x7UL << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0            (0x1UL << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1            (0x2UL << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2            (0x4UL << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos           (16U)     
-#define LCD_FCR_BLINK_Msk           (0x3UL << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
-#define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0             (0x1UL << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1             (0x2UL << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos             (18U)     
-#define LCD_FCR_DIV_Msk             (0xFUL << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
-#define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos              (22U)     
-#define LCD_FCR_PS_Msk              (0xFUL << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
-#define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos              (0U)      
-#define LCD_SR_ENS_Msk              (0x1UL << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
-#define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos              (1U)      
-#define LCD_SR_SOF_Msk              (0x1UL << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
-#define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos              (2U)      
-#define LCD_SR_UDR_Msk              (0x1UL << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
-#define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos              (3U)      
-#define LCD_SR_UDD_Msk              (0x1UL << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
-#define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos              (4U)      
-#define LCD_SR_RDY_Msk              (0x1UL << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
-#define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos            (5U)      
-#define LCD_SR_FCRSR_Msk            (0x1UL << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
-#define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos            (1U)      
-#define LCD_CLR_SOFC_Msk            (0x1UL << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
-#define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos            (3U)      
-#define LCD_CLR_UDDC_Msk            (0x1UL << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
-#define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos    (0U)      
-#define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)      
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)      
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)      
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)      
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)      
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)      
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)      
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)      
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)      
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)      
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)      
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)      
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)      
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)      
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)      
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)      
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)      
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)      
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)      
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)      
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)      
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)      
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)      
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)      
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)      
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)      
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)     
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)     
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)     
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)     
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)     
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)     
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)     
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)     
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)      
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)      
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)      
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)      
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)      
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)      
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)             
-#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)             
-#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)             
-#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)             
-#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)             
-#define FW_VDSSA_ADD_Msk     (0x3FFUL << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)             
-#define FW_VDSL_LENG_Msk     (0x3FFUL << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)             
-#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)             
-#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)             
-#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)       
-#define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)       
-#define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)       
-#define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)       
-#define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)       
-#define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)       
-#define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)       
-#define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)       
-#define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)      
-#define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)      
-#define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)      
-#define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)      
-#define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)       
-#define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)       
-#define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)       
-#define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)       
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)       
-#define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)       
-#define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)       
-#define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)       
-#define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos          (10U)      
-#define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
-#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-#define RCC_MCO3_SUPPORT            /*!<Support MCO3 */
-#define RCC_MCO3_AF2_SUPPORT        /*!<Support MCO3 on Alternate Function AF0 */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U) 
-#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U) 
-#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U) 
-#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U) 
-#define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U) 
-#define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN_Pos              (5U) 
-#define RCC_CR_HSIOUTEN_Msk              (0x1UL << RCC_CR_HSIOUTEN_Pos)         /*!< 0x00000020 */
-#define RCC_CR_HSIOUTEN                  RCC_CR_HSIOUTEN_Msk                   /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION_Pos                 (8U) 
-#define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U) 
-#define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)
-#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)
-#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)
-#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)
-#define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)
-#define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC/LCD prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)
-#define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)
-#define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U) 
-#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U) 
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)
-#define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CRRCR register  *****************/
-#define RCC_CRRCR_HSI48ON_Pos            (0U) 
-#define RCC_CRRCR_HSI48ON_Msk            (0x1UL << RCC_CRRCR_HSI48ON_Pos)       /*!< 0x00000001 */
-#define RCC_CRRCR_HSI48ON                RCC_CRRCR_HSI48ON_Msk                 /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY_Pos           (1U) 
-#define RCC_CRRCR_HSI48RDY_Msk           (0x1UL << RCC_CRRCR_HSI48RDY_Pos)      /*!< 0x00000002 */
-#define RCC_CRRCR_HSI48RDY               RCC_CRRCR_HSI48RDY_Msk                /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48DIV6OUTEN_Pos     (2U) 
-#define RCC_CRRCR_HSI48DIV6OUTEN_Msk     (0x1UL << RCC_CRRCR_HSI48DIV6OUTEN_Pos) /*!< 0x00000004 */
-#define RCC_CRRCR_HSI48DIV6OUTEN         RCC_CRRCR_HSI48DIV6OUTEN_Msk          /*!< HSI 48MHz DIV6 out enable */
-#define RCC_CRRCR_HSI48CAL_Pos           (8U) 
-#define RCC_CRRCR_HSI48CAL_Msk           (0xFFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF00 */
-#define RCC_CRRCR_HSI48CAL               RCC_CRRCR_HSI48CAL_Msk                /*!< HSI 48MHz clock Calibration */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-#define RCC_CFGR_MCOSEL_HSI48_Pos            (27U)                             
-#define RCC_CFGR_MCOSEL_HSI48_Msk            (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
-#define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCOSEL_HSI48_Msk         /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#ifdef RCC_CFGR_MCOSEL_HSI48
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-#endif
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U) 
-#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U) 
-#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U) 
-#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U) 
-#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U) 
-#define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U) 
-#define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE_Pos          (6U) 
-#define RCC_CIER_HSI48RDYIE_Msk          (0x1UL << RCC_CIER_HSI48RDYIE_Pos)     /*!< 0x00000040 */
-#define RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE_Msk               /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U) 
-#define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U) 
-#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U) 
-#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U) 
-#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U) 
-#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U) 
-#define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U) 
-#define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF_Pos           (6U) 
-#define RCC_CIFR_HSI48RDYF_Msk           (0x1UL << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000040 */
-#define RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF_Msk                /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U) 
-#define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U) 
-#define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U) 
-#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U) 
-#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U) 
-#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U) 
-#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U) 
-#define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U) 
-#define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC_Pos           (6U) 
-#define RCC_CICR_HSI48RDYC_Msk           (0x1UL << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000040 */
-#define RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC_Msk                /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U) 
-#define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U) 
-#define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U) 
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U) 
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U) 
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U) 
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPERST_Pos          (4U) 
-#define RCC_IOPRSTR_IOPERST_Msk          (0x1UL << RCC_IOPRSTR_IOPERST_Pos)     /*!< 0x00000010 */
-#define RCC_IOPRSTR_IOPERST              RCC_IOPRSTR_IOPERST_Msk               /*!< GPIO port E reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U) 
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOERST                RCC_IOPRSTR_IOPERST        /*!< GPIO port E reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U) 
-#define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U) 
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST_Pos           (16U)
-#define RCC_AHBRSTR_TSCRST_Msk           (0x1UL << RCC_AHBRSTR_TSCRST_Pos)      /*!< 0x00010000 */
-#define RCC_AHBRSTR_TSCRST               RCC_AHBRSTR_TSCRST_Msk                /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST_Pos           (20U)
-#define RCC_AHBRSTR_RNGRST_Msk           (0x1UL << RCC_AHBRSTR_RNGRST_Pos)      /*!< 0x00100000 */
-#define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk                /*!< RNG reset */
-#define RCC_AHBRSTR_CRYPRST_Pos          (24U)
-#define RCC_AHBRSTR_CRYPRST_Msk          (0x1UL << RCC_AHBRSTR_CRYPRST_Pos)     /*!< 0x01000000 */
-#define RCC_AHBRSTR_CRYPRST              RCC_AHBRSTR_CRYPRST_Msk               /*!< Crypto reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U) 
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U) 
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U) 
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U) 
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1UL << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos         (1U)
-#define RCC_APB1RSTR_TIM3RST_Msk         (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)    /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST             RCC_APB1RSTR_TIM3RST_Msk              /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos         (5U)
-#define RCC_APB1RSTR_TIM7RST_Msk         (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)    /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST             RCC_APB1RSTR_TIM7RST_Msk              /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos          (9U)
-#define RCC_APB1RSTR_LCDRST_Msk          (0x1UL << RCC_APB1RSTR_LCDRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST              RCC_APB1RSTR_LCDRST_Msk               /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
-#define RCC_APB1RSTR_USART4RST_Pos       (19U)
-#define RCC_APB1RSTR_USART4RST_Msk       (0x1UL << RCC_APB1RSTR_USART4RST_Pos)  /*!< 0x00080000 */
-#define RCC_APB1RSTR_USART4RST           RCC_APB1RSTR_USART4RST_Msk            /*!< USART4 reset */
-#define RCC_APB1RSTR_USART5RST_Pos       (20U)
-#define RCC_APB1RSTR_USART5RST_Msk       (0x1UL << RCC_APB1RSTR_USART5RST_Pos)  /*!< 0x00100000 */
-#define RCC_APB1RSTR_USART5RST           RCC_APB1RSTR_USART5RST_Msk            /*!< USART5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos          (23U)
-#define RCC_APB1RSTR_USBRST_Msk          (0x1UL << RCC_APB1RSTR_USBRST_Pos)     /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST              RCC_APB1RSTR_USBRST_Msk               /*!< USB reset */
-#define RCC_APB1RSTR_CRSRST_Pos          (27U)
-#define RCC_APB1RSTR_CRSRST_Msk          (0x1UL << RCC_APB1RSTR_CRSRST_Pos)     /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST              RCC_APB1RSTR_CRSRST_Msk               /*!< CRS reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
-#define RCC_APB1RSTR_DACRST_Pos          (29U)
-#define RCC_APB1RSTR_DACRST_Msk          (0x1UL << RCC_APB1RSTR_DACRST_Pos)     /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST              RCC_APB1RSTR_DACRST_Msk               /*!< DAC reset */
-#define RCC_APB1RSTR_I2C3RST_Pos         (30U)
-#define RCC_APB1RSTR_I2C3RST_Msk         (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)    /*!< 0x40000000 */
-#define RCC_APB1RSTR_I2C3RST             RCC_APB1RSTR_I2C3RST_Msk              /*!< I2C3  reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U) 
-#define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U) 
-#define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U) 
-#define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U) 
-#define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPEEN_Pos            (4U) 
-#define RCC_IOPENR_IOPEEN_Msk            (0x1UL << RCC_IOPENR_IOPEEN_Pos)       /*!< 0x00000010 */
-#define RCC_IOPENR_IOPEEN                RCC_IOPENR_IOPEEN_Msk                 /*!< GPIO port E clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U) 
-#define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOEEN                  RCC_IOPENR_IOPEEN        /*!< GPIO port E clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U) 
-#define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U) 
-#define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)
-#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN_Pos             (16U)
-#define RCC_AHBENR_TSCEN_Msk             (0x1UL << RCC_AHBENR_TSCEN_Pos)        /*!< 0x00010000 */
-#define RCC_AHBENR_TSCEN                 RCC_AHBENR_TSCEN_Msk                  /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN_Pos             (20U)
-#define RCC_AHBENR_RNGEN_Msk             (0x1UL << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00100000 */
-#define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk                  /*!< RNG clock enable */
-#define RCC_AHBENR_CRYPEN_Pos            (24U)
-#define RCC_AHBENR_CRYPEN_Msk            (0x1UL << RCC_AHBENR_CRYPEN_Pos)       /*!< 0x01000000 */
-#define RCC_AHBENR_CRYPEN                RCC_AHBENR_CRYPEN_Msk                 /*!< Crypto clock enable*/
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U) 
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U) 
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U) 
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U) 
-#define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U) 
-#define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)
-#define RCC_APB2ENR_USART1EN_Msk         (0x1UL << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)
-#define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U) 
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM3EN_Pos           (1U) 
-#define RCC_APB1ENR_TIM3EN_Msk           (0x1UL << RCC_APB1ENR_TIM3EN_Pos)      /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN               RCC_APB1ENR_TIM3EN_Msk                /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U) 
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1UL << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos           (5U) 
-#define RCC_APB1ENR_TIM7EN_Msk           (0x1UL << RCC_APB1ENR_TIM7EN_Pos)      /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN               RCC_APB1ENR_TIM7EN_Msk                /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos            (9U) 
-#define RCC_APB1ENR_LCDEN_Msk            (0x1UL << RCC_APB1ENR_LCDEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                RCC_APB1ENR_LCDEN_Msk                 /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1UL << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)
-#define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_USART4EN_Pos         (19U)
-#define RCC_APB1ENR_USART4EN_Msk         (0x1UL << RCC_APB1ENR_USART4EN_Pos)    /*!< 0x00080000 */
-#define RCC_APB1ENR_USART4EN             RCC_APB1ENR_USART4EN_Msk              /*!< USART4 clock enable */
-#define RCC_APB1ENR_USART5EN_Pos         (20U)
-#define RCC_APB1ENR_USART5EN_Msk         (0x1UL << RCC_APB1ENR_USART5EN_Pos)    /*!< 0x00100000 */
-#define RCC_APB1ENR_USART5EN             RCC_APB1ENR_USART5EN_Msk              /*!< USART5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1UL << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos            (23U)
-#define RCC_APB1ENR_USBEN_Msk            (0x1UL << RCC_APB1ENR_USBEN_Pos)       /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                RCC_APB1ENR_USBEN_Msk                 /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN_Pos            (27U)
-#define RCC_APB1ENR_CRSEN_Msk            (0x1UL << RCC_APB1ENR_CRSEN_Pos)       /*!< 0x08000000 */
-#define RCC_APB1ENR_CRSEN                RCC_APB1ENR_CRSEN_Msk                 /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)
-#define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN_Pos            (29U)
-#define RCC_APB1ENR_DACEN_Msk            (0x1UL << RCC_APB1ENR_DACEN_Pos)       /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                RCC_APB1ENR_DACEN_Msk                 /*!< DAC clock enable */
-#define RCC_APB1ENR_I2C3EN_Pos           (30U)
-#define RCC_APB1ENR_I2C3EN_Msk           (0x1UL << RCC_APB1ENR_I2C3EN_Pos)      /*!< 0x40000000 */
-#define RCC_APB1ENR_I2C3EN               RCC_APB1ENR_I2C3EN_Msk                /*!< I2C3 clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U) 
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U) 
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U) 
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U) 
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPESMEN_Pos        (4U) 
-#define RCC_IOPSMENR_IOPESMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos)   /*!< 0x00000010 */
-#define RCC_IOPSMENR_IOPESMEN            RCC_IOPSMENR_IOPESMEN_Msk             /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U) 
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOESMEN              RCC_IOPSMENR_IOPESMEN        /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U) 
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U) 
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U) 
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN_Pos         (16U)
-#define RCC_AHBSMENR_TSCSMEN_Msk         (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos)    /*!< 0x00010000 */
-#define RCC_AHBSMENR_TSCSMEN             RCC_AHBSMENR_TSCSMEN_Msk              /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN_Pos         (20U)
-#define RCC_AHBSMENR_RNGSMEN_Msk         (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00100000 */
-#define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk              /*!< RNG clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRYPSMEN_Pos        (24U)
-#define RCC_AHBSMENR_CRYPSMEN_Msk        (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos)   /*!< 0x01000000 */
-#define RCC_AHBSMENR_CRYPSMEN            RCC_AHBSMENR_CRYPSMEN_Msk             /*!< Crypto clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U) 
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U) 
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U) 
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U) 
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U) 
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM3SMEN_Pos       (1U) 
-#define RCC_APB1SMENR_TIM3SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM3SMEN_Pos)  /*!< 0x00000002 */
-#define RCC_APB1SMENR_TIM3SMEN           RCC_APB1SMENR_TIM3SMEN_Msk            /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U) 
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM7SMEN_Pos       (5U) 
-#define RCC_APB1SMENR_TIM7SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM7SMEN_Pos)  /*!< 0x00000020 */
-#define RCC_APB1SMENR_TIM7SMEN           RCC_APB1SMENR_TIM7SMEN_Msk            /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LCDSMEN_Pos        (9U) 
-#define RCC_APB1SMENR_LCDSMEN_Msk        (0x1UL << RCC_APB1SMENR_LCDSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB1SMENR_LCDSMEN            RCC_APB1SMENR_LCDSMEN_Msk             /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART4SMEN_Pos     (19U)
-#define RCC_APB1SMENR_USART4SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1SMENR_USART4SMEN         RCC_APB1SMENR_USART4SMEN_Msk          /*!< USART4 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART5SMEN_Pos     (20U)
-#define RCC_APB1SMENR_USART5SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1SMENR_USART5SMEN         RCC_APB1SMENR_USART5SMEN_Msk          /*!< USART5 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN_Pos        (23U)
-#define RCC_APB1SMENR_USBSMEN_Msk        (0x1UL << RCC_APB1SMENR_USBSMEN_Pos)   /*!< 0x00800000 */
-#define RCC_APB1SMENR_USBSMEN            RCC_APB1SMENR_USBSMEN_Msk             /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN_Pos        (27U)
-#define RCC_APB1SMENR_CRSSMEN_Msk        (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos)   /*!< 0x08000000 */
-#define RCC_APB1SMENR_CRSSMEN            RCC_APB1SMENR_CRSSMEN_Msk             /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN_Pos        (29U)
-#define RCC_APB1SMENR_DACSMEN_Msk        (0x1UL << RCC_APB1SMENR_DACSMEN_Pos)   /*!< 0x20000000 */
-#define RCC_APB1SMENR_DACSMEN            RCC_APB1SMENR_DACSMEN_Msk             /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C3SMEN_Pos       (30U)
-#define RCC_APB1SMENR_I2C3SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C3SMEN_Pos)  /*!< 0x40000000 */
-#define RCC_APB1SMENR_I2C3SMEN           RCC_APB1SMENR_I2C3SMEN_Msk            /*!< I2C3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U) 
-#define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U) 
-#define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-/*!< I2C3 Clock source selection */
-#define RCC_CCIPR_I2C3SEL_Pos            (16U)
-#define RCC_CCIPR_I2C3SEL_Msk            (0x3UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00030000 */
-#define RCC_CCIPR_I2C3SEL                RCC_CCIPR_I2C3SEL_Msk                 /*!< I2C3SEL [1:0] bits */
-#define RCC_CCIPR_I2C3SEL_0              (0x1UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00010000 */
-#define RCC_CCIPR_I2C3SEL_1              (0x2UL << RCC_CCIPR_I2C3SEL_Pos)       /*!< 0x00020000 */
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*!< HSI48 Clock source selection */ 
-#define RCC_CCIPR_HSI48SEL_Pos           (26U)
-#define RCC_CCIPR_HSI48SEL_Msk           (0x1UL << RCC_CCIPR_HSI48SEL_Pos)      /*!< 0x04000000 */
-#define RCC_CCIPR_HSI48SEL               RCC_CCIPR_HSI48SEL_Msk                /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Legacy defines */
-#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U) 
-#define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U) 
-#define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U) 
-#define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U) 
-#define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)
-#define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)
-#define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)
-#define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)
-#define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)
-#define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)
-#define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)
-#define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)
-#define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)
-#define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)
-#define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)
-#define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)
-#define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)
-#define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)
-#define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)
-#define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)
-#define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos    (2U)              
-#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
-#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
-#define RNG_CR_IE_Pos       (3U)              
-#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
-#define RNG_CR_IE           RNG_CR_IE_Msk                                      
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)              
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
-#define RNG_SR_CECS_Pos     (1U)              
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
-#define RNG_SR_SECS_Pos     (2U)              
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
-#define RNG_SR_CEIS_Pos     (5U)              
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
-#define RNG_SR_SEIS_Pos     (6U)              
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)  
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)  
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)  
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)  
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)   
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)   
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)   
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)  
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)  
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)  
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)  
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)   
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)   
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)   
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)  
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)  
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)  
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)  
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BKP_Pos                 (18U)  
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)  
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)  
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)  
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)  
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)  
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)  
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)  
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)  
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)   
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)   
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)   
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)   
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)   
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)   
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)   
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)  
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP3F_Pos             (15U)  
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)  
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)  
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)  
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)  
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)  
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)   
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)   
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)   
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)   
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)   
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)   
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)   
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)   
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)   
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)   
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)  
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)   
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)   
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)  
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)  
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)  
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)  
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)  
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)  
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)  
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)  
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)  
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)  
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)   
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)   
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)   
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)   
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)  
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)  
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)  
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)  
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)  
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)  
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)  
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)  
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)  
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)  
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)   
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)   
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)   
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)   
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)   
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)   
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)   
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)  
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)  
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)  
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)  
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)  
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)   
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)   
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)   
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)  
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)  
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)   
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)   
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)   
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)   
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)  
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)  
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)  
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)   
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)  
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)  
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)  
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)  
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)  
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)  
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)  
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)  
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)  
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)  
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)  
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)  
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)   
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)   
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)   
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)   
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)   
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)   
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)   
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)   
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)   
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)   
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)  
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)   
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)   
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)   
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)   
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)   
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)   
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)   
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)   
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)      
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)      
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)      
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)      
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)      
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)      
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)      
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)      
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)     
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)     
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)     
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)     
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)     
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)     
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)      
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)      
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)      
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)      
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)      
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)      
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)      
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)      
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)      
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)      
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)      
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)      
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)      
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)      
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)      
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)      
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)      
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)      
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)      
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)      
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)      
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)      
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)      
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)      
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)      
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)      
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)     
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)     
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)     
-#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */
-#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)      
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)      
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)      
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_UFB_Pos                     (3U)                          
-#define SYSCFG_CFGR1_UFB_Msk                     (0x1UL << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */
-#define SYSCFG_CFGR1_UFB                         SYSCFG_CFGR1_UFB_Msk          /*!< User bank swapping */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_CAPA_Pos                    (1U)                          
-#define SYSCFG_CFGR2_CAPA_Msk                    (0x1FUL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x0000003E */
-#define SYSCFG_CFGR2_CAPA                        SYSCFG_CFGR2_CAPA_Msk         /*!< Connection of internal Vlcd rail to external capacitors */
-#define SYSCFG_CFGR2_CAPA_0                      (0x01UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR2_CAPA_1                      (0x02UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000004 */
-#define SYSCFG_CFGR2_CAPA_2                      (0x04UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000008 */
-#define SYSCFG_CFGR2_CAPA_3                      (0x08UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR2_CAPA_4                      (0x10UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-#define SYSCFG_CFGR2_I2C3_FMP_Pos                (14U)                         
-#define SYSCFG_CFGR2_I2C3_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */
-#define SYSCFG_CFGR2_I2C3_FMP                    SYSCFG_CFGR2_I2C3_FMP_Msk     /*!< I2C3 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD                  (0x00000003U)                 /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE                  (0x00000004U)                 /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD                  (0x00000030U)                 /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE                  (0x00000040U)                 /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE                  (0x00000400U)                 /*!< PE[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD                  (0x00003000U)                 /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE                  (0x00004000U)                 /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD                  (0x00000003U)                 /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE                  (0x00000004U)                 /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD                  (0x00000030U)                 /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE                  (0x00000040U)                 /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD                  (0x00000300U)                 /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE                  (0x00000400U)                 /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD                  (0x00003000U)                 /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE                  (0x00004000U)                 /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD                  (0x00000003U)                 /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE                  (0x00000004U)                 /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD                  (0x00000030U)                 /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE                  (0x00000040U)                 /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH                  (0x00000050U)                 /*!< PH[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD                 (0x00000300U)                 /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE                 (0x00000400U)                 /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH                 (0x00000500U)                 /*!< PH[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD                 (0x00003000U)                 /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE                 (0x00004000U)                 /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD                 (0x00000003U)                 /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE                 (0x00000004U)                 /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD                 (0x00000030U)                 /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE                 (0x00000040U)                 /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD                 (0x00000300U)                 /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE                 (0x00000400U)                 /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD                 (0x00003000U)                 /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE                 (0x00004000U)                 /*!< PE[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)                          
-#define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48_Pos             (13U)                         
-#define SYSCFG_CFGR3_ENREF_HSI48_Msk             (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR3_ENREF_HSI48                 SYSCFG_CFGR3_ENREF_HSI48_Msk  /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
-#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_REF_HSI48_RDYF           SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)*/
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#define TIM_TIM2_REMAP_HSI_SUPPORT       /*!<Support remap HSI on TIM2 */
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)        
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)        
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)        
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)        
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)        
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)        
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)        
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)        
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)        
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)        
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)        
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)        
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos           (4U)        
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)        
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)        
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)       
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)       
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)       
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)        
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)        
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)        
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)        
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)        
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)        
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)        
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)        
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)       
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)       
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)       
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)       
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)        
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)        
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)        
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)        
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)        
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)        
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)        
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)       
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)       
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)       
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)        
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)        
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)        
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)        
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)        
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)        
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)        
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)        
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)        
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)        
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)        
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)        
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)       
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)       
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)       
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)       
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)        
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)        
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)       
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)       
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)        
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)        
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)        
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)        
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)        
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)        
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)       
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)       
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)       
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)       
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)        
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)        
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)       
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)       
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)        
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)        
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)        
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)        
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)        
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)        
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)        
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)        
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)       
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)       
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)       
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)       
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)        
-#define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)        
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)        
-#define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)        
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)        
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)        
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)        
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)        
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)        
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)        
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)         
-#define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)         
-#define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)        
-#define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)        
-#define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)        
-#define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)        
-#define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)        
-#define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-#define TIM3_OR_ETR_RMP_Pos      (0U)         
-#define TIM3_OR_ETR_RMP_Msk      (0x3UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000003 */
-#define TIM3_OR_ETR_RMP          TIM3_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
-#define TIM3_OR_ETR_RMP_0        (0x1UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM3_OR_ETR_RMP_1        (0x2UL << TIM3_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM3_OR_TI1_RMP_Pos      (2U)         
-#define TIM3_OR_TI1_RMP_Msk      (0x1UL << TIM3_OR_TI1_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM3_OR_TI1_RMP          TIM3_OR_TI1_RMP_Msk                           /*!<TI1_RMP[2] bit                      */
-#define TIM3_OR_TI2_RMP_Pos      (3U)         
-#define TIM3_OR_TI2_RMP_Msk      (0x1UL << TIM3_OR_TI2_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM3_OR_TI2_RMP          TIM3_OR_TI2_RMP_Msk                           /*!<TI2_RMP[3] bit                      */
-#define TIM3_OR_TI4_RMP_Pos      (4U)         
-#define TIM3_OR_TI4_RMP_Msk      (0x1UL << TIM3_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-#define TIM3_OR_TI4_RMP          TIM3_OR_TI4_RMP_Msk                           /*!<TI4_RMP[4] bit                      */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE_Pos          (0U)         
-#define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
-#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
-#define TSC_CR_START_Pos         (1U)         
-#define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
-#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
-#define TSC_CR_AM_Pos            (2U)         
-#define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
-#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL_Pos       (3U)         
-#define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
-#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF_Pos         (4U)         
-#define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
-#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
-
-#define TSC_CR_MCV_Pos           (5U)         
-#define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
-#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
-#define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
-#define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
-
-#define TSC_CR_PGPSC_Pos         (12U)        
-#define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
-#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
-#define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
-#define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
-
-#define TSC_CR_SSPSC_Pos         (15U)        
-#define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
-#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE_Pos           (16U)        
-#define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
-#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD_Pos           (17U)        
-#define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
-#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
-#define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
-#define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
-#define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
-#define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
-#define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
-#define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
-
-#define TSC_CR_CTPL_Pos          (24U)        
-#define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
-#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
-#define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
-#define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
-#define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
-
-#define TSC_CR_CTPH_Pos          (28U)        
-#define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
-#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
-#define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
-#define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
-#define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE_Pos        (0U)         
-#define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
-#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE_Pos        (1U)         
-#define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
-#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC_Pos        (0U)         
-#define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
-#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC_Pos        (1U)         
-#define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
-#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF_Pos         (0U)         
-#define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
-#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
-#define TSC_ISR_MCEF_Pos         (1U)         
-#define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
-#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1_Pos     (0U)         
-#define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2_Pos     (1U)         
-#define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3_Pos     (2U)         
-#define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4_Pos     (3U)         
-#define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1_Pos     (4U)         
-#define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2_Pos     (5U)         
-#define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3_Pos     (6U)         
-#define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4_Pos     (7U)         
-#define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1_Pos     (8U)         
-#define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2_Pos     (9U)         
-#define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3_Pos     (10U)        
-#define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4_Pos     (11U)        
-#define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1_Pos     (12U)        
-#define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2_Pos     (13U)        
-#define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3_Pos     (14U)        
-#define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4_Pos     (15U)        
-#define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1_Pos     (16U)        
-#define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2_Pos     (17U)        
-#define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3_Pos     (18U)        
-#define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4_Pos     (19U)        
-#define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1_Pos     (20U)        
-#define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2_Pos     (21U)        
-#define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3_Pos     (22U)        
-#define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4_Pos     (23U)        
-#define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1_Pos     (24U)        
-#define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2_Pos     (25U)        
-#define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3_Pos     (26U)        
-#define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4_Pos     (27U)        
-#define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1_Pos     (28U)        
-#define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2_Pos     (29U)        
-#define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3_Pos     (30U)        
-#define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4_Pos     (31U)        
-#define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1_Pos    (0U)         
-#define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
-#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2_Pos    (1U)         
-#define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
-#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3_Pos    (2U)         
-#define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
-#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4_Pos    (3U)         
-#define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
-#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1_Pos    (4U)         
-#define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
-#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2_Pos    (5U)         
-#define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
-#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3_Pos    (6U)         
-#define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
-#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4_Pos    (7U)         
-#define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
-#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1_Pos    (8U)         
-#define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
-#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2_Pos    (9U)         
-#define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
-#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3_Pos    (10U)        
-#define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
-#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4_Pos    (11U)        
-#define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
-#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1_Pos    (12U)        
-#define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
-#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2_Pos    (13U)        
-#define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
-#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3_Pos    (14U)        
-#define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
-#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4_Pos    (15U)        
-#define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
-#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1_Pos    (16U)        
-#define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
-#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2_Pos    (17U)        
-#define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
-#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3_Pos    (18U)        
-#define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
-#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4_Pos    (19U)        
-#define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
-#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1_Pos    (20U)        
-#define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
-#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2_Pos    (21U)        
-#define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
-#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3_Pos    (22U)        
-#define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
-#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4_Pos    (23U)        
-#define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
-#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1_Pos    (24U)        
-#define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
-#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2_Pos    (25U)        
-#define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
-#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3_Pos    (26U)        
-#define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
-#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4_Pos    (27U)        
-#define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
-#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1_Pos    (28U)        
-#define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
-#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2_Pos    (29U)        
-#define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
-#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3_Pos    (30U)        
-#define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
-#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4_Pos    (31U)        
-#define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
-#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1_Pos     (0U)         
-#define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2_Pos     (1U)         
-#define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3_Pos     (2U)         
-#define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4_Pos     (3U)         
-#define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1_Pos     (4U)         
-#define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2_Pos     (5U)         
-#define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3_Pos     (6U)         
-#define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4_Pos     (7U)         
-#define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1_Pos     (8U)         
-#define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2_Pos     (9U)         
-#define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3_Pos     (10U)        
-#define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4_Pos     (11U)        
-#define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1_Pos     (12U)        
-#define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2_Pos     (13U)        
-#define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3_Pos     (14U)        
-#define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4_Pos     (15U)        
-#define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1_Pos     (16U)        
-#define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2_Pos     (17U)        
-#define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3_Pos     (18U)        
-#define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4_Pos     (19U)        
-#define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1_Pos     (20U)        
-#define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2_Pos     (21U)        
-#define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3_Pos     (22U)        
-#define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4_Pos     (23U)        
-#define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1_Pos     (24U)        
-#define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2_Pos     (25U)        
-#define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3_Pos     (26U)        
-#define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4_Pos     (27U)        
-#define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1_Pos     (28U)        
-#define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2_Pos     (29U)        
-#define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3_Pos     (30U)        
-#define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4_Pos     (31U)        
-#define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1_Pos     (0U)         
-#define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2_Pos     (1U)         
-#define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3_Pos     (2U)         
-#define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4_Pos     (3U)         
-#define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1_Pos     (4U)         
-#define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2_Pos     (5U)         
-#define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3_Pos     (6U)         
-#define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4_Pos     (7U)         
-#define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1_Pos     (8U)         
-#define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2_Pos     (9U)         
-#define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3_Pos     (10U)        
-#define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4_Pos     (11U)        
-#define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1_Pos     (12U)        
-#define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2_Pos     (13U)        
-#define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3_Pos     (14U)        
-#define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4_Pos     (15U)        
-#define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1_Pos     (16U)        
-#define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2_Pos     (17U)        
-#define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3_Pos     (18U)        
-#define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4_Pos     (19U)        
-#define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1_Pos     (20U)        
-#define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2_Pos     (21U)        
-#define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3_Pos     (22U)        
-#define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4_Pos     (23U)        
-#define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1_Pos     (24U)        
-#define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2_Pos     (25U)        
-#define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3_Pos     (26U)        
-#define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4_Pos     (27U)        
-#define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1_Pos     (28U)        
-#define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2_Pos     (29U)        
-#define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3_Pos     (30U)        
-#define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4_Pos     (31U)        
-#define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E_Pos       (0U)         
-#define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
-#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E_Pos       (1U)         
-#define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
-#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E_Pos       (2U)         
-#define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
-#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E_Pos       (3U)         
-#define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
-#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E_Pos       (4U)         
-#define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
-#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E_Pos       (5U)         
-#define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
-#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E_Pos       (6U)         
-#define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
-#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E_Pos       (7U)         
-#define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
-#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S_Pos       (16U)        
-#define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
-#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S_Pos       (17U)        
-#define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
-#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S_Pos       (18U)        
-#define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
-#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S_Pos       (19U)        
-#define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
-#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S_Pos       (20U)        
-#define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
-#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S_Pos       (21U)        
-#define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
-#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S_Pos       (22U)        
-#define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
-#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S_Pos       (23U)        
-#define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
-#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT_Pos       (0U)         
-#define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
-#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)    
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)    
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)    
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)    
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)    
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)    
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)    
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)    
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)    
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)   
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)   
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)   
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)   
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)   
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)   
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)   
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)   
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)   
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)   
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)   
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)   
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)    
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)    
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)    
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)    
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)    
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)   
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)   
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)   
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)   
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)   
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)   
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)   
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)   
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)   
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)   
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)   
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)   
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)   
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)    
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)    
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)    
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)    
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)    
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)    
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)    
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)    
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)    
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)    
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)   
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)   
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)   
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)   
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)   
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)   
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)   
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)   
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)   
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)   
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)    
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)    
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)    
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)    
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)    
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)   
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)    
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)    
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)    
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)    
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)    
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)    
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)    
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)    
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)    
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)    
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)    
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)    
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)    
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)    
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)    
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)   
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)   
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)   
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)   
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)   
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)   
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)   
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)   
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)   
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)   
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)   
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)   
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)    
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)    
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)    
-#define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)    
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)    
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)    
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)    
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)    
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)   
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)   
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)   
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)   
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/* Compatibility defines with other series */
-#define USART_ICR_NECF                USART_ICR_NCF
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)    
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)    
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         USB Device General registers                       */
-/*                                                                            */
-/******************************************************************************/
-#define USB_BASE                              (0x40005C00U)                    /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR_Pos           (13U)       
-#define USB_PMAADDR_Msk           (0x20003UL << USB_PMAADDR_Pos)                /*!< 0x40006000 */
-#define USB_PMAADDR               USB_PMAADDR_Msk                              /*!< USB_IP Packet Memory Area base address */
-                                             
-#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
-#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
-#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
-#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
-#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
-#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
-#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
-
-/****************************  ISTR interrupt events  *************************/
-#define USB_ISTR_CTR                          ((uint16_t)0x8000U)              /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR                       ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR                          ((uint16_t)0x2000U)              /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP                         ((uint16_t)0x1000U)              /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP                         ((uint16_t)0x0800U)              /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET                        ((uint16_t)0x0400U)              /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF                          ((uint16_t)0x0200U)              /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF                         ((uint16_t)0x0100U)              /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ                        ((uint16_t)0x0080U)              /*!< LPM L1 state request  */
-#define USB_ISTR_DIR                          ((uint16_t)0x0010U)              /*!< DIRection of transaction (read-only bit)  */
-#define USB_ISTR_EP_ID                        ((uint16_t)0x000FU)              /*!< EndPoint IDentifier (read-only bit)  */
-
-#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
-#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
-#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
-#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
-#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
-#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
-#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
-#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
-/*************************  CNTR control register bits definitions  ***********/
-#define USB_CNTR_CTRM                         ((uint16_t)0x8000U)              /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM                      ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM                         ((uint16_t)0x2000U)              /*!< ERRor Mask */
-#define USB_CNTR_WKUPM                        ((uint16_t)0x1000U)              /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM                        ((uint16_t)0x0800U)              /*!< SUSPend Mask */
-#define USB_CNTR_RESETM                       ((uint16_t)0x0400U)              /*!< RESET Mask   */
-#define USB_CNTR_SOFM                         ((uint16_t)0x0200U)              /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM                        ((uint16_t)0x0100U)              /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM                       ((uint16_t)0x0080U)              /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME                     ((uint16_t)0x0020U)              /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME                       ((uint16_t)0x0010U)              /*!< RESUME request */
-#define USB_CNTR_FSUSP                        ((uint16_t)0x0008U)              /*!< Force SUSPend */
-#define USB_CNTR_LPMODE                       ((uint16_t)0x0004U)              /*!< Low-power MODE */
-#define USB_CNTR_PDWN                         ((uint16_t)0x0002U)              /*!< Power DoWN */
-#define USB_CNTR_FRES                         ((uint16_t)0x0001U)              /*!< Force USB RESet */
-/*************************  BCDR control register bits definitions  ***********/
-#define USB_BCDR_DPPU                         ((uint16_t)0x8000U)              /*!< DP Pull-up Enable */  
-#define USB_BCDR_PS2DET                       ((uint16_t)0x0080U)              /*!< PS2 port or proprietary charger detected */  
-#define USB_BCDR_SDET                         ((uint16_t)0x0040U)              /*!< Secondary detection (SD) status */  
-#define USB_BCDR_PDET                         ((uint16_t)0x0020U)              /*!< Primary detection (PD) status */ 
-#define USB_BCDR_DCDET                        ((uint16_t)0x0010U)              /*!< Data contact detection (DCD) status */ 
-#define USB_BCDR_SDEN                         ((uint16_t)0x0008U)              /*!< Secondary detection (SD) mode enable */ 
-#define USB_BCDR_PDEN                         ((uint16_t)0x0004U)              /*!< Primary detection (PD) mode enable */  
-#define USB_BCDR_DCDEN                        ((uint16_t)0x0002U)              /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN                        ((uint16_t)0x0001U)              /*!< Battery charging detector (BCD) enable */
-/***************************  LPM register bits definitions  ******************/
-#define USB_LPMCSR_BESL                       ((uint16_t)0x00F0U)              /*!< BESL value received with last ACKed LPM Token  */ 
-#define USB_LPMCSR_REMWAKE                    ((uint16_t)0x0008U)              /*!< bRemoteWake value received with last ACKed LPM Token */ 
-#define USB_LPMCSR_LPMACK                     ((uint16_t)0x0002U)              /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN                      ((uint16_t)0x0001U)              /*!< LPM support enable  */
-/********************  FNR Frame Number Register bit definitions   ************/
-#define USB_FNR_RXDP                          ((uint16_t)0x8000U)              /*!< status of D+ data line */
-#define USB_FNR_RXDM                          ((uint16_t)0x4000U)              /*!< status of D- data line */
-#define USB_FNR_LCK                           ((uint16_t)0x2000U)              /*!< LoCKed */
-#define USB_FNR_LSOF                          ((uint16_t)0x1800U)              /*!< Lost SOF */
-#define USB_FNR_FN                            ((uint16_t)0x07FFU)              /*!< Frame Number */
-/********************  DADDR Device ADDRess bit definitions    ****************/
-#define USB_DADDR_EF                          ((uint8_t)0x80U)                 /*!< USB device address Enable Function */
-#define USB_DADDR_ADD                         ((uint8_t)0x7FU)                 /*!< USB device address */
-/******************************  Endpoint register    *************************/
-#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
-#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
-#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
-#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
-#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
-#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
-#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
-#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
-/* bit positions */ 
-#define USB_EP_CTR_RX                         ((uint16_t)0x8000U)              /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX                        ((uint16_t)0x4000U)              /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT                         ((uint16_t)0x3000U)              /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP                          ((uint16_t)0x0800U)              /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD                        ((uint16_t)0x0600U)              /*!<  EndPoint TYPE */
-#define USB_EP_KIND                           ((uint16_t)0x0100U)              /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX                         ((uint16_t)0x0080U)              /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX                        ((uint16_t)0x0040U)              /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT                         ((uint16_t)0x0030U)              /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD                      ((uint16_t)0x000FU)              /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK                      ((uint16_t)0x0600U)              /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           ((uint16_t)0x0000U)              /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        ((uint16_t)0x0200U)              /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    ((uint16_t)0x0400U)              /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      ((uint16_t)0x0600U)              /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
-                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       ((uint16_t)0x0010U)              /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         ((uint16_t)0x0020U)              /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       ((uint16_t)0x0030U)              /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        ((uint16_t)0x0010U)              /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        ((uint16_t)0x0020U)              /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       ((uint16_t)0x1000U)              /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         ((uint16_t)0x2000U)              /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       ((uint16_t)0x3000U)              /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        ((uint16_t)0x1000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        ((uint16_t)0x2000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)          
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)          
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)          
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)          
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)          
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)          
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* AES Instances ********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                                   ((INSTANCE) == I2C3))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                     ((INSTANCE) == I2C3))
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/************* LPTIM instances supporting the encoder mode feature ************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM7)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM3)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3) || \
-                                            ((INSTANCE) == TIM6) || \
-                                            ((INSTANCE) == TIM7))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                           ((INSTANCE) == TIM3))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-   (((((INSTANCE) == TIM2) ||                  \
-      ((INSTANCE) == TIM3))                    \
-     &&                                        \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM3)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM3)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM3)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM3)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM7)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                                ((INSTANCE) == TIM3))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/****************************** TSC Instances *********************************/
-#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART4) || \
-                                    ((INSTANCE) == USART5))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART4) || \
-                                     ((INSTANCE) == USART5))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART4) || \
-                                           ((INSTANCE) == USART5) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/******************************* USB Instances *******************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define LPUART1_IRQn                   AES_RNG_LPUART1_IRQn
-#define AES_LPUART1_IRQn               AES_RNG_LPUART1_IRQn
-#define RNG_LPUART1_IRQn               AES_RNG_LPUART1_IRQn
-#define TIM6_IRQn                      TIM6_DAC_IRQn
-#define RCC_IRQn                       RCC_CRS_IRQn
-#define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
-#define ADC1_IRQn                      ADC1_COMP_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             AES_RNG_LPUART1_IRQHandler
-#define RNG_LPUART1_IRQHandler         AES_RNG_LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         AES_RNG_LPUART1_IRQHandler
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
-#define RCC_IRQHandler                 RCC_CRS_IRQHandler
-#define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
-#define ADC1_IRQHandler                ADC1_COMP_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L083xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h
deleted file mode 100644
index 1f03d6dd51..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L0xx devices.            
-  *            
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral's drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral's registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */ 
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx
-  * @{
-  */
-    
-#ifndef __STM32L0xx_H
-#define __STM32L0xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-   
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/**
-  * @brief STM32 Family
-  */
-#if !defined (STM32L0)
-#define STM32L0
-#endif /* STM32L0 */
-
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L010xB) && \
-    !defined (STM32L011xx) && !defined (STM32L021xx) && \
-    !defined (STM32L031xx) && !defined (STM32L041xx) && \
-    !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \
-    !defined (STM32L062xx) && !defined (STM32L063xx) && \
-    !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \
-    !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx)
-  /* #define STM32L010x4 */   /*!< STM32L010K4, STM32L010F4 Devices                                                                                                                      */
-  /* #define STM32L010x6 */   /*!< STM32L010C6 Devices                                                                                                                                   */
-  /* #define STM32L010x8 */   /*!< STM32L010K8, STM32L010R8 Devices                                                                                                                      */
-  /* #define STM32L010xB */   /*!< STM32L010RB Devices                                                                                                                                   */
-  /* #define STM32L011xx */   /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices                                                                               */
-  /* #define STM32L021xx */   /*!< STM32L021D4, STM32L021F4, STM32L021G4, STM32L021K4 Devices                                                                                            */
-  /* #define STM32L031xx */   /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices                                                                               */
-  /* #define STM32L041xx */   /*!< STM32L041C6, STM32L041K6, STM32L041G6, STM32L041F6, STM32L041E6 Devices                                                                               */
-  /* #define STM32L051xx */   /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8, STM32L051K6, STM32L051T6, STM32L051T8 Devices                                        */
-  /* #define STM32L052xx */   /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8, STM32L052T6, STM32L052T8 Devices                                        */
-  /* #define STM32L053xx */   /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices                                                                                            */
-  /* #define STM32L062xx */   /*!< STM32L062K8 Devices                                                                                                                                   */
-  /* #define STM32L063xx */   /*!< STM32L063C8, STM32L063R8 Devices                                                                                                                      */
-  /* #define STM32L071xx */   /*!< STM32L071V8, STM32L071K8, STM32L071VB, STM32L071RB, STM32L071CB, STM32L071KB, STM32L071VZ, STM32L071RZ, STM32L071CZ, STM32L071KZ, STM32L071C8 Devices */
-  /* #define STM32L072xx */   /*!< STM32L072V8, STM32L072VB, STM32L072RB, STM32L072CB, STM32L072VZ, STM32L072RZ, STM32L072CZ, STM32L072KB, STM32L072KZ Devices                           */
-  /* #define STM32L073xx */   /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ, STM32L073CB, STM32L073CZ Devices                                                     */
-  /* #define STM32L081xx */   /*!< STM32L081CB, STM32L081CZ, STM32L081KZ Devices                                                                                                         */
-  /* #define STM32L082xx */   /*!< STM32L082KB, STM32L082KZ, STM32L082CZ Devices                                                                                                         */
-  /* #define STM32L083xx */   /*!< STM32L083V8, STM32L083VB, STM32L083RB, STM32L083VZ, STM32L083RZ, STM32L083CB, STM32L083CZ Devices                                                     */
-#endif
-   
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_HAL_DRIVER */
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number
-  */
-#define __STM32L0xx_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32L0xx_CMSIS_VERSION_SUB1   (0x09) /*!< [23:16] sub1 version */
-#define __STM32L0xx_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
-#define __STM32L0xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
-#define __STM32L0xx_CMSIS_VERSION        ((__STM32L0xx_CMSIS_VERSION_MAIN     << 24)\
-                                         |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
-                                         |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
-                                         |(__STM32L0xx_CMSIS_VERSION_RC))
-                                             
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-#if defined(STM32L010xB)
-  #include "stm32l010xb.h"
-#elif defined(STM32L010x8)
-  #include "stm32l010x8.h"
-#elif defined(STM32L010x6)
-  #include "stm32l010x6.h"
-#elif defined(STM32L010x4)
-  #include "stm32l010x4.h"
-#elif defined(STM32L011xx)
-  #include "stm32l011xx.h"
-#elif defined(STM32L021xx)
-  #include "stm32l021xx.h"
-#elif defined(STM32L031xx)
-  #include "stm32l031xx.h"
-#elif defined(STM32L041xx)
-  #include "stm32l041xx.h"
-#elif defined(STM32L051xx)
-  #include "stm32l051xx.h"
-#elif defined(STM32L052xx)
-  #include "stm32l052xx.h"
-#elif defined(STM32L053xx)
-  #include "stm32l053xx.h"
-#elif defined(STM32L062xx)
-  #include "stm32l062xx.h"
-#elif defined(STM32L063xx)
-  #include "stm32l063xx.h"
-#elif defined(STM32L071xx)
-  #include "stm32l071xx.h"
-#elif defined(STM32L072xx)
-  #include "stm32l072xx.h"
-#elif defined(STM32L073xx)
-  #include "stm32l073xx.h"
-#elif defined(STM32L082xx)
-  #include "stm32l082xx.h"
-#elif defined(STM32L083xx)
-  #include "stm32l083xx.h"
-#elif defined(STM32L081xx)
-  #include "stm32l081xx.h"
-#else
- #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */ 
-typedef enum 
-{
-  RESET = 0, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum 
-{
-  SUCCESS = 0,
-  ERROR = !SUCCESS
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/* Use of interrupt control for register exclusive access */
-/* Atomic 32-bit register access macro to set one or several bits */
-#define ATOMIC_SET_BIT(REG, BIT)                             \
-  do {                                                       \
-    uint32_t primask;                                        \
-    primask = __get_PRIMASK();                               \
-    __set_PRIMASK(1);                                        \
-    SET_BIT((REG), (BIT));                                   \
-    __set_PRIMASK(primask);                                  \
-  } while(0)
-
-/* Atomic 32-bit register access macro to clear one or several bits */
-#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
-  do {                                                       \
-    uint32_t primask;                                        \
-    primask = __get_PRIMASK();                               \
-    __set_PRIMASK(1);                                        \
-    CLEAR_BIT((REG), (BIT));                                 \
-    __set_PRIMASK(primask);                                  \
-  } while(0)
-
-/* Atomic 32-bit register access macro to clear and set one or several bits */
-#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)            \
-  do {                                                       \
-    uint32_t primask;                                        \
-    primask = __get_PRIMASK();                               \
-    __set_PRIMASK(1);                                        \
-    MODIFY_REG((REG), (CLEARMSK), (SETMASK));                \
-    __set_PRIMASK(primask);                                  \
-  } while(0)
-
-/* Atomic 16-bit register access macro to set one or several bits */
-#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT)                                   \
-
-/* Atomic 16-bit register access macro to clear one or several bits */
-#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT)                               \
-
-/* Atomic 16-bit register access macro to clear and set one or several bits */
-#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32l0xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L0xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h
deleted file mode 100644
index 8c30248164..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32L0XX_H
-#define __SYSTEM_STM32L0XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32L0xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32L0xx_System_Exported_types
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-/*
-*/
-extern const uint8_t AHBPrescTable[16];   /*!< AHB prescalers table values */
-extern const uint8_t APBPrescTable[8];    /*!< APB prescalers table values */
-extern const uint8_t PLLMulTable[9];      /*!< PLL multipiers table values */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32L0XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Release_Notes.html b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Release_Notes.html
deleted file mode 100644
index b36c0a1f71..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Release_Notes.html
+++ /dev/null
@@ -1,381 +0,0 @@
-<!DOCTYPE html>
-<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
-<head>
-  <meta charset="utf-8" />
-  <meta name="generator" content="pandoc" />
-  <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
-  <title>Release Notes for STM32L0xx CMSIS</title>
-  <style>
-      code{white-space: pre-wrap;}
-      span.smallcaps{font-variant: small-caps;}
-      span.underline{text-decoration: underline;}
-      div.column{display: inline-block; vertical-align: top; width: 50%;}
-  </style>
-  <link rel="stylesheet" href="_htmresc/mini-st.css" />
-  <!--[if lt IE 9]>
-    <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
-  <![endif]-->
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-<h1 id="release-notes-for-stm32l0xx-cmsis"><small>Release Notes for</small> <mark>STM32L0xx CMSIS</mark></h1>
-<p>Copyright © 2009-2018 ARM Limited - STMicroelectronics<br />
-</p>
-<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
-</center>
-</div>
-</div>
-<h1 id="license">License</h1>
-<p>Licensed by ST under Apache-2.0 license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
-<p><a href="../../../LICENSE.txt">Apache License v2.0</a></p>
-<h1 id="purpose">Purpose</h1>
-<p>This driver provides the CMSIS device for the stm32l1xx products. This covers:</p>
-<ul>
-<li>STM32L010xx devices</li>
-<li>STM32L011xx and STM32L021xx devices</li>
-<li>STM32L031xx and STM32L041xx devices</li>
-<li>STM32L051xx, STM32L052xx, STM32L053xx, STM32L062xx and STM32L063xx devices</li>
-<li>STM32L071xx, STM32L072xx, STM32L073xx, STM32L082xx and STM32L083xx devices</li>
-</ul>
-<p>This driver is composed of the descriptions of the registers under “Include” directory.</p>
-<p>Various template file are provided to easily build an application. They can be adapted to fit applications requirements.</p>
-<ul>
-<li>Templates/system_stm32l0xx.c contains the initialization code referred as SystemInit.</li>
-<li>Startup files are provided as example for IAR©, KEIL© and SW4STM32©.</li>
-<li>Linker files are provided as example for IAR©, KEIL© and SW4STM32©.</li>
-</ul>
-</div>
-<div class="col-sm-12 col-lg-8">
-<h1 id="update-history">Update History</h1>
-<div class="collapse">
-<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V1.9.2 / 16-July-2021</label>
-<div>
-<h2 id="main-changes">Main Changes</h2>
-<h3 id="maintenance-release">Maintenance release</h3>
-<h2 id="contents">Contents</h2>
-<ul>
-<li>Added new atomic register access macros in stm32l0xx.h file.</li>
-<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.9.1 / 28-October-2020</label>
-<div>
-<h2 id="main-changes-1">Main Changes</h2>
-<h3 id="maintenance-release-1">Maintenance release</h3>
-<h2 id="contents-1">Contents</h2>
-<ul>
-<li>system_stm32l0xx.c
-<ul>
-<li>SystemInit(): update to don’t reset RCC registers to its reset values.</li>
-<li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive: USER_VECT_TAB_ADDRESS.</li>
-</ul></li>
-<li>All header files
-<ul>
-<li>Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro.</li>
-</ul></li>
-<li>Remove stm32l061xx.h header file.</li>
-<li>Add License.md and Readme.md files required for GitHub publication</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.9.0 / 26-October-2018</label>
-<div>
-<h2 id="main-changes-2">Main Changes</h2>
-<h3 id="maintenance-release-2">Maintenance release</h3>
-<h3 id="first-release-supporting-l0-value-lines">First release supporting L0 Value Lines</h3>
-<h2 id="contents-2">Contents</h2>
-<ul>
-<li>Add the support of STM32L010xx devices
-<ul>
-<li>Add stm32l010xb.h, stm32l010x8.h, stm32l010x6.h and stm32l010x4.h device description files</li>
-<li>Add startup_stm32l010xb.s, startup_stm32l010x8.s, startup_stm32l010x6.s and startup_stm32l010x4.s startup files for EWARM, MDK-ARM and SW4STM32 toolchains</li>
-<li>Add EWARM associated linker files for execution from internal RAM or internal FLASH</li>
-</ul></li>
-<li>stm32l0xx.h
-<ul>
-<li>Add the following device defines:
-<ul>
-<li>“#define STM32L010xB” for all STM32L010xB devices</li>
-<li>“#define STM32L010x8” for all STM32L010x8 devices</li>
-<li>“#define STM32L010x6” for all STM32L010x6 devices</li>
-<li>“#define STM32L010x4” for all STM32L010x4 devices</li>
-</ul></li>
-<li>Align ErrorStatus typedef to common error handling.</li>
-</ul></li>
-<li>All stm32l0xxxx.h device description files.h
-<ul>
-<li>[MISRAC2012-Rule-10.6] Use ‘UL’ postfix for _Msk definitions and memory/peripheral base addresses</li>
-<li>Correct comments in the bit definition of RCC_AHBRST, RCC_APB2RSTR and RCC_APB1RSTR registers.</li>
-<li>Rename RTC_CR_BCK bit to RTC_CR_BKP to be aligned with reference manual.</li>
-<li>Add missing definition of IS_TSC_ALL_INSTANCE after TSC driver update.</li>
-<li>Add back the bit definition of SYSCFG_CFGR3_EN_VREFINT in SYSCFG_CFGR3 register.</li>
-<li>Rename GPIO_AFRL_AFRLx and GPIO_AFRL_AFRHx bit definitions (from GPIO_AFRL/AFRH registers) to GPIO_AFRL_AFSELx.</li>
-<li>Align IS_TIM_XXX_INSTANCE definitions with other series.</li>
-<li>Remove cast (uint8_t) in CRC_IDR_IDR definition.</li>
-<li>Add missing definition of IS_PCD_ALL_INSTANCE macro after USB driver update.</li>
-<li>Add definition of IS_UART_DRIVER_ENABLE_INSTANCE macro after UART driver update.</li>
-<li>Add compatibility definition of USART_ICR_NECF / USART_ICR_NCF with others series.</li>
-<li>Update IS_UART_INSTANCE macro definition.</li>
-<li>Add definition of IS_LPTIM_ENCODER_INTERFACE_INSTANCE macro after LPTIM driver update.</li>
-<li>Move definition of FLASH_BANK2_BASE start address to stm32l0xx_hal_flash.h to be dependant on Memory Size register.</li>
-<li>Update interrupt definition to use DMA1_Channel4_5_IRQn for STM32L011xx and STM32L021xx devices.</li>
-<li>Correct PWR_WAKEUP_PIN definitions for L011xx and L021xx devices.</li>
-</ul></li>
-<li>system_stm32l0xx.c
-<ul>
-<li>Update file to correct comments for VECT_TAB_OFFSET definition.</li>
-<li>Update default MSI_VALUE reset value set in SystemCoreClock.</li>
-<li>Update SystemCoreClockUpdate() function to check HSI16DIVF for HSI divided by 4.</li>
-</ul></li>
-<li>startup_stm32l0xxxx.s
-<ul>
-<li>Update startup files to use DMA1_Channel4_5_IRQn/IRQHandler for STM32L011xx and STM32L01xx devices.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.8.0 / 12-January-2018</label>
-<div>
-<h2 id="main-changes-3">Main Changes</h2>
-<h3 id="internal-release">Internal release</h3>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.7.2 / 25-August-2017</label>
-<div>
-<h2 id="main-changes-4">Main Changes</h2>
-<h3 id="maintenance-release-3">Maintenance release</h3>
-<h2 id="contents-3">Contents</h2>
-<ul>
-<li>Removed DATE and VERSION fields from header files.</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.7.1 / 25-November-2016</label>
-<div>
-<h2 id="main-changes-5">Main Changes</h2>
-<h3 id="maintenance-release-4">Maintenance release</h3>
-<h2 id="contents-4">Contents</h2>
-<ul>
-<li>Updated IS_COMP_COMMON_INSTANCE() macro.</li>
-<li>Corrected ADC_CFGR2_TOVS bit and mask definitions.</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.7.0 / 31-May-2016</label>
-<div>
-<h2 id="main-changes-6">Main Changes</h2>
-<h3 id="maintenance-release-5">Maintenance release</h3>
-<h2 id="contents-5">Contents</h2>
-<ul>
-<li>Added Pos and Msk macros missing within the CMSIS stm32l083xx.h file.</li>
-<li>Added LCD_CR_BUFEN bit definition in LCD CR register for stm32l053xx, stm32l063xx, stm32l073xx, stm32l083xx devices.</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.6.0 / 15-April-2016</label>
-<div>
-<h2 id="main-changes-7">Main Changes</h2>
-<h3 id="maintenance-release-6">Maintenance release</h3>
-<h2 id="contents-6">Contents</h2>
-<ul>
-<li><p>Add Pos and Msk macros within the CMSIS files.</p>
-<ul>
-<li>For example, on the previous CMSIS version (V1.5.0), the constant ADC_IER_EOCALIE was defined as follow :
-<ul>
-<li>#define ADC_IER_EOCALIE ((uint32_t)0x00000800U)</li>
-</ul></li>
-<li>On this new CMSIS version (V1.6.0), the constant ADC_IER_EOCALIE is now defined as follow :
-<ul>
-<li>#define ADC_IER_EOCALIE_Pos (11U)</li>
-<li>#define ADC_IER_EOCALIE_Msk (0x1U &lt;&lt; ADC_IER_EOCALIE_Pos)</li>
-<li>#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk</li>
-</ul></li>
-<li>The same rule applies on all the other constants present inside the CMSIS files.</li>
-</ul></li>
-<li><p>MISRA C 2004 rule 10.6 compliancy. (A ‘U’ suffix shall be applied to all constants of unisgned type).</p></li>
-<li><p>Several SYSCFG definition changes :</p></li>
-<li><p>SYSCFG_CFGR3_EN_VREFINT enable bit suppressed. (no more needed and must not be used).</p></li>
-<li><p>SYSCFG_CFGR3_EN_BGAP define suppressed.</p></li>
-<li><p>SYSCFG_CFGR3_REF_HSI48_RDYF, SYSCFG_CFGR3_SENSOR_ADC_RDYF, SYSCFG_CFGR3_VREFINT_ADC_RDYF, SYSCFG_CFGR3_VREFINT_COMP_RDYF flags suppressed, SYSCFG_CFGR3_VREFINT_RDYF must be used instead (this flag is a combination of the 4 suppressed flags).</p></li>
-<li><p>Added SYSCFG_CFGR3_REF_RC48MHz_RDYF, SYSCFG_CFGR3_REF_HSI48_RDYF, SYSCFG_VREFINT_ADC_RDYF, SYSCFG_CFGR3_SENSOR_ADC_RDYF, SYSCFG_CFGR3_VREFINT_ADC_RDYF and SYSCFG_CFGR3_VREFINT_COMP_RDYF defines.</p></li>
-<li><p>Aligned register namings with the different L0 Reference Manual (For STM32L0x1 : RM0377 Rev5, for STM32L0x2 : RM0367 Rev2, for STM32L0x3 : RM0367 Rev4). The list of the modification is listed hereafter :</p>
-<ul>
-<li>Introduced new masks in EXTI bit definitions in order to simplify LL source code.</li>
-<li>Renamed RCC_CFGR_MCO_x into RCC_CFGR_MCOSEL_x</li>
-<li>Added FLASHSIZE_BASE, UID_BASE and SRAM_SIZE_MAX defines.</li>
-<li>Renamed macro IS_DMA_ALL_INSTANCE() to IS_DMA_STREAM_ALL_INSTANCE().</li>
-<li>Added new macros: IS_I2C_WAKEUP_FROMSTOP_INSTANCE(), IS_ADC_COMMON_INSTANCE() and IS_LPUART_INSTANCE().</li>
-<li>Added new defines PWR_PVD_SUPPORT to handle the PVD feature.</li>
-<li>Corrected the value of FLASH_END for STM32L011xx or STM32L021xx devices.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.5.0 / 8-January-2016</label>
-<div>
-<h2 id="main-changes-8">Main Changes</h2>
-<h3 id="maintenance-release-7">Maintenance release</h3>
-<h2 id="contents-7">Contents</h2>
-<ul>
-<li>MISRA C 2004 rule 5.1 and rule 10.6 compliancy.</li>
-<li>Several renaming in order to be aligned with the Reference Manual.The list of the modification is listed hereafter :
-<ul>
-<li>Adding of a new COMP_Common_TypeDef structure.</li>
-<li>Removal of the RCR field inside the TIM_TypeDef structure.</li>
-<li>Adding of a new define COMP12_COMMON</li>
-<li>Adding of a new define DAC1 (same as DAC)</li>
-<li>Adding of a new define ADC1_COMMON</li>
-<li>Adding of a new define ADC_CHSELR_CHSEL</li>
-<li>Adding of a new define COMP_CSR_WINMODE</li>
-<li>Adding of a new define DAC_CHANNEL2_SUPPORT</li>
-<li>Renaming of EXTI_RTSR_TRx into EXTI_RTSR_RTx with x = {0,..22}</li>
-<li>Renaming of EXTI_FTSR_TRx into EXTI_FTSR_FTx with x = {0,..22}</li>
-<li>Renaming of EXTI_SWIER_SWIERx into EXTI_SWIER_SWIx with x = {0,..22}</li>
-<li>Renaming of EXTI_PR_PRx into EXTI_PR_PIFx with x = {0,..22}</li>
-<li>Renaming of RCC_IOPRSTR_GPIOxRST into RCC_IOPRSTR_IOPxRST with x = {A,B,C,D,E,H}</li>
-<li>Add a new define RCC_AHBRSTR_DMA1RST</li>
-<li>Add a new define RCC_APB2RSTR_ADC1RST</li>
-<li>Add a new define RCC_APB2RSTR_DBGMCURST</li>
-<li>Renaming of RCC_IOPENR_GPIOxEN into RCC_IOPENR_IOPxEN with x = {A,B,C,D,E,H}</li>
-<li>Add a new define RCC_AHBENR_DMA1EN</li>
-<li>Rename RCC_APB2ENR_MIFIEN into RCC_APB2ENR_FWEN</li>
-<li>Rename RCC_APB2ENR_ADC1EN into RCC_APB2ENR_ADCEN</li>
-<li>Rename RCC_APB2ENR_DBGMCUEN into RCC_APB2ENR_DBGEN</li>
-<li>Rename RCC_IOPSMENR_GPIOxSMEN into RCC_IOPSMENR_IOPxSMEN with x = {A,B,C,D,E,H}</li>
-<li>Add a new define RCC_AHBSMENR_DMA1SMEN</li>
-<li>Rename RCC_APB2SMENR_ADC1SMEN into RCC_APB2SMENR_ADCSMEN</li>
-<li>Rename RCC_APB2SMENR_DBGMCUSMEN into RCC_APB2SMENR_DBGSMEN</li>
-<li>Add new defines TIM_TIM2_REMAP_HSI_SUPPORT and TIM_TIM2_REMAP_HSI48_SUPPORT</li>
-<li>Remove the following defines : TIM_CR2_CCPC, TIM_CR2_CCUS, TIM_CR2_OIS1, TIM_CR2_OIS1N, TIM_CR2_OIS2,TIM_CR2_OIS2N, TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_CR2_OIS4</li>
-<li>Remove TIM_SR_COMIF and TIM_SR_BIF</li>
-<li>Remove TIM_EGR_COMG and TIM_EGR_BG</li>
-<li>Remove TIM_CCER_CC1NE, TIM_CCER_CC2NE and TIM_CCER_CC3NE</li>
-<li>Remove TIM_RCR_REP</li>
-<li>Rename USART_ISR_LBD into USART_ISR_LBDF</li>
-<li>Rename WWDG_CR_Tx into WWDG_CR_T_x with x = {0,..6}</li>
-<li>Rename WWDG_CFR_WDGTBx into WWDG_CFR_WDGTB_x with x = {0,1}</li>
-<li>Add several macros to check Timer instances (IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(), IS_TIM_CLOCK_DIVISION_INSTANCE(), …)</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.4.0 / 16-October-2015</label>
-<div>
-<h2 id="main-changes-9">Main Changes</h2>
-<h3 id="maintenance-release-8">Maintenance release</h3>
-<ul>
-<li>Update all the files to support STM32L011xx and STM32L021xx.</li>
-</ul>
-<h2 id="contents-8">Contents</h2>
-<ul>
-<li>Remove the Debug Monitor handler from the startup files (not supported on L0).</li>
-<li>Renamings and usage of some aliases in order to be compliant with the RefManuals.</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.3.0 / 9-Sept-2015</label>
-<div>
-<h2 id="main-changes-10">Main Changes</h2>
-<h3 id="maintenance-release-9">Maintenance release</h3>
-<ul>
-<li>Update all the files to support <strong>STM32L031xx</strong> and <strong>STM32L041xx</strong>.</li>
-</ul>
-<h2 id="contents-9">Contents</h2>
-<ul>
-<li>Several renamings in order to be compliant with the specifications.</li>
-<li>Adding of new bit definitions (COMP_CSR_COMP2LPTIM1IN1, SYSCFG_CFGR1_UFB, I2C_OAR2_x, LCD_CR_MUX_SEG, RTC_BKP_NUMBER)</li>
-<li>Update of several registers and structures (CRC_TypeDef, TIM_TypeDef)</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.2.0 / 6-February-2015</label>
-<div>
-<h2 id="main-changes-11">Main Changes</h2>
-<h3 id="maintenance-release-10">Maintenance release</h3>
-<ul>
-<li>Added the set of CMSIS files for the <strong>STM32L07xx</strong> and <strong>STM32L08xx</strong> family</li>
-</ul>
-<h2 id="contents-10">Contents</h2>
-<ul>
-<li>Add IAR set of files STM32L073xx - STM32L072xx - STM32L071xx - STM32L083xx - STM32L082xx - STM32L081xx</li>
-<li>Added MDK-ARM startup files for L071xx, L072xx, L073xx, L081xx, L082xx, L083xx</li>
-<li>Added Atollic startup files for L071xx, L072xx, L073xx, L081xx, L082xx, L083xx</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.1.0 / 18-June-2014</label>
-<div>
-<h2 id="main-changes-12">Main Changes</h2>
-<h3 id="maintenance-release-11">Maintenance release</h3>
-<h2 id="contents-11">Contents</h2>
-<ul>
-<li><strong>Header files</strong>
-<ul>
-<li>Add defines for memories base and end addresses:
-<ul>
-<li>FLASH_END, DATA_EEPROM_BASE and DATA_EEPROM_END (instead of having them in stm32l0xx_hal_flash.h file)</li>
-</ul></li>
-<li>Peripheral register structures definition is aligned on 32 bit</li>
-<li>FLASH_SR_FWWER value fixed to 0x00020000 instead of 0x00010000</li>
-<li>Add missing EXTI register bits definition
-<ul>
-<li>IMR and EMR registers: bits 18, 20, 26, 28, 29</li>
-<li>FTSR, RTSR, PR and SWIER registers: bits 20, 21, 22</li>
-</ul></li>
-<li>Update some bits definition to be in line with latest version of the Reference Manual
-<ul>
-<li>Rename FLASH_SR_ENHV into FLASH_SR_ENDHV</li>
-<li>Rename SYSCFG_VREFINT_ADC_RDYF into SYSCFG_CFGR3_VREFINT_ADC_RDYF</li>
-<li>Rename ADC_SMPR_SMPR_xxx into ADC_SMPR_SMP_xxx</li>
-<li>Rename SYSCFG_CFGR3_VREFINT_ADC_RDYF into SYSCFG_VREFINT_ADC_RDYF Note: aliases has been added to keep compatibility with previous version</li>
-</ul></li>
-</ul></li>
-<li><strong>system_stm32l0xx.c</strong>
-<ul>
-<li>Use "__IO const" instead of "__I", to avoid any compilation issue when __cplusplus switch is defined</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.0.1 / 24-April-2014</label>
-<div>
-<h2 id="main-changes-13">Main Changes</h2>
-<h3 id="first-official-release">First official release</h3>
-<h2 id="contents-12">Contents</h2>
-<ul>
-<li>Update gcc startup files</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 22-April-2014</label>
-<div>
-<h2 id="main-changes-14">Main Changes</h2>
-<h3 id="first-official-release-1">First official release</h3>
-</div>
-</div>
-</div>
-</div>
-<footer class="sticky">
-For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a>
-</footer>
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diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l010x4.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l010x4.s
deleted file mode 100644
index a6054232fa..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l010x4.s
+++ /dev/null
@@ -1,253 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l010x4.s
-;* Author             : MCD Application Team
-;* Description        : STM32l010x4 Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size      EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     0                              ; Reserved
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
-                DCD     ADC1_IRQHandler                ; ADC1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-   
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit
-
-        LDR     R0, =__initial_sp          ; set stack pointer
-        MSR     MSP, R0
-
-;;Check if boot space corresponds to system memory
-
-        LDR R0,=0x00000004
-        LDR R1, [R0]
-        LSRS R1, R1, #24
-        LDR R2,=0x1F
-        CMP R1, R2
-
-        BNE ApplicationStart
-
-;; SYSCFG clock enable
-
-        LDR R0,=0x40021034
-        LDR R1,=0x00000001
-        STR R1, [R0]
-
-;; Set CFGR1 register with flash memory remap at address 0
-
-        LDR R0,=0x40010000
-        LDR R1,=0x00000000
-        STR R1, [R0]
-
-ApplicationStart
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler                 [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
-                EXPORT  ADC1_IRQHandler                [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  LPUART1_IRQHandler             [WEAK]
-
-WWDG_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_IRQHandler
-ADC1_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM21_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART2_IRQHandler
-LPUART1_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l010x6.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l010x6.s
deleted file mode 100644
index 49bf18d528..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l010x6.s
+++ /dev/null
@@ -1,253 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l010x6.s
-;* Author             : MCD Application Team
-;* Description        : STM32l010x6 Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size      EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     0                              ; Reserved
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_IRQHandler                ; ADC1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-   
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit
-
-        LDR     R0, =__initial_sp          ; set stack pointer
-        MSR     MSP, R0
-
-;;Check if boot space corresponds to system memory
-
-        LDR R0,=0x00000004
-        LDR R1, [R0]
-        LSRS R1, R1, #24
-        LDR R2,=0x1F
-        CMP R1, R2
-
-        BNE ApplicationStart
-
-;; SYSCFG clock enable
-
-        LDR R0,=0x40021034
-        LDR R1,=0x00000001
-        STR R1, [R0]
-
-;; Set CFGR1 register with flash memory remap at address 0
-
-        LDR R0,=0x40010000
-        LDR R1,=0x00000000
-        STR R1, [R0]
-
-ApplicationStart
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler                 [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_IRQHandler                [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  LPUART1_IRQHandler             [WEAK]
-
-WWDG_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM21_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART2_IRQHandler
-LPUART1_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l010x8.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l010x8.s
deleted file mode 100644
index b0e21f6d3e..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l010x8.s
+++ /dev/null
@@ -1,253 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l010x8.s
-;* Author             : MCD Application Team
-;* Description        : STM32l010x8 Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size      EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     0                              ; Reserved
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_IRQHandler                ; ADC1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-   
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit
-
-        LDR     R0, =__initial_sp          ; set stack pointer
-        MSR     MSP, R0
-
-;;Check if boot space corresponds to system memory
-
-        LDR R0,=0x00000004
-        LDR R1, [R0]
-        LSRS R1, R1, #24
-        LDR R2,=0x1F
-        CMP R1, R2
-
-        BNE ApplicationStart
-
-;; SYSCFG clock enable
-
-        LDR R0,=0x40021034
-        LDR R1,=0x00000001
-        STR R1, [R0]
-
-;; Set CFGR1 register with flash memory remap at address 0
-
-        LDR R0,=0x40010000
-        LDR R1,=0x00000000
-        STR R1, [R0]
-
-ApplicationStart
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler                 [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_IRQHandler                [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  LPUART1_IRQHandler             [WEAK]
-
-WWDG_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM21_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART2_IRQHandler
-LPUART1_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l010xb.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l010xb.s
deleted file mode 100644
index c077b84501..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l010xb.s
+++ /dev/null
@@ -1,255 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l010xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32l010xB Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size      EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     0                              ; Reserved
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_IRQHandler                ; ADC1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-   
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit
-
-        LDR     R0, =__initial_sp          ; set stack pointer
-        MSR     MSP, R0
-
-;;Check if boot space corresponds to system memory
-
-        LDR R0,=0x00000004
-        LDR R1, [R0]
-        LSRS R1, R1, #24
-        LDR R2,=0x1F
-        CMP R1, R2
-
-        BNE ApplicationStart
-
-;; SYSCFG clock enable
-
-        LDR R0,=0x40021034
-        LDR R1,=0x00000001
-        STR R1, [R0]
-
-;; Set CFGR1 register with flash memory remap at address 0
-
-        LDR R0,=0x40010000
-        LDR R1,=0x00000000
-        STR R1, [R0]
-
-ApplicationStart
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler                 [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_IRQHandler                [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  LPUART1_IRQHandler             [WEAK]
-
-WWDG_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART2_IRQHandler
-LPUART1_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l011xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l011xx.s
deleted file mode 100644
index 3799a81f3a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l011xx.s
+++ /dev/null
@@ -1,255 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l011xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l011xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size      EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-   
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit
-
-        LDR     R0, =__initial_sp          ; set stack pointer
-        MSR     MSP, R0
-
-;;Check if boot space corresponds to system memory
-
-        LDR R0,=0x00000004
-        LDR R1, [R0]
-        LSRS R1, R1, #24
-        LDR R2,=0x1F
-        CMP R1, R2
-
-        BNE ApplicationStart
-
-;; SYSCFG clock enable
-
-        LDR R0,=0x40021034
-        LDR R1,=0x00000001
-        STR R1, [R0]
-
-;; Set CFGR1 register with flash memory remap at address 0
-
-        LDR R0,=0x40010000
-        LDR R1,=0x00000000
-        STR R1, [R0]
-
-ApplicationStart
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler                 [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  LPUART1_IRQHandler             [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM21_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART2_IRQHandler
-LPUART1_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l021xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l021xx.s
deleted file mode 100644
index f10d893315..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l021xx.s
+++ /dev/null
@@ -1,255 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l021xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l021xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_LPUART1_IRQHandler         ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-   
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit
-
-        LDR     R0, =__initial_sp          ; set stack pointer
-        MSR     MSP, R0
-
-;;Check if boot space corresponds to system memory
-
-        LDR R0,=0x00000004
-        LDR R1, [R0]
-        LSRS R1, R1, #24
-        LDR R2,=0x1F
-        CMP R1, R2
-
-        BNE ApplicationStart
-
-;; SYSCFG clock enable
-
-        LDR R0,=0x40021034
-        LDR R1,=0x00000001
-        STR R1, [R0]
-
-;; Set CFGR1 register with flash memory remap at address 0
-
-        LDR R0,=0x40010000
-        LDR R1,=0x00000000
-        STR R1, [R0]
-
-ApplicationStart
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler                 [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  AES_LPUART1_IRQHandler         [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM21_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART2_IRQHandler
-AES_LPUART1_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l031xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l031xx.s
deleted file mode 100644
index 04e85f5002..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l031xx.s
+++ /dev/null
@@ -1,230 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l031xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l031xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size      EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-   
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler                 [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  LPUART1_IRQHandler             [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART2_IRQHandler
-LPUART1_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l041xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l041xx.s
deleted file mode 100644
index aa049f57a9..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l041xx.s
+++ /dev/null
@@ -1,230 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l041xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l041xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_LPUART1_IRQHandler         ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-   
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler                 [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  AES_LPUART1_IRQHandler         [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART2_IRQHandler
-AES_LPUART1_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l051xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l051xx.s
deleted file mode 100644
index 93f7eac537..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l051xx.s
+++ /dev/null
@@ -1,240 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l051xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l051xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_IRQHandler                ; TIM6
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM6_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  LPUART1_IRQHandler             [WEAK]
-
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM6_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-LPUART1_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l052xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l052xx.s
deleted file mode 100644
index 283eb26218..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l052xx.s
+++ /dev/null
@@ -1,243 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l052xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l052xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     0                              ; Reserved
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM6_DAC_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-RNG_LPUART1_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l053xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l053xx.s
deleted file mode 100644
index 4feef74feb..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l053xx.s
+++ /dev/null
@@ -1,245 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l053xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l053xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler                 [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM6_DAC_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-RNG_LPUART1_IRQHandler
-LCD_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l062xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l062xx.s
deleted file mode 100644
index cc75c4ba0d..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l062xx.s
+++ /dev/null
@@ -1,243 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l062xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l062xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler                ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_RNG_LPUART1_IRQHandler     ; AES, RNG and LPUART1
-                DCD     0                              ; Reserved
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM21_IRQHandler                [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  AES_RNG_LPUART1_IRQHandler     [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM6_DAC_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-AES_RNG_LPUART1_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l063xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l063xx.s
deleted file mode 100644
index 883a417095..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l063xx.s
+++ /dev/null
@@ -1,245 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l063xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l063xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_RNG_LPUART1_IRQHandler     ; AES, RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                 [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  AES_RNG_LPUART1_IRQHandler     [WEAK]
-                EXPORT  LCD_IRQHandler                 [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM6_DAC_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-AES_RNG_LPUART1_IRQHandler
-LCD_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l071xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l071xx.s
deleted file mode 100644
index 4232fd08ca..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l071xx.s
+++ /dev/null
@@ -1,246 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l071xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l071xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_IRQHandler                ; TIM6
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-   
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler                 [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  USART4_5_IRQHandler            [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM3_IRQHandler                [WEAK]
-                EXPORT  TIM6_IRQHandler                [WEAK]
-                EXPORT  TIM7_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  I2C3_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  LPUART1_IRQHandler             [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-USART4_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-LPUART1_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l072xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l072xx.s
deleted file mode 100644
index 15d7761d93..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l072xx.s
+++ /dev/null
@@ -1,251 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l072xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l072xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C lbrary (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     0                              ; Reserved
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  USART4_5_IRQHandler            [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM3_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  I2C3_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-USART4_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-RNG_LPUART1_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l073xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l073xx.s
deleted file mode 100644
index bcffd11722..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l073xx.s
+++ /dev/null
@@ -1,253 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l073xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l073xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  USART4_5_IRQHandler            [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM3_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  I2C3_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler                 [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-USART4_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-RNG_LPUART1_IRQHandler
-LCD_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l081xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l081xx.s
deleted file mode 100644
index 1dd01b9045..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l081xx.s
+++ /dev/null
@@ -1,246 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l081xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l081xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_IRQHandler                ; TIM6
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_LPUART1_IRQHandler         ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-   
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler                 [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  USART4_5_IRQHandler            [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM3_IRQHandler                [WEAK]
-                EXPORT  TIM6_IRQHandler                [WEAK]
-                EXPORT  TIM7_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  I2C3_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  AES_LPUART1_IRQHandler         [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-USART4_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-AES_LPUART1_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l082xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l082xx.s
deleted file mode 100644
index 5f431b3436..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l082xx.s
+++ /dev/null
@@ -1,251 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l082xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l082xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_RNG_LPUART1_IRQHandler     ; RNG and LPUART1
-                DCD     0                              ; Reserved
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  USART4_5_IRQHandler            [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM3_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  I2C3_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  AES_RNG_LPUART1_IRQHandler     [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-USART4_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-AES_RNG_LPUART1_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l083xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l083xx.s
deleted file mode 100644
index 4ccbdbb16d..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l083xx.s
+++ /dev/null
@@ -1,253 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32l083xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32l083xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_RNG_LPUART1_IRQHandler     ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  USART4_5_IRQHandler            [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM3_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  I2C3_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  AES_RNG_LPUART1_IRQHandler     [WEAK]
-                EXPORT  LCD_IRQHandler                 [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-USART4_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-AES_RNG_LPUART1_IRQHandler
-LCD_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l010x4.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l010x4.s
deleted file mode 100644
index c48168e554..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l010x4.s
+++ /dev/null
@@ -1,275 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l010x4.s
-  * @author    MCD Application Team
-  * @brief     STM32L010x4 Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/*Check if boot space corresponds to system memory*/
-
-    LDR R0,=0x00000004
-    LDR R1, [R0]
-    LSRS R1, R1, #24
-    LDR R2,=0x1F
-    CMP R1, R2
-    BNE ApplicationStart
-
- /*SYSCFG clock enable*/
-    LDR R0,=0x40021034
-    LDR R1,=0x00000001
-    STR R1, [R0]
-
-/*Set CFGR1 register with flash memory remap at address 0*/
-    LDR R0,=0x40010000
-    LDR R1,=0x00000000
-    STR R1, [R0]
-
-ApplicationStart:
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     0                                 /* Reserved                     */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_IRQHandler                    /* RCC                          */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     0                                 /* Reserved                     */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_IRQHandler        /* DMA1 Channel 4 and Channel 5 */
-  .word     ADC1_IRQHandler                   /* ADC1                         */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     0                                 /* Reserved                     */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     LPUART1_IRQHandler                /* LPUART1                      */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_IRQHandler
-   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
-   .weak      ADC1_IRQHandler
-   .thumb_set ADC1_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      LPUART1_IRQHandler
-   .thumb_set LPUART1_IRQHandler,Default_Handler
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l010x6.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l010x6.s
deleted file mode 100644
index 73ad451876..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l010x6.s
+++ /dev/null
@@ -1,275 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l010x6.s
-  * @author    MCD Application Team
-  * @brief     STM32L010x6 Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/*Check if boot space corresponds to system memory*/
-
-    LDR R0,=0x00000004
-    LDR R1, [R0]
-    LSRS R1, R1, #24
-    LDR R2,=0x1F
-    CMP R1, R2
-    BNE ApplicationStart
-
- /*SYSCFG clock enable*/
-    LDR R0,=0x40021034
-    LDR R1,=0x00000001
-    STR R1, [R0]
-
-/*Set CFGR1 register with flash memory remap at address 0*/
-    LDR R0,=0x40010000
-    LDR R1,=0x00000000
-    STR R1, [R0]
-
-ApplicationStart:
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     0                                 /* Reserved                     */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_IRQHandler                    /* RCC                          */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     0                                 /* Reserved                     */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_IRQHandler                   /* ADC1                         */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     0                                 /* Reserved                     */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     LPUART1_IRQHandler                /* LPUART1                      */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_IRQHandler
-   .thumb_set ADC1_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      LPUART1_IRQHandler
-   .thumb_set LPUART1_IRQHandler,Default_Handler
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l010x8.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l010x8.s
deleted file mode 100644
index efe360bb3e..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l010x8.s
+++ /dev/null
@@ -1,275 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l010x8.s
-  * @author    MCD Application Team
-  * @brief     STM32L010x8 Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/*Check if boot space corresponds to system memory*/
-
-    LDR R0,=0x00000004
-    LDR R1, [R0]
-    LSRS R1, R1, #24
-    LDR R2,=0x1F
-    CMP R1, R2
-    BNE ApplicationStart
-
- /*SYSCFG clock enable*/
-    LDR R0,=0x40021034
-    LDR R1,=0x00000001
-    STR R1, [R0]
-
-/*Set CFGR1 register with flash memory remap at address 0*/
-    LDR R0,=0x40010000
-    LDR R1,=0x00000000
-    STR R1, [R0]
-
-ApplicationStart:
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     0                                 /* Reserved                     */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_IRQHandler                    /* RCC                          */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     0                                 /* Reserved                     */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_IRQHandler                   /* ADC1                         */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     0                                 /* Reserved                     */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     LPUART1_IRQHandler                /* LPUART1                      */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_IRQHandler
-   .thumb_set ADC1_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      LPUART1_IRQHandler
-   .thumb_set LPUART1_IRQHandler,Default_Handler
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l010xb.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l010xb.s
deleted file mode 100644
index e1bac89407..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l010xb.s
+++ /dev/null
@@ -1,278 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l010xb.s
-  * @author    MCD Application Team
-  * @brief     STM32L010xB Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/*Check if boot space corresponds to system memory*/
-
-    LDR R0,=0x00000004
-    LDR R1, [R0]
-    LSRS R1, R1, #24
-    LDR R2,=0x1F
-    CMP R1, R2
-    BNE ApplicationStart
-
- /*SYSCFG clock enable*/
-    LDR R0,=0x40021034
-    LDR R1,=0x00000001
-    STR R1, [R0]
-
-/*Set CFGR1 register with flash memory remap at address 0*/
-    LDR R0,=0x40010000
-    LDR R1,=0x00000000
-    STR R1, [R0]
-
-ApplicationStart:
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     0                                 /* Reserved                     */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_IRQHandler                    /* RCC                          */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     0                                 /* Reserved                     */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_IRQHandler                   /* ADC1                         */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     0                                 /* Reserved                     */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     LPUART1_IRQHandler                /* LPUART1                      */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_IRQHandler
-   .thumb_set ADC1_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      LPUART1_IRQHandler
-   .thumb_set LPUART1_IRQHandler,Default_Handler
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l011xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l011xx.s
deleted file mode 100644
index af0dd00d28..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l011xx.s
+++ /dev/null
@@ -1,278 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l011xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L011xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/*Check if boot space corresponds to system memory*/
-
-    LDR R0,=0x00000004
-    LDR R1, [R0]
-    LSRS R1, R1, #24
-    LDR R2,=0x1F
-    CMP R1, R2
-    BNE ApplicationStart
-
- /*SYSCFG clock enable*/
-    LDR R0,=0x40021034
-    LDR R1,=0x00000001
-    STR R1, [R0]
-
-/*Set CFGR1 register with flash memory remap at address 0*/
-    LDR R0,=0x40010000
-    LDR R1,=0x00000000
-    STR R1, [R0]
-
-ApplicationStart:
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_IRQHandler                    /* RCC                          */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     0                                 /* Reserved                     */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_IRQHandler        /* DMA1 Channel 4 and Channel 5 */
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     0                                 /* Reserved                     */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     LPUART1_IRQHandler                /* LPUART1                      */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_IRQHandler
-   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      LPUART1_IRQHandler
-   .thumb_set LPUART1_IRQHandler,Default_Handler
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l021xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l021xx.s
deleted file mode 100644
index 46eddad9d5..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l021xx.s
+++ /dev/null
@@ -1,278 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l021xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L021xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/*Check if boot space corresponds to system memory*/
-
-    LDR R0,=0x00000004
-    LDR R1, [R0]
-    LSRS R1, R1, #24
-    LDR R2,=0x1F
-    CMP R1, R2
-    BNE ApplicationStart
-
- /*SYSCFG clock enable*/
-    LDR R0,=0x40021034
-    LDR R1,=0x00000001
-    STR R1, [R0]
-
-/*Set CFGR1 register with flash memory remap at address 0*/
-    LDR R0,=0x40010000
-    LDR R1,=0x00000000
-    STR R1, [R0]
-
-ApplicationStart:
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_IRQHandler                    /* RCC                          */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     0                                 /* Reserved                     */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_IRQHandler        /* DMA1 Channel 4 and Channel 5 */
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     0                                 /* Reserved                     */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     AES_LPUART1_IRQHandler            /* AES and LPUART1              */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_IRQHandler
-   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      AES_LPUART1_IRQHandler
-   .thumb_set AES_LPUART1_IRQHandler,Default_Handler
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l031xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l031xx.s
deleted file mode 100644
index eb3af0d65e..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l031xx.s
+++ /dev/null
@@ -1,261 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l031xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L031xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_IRQHandler                    /* RCC                          */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     0                                 /* Reserved                     */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     0                                 /* Reserved                     */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     LPUART1_IRQHandler                /* LPUART1                      */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      LPUART1_IRQHandler
-   .thumb_set LPUART1_IRQHandler,Default_Handler
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l041xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l041xx.s
deleted file mode 100644
index 5b27b27177..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l041xx.s
+++ /dev/null
@@ -1,261 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l041xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L041xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_IRQHandler                    /* RCC                          */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     0                                 /* Reserved                     */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     0                                 /* Reserved                     */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     AES_LPUART1_IRQHandler            /* AES and LPUART1              */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      AES_LPUART1_IRQHandler
-   .thumb_set AES_LPUART1_IRQHandler,Default_Handler
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l051xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l051xx.s
deleted file mode 100644
index 95b7d36ec5..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l051xx.s
+++ /dev/null
@@ -1,272 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l051xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L051xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0         
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler                   /* Window WatchDog              */
-  .word  PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word  RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word  FLASH_IRQHandler                  /* FLASH                        */
-  .word  RCC_IRQHandler                    /* RCC                          */
-  .word  EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word  EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word  EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word  0                                 /* Reserved                     */
-  .word  DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word  DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word  DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word  ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word  LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word  0                                 /* Reserved                     */
-  .word  TIM2_IRQHandler                   /* TIM2                         */
-  .word  0                                 /* Reserved                     */
-  .word  TIM6_IRQHandler                   /* TIM6                         */
-  .word  0               				           /* Reserved                     */
-  .word  0              					          /* Reserved                     */
-  .word  TIM21_IRQHandler                  /* TIM21                        */
-  .word  0                                 /* Reserved                     */
-  .word  TIM22_IRQHandler                  /* TIM22                        */
-  .word  I2C1_IRQHandler                   /* I2C1                         */
-  .word  I2C2_IRQHandler                   /* I2C2                         */
-  .word  SPI1_IRQHandler                   /* SPI1                         */
-  .word  SPI2_IRQHandler                   /* SPI2                         */
-  .word  USART1_IRQHandler                 /* USART1                       */
-  .word  USART2_IRQHandler                 /* USART2                       */
-  .word  LPUART1_IRQHandler                /* LPUART1                      */
-  .word  0                                 /* Reserved                     */
-  .word  0                                 /* Reserved                     */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM6_IRQHandler
-   .thumb_set TIM6_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      LPUART1_IRQHandler
-   .thumb_set LPUART1_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l052xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l052xx.s
deleted file mode 100644
index c0e4b51e8c..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l052xx.s
+++ /dev/null
@@ -1,278 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l052xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L052xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler                   /* Window WatchDog              */
-  .word  PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word  RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word  FLASH_IRQHandler                  /* FLASH                        */
-  .word  RCC_CRS_IRQHandler                /* RCC and CRS                  */
-  .word  EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word  EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word  EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word  TSC_IRQHandler                     /* TSC                           */
-  .word  DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word  DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word  DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word  ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word  LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word  0                                 /* Reserved                     */
-  .word  TIM2_IRQHandler                   /* TIM2                         */
-  .word  0                                 /* Reserved                     */
-  .word  TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
-  .word  0               				          /* Reserved                     */
-  .word  0              					          /* Reserved                     */
-  .word  TIM21_IRQHandler                  /* TIM21                        */
-  .word  0                                 /* Reserved                     */
-  .word  TIM22_IRQHandler                  /* TIM22                        */
-  .word  I2C1_IRQHandler                   /* I2C1                         */
-  .word  I2C2_IRQHandler                   /* I2C2                         */
-  .word  SPI1_IRQHandler                   /* SPI1                         */
-  .word  SPI2_IRQHandler                   /* SPI2                         */
-  .word  USART1_IRQHandler                 /* USART1                       */
-  .word  USART2_IRQHandler                 /* USART2                       */
-  .word  RNG_LPUART1_IRQHandler            /* RNG and LPUART1              */
-  .word  0                                 /* Reserved                     */
-  .word  USB_IRQHandler                    /* USB                          */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_CRS_IRQHandler
-   .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      TSC_IRQHandler
-   .thumb_set TSC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      RNG_LPUART1_IRQHandler
-   .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
-
-   .weak      USB_IRQHandler
-   .thumb_set USB_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l053xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l053xx.s
deleted file mode 100644
index 0138341b25..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l053xx.s
+++ /dev/null
@@ -1,281 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l053xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L053xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_CRS_IRQHandler                /* RCC and CRS                  */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     TSC_IRQHandler                     /* TSC                           */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
-  .word     0               				          /* Reserved                     */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     RNG_LPUART1_IRQHandler            /* RNG and LPUART1              */
-  .word     LCD_IRQHandler                    /* LCD                          */
-  .word     USB_IRQHandler                    /* USB                          */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_CRS_IRQHandler
-   .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      TSC_IRQHandler
-   .thumb_set TSC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      RNG_LPUART1_IRQHandler
-   .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
-
-   .weak      LCD_IRQHandler
-   .thumb_set LCD_IRQHandler,Default_Handler
-
-   .weak      USB_IRQHandler
-   .thumb_set USB_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l062xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l062xx.s
deleted file mode 100644
index 3f27a9e122..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l062xx.s
+++ /dev/null
@@ -1,278 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l062xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L062xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_CRS_IRQHandler                /* RCC and CRS                  */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     TSC_IRQHandler                     /* TSC                           */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
-  .word     0               				          /* Reserved                     */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     AES_RNG_LPUART1_IRQHandler        /* AES, RNG and LPUART1         */
-  .word     0                                 /* Reserved                     */
-  .word     USB_IRQHandler                    /* USB                          */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_CRS_IRQHandler
-   .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      TSC_IRQHandler
-   .thumb_set TSC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      AES_RNG_LPUART1_IRQHandler
-   .thumb_set AES_RNG_LPUART1_IRQHandler,Default_Handler
-
-   .weak      USB_IRQHandler
-   .thumb_set USB_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l063xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l063xx.s
deleted file mode 100644
index 10a08c8dda..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l063xx.s
+++ /dev/null
@@ -1,281 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l063xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L063xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_CRS_IRQHandler                /* RCC and CRS                  */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     TSC_IRQHandler                     /* TSC                           */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
-  .word     0               				          /* Reserved                     */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     AES_RNG_LPUART1_IRQHandler        /* AES, RNG and LPUART1         */
-  .word     LCD_IRQHandler                    /* LCD                          */
-  .word     USB_IRQHandler                    /* USB                          */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_CRS_IRQHandler
-   .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      TSC_IRQHandler
-   .thumb_set TSC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      AES_RNG_LPUART1_IRQHandler
-   .thumb_set AES_RNG_LPUART1_IRQHandler,Default_Handler
-
-   .weak      LCD_IRQHandler
-   .thumb_set LCD_IRQHandler,Default_Handler
-
-   .weak      USB_IRQHandler
-   .thumb_set USB_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l071xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l071xx.s
deleted file mode 100644
index c575b75396..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l071xx.s
+++ /dev/null
@@ -1,284 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l071xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L071xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_IRQHandler                    /* RCC                          */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     0                                 /* Reserved                     */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     USART4_5_IRQHandler               /* USART4 and USART 5           */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     TIM3_IRQHandler                   /* TIM3                         */
-  .word     TIM6_IRQHandler                   /* TIM6 and DAC                 */
-  .word     TIM7_IRQHandler 				          /* TIM7                         */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     I2C3_IRQHandler                   /* I2C3                         */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     LPUART1_IRQHandler                /* LPUART1                      */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      USART4_5_IRQHandler
-   .thumb_set USART4_5_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM3_IRQHandler
-   .thumb_set TIM3_IRQHandler,Default_Handler
-
-   .weak      TIM6_IRQHandler
-   .thumb_set TIM6_IRQHandler,Default_Handler
-
-   .weak      TIM7_IRQHandler
-   .thumb_set TIM7_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C3_IRQHandler
-   .thumb_set I2C3_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      LPUART1_IRQHandler
-   .thumb_set LPUART1_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l072xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l072xx.s
deleted file mode 100644
index e284dd1708..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l072xx.s
+++ /dev/null
@@ -1,290 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l072xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L072xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_CRS_IRQHandler                /* RCC and CRS                  */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     TSC_IRQHandler                     /* TSC                           */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     USART4_5_IRQHandler               /* USART4 and USART 5           */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     TIM3_IRQHandler                   /* TIM3                         */
-  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
-  .word     TIM7_IRQHandler 				          /* TIM7                         */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     I2C3_IRQHandler                   /* I2C3                         */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     RNG_LPUART1_IRQHandler            /* RNG and LPUART1              */
-  .word     0                                 /* Reserved                     */
-  .word     USB_IRQHandler                    /* USB                          */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_CRS_IRQHandler
-   .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      TSC_IRQHandler
-   .thumb_set TSC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      USART4_5_IRQHandler
-   .thumb_set USART4_5_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM3_IRQHandler
-   .thumb_set TIM3_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM7_IRQHandler
-   .thumb_set TIM7_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C3_IRQHandler
-   .thumb_set I2C3_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      RNG_LPUART1_IRQHandler
-   .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
-
-   .weak      USB_IRQHandler
-   .thumb_set USB_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l073xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l073xx.s
deleted file mode 100644
index 3b581776bd..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l073xx.s
+++ /dev/null
@@ -1,293 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l073xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L073xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_CRS_IRQHandler                /* RCC and CRS                  */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     TSC_IRQHandler                     /* TSC                           */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     USART4_5_IRQHandler               /* USART4 and USART 5           */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     TIM3_IRQHandler                   /* TIM3                         */
-  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
-  .word     TIM7_IRQHandler 				          /* TIM7                         */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     I2C3_IRQHandler                   /* I2C3                         */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     RNG_LPUART1_IRQHandler            /* RNG and LPUART1              */
-  .word     LCD_IRQHandler                    /* LCD                          */
-  .word     USB_IRQHandler                    /* USB                          */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_CRS_IRQHandler
-   .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      TSC_IRQHandler
-   .thumb_set TSC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      USART4_5_IRQHandler
-   .thumb_set USART4_5_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM3_IRQHandler
-   .thumb_set TIM3_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM7_IRQHandler
-   .thumb_set TIM7_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C3_IRQHandler
-   .thumb_set I2C3_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      RNG_LPUART1_IRQHandler
-   .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
-
-   .weak      LCD_IRQHandler
-   .thumb_set LCD_IRQHandler,Default_Handler
-
-   .weak      USB_IRQHandler
-   .thumb_set USB_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l081xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l081xx.s
deleted file mode 100644
index 6ab67a73b7..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l081xx.s
+++ /dev/null
@@ -1,285 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l081xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L081xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_IRQHandler                    /* RCC                          */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     0                                 /* Reserved                     */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     USART4_5_IRQHandler               /* USART4 and USART 5           */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     TIM3_IRQHandler                   /* TIM3                         */
-  .word     TIM6_IRQHandler                   /* TIM6                         */
-  .word     TIM7_IRQHandler 				          /* TIM7                         */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     I2C3_IRQHandler                   /* I2C3                         */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     AES_LPUART1_IRQHandler            /* AES and LPUART1              */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      USART4_5_IRQHandler
-   .thumb_set USART4_5_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM3_IRQHandler
-   .thumb_set TIM3_IRQHandler,Default_Handler
-
-   .weak      TIM6_IRQHandler
-   .thumb_set TIM6_IRQHandler,Default_Handler
-
-   .weak      TIM7_IRQHandler
-   .thumb_set TIM7_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C3_IRQHandler
-   .thumb_set I2C3_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      AES_LPUART1_IRQHandler
-   .thumb_set AES_LPUART1_IRQHandler,Default_Handler
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l082xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l082xx.s
deleted file mode 100644
index 2f9664cb76..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l082xx.s
+++ /dev/null
@@ -1,290 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l082xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L082xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_CRS_IRQHandler                /* RCC and CRS                  */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     TSC_IRQHandler                     /* TSC                           */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     USART4_5_IRQHandler               /* USART4 and USART 5           */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     TIM3_IRQHandler                   /* TIM3                         */
-  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
-  .word     TIM7_IRQHandler 				          /* TIM7                         */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     I2C3_IRQHandler                   /* I2C3                         */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     AES_RNG_LPUART1_IRQHandler        /* AES, RNG and LPUART1         */
-  .word     0                                 /* Reserved                     */
-  .word     USB_IRQHandler                    /* USB                          */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_CRS_IRQHandler
-   .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      TSC_IRQHandler
-   .thumb_set TSC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      USART4_5_IRQHandler
-   .thumb_set USART4_5_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM3_IRQHandler
-   .thumb_set TIM3_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM7_IRQHandler
-   .thumb_set TIM7_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C3_IRQHandler
-   .thumb_set I2C3_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      AES_RNG_LPUART1_IRQHandler
-   .thumb_set AES_RNG_LPUART1_IRQHandler,Default_Handler
-
-   .weak      USB_IRQHandler
-   .thumb_set USB_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l083xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l083xx.s
deleted file mode 100644
index a515f686a5..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l083xx.s
+++ /dev/null
@@ -1,293 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l083xx.s
-  * @author    MCD Application Team
-  * @brief     STM32L083xx Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_CRS_IRQHandler                /* RCC and CRS                  */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     TSC_IRQHandler                     /* TSC                           */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     USART4_5_IRQHandler               /* USART4 and USART 5           */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     TIM3_IRQHandler                   /* TIM3                         */
-  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
-  .word     TIM7_IRQHandler 				          /* TIM7                         */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     I2C3_IRQHandler                   /* I2C3                         */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     AES_RNG_LPUART1_IRQHandler        /* AES, RNG and LPUART1         */
-  .word     LCD_IRQHandler                    /* LCD                          */
-  .word     USB_IRQHandler                    /* USB                          */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_CRS_IRQHandler
-   .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      TSC_IRQHandler
-   .thumb_set TSC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      USART4_5_IRQHandler
-   .thumb_set USART4_5_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM3_IRQHandler
-   .thumb_set TIM3_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM7_IRQHandler
-   .thumb_set TIM7_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C3_IRQHandler
-   .thumb_set I2C3_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      AES_RNG_LPUART1_IRQHandler
-   .thumb_set AES_RNG_LPUART1_IRQHandler,Default_Handler
-
-   .weak      LCD_IRQHandler
-   .thumb_set LCD_IRQHandler,Default_Handler
-
-   .weak      USB_IRQHandler
-   .thumb_set USB_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x4_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x4_flash.icf
deleted file mode 100644
index df2b701643..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x4_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x08003FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x200007FF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x6_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x6_flash.icf
deleted file mode 100644
index 50f3429d49..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x6_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x08007FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x8_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x8_flash.icf
deleted file mode 100644
index 5103af67a2..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x8_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010xb_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010xb_flash.icf
deleted file mode 100644
index b736298384..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010xb_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_flash.icf
deleted file mode 100644
index 2c509140db..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x08003FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x200007FF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_sram.icf
deleted file mode 100644
index 21e87f4cbc..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200004FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000500;
-define symbol __ICFEDIT_region_RAM_end__   = 0x200007FF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_flash.icf
deleted file mode 100644
index 2c509140db..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x08003FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x200007FF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_sram.icf
deleted file mode 100644
index 21e87f4cbc..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200004FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000500;
-define symbol __ICFEDIT_region_RAM_end__   = 0x200007FF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_flash.icf
deleted file mode 100644
index b23b63e7cd..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x08007FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_sram.icf
deleted file mode 100644
index bdcd3702bb..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200009FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000A00;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_flash.icf
deleted file mode 100644
index b23b63e7cd..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x08007FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_sram.icf
deleted file mode 100644
index bdcd3702bb..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200009FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000A00;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_flash.icf
deleted file mode 100644
index 667bb40456..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_sram.icf
deleted file mode 100644
index 42ede5c303..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_flash.icf
deleted file mode 100644
index 667bb40456..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_sram.icf
deleted file mode 100644
index 42ede5c303..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_flash.icf
deleted file mode 100644
index 667bb40456..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_sram.icf
deleted file mode 100644
index 42ede5c303..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_flash.icf
deleted file mode 100644
index 667bb40456..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_sram.icf
deleted file mode 100644
index 42ede5c303..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_flash.icf
deleted file mode 100644
index 667bb40456..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_sram.icf
deleted file mode 100644
index 42ede5c303..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_flash.icf
deleted file mode 100644
index 667bb40456..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_sram.icf
deleted file mode 100644
index 42ede5c303..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_flash.icf
deleted file mode 100644
index 7b89f73b85..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0802FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_sram.icf
deleted file mode 100644
index 48b9fe84ce..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x20002FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20003000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_flash.icf
deleted file mode 100644
index 7b89f73b85..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0802FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_sram.icf
deleted file mode 100644
index 48b9fe84ce..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x20002FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20003000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_flash.icf
deleted file mode 100644
index 7b89f73b85..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0802FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_sram.icf
deleted file mode 100644
index 48b9fe84ce..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x20002FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20003000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_flash.icf
deleted file mode 100644
index 7b89f73b85..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0802FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_sram.icf
deleted file mode 100644
index 48b9fe84ce..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x20002FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20003000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_flash.icf
deleted file mode 100644
index 7b89f73b85..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0802FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_sram.icf
deleted file mode 100644
index 48b9fe84ce..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x20002FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20003000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_flash.icf
deleted file mode 100644
index 7b89f73b85..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_flash.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0802FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_sram.icf
deleted file mode 100644
index 48b9fe84ce..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x20002FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20003000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20004FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l010x4.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l010x4.s
deleted file mode 100644
index 279a453729..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l010x4.s
+++ /dev/null
@@ -1,279 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l010x4.s
-;* Author             : MCD Application Team
-;* Description        : STM32L010x4 Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     0                              ; Reserved
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
-                DCD     ADC1_IRQHandler                ; ADC1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved    
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =sfe(CSTACK)          ; set stack pointer
-        MSR     MSP, R0 
-;;Check if boot space corresponds to system memory 
-        LDR R0,=0x00000004
-        LDR R1, [R0]
-        LSRS R1, R1, #24
-        LDR R2,=0x1F
-        CMP R1, R2
-        BNE ApplicationStart       
-;; SYSCFG clock enable         
-        LDR R0,=0x40021034 
-        LDR R1,=0x00000001
-        STR R1, [R0]
-;; Set CFGR1 register with flash memory remap at address 0
-        LDR R0,=0x40010000 
-        LDR R1,=0x00000000
-        STR R1, [R0]
-
-ApplicationStart
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-            
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_IRQHandler
-        B DMA1_Channel4_5_IRQHandler
-        
-                
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-                
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l010x6.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l010x6.s
deleted file mode 100644
index 1cc87d59ce..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l010x6.s
+++ /dev/null
@@ -1,279 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l010x6.s
-;* Author             : MCD Application Team
-;* Description        : STM32L010x6 Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     0                              ; Reserved
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_IRQHandler                ; ADC1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved    
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =sfe(CSTACK)          ; set stack pointer
-        MSR     MSP, R0 
-;;Check if boot space corresponds to system memory 
-        LDR R0,=0x00000004
-        LDR R1, [R0]
-        LSRS R1, R1, #24
-        LDR R2,=0x1F
-        CMP R1, R2
-        BNE ApplicationStart       
-;; SYSCFG clock enable         
-        LDR R0,=0x40021034 
-        LDR R1,=0x00000001
-        STR R1, [R0]
-;; Set CFGR1 register with flash memory remap at address 0
-        LDR R0,=0x40010000 
-        LDR R1,=0x00000000
-        STR R1, [R0]
-
-ApplicationStart
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-            
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-                
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l010x8.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l010x8.s
deleted file mode 100644
index a60c72549e..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l010x8.s
+++ /dev/null
@@ -1,279 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l010x8.s
-;* Author             : MCD Application Team
-;* Description        : STM32L010x8 Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     0                              ; Reserved
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_IRQHandler                ; ADC1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved    
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =sfe(CSTACK)          ; set stack pointer
-        MSR     MSP, R0 
-;;Check if boot space corresponds to system memory 
-        LDR R0,=0x00000004
-        LDR R1, [R0]
-        LSRS R1, R1, #24
-        LDR R2,=0x1F
-        CMP R1, R2
-        BNE ApplicationStart       
-;; SYSCFG clock enable         
-        LDR R0,=0x40021034 
-        LDR R1,=0x00000001
-        STR R1, [R0]
-;; Set CFGR1 register with flash memory remap at address 0
-        LDR R0,=0x40010000 
-        LDR R1,=0x00000000
-        STR R1, [R0]
-
-ApplicationStart
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-            
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-                
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l010xb.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l010xb.s
deleted file mode 100644
index aa3f09a354..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l010xb.s
+++ /dev/null
@@ -1,279 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l010xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32L010xB Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     0                              ; Reserved
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_IRQHandler                ; ADC1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved    
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =sfe(CSTACK)          ; set stack pointer
-        MSR     MSP, R0 
-;;Check if boot space corresponds to system memory 
-        LDR R0,=0x00000004
-        LDR R1, [R0]
-        LSRS R1, R1, #24
-        LDR R2,=0x1F
-        CMP R1, R2
-        BNE ApplicationStart       
-;; SYSCFG clock enable         
-        LDR R0,=0x40021034 
-        LDR R1,=0x00000001
-        STR R1, [R0]
-;; Set CFGR1 register with flash memory remap at address 0
-        LDR R0,=0x40010000 
-        LDR R1,=0x00000000
-        STR R1, [R0]
-
-ApplicationStart
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-            
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-                
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l011xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l011xx.s
deleted file mode 100644
index cc3d0064a7..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l011xx.s
+++ /dev/null
@@ -1,285 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l011xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L011xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved    
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =sfe(CSTACK)          ; set stack pointer
-        MSR     MSP, R0 
-;;Check if boot space corresponds to system memory 
-        LDR R0,=0x00000004
-        LDR R1, [R0]
-        LSRS R1, R1, #24
-        LDR R2,=0x1F
-        CMP R1, R2
-        BNE ApplicationStart       
-;; SYSCFG clock enable         
-        LDR R0,=0x40021034 
-        LDR R1,=0x00000001
-        STR R1, [R0]
-;; Set CFGR1 register with flash memory remap at address 0
-        LDR R0,=0x40010000 
-        LDR R1,=0x00000000
-        STR R1, [R0]
-
-ApplicationStart
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-            
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_IRQHandler
-        B DMA1_Channel4_5_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-                
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l021xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l021xx.s
deleted file mode 100644
index caf84d5e65..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l021xx.s
+++ /dev/null
@@ -1,284 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l021xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L021xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved     
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_LPUART1_IRQHandler         ; AES and LPUART1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =sfe(CSTACK)          ; set stack pointer
-        MSR     MSP, R0 
-;;Check if boot space corresponds to system memory 
-        LDR R0,=0x00000004
-        LDR R1, [R0]
-        LSRS R1, R1, #24
-        LDR R2,=0x1F
-        CMP R1, R2
-        BNE ApplicationStart       
-;; SYSCFG clock enable         
-        LDR R0,=0x40021034 
-        LDR R1,=0x00000001
-        STR R1, [R0]
-;; Set CFGR1 register with flash memory remap at address 0
-        LDR R0,=0x40010000 
-        LDR R1,=0x00000000
-        STR R1, [R0]
-
-ApplicationStart
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-            
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_IRQHandler
-        B DMA1_Channel4_5_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-                
-        PUBWEAK AES_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_LPUART1_IRQHandler
-        B AES_LPUART1_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l031xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l031xx.s
deleted file mode 100644
index 69e3721fce..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l031xx.s
+++ /dev/null
@@ -1,271 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l031xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L031xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved    
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-            
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-                
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l041xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l041xx.s
deleted file mode 100644
index 0e352717c7..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l041xx.s
+++ /dev/null
@@ -1,272 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l041xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L041xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved     
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_LPUART1_IRQHandler         ; AES and LPUART1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-            
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-                
-        PUBWEAK AES_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_LPUART1_IRQHandler
-        B AES_LPUART1_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l051xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l051xx.s
deleted file mode 100644
index 551dd45d0a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l051xx.s
+++ /dev/null
@@ -1,294 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l051xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L051xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_IRQHandler                ; TIM6
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-            
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l052xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l052xx.s
deleted file mode 100644
index 6622f029e8..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l052xx.s
+++ /dev/null
@@ -1,306 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l052xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L052xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     0                              ; Reserved    
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_LPUART1_IRQHandler
-        B RNG_LPUART1_IRQHandler
-        
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l053xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l053xx.s
deleted file mode 100644
index e353615121..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l053xx.s
+++ /dev/null
@@ -1,311 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l053xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L053xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler                ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_LPUART1_IRQHandler
-        B RNG_LPUART1_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l062xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l062xx.s
deleted file mode 100644
index fa71383d91..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l062xx.s
+++ /dev/null
@@ -1,306 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l062xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L062xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                  ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler                ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_RNG_LPUART1_IRQHandler     ; AES, RNG and LPUART1
-                DCD     0                              ; Reserved    
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK AES_RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_RNG_LPUART1_IRQHandler
-        B AES_RNG_LPUART1_IRQHandler
-        
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l063xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l063xx.s
deleted file mode 100644
index 66cfe20247..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l063xx.s
+++ /dev/null
@@ -1,311 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l063xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L063xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                  ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler                ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_RNG_LPUART1_IRQHandler     ; AES, RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK AES_RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_RNG_LPUART1_IRQHandler
-        B AES_RNG_LPUART1_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l071xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l071xx.s
deleted file mode 100644
index 1372dd19b1..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l071xx.s
+++ /dev/null
@@ -1,316 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l071xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L071xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_IRQHandler                ; TIM6
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                 
-        PUBWEAK USART4_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART4_5_IRQHandler
-        B USART4_5_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-                
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-                
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK I2C3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_IRQHandler
-        B I2C3_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l072xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l072xx.s
deleted file mode 100644
index a6804a175c..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l072xx.s
+++ /dev/null
@@ -1,328 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l072xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L072xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     0                              ; Reserved
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                 
-        PUBWEAK USART4_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART4_5_IRQHandler
-        B USART4_5_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-                
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK I2C3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_IRQHandler
-        B I2C3_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_LPUART1_IRQHandler
-        B RNG_LPUART1_IRQHandler
-        
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l073xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l073xx.s
deleted file mode 100644
index fc3b8d2501..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l073xx.s
+++ /dev/null
@@ -1,333 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l073xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L073xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                 
-        PUBWEAK USART4_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART4_5_IRQHandler
-        B USART4_5_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-                
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK I2C3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_IRQHandler
-        B I2C3_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_LPUART1_IRQHandler
-        B RNG_LPUART1_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l081xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l081xx.s
deleted file mode 100644
index e906833e5a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l081xx.s
+++ /dev/null
@@ -1,316 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l081xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L081xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_IRQHandler                ; TIM6
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_LPUART1_IRQHandler         ; AES and LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                 
-        PUBWEAK USART4_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART4_5_IRQHandler
-        B USART4_5_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-                
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-                
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK I2C3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_IRQHandler
-        B I2C3_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK AES_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_LPUART1_IRQHandler
-        B AES_LPUART1_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l082xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l082xx.s
deleted file mode 100644
index 92ce027c9a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l082xx.s
+++ /dev/null
@@ -1,328 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l082xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L082xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_RNG_LPUART1_IRQHandler     ; AES, RNG and LPUART1
-                DCD     0                              ; Reserved
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                 
-        PUBWEAK USART4_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART4_5_IRQHandler
-        B USART4_5_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-                
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK I2C3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_IRQHandler
-        B I2C3_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK AES_RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_RNG_LPUART1_IRQHandler
-        B AES_RNG_LPUART1_IRQHandler
-        
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l083xx.s b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l083xx.s
deleted file mode 100644
index c99f5c1642..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l083xx.s
+++ /dev/null
@@ -1,333 +0,0 @@
-;*******************************************************************************
-;* File Name          : startup_stm32l083xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L083xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     AES_RNG_LPUART1_IRQHandler     ; AES, RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                 
-        PUBWEAK USART4_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART4_5_IRQHandler
-        B USART4_5_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-                
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK I2C3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_IRQHandler
-        B I2C3_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK AES_RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_RNG_LPUART1_IRQHandler
-        B AES_RNG_LPUART1_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c
deleted file mode 100644
index 00a513c9db..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.c
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l0xx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Defines
-  * @{
-  */
-/************************* Miscellaneous Configuration ************************/
-
-/* Note: Following vector table addresses must be defined in line with linker
-         configuration. */
-/*!< Uncomment the following line if you need to relocate the vector table
-     anywhere in Flash or Sram, else the vector table is kept at the automatic
-     remap of boot address selected */
-/* #define USER_VECT_TAB_ADDRESS */
-
-#if defined(USER_VECT_TAB_ADDRESS)
-/*!< Uncomment the following line if you need to relocate your vector Table
-     in Sram else user remap will be done in Flash. */
-/* #define VECT_TAB_SRAM */
-#if defined(VECT_TAB_SRAM)
-#define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
-                                                     This value must be a multiple of 0x200. */
-#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
-                                                     This value must be a multiple of 0x200. */
-#else
-#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
-                                                     This value must be a multiple of 0x200. */
-#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
-                                                     This value must be a multiple of 0x200. */
-#endif /* VECT_TAB_SRAM */
-#endif /* USER_VECT_TAB_ADDRESS */
-
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-  uint32_t SystemCoreClock = 2097152U; /* 32.768 kHz * 2^6 */
-  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
-  const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
-  const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Configure the Vector Table location add offset address ------------------*/
-#if defined (USER_VECT_TAB_ADDRESS)
-  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#endif /* USER_VECT_TAB_ADDRESS */
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
-  *             value as defined by the MSI range.
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00U:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> RCC_ICSCR_MSIRANGE_Pos;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-    case 0x04U:  /* HSI used as system clock */
-      if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
-      {
-        SystemCoreClock = HSI_VALUE / 4U;
-      }
-      else
-      {
-        SystemCoreClock = HSI_VALUE;
-      }
-      break;
-    case 0x08U:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    default:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)];
-      plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U;
-
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
-        {
-          SystemCoreClock = (((HSI_VALUE / 4U) * pllmul) / plldiv);
-        }
-        else
-        {
-          SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-        }
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/SConscript b/bsp/stm32/libraries/STM32L0xx_HAL/SConscript
deleted file mode 100644
index 1d18ead49e..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/SConscript
+++ /dev/null
@@ -1,92 +0,0 @@
-import rtconfig
-from building import *
-
-# get current directory
-cwd = GetCurrentDir()
-
-# The set of source files associated with this SConscript file.
-
-src = Split('''
-CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp_ex.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c
-STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c
-''')
-
-if GetDepend(['RT_USING_SERIAL']) or GetDepend(['RT_USING_NANO', 'RT_USING_CONSOLE']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c']
-
-if GetDepend(['RT_USING_I2C']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c']
-
-if GetDepend(['RT_USING_SPI']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi_ex.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_qspi.c']
-
-if GetDepend(['RT_USING_USB']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_hcd.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usb.c']
-
-if GetDepend(['RT_USING_CAN']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_can.c']
-
-if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c']
-
-if GetDepend(['RT_USING_ADC']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c']
-
-if GetDepend(['RT_USING_RTC']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c']
-
-if GetDepend(['RT_USING_WDT']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_wwdg.c']
-
-if GetDepend(['RT_USING_SDIO']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_sd.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_sd_ex.c']
-
-if GetDepend(['RT_USING_AUDIO']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_sai.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_sai_ex.c']
-
-if GetDepend(['RT_USING_MTD_NOR']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_nor.c']
-
-if GetDepend(['RT_USING_MTD_NAND']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_nand.c']
-
-if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c']
-    src += ['STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c']
-
-path = [cwd + '/STM32L0xx_HAL_Driver/Inc',
-    cwd + '/CMSIS/Device/ST/STM32L0xx/Include']
-
-CPPDEFINES = ['USE_HAL_DRIVER']
-group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
-
-Return('group')
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
deleted file mode 100644
index ae83378c19..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ /dev/null
@@ -1,3840 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_hal_legacy.h
-  * @author  MCD Application Team
-  * @brief   This file contains aliases definition for the STM32Cube HAL constants
-  *          macros and functions maintained for legacy purpose.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32_HAL_LEGACY
-#define STM32_HAL_LEGACY
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5)
-#define CRYP_DATATYPE_32B               CRYP_NO_SWAP
-#define CRYP_DATATYPE_16B               CRYP_HALFWORD_SWAP
-#define CRYP_DATATYPE_8B                CRYP_BYTE_SWAP
-#define CRYP_DATATYPE_1B                CRYP_BIT_SWAP
-#define CRYP_CCF_CLEAR                  CRYP_CLEAR_CCF
-#define CRYP_ERR_CLEAR                  CRYP_CLEAR_RWEIF
-#endif /* STM32U5 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP                   ADC_REGULAR_GROUP
-#define INJECTED_GROUP                  ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT                       ADC_AWD_EVENT
-#define AWD1_EVENT                      ADC_AWD1_EVENT
-#define AWD2_EVENT                      ADC_AWD2_EVENT
-#define AWD3_EVENT                      ADC_AWD3_EVENT
-#define OVR_EVENT                       ADC_OVR_EVENT
-#define JQOVF_EVENT                     ADC_JQOVF_EVENT
-#define ALL_CHANNELS                    ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
-#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
-
-#if defined(STM32H7)
-#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
-#endif /* STM32H7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
-#if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
-#endif
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
-#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
-#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
-#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
-
-#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
-#if defined(STM32L0)
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
-/* to the second dedicated IO (only for COMP2).                               */
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
-#else
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
-#endif
-#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
-/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
-#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC_WAVE_NONE                                   0x00000000U
-#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
-#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
-#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
-
-#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
-#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
-#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
-#endif
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
-#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
-#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
-#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-#if defined(STM32L4)
-
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
-#endif
-
-#endif /* STM32L4 */
-
-#if defined(STM32G0)
-#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
-#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM
-#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM
-
-#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM
-#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM
-#endif
-
-#if defined(STM32H7)
-
-#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
-
-#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
-#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
-
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
-
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
-
-#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
-#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
-
-#endif /* STM32H7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP                    OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE                      FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW                     OB_IWDG_SW
-#define OB_WDG_HW                     OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
-#if defined(STM32G0)
-#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
-#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
-#else
-#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
-#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
-#endif
-#if defined(STM32H7)
-#define FLASH_FLAG_SNECCE_BANK1RR     FLASH_FLAG_SNECCERR_BANK1
-#define FLASH_FLAG_DBECCE_BANK1RR     FLASH_FLAG_DBECCERR_BANK1
-#define FLASH_FLAG_STRBER_BANK1R      FLASH_FLAG_STRBERR_BANK1
-#define FLASH_FLAG_SNECCE_BANK2RR     FLASH_FLAG_SNECCERR_BANK2
-#define FLASH_FLAG_DBECCE_BANK2RR     FLASH_FLAG_DBECCERR_BANK2
-#define FLASH_FLAG_STRBER_BANK2R      FLASH_FLAG_STRBERR_BANK2
-#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
-#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
-#endif /* STM32H7 */
-#if defined(STM32U5)
-#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
-#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
-#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
-#define OB_USER_nSWBOOT0              OB_USER_NSWBOOT0
-#define OB_USER_nBOOT0                OB_USER_NBOOT0
-#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
-#define OB_nBOOT0_SET                 OB_NBOOT0_SET
-#endif /* STM32U5 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#if defined(STM32H7)
-#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
-#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
-#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
-#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
-#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
-#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
-#endif /* STM32H7 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
-#if defined(STM32G4)
-
-#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
-#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
-#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
-#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
-#endif /* STM32G4 */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
-  * @{
-  */
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
-#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
-#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
-/**
-  * @}
-  */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
-#define GET_GPIO_INDEX                            GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32H7)
-#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
-#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
-#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
-#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
-#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
-#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
-
-#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
-    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
-#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
-#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
-#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
-#endif /* STM32H7 */
-
-#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
-#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
-#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
-
-#if defined(STM32L1)
-#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
-#define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
-#define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
-#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
-
-#if defined(STM32G4)
-#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
-#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
-#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
-#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
-#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A
-#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B
-#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
-#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
-#endif /* STM32G4 */
-
-#if defined(STM32H7)
-#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-
-#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-#endif /* STM32H7 */
-
-#if defined(STM32F3)
-/** @brief Constants defining available sources associated to external events.
-  */
-#define HRTIM_EVENTSRC_1              (0x00000000U)
-#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
-#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
-#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
-
-/** @brief Constants defining the DLL calibration periods (in micro seconds)
-  */
-#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
-#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
-#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
-#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
-
-#endif /* STM32F3 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
-#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-#if defined(STM32U5)
-#define LPTIM_ISR_CC1        LPTIM_ISR_CC1IF
-#define LPTIM_ISR_CC2        LPTIM_ISR_CC2IF
-#endif /* STM32U5 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef             NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE                    NOR_WRITE
-#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
-
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
-
-#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
-#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
-#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
-#endif
-
-#if defined(STM32L4) || defined(STM32L5)
-#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER
-#elif defined(STM32G4)
-#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
-
-#if defined(STM32H7)
-#define I2S_IT_TXE               I2S_IT_TXP
-#define I2S_IT_RXNE              I2S_IT_RXP
-
-#define I2S_FLAG_TXE             I2S_FLAG_TXP
-#define I2S_FLAG_RXNE            I2S_FLAG_RXP
-#endif
-
-#if defined(STM32F7)
-#define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA                       ATA_DATA
-#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD                  ATA_CARD_HEAD
-#define CF_STATUS_CMD                 ATA_STATUS_CMD
-#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
-#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define FORMAT_BIN                  RTC_FORMAT_BIN
-#define FORMAT_BCD                  RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
-
-#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
-#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
-
-#if defined(STM32H7)
-#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
-#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
-
-#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
-#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
-#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL
-#endif /* STM32H7 */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
-
-#if defined(STM32H7)
-
-#define SPI_FLAG_TXE                    SPI_FLAG_TXP
-#define SPI_FLAG_RXNE                   SPI_FLAG_RXP
-
-#define SPI_IT_TXE                      SPI_IT_TXP
-#define SPI_IT_RXNE                     SPI_IT_RXP
-
-#define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
-#define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
-#define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
-#define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
-
-#endif /* STM32H7 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
-
-#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
-#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
-#define TIM_DMABase_SR                   TIM_DMABASE_SR
-#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
-#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
-#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
-#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
-#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
-#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
-#define TIM_DMABase_OR                   TIM_DMABASE_OR
-
-#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
-
-#if defined(STM32L0)
-#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
-#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
-#endif
-
-#if defined(STM32F3)
-#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
-#endif
-
-#if defined(STM32H7)
-#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
-#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
-#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
-#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
-#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
-#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
-#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
-#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
-#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
-#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
-#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
-#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
-#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
-#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
-#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
-
-#define __DIV_LPUART                    UART_DIV_LPUART
-
-#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED               USART_NACK_ENABLE
-#define USARTNACK_DISABLED              USART_NACK_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CFR_BASE                    WWDG_CFR_BASE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0                CAN_IT_TME
-#define CAN_IT_RQCP1                CAN_IT_TME
-#define CAN_IT_RQCP2                CAN_IT_TME
-#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define VLAN_TAG                ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR              0x00000100U
-#define ETH_MMCRIR             0x00000104U
-#define ETH_MMCTIR             0x00000108U
-#define ETH_MMCRIMR            0x0000010CU
-#define ETH_MMCTIMR            0x00000110U
-#define ETH_MMCTGFSCCR         0x0000014CU
-#define ETH_MMCTGFMSCCR        0x00000150U
-#define ETH_MMCTGFCR           0x00000168U
-#define ETH_MMCRFCECR          0x00000194U
-#define ETH_MMCRFAECR          0x00000198U
-#define ETH_MMCRGUFCR          0x000001C4U
-
-#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
-#if defined(STM32F1)
-#else
-#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF             DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
-
-/**
-  * @}
-  */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
-  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
-  || defined(STM32H7)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
-#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
-#define CM_RGB888               DMA2D_INPUT_RGB888
-#define CM_RGB565               DMA2D_INPUT_RGB565
-#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
-#define CM_L8                   DMA2D_INPUT_L8
-#define CM_AL44                 DMA2D_INPUT_AL44
-#define CM_AL88                 DMA2D_INPUT_AL88
-#define CM_L4                   DMA2D_INPUT_L4
-#define CM_A8                   DMA2D_INPUT_A8
-#define CM_A4                   DMA2D_INPUT_A4
-/**
-  * @}
-  */
-#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
-  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
-  || defined(STM32H7) || defined(STM32U5)
-/** @defgroup DMA2D_Aliases DMA2D API Aliases
-  * @{
-  */
-#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
-                                                                        for compatibility with legacy code */
-/**
-  * @}
-  */
-
-#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 || STM32U5 */
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
-  * @{
-  */
-
-#if defined(STM32U5)
-#define HAL_DCACHE_CleanInvalidateByAddr     HAL_DCACHE_CleanInvalidByAddr
-#define HAL_DCACHE_CleanInvalidateByAddr_IT  HAL_DCACHE_CleanInvalidByAddr_IT
-#endif /* STM32U5 */
-
-/**
-  * @}
-  */
-
-#if !defined(STM32F2)
-/** @defgroup HASH_alias HASH API alias
-  * @{
-  */
-#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< Redirection for compatibility with legacy code */
-/**
-  *
-  * @}
-  */
-#endif /* STM32F2 */
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
-#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
-#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
-
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
-
-#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
-#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
-#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
-#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
-
-#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
-#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
-#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
-#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
-#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
-#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
-#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
-#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
-#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
-#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
-
-#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
-                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
-                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
-#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
-#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
-#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
-#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
-#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
-
-/**
-  * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
-                                                                 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
-#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
-#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
-#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
-#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
-#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
-#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-
-#if defined(STM32F4)
-#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
-#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
-#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
-#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
-#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
-#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
-#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
-#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
-#endif /* STM32F4 */
-/**
-  * @}
- */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
-  * @{
-  */
-
-#if defined(STM32G0)
-#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
-#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
-#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
-#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
-#endif
-#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
-#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
-#define CR_PMODE_BB                                   CR_VOS_BB
-
-#define DBP_BitNumber                                 DBP_BIT_NUMBER
-#define PVDE_BitNumber                                PVDE_BIT_NUMBER
-#define PMODE_BitNumber                               PMODE_BIT_NUMBER
-#define EWUP_BitNumber                                EWUP_BIT_NUMBER
-#define FPDS_BitNumber                                FPDS_BIT_NUMBER
-#define ODEN_BitNumber                                ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
-#define BRE_BitNumber                                 BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
-
-/**
-  * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError                                TIM_DMAError
-#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
-#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
-#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
-#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
-#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
-#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
-#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-#define HAL_LTDC_Relaod           HAL_LTDC_Reload
-#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
-#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define AES_IT_CC                      CRYP_IT_CC
-#define AES_IT_ERR                     CRYP_IT_ERR
-#define AES_FLAG_CCF                   CRYP_FLAG_CCF
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
-#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
-
-#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
-#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
-#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1                                   ADC_SQR1
-#define __HAL_ADC_SMPR1                                  ADC_SMPR1
-#define __HAL_ADC_SMPR2                                  ADC_SMPR2
-#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
-#define __HAL_ADC_JSQR                                   ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#if defined(STM32H7)
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
-#else
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#endif /* STM32H7 */
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32F3)
-#define COMP_START                                       __HAL_COMP_ENABLE
-#define COMP_STOP                                        __HAL_COMP_DISABLE
-#define COMP_LOCK                                        __HAL_COMP_LOCK
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro             */
-/*       is COMP_FLAG_LOCK.                                                   */
-/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
-/*       argument.                                                            */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
-  * @}
-  */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-/**
-  * @}
-  */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
-                           ((WAVE) == DAC_WAVE_NOISE)|| \
-                           ((WAVE) == DAC_WAVE_TRIANGLE))
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_WRPAREA          IS_OB_WRPAREA
-#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE        IS_FLASH_TYPEERASE
-#define IS_NBSECTORS        IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
-#if defined(STM32F1)
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
-#else
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
-#endif /* STM32F1 */
-#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
-#define __HAL_I2C_SPEED                 I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
-
-#if defined(STM32H7)
-#define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
-#endif /* STM32F4 */
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
-  * @{
-  */
-
-#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
-                                         )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-
-#if defined(STM32WB)
-#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
-#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
-#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
-#define QSPI_IRQHandler QUADSPI_IRQHandler
-#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
-
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
-#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
-#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
-#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
-#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
-#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
-#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
-#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-
-#if defined(STM32H7)
-#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
-#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
-
-#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
-#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
-
-
-#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
-#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
-#endif
-
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-
-#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
-#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
-#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
-#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
-#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
-#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
-#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
-#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
-#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
-#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
-#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
-#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
-#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
-#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
-#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
-#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
-#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
-#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
-#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
-#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
-#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
-#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
-#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
-#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
-#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
-#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32L1)
-#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
-#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
-#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
-#endif /* STM32L1 */
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection               SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection                 Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#if defined(STM32H7)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
-
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
-#endif
-
-#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14                RCC_IT_HSI14RDY
-
-#define RCC_IT_CSSLSE               RCC_IT_LSECSS
-#define RCC_IT_CSSHSE               RCC_IT_CSS
-
-#define RCC_PLLMUL_3                RCC_PLL_MUL3
-#define RCC_PLLMUL_4                RCC_PLL_MUL4
-#define RCC_PLLMUL_6                RCC_PLL_MUL6
-#define RCC_PLLMUL_8                RCC_PLL_MUL8
-#define RCC_PLLMUL_12               RCC_PLL_MUL12
-#define RCC_PLLMUL_16               RCC_PLL_MUL16
-#define RCC_PLLMUL_24               RCC_PLL_MUL24
-#define RCC_PLLMUL_32               RCC_PLL_MUL32
-#define RCC_PLLMUL_48               RCC_PLL_MUL48
-
-#define RCC_PLLDIV_2                RCC_PLL_DIV2
-#define RCC_PLLDIV_3                RCC_PLL_DIV3
-#define RCC_PLLDIV_4                RCC_PLL_DIV4
-
-#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV               RCC_MCODIV_1
-#define RCC_MCO_DIV1                RCC_MCODIV_1
-#define RCC_MCO_DIV2                RCC_MCODIV_2
-#define RCC_MCO_DIV4                RCC_MCODIV_4
-#define RCC_MCO_DIV8                RCC_MCODIV_8
-#define RCC_MCO_DIV16               RCC_MCODIV_16
-#define RCC_MCO_DIV32               RCC_MCODIV_32
-#define RCC_MCO_DIV64               RCC_MCODIV_64
-#define RCC_MCO_DIV128              RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
-#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
-#else
-#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
-#endif
-
-#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB            RCC_CR_HSION_BB
-#define CR_CSSON_BB            RCC_CR_CSSON_BB
-#define CR_PLLON_BB            RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB            RCC_CR_MSION_BB
-#define CSR_LSION_BB           RCC_CSR_LSION_BB
-#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB            RCC_CR_HSEON_BB
-#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection         Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
-#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
-#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
-#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
-
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
-#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
-#if defined(STM32U5)
-#define MSIKPLLModeSEL  RCC_MSIKPLL_MODE_SEL
-#define MSISPLLModeSEL  RCC_MSISPLL_MODE_SEL
-#define __HAL_RCC_AHB21_CLK_DISABLE           __HAL_RCC_AHB2_1_CLK_DISABLE
-#define __HAL_RCC_AHB22_CLK_DISABLE           __HAL_RCC_AHB2_2_CLK_DISABLE
-#define __HAL_RCC_AHB1_CLK_Disable_Clear      __HAL_RCC_AHB1_CLK_ENABLE
-#define __HAL_RCC_AHB21_CLK_Disable_Clear     __HAL_RCC_AHB2_1_CLK_ENABLE
-#define __HAL_RCC_AHB22_CLK_Disable_Clear     __HAL_RCC_AHB2_2_CLK_ENABLE
-#define __HAL_RCC_AHB3_CLK_Disable_Clear      __HAL_RCC_AHB3_CLK_ENABLE
-#define __HAL_RCC_APB1_CLK_Disable_Clear      __HAL_RCC_APB1_CLK_ENABLE
-#define __HAL_RCC_APB2_CLK_Disable_Clear      __HAL_RCC_APB2_CLK_ENABLE
-#define __HAL_RCC_APB3_CLK_Disable_Clear      __HAL_RCC_APB3_CLK_ENABLE
-#define IS_RCC_MSIPLLModeSelection            IS_RCC_MSIPLLMODE_SELECT
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
-#else
-#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
-#endif
-#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
-                                                       (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
-                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif   /* STM32F1 */
-
-#define IS_ALARM                                  IS_RTC_ALARM
-#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
-#define IS_TAMPER                                 IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
-#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
-
-#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
-#define eMMC_HIGH_VOLTAGE_RANGE     EMMC_HIGH_VOLTAGE_RANGE
-#define eMMC_DUAL_VOLTAGE_RANGE     EMMC_DUAL_VOLTAGE_RANGE
-#define eMMC_LOW_VOLTAGE_RANGE      EMMC_LOW_VOLTAGE_RANGE
-
-#define SDMMC_NSpeed_CLK_DIV        SDMMC_NSPEED_CLK_DIV
-#define SDMMC_HSpeed_CLK_DIV        SDMMC_HSPEED_CLK_DIV
-#endif
-
-#if defined(STM32F4) || defined(STM32F2)
-#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
-#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
-#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
-#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
-#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
-#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
-#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
-#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
-#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
-#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
-#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
-#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
-#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
-#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
-#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
-#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
-#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
-#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
-#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define  SDMMC1_IRQn                SDIO_IRQn
-#define  SDMMC1_IRQHandler          SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
-#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
-#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
-#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
-#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
-#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
-#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
-#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
-#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
-#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
-#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
-#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
-#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
-#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
-#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
-#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
-#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
-#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
-#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
-#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define  SDIO_IRQn                  SDMMC1_IRQn
-#define  SDIO_IRQHandler            SDMMC1_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
-#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
-#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
-#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
-#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
-#endif
-
-#if defined(STM32H7) || defined(STM32L5)
-#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
-#define __USART_ENABLE                  __HAL_USART_ENABLE
-#define __USART_DISABLE                 __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
-#define USART_OVERSAMPLING_16               0x00000000U
-#define USART_OVERSAMPLING_8                USART_CR1_OVER8
-
-#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
-                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))
-#endif /* STM32F0 || STM32F3 || STM32F7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
-#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE                     SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32H7)
-#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
-#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
-#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
-#endif /* STM32L4 || STM32F4 || STM32F7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32_HAL_LEGACY */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32_assert_template.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32_assert_template.h
deleted file mode 100644
index 3e9f2586a2..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32_assert_template.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_assert.h
-  * @author  MCD Application Team
-  * @brief   STM32 assert template file.
-  *          This file should be copied to the application folder and renamed
-  *          to stm32_assert.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_ASSERT_H
-#define __STM32_ASSERT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Includes ------------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32_ASSERT_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h
deleted file mode 100644
index 8aa30b1988..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h
+++ /dev/null
@@ -1,487 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal.h
-  * @author  MCD Application Team
-  * @brief   This file contains all the functions prototypes for the HAL
-  *          module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_H
-#define __STM32L0xx_HAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_conf.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup HAL HAL
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
-  * @{
-  */
-
-/** @defgroup HAL_TICK_FREQ Tick Frequency
-  * @{
-  */
-typedef enum
-{
-  HAL_TICK_FREQ_10HZ         = 100U,
-  HAL_TICK_FREQ_100HZ        = 10U,
-  HAL_TICK_FREQ_1KHZ         = 1U,
-  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
-} HAL_TickFreqTypeDef;
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_BootMode Boot Mode
-  * @{
-  */
-#define SYSCFG_BOOT_MAINFLASH          (0x00000000U)
-#define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_CFGR1_BOOT_MODE_0
-#define SYSCFG_BOOT_SRAM               SYSCFG_CFGR1_BOOT_MODE
-
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Low_Power_Config DBGMCU Low Power Configuration
-  * @{
-  */
-#define DBGMCU_SLEEP                 DBGMCU_CR_DBG_SLEEP
-#define DBGMCU_STOP                  DBGMCU_CR_DBG_STOP
-#define DBGMCU_STANDBY               DBGMCU_CR_DBG_STANDBY
-#define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U))
-
-
-/**
-  * @}
-  */
-
-#if defined (LCD_BASE) /* STM32L0x3xx only */
-/** @defgroup SYSCFG_LCD_EXT_CAPA SYSCFG LCD External Capacitors
-  * @{
-  */
-#define SYSCFG_LCD_EXT_CAPA             SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */
-#define SYSCFG_VLCD_PB2_EXT_CAPA_ON     SYSCFG_CFGR2_CAPA_0  /*!< Connection on PB2   */
-#define SYSCFG_VLCD_PB12_EXT_CAPA_ON    SYSCFG_CFGR2_CAPA_1  /*!< Connection on PB12  */
-#define SYSCFG_VLCD_PB0_EXT_CAPA_ON     SYSCFG_CFGR2_CAPA_2  /*!< Connection on PB0   */
-#if defined (SYSCFG_CFGR2_CAPA_3)
-#define SYSCFG_VLCD_PE11_EXT_CAPA_ON    SYSCFG_CFGR2_CAPA_3  /*!< Connection on PE11  */
-#endif
-#if defined (SYSCFG_CFGR2_CAPA_4)
-#define SYSCFG_VLCD_PE12_EXT_CAPA_ON    SYSCFG_CFGR2_CAPA_4  /*!< Connection on PE12  */
-#endif
-
-/**
-  * @}
-  */
-#endif
-
-/** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection
-  * @{
-  */
-#define SYSCFG_VREFINT_OUT_NONE          (0x00000000U)           /* no pad connected */
-#define SYSCFG_VREFINT_OUT_PB0           SYSCFG_CFGR3_VREF_OUT_0 /* Selects PBO as output for the Vrefint */
-#define SYSCFG_VREFINT_OUT_PB1           SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */
-#define SYSCFG_VREFINT_OUT_PB0_PB1       SYSCFG_CFGR3_VREF_OUT   /* Selects PBO and PB1 as output for the Vrefint */
-
-#define IS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT)   (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE)  || \
-                                                ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0)  || \
-                                                ((OUTPUT) == SYSCFG_VREFINT_OUT_PB1)  || \
-                                                ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1))
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_flags_definition SYSCFG Flags Definition
-  * @{
-  */
-#define SYSCFG_FLAG_VREFINT_READY      SYSCFG_CFGR3_VREFINT_RDYF
-
-#define IS_SYSCFG_FLAG(FLAG)           ((FLAG) == SYSCFG_FLAG_VREFINT_READY))
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_FastModePlus_GPIO Fast Mode Plus on GPIO
-  * @{
-  */
-/** @brief  Fast mode Plus driving capability on a specific GPIO
-  */
-#if defined (SYSCFG_CFGR2_I2C_PB6_FMP)
-#define SYSCFG_FASTMODEPLUS_PB6       SYSCFG_CFGR2_I2C_PB6_FMP  /* Enable Fast Mode Plus on PB6 */
-#endif
-#if defined (SYSCFG_CFGR2_I2C_PB7_FMP)
-#define SYSCFG_FASTMODEPLUS_PB7       SYSCFG_CFGR2_I2C_PB7_FMP  /* Enable Fast Mode Plus on PB7 */
-#endif
-#if defined (SYSCFG_CFGR2_I2C_PB8_FMP)
-#define SYSCFG_FASTMODEPLUS_PB8       SYSCFG_CFGR2_I2C_PB8_FMP  /* Enable Fast Mode Plus on PB8 */
-#endif
-#if defined (SYSCFG_CFGR2_I2C_PB9_FMP)
-#define SYSCFG_FASTMODEPLUS_PB9       SYSCFG_CFGR2_I2C_PB9_FMP  /* Enable Fast Mode Plus on PB9 */
-#endif
-
-#define IS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6)  || \
-                                     (((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7)  || \
-                                     (((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8)  || \
-                                     (((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9)  )
-/**
- * @}
- */
- /**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup HAL_Exported_Macros HAL Exported Macros
-  * @{
-  */
-
-/** @brief  Freeze/Unfreeze Peripherals in Debug mode
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
-/**
-  * @brief  TIM2 Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_TIM2()     SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM2()   CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)
-#endif
-
-#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
-/**
-  * @brief  TIM3 Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_TIM3()     SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM3()   CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)
-#endif
-
-#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
-/**
-  * @brief  TIM6 Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_TIM6()     SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM6()   CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
-#endif
-
-#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
-/**
-  * @brief  TIM7 Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_TIM7()     SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM7()   CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
-#endif
-
-#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
-/**
-  * @brief  RTC Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_RTC()      SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
-#define __HAL_DBGMCU_UNFREEZE_RTC()    CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
-#endif
-
-#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
-/**
-  * @brief  WWDG Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_WWDG()     SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_WWDG()   CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
-#endif
-
-#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
-/**
-  * @brief  IWDG Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_IWDG()     SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_IWDG()   CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
-#endif
-
-#if defined (DBGMCU_APB1_FZ_DBG_I2C1_STOP)
-/**
-  * @brief  I2C1 Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
-#endif
-
-#if defined (DBGMCU_APB1_FZ_DBG_I2C2_STOP)
-/**
-  * @brief  I2C2 Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU()   SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
-#endif
-
-#if defined (DBGMCU_APB1_FZ_DBG_I2C3_STOP)
-/**
-  * @brief  I2C3 Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
-#endif
-
-#if defined (DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
-/**
-  * @brief  LPTIMER Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_LPTIMER()        SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
-#define __HAL_DBGMCU_UNFREEZE_LPTIMER()      CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
-#endif
-
-#if defined (DBGMCU_APB2_FZ_DBG_TIM22_STOP)
-/**
-  * @brief  TIM22 Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_TIM22()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM22()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP)
-#endif
-
-#if defined (DBGMCU_APB2_FZ_DBG_TIM21_STOP)
-/**
-  * @brief  TIM21 Peripherals Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_TIM21()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM21()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP)
-#endif
-
-/** @brief  Main Flash memory mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FLASH()     CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
-
-/** @brief  System Flash memory mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()      MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
-
-
-/** @brief  Embedded SRAM mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_SRAM()             MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1)
-
-/** @brief  Configuration of the DBG Low Power mode.
-  * @param  __DBGLPMODE__ bit field to indicate in wich Low Power mode DBG is still active.
-  *         This parameter can be a value of
-  *         - DBGMCU_SLEEP
-  *         - DBGMCU_STOP
-  *         - DBGMCU_STANDBY
-  */
-#define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__)    do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \
-                                                       MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \
-                                                     } while (0)
-
-#if defined (LCD_BASE) /* STM32L0x3xx only */
-
-/** @brief  Macro to configure the VLCD Decoupling capacitance connection.
-  *
-  * @param  __SYSCFG_VLCD_CAPA__ specifies the decoupling of LCD capacitance for rails connection on GPIO.
-  *          This parameter can be a combination of following values (when available):
-  *            @arg SYSCFG_VLCD_PB2_EXT_CAPA_ON:  Connection on PB2
-  *            @arg SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12
-  *            @arg SYSCFG_VLCD_PB0_EXT_CAPA_ON:  Connection on PB0
-  *            @arg SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11
-  *            @arg SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12
-  * @retval None
-  */
-#define __HAL_SYSCFG_VLCD_CAPA_CONFIG(__SYSCFG_VLCD_CAPA__) \
-                  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA, (uint32_t)(__SYSCFG_VLCD_CAPA__))
-
-/**
-  * @brief  Returns the decoupling of LCD capacitance configured by user.
-  * @retval The LCD capacitance connection as configured by user. The returned can be a combination of :
-  *            SYSCFG_VLCD_PB2_EXT_CAPA_ON:  Connection on PB2
-  *            SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12
-  *            SYSCFG_VLCD_PB0_EXT_CAPA_ON:  Connection on PB0
-  *            SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11
-  *            SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12
-  */
-#define __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG()          READ_BIT(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA)
-
-#endif
-
-/**
-  * @brief  Returns the boot mode as configured by user.
-  * @retval The boot mode as configured by user. The returned can be a value of :
-  *     - SYSCFG_BOOT_MAINFLASH
-  *     - SYSCFG_BOOT_SYSTEMFLASH
-  *     - SYSCFG_BOOT_SRAM
-  */
-#define __HAL_SYSCFG_GET_BOOT_MODE()          READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE)
-
-
-/** @brief  Check whether the specified SYSCFG flag is set or not.
-  * @param  __FLAG__ specifies the flag to check.
-  *         The only parameter supported is SYSCFG_FLAG_VREFINT_READY
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Fast mode Plus driving capability enable macro
-  * @param __FASTMODEPLUS__ This parameter can be a value of :
-  *     @arg SYSCFG_FASTMODEPLUS_PB6
-  *     @arg SYSCFG_FASTMODEPLUS_PB7
-  *     @arg SYSCFG_FASTMODEPLUS_PB8
-  *     @arg SYSCFG_FASTMODEPLUS_PB9
-  */
-#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
-                                                                SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__));                 \
-                                                               }while(0)
-/** @brief  Fast mode Plus driving capability disable macro
-  * @param __FASTMODEPLUS__ This parameter can be a value of :
-  *     @arg SYSCFG_FASTMODEPLUS_PB6
-  *     @arg SYSCFG_FASTMODEPLUS_PB7
-  *     @arg SYSCFG_FASTMODEPLUS_PB8
-  *     @arg SYSCFG_FASTMODEPLUS_PB9
-  */
-#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
-                                                                CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__));               \
-                                                               }while(0)
-
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Private_Macros HAL Private Macros
-  * @{
-  */
-#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
-                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
-                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
-/**
-  * @}
-  */
-
-/* Exported variables --------------------------------------------------------*/
-/** @defgroup HAL_Exported_Variables HAL Exported Variables
-  * @{
-  */
-extern __IO uint32_t uwTick;
-extern uint32_t uwTickPrio;
-extern HAL_TickFreqTypeDef uwTickFreq;
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
-  * @{
-  */
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and de-initialization functions
- * @{
-  */
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions
-  * @brief    Peripheral Control functions
-  * @{
-  */
-void HAL_IncTick(void);
-void HAL_Delay(uint32_t Delay);
-uint32_t HAL_GetTick(void);
-uint32_t HAL_GetTickPrio(void);
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
-HAL_TickFreqTypeDef HAL_GetTickFreq(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-uint32_t HAL_GetUIDw0(void);
-uint32_t HAL_GetUIDw1(void);
-uint32_t HAL_GetUIDw2(void);
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Peripheral Control functions
-  * @brief    DBGMCU Peripheral Control functions
-  * @{
-  */
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph);
-void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph);
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group4 SYSCFG Peripheral Control functions
-  * @brief    SYSCFG Peripheral Control functions
-  * @{
-  */
-uint32_t  HAL_SYSCFG_GetBootMode(void);
-void HAL_SYSCFG_Enable_Lock_VREFINT(void);
-void HAL_SYSCFG_Disable_Lock_VREFINT(void);
-void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/* Define the private group ***********************************/
-/**************************************************************/
-/** @defgroup HAL_Private HAL Private
-  * @{
-  */
-/**
-  * @}
-  */
-/**************************************************************/
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h
deleted file mode 100644
index 54f6f1dbf9..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h
+++ /dev/null
@@ -1,1192 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_adc.h
-  * @author  MCD Application Team
-  * @brief   Header file of ADC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_ADC_H
-#define __STM32L0xx_HAL_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Types ADC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  ADC group regular oversampling structure definition
-  */
-typedef struct
-{
-  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
-                                               This parameter can be a value of @ref ADC_Oversampling_Ratio */
-
-  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
-                                               This parameter can be a value of @ref ADC_Right_Bit_Shift */
-
-  uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
-                                               This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
-}ADC_OversamplingTypeDef;
-
-/**
-  * @brief  Structure definition of ADC instance and ADC group regular.
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
-  *            ScanConvMode, EOCSelection, LowPowerAutoWait.
-  *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
-  *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
-  * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled
-  *          - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular.
-  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
-  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter 
-  *         (which fulfills the ADC state condition) on the fly).
-  */
-typedef struct
-{
-  uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator) and clock prescaler.
-                                       This parameter can be a value of @ref ADC_ClockPrescaler.
-                                       Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
-                                             if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 
-                                             must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
-                                       Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level.
-                                       Note: This parameter can be modified only if the ADC is disabled. */
-
-  uint32_t Resolution;            /*!< Configure the ADC resolution. 
-                                       This parameter can be a value of @ref ADC_Resolution */
-
-  uint32_t DataAlign;             /*!< Specify ADC data alignment in conversion data register (right or left).
-                                       Refer to reference manual for alignments formats versus resolutions.
-                                       This parameter can be a value of @ref ADC_Data_align */
-
-  uint32_t ScanConvMode;          /*!< Configure the sequencer of regular group.
-                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
-                                       Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
-                                       If only 1 channel is set: Conversion is performed in single mode.
-                                       If several channels are set:  Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
-                                                                     Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0).
-                                       This parameter can be a value of @ref ADC_Scan_mode */
-
-  uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
-                                       This parameter can be a value of @ref ADC_EOCSelection. */
-
-  uint32_t LowPowerAutoWait;      /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
-                                       conversion (for ADC group regular) has been retrieved by user software,
-                                       using function HAL_ADC_GetValue().
-                                       This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
-                                       for low frequency applications. 
-                                       This parameter can be set to ENABLE or DISABLE.
-                                       Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
-                                             to free the IRQ vector sequencer.
-                                             Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
-                                             use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */
-
-  uint32_t LowPowerAutoPowerOff;  /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
-                                       This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
-                                       This parameter can be set to ENABLE or DISABLE.
-                                       Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
-
-  FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
-                                       after the first ADC conversion start trigger occurred (software start or external trigger).
-                                       This parameter can be set to ENABLE or DISABLE. */
-
-  FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
-                                       (main sequence subdivided in successive parts).
-                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
-                                       This parameter can be set to ENABLE or DISABLE.
-                                       Note: On this STM32 serie, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */
-
-  uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion start.
-                                       If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
-                                       This parameter can be a value of @ref ADC_regular_external_trigger_source.
-                                       Caution: external trigger source is common to all ADC instances. */
-                                                                                                        
-  uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start.
-                                       If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
-                                       This parameter can be a value of @ref ADC_regular_external_trigger_edge */
-
-  FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
-                                       or in continuous mode (DMA transfer unlimited, whatever number of conversions).
-                                       This parameter can be set to ENABLE or DISABLE.
-                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
-
-  uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
-                                       This parameter can be a value of @ref ADC_Overrun.
-                                       Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 
-                                       end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 
-                                       HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
-                                       Note: Error reporting with respect to the conversion mode:
-                                             - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 
-                                               overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
-                                             - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
-
-  uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
-                                       it is mandatory to first enable the Low Frequency Mode.
-                                       This parameter can be set to ENABLE or DISABLE.
-                                       Note: This parameter can be modified only if there is no conversion is ongoing. */
-
-
-  uint32_t SamplingTime;                 /*!< The sample time common to all channels.
-                                              Unit: ADC clock cycles
-                                              This parameter can be a value of @ref ADC_sampling_times
-                                              Note: This parameter can be modified only if there is no conversion ongoing. */
-
-  uint32_t OversamplingMode;              /*!< Specify whether the oversampling feature is enabled or disabled.
-                                               This parameter can be set to ENABLE or DISABLE.
-                                               Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
-
-
-  ADC_OversamplingTypeDef  Oversample;   /*!< Specify the Oversampling parameters
-                                              Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
-}ADC_InitTypeDef;
-
-/**
-  * @brief  Structure definition of ADC channel for regular group
-  * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled or enabled without conversion on going on regular group.
-  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
-  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
-  */
-typedef struct
-{
-  uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
-                                        This parameter can be a value of @ref ADC_channels
-                                        Note: Depending on devices, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
-
-  uint32_t Rank;                   /*!< Add or remove the channel from ADC regular group sequencer. 
-                                        On STM32L0 devices,  number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number 
-                                        (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
-                                        Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
-                                        This parameter can be a value of @ref ADC_rank */
-}ADC_ChannelConfTypeDef;
-
-/**
-  * @brief  Structure definition of ADC analog watchdog
-  * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC group regular
-  *          - For parameters 'HighThreshold' and 'LowThreshold': ADC enabled with conversion on going on regular group (AWD thresholds can be modify on the fly while ADC conversion is on going)
-  */
-typedef struct
-{
-  uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all channels.
-                                   This parameter can be a value of @ref ADC_analog_watchdog_mode */
-
-  uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
-                                   This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
-                                   This parameter can be a value of @ref ADC_channels */
-
-  FunctionalState ITMode;     /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
-                                   This parameter can be set to ENABLE or DISABLE */
-  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
-                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits),
-                                   this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
-
-  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
-                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits),
-                                   this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
-}ADC_AnalogWDGConfTypeDef;
-
-/**
-  * @brief  HAL ADC state machine: ADC states definition (bitfields)
-  * @note   ADC state machine is managed by bitfields, state must be compared
-  *         with bit by bit.
-  *         For example:                                                         
-  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
-  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
-  */
-/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET             (0x00000000U)    /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY             (0x00000001U)    /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002U)    /*!< ADC is busy due to an internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT           (0x00000004U)    /*!< TimeOut occurrence */
-
-/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010U)    /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020U)    /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA         (0x00000040U)    /*!< DMA error occurrence */
-
-/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY          (0x00000100U)    /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
-                                                              external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_REG_EOC           (0x00000200U)    /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR           (0x00000400U)    /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP         (0x00000800U)    /*!< Not available on this STM32 serie: End Of Sampling flag raised  */
-
-/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY          (0x00001000U)    /*!< Not available on this STM32 serie: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
-                                                              external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_INJ_EOC           (0x00002000U)    /*!< Not available on this STM32 serie: Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF         (0x00004000U)    /*!< Not available on this STM32 serie: Injected queue overflow occurrence */
-
-/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1              (0x00010000U)    /*!< Out-of-window occurrence of ADC analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2              (0x00020000U)    /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3              (0x00040000U)    /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 3 */
-
-/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000U)    /*!< Not available on this STM32 serie: ADC in multimode slave state, controlled by another ADC master (when feature available) */
-
-
-
-/** 
-  * @brief  ADC handle Structure definition
-  */
-typedef struct __ADC_HandleTypeDef
-{
-  ADC_TypeDef                   *Instance;              /*!< Register base address */
-
-  ADC_InitTypeDef               Init;                   /*!< ADC required parameters */
-
-  DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
-
-  HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
-
-  __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
-
-  __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
-
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
-  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
-  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
-  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
-  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
-  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-}ADC_HandleTypeDef;
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL ADC Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
-  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
-  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
-  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
-  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
-  HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID          */
-  HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID        */
-} HAL_ADC_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL ADC Callback pointer definition
-  */
-typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
-
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants ADC Exported Constants
-  * @{
-  */
-
-/** @defgroup ADC_Error_Code ADC Error Code
-  * @{
-  */
-#define HAL_ADC_ERROR_NONE        (0x00U)   /*!< No error                                    */
-#define HAL_ADC_ERROR_INTERNAL    (0x01U)   /*!< ADC peripheral internal error (problem of clocking,
-                                                enable/disable, erroneous state, ...)        */
-#define HAL_ADC_ERROR_OVR         (0x02U)   /*!< Overrun error                               */
-#define HAL_ADC_ERROR_DMA         (0x04U)   /*!< DMA transfer error                          */
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_TimeOut_Values ADC TimeOut Values
-  * @{
-  */
-
-  /* Fixed timeout values for ADC calibration, enable settling time, disable  */
-  /* settling time.                                                           */
-  /* Values defined to be higher than worst cases: low clocks freq,           */
-  /* maximum prescalers.                                                      */
-  /* Unit: ms                                                                 */      
-#define ADC_ENABLE_TIMEOUT            10U
-#define ADC_DISABLE_TIMEOUT           10U
-#define ADC_STOP_CONVERSION_TIMEOUT   10U
-
-  /* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have  */
-  /* the minimum number of CPU cycles to fulfill this delay                   */
-  #define ADC_DELAY_10US_MIN_CPU_CYCLES         1800U 
-/**
-  * @}
-  */
-
-/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
-  * @{
-  */     
-#define ADC_CLOCK_ASYNC_DIV1              (0x00000000U)                               /*!< ADC Asynchronous clock mode divided by 1 */
-#define ADC_CLOCK_ASYNC_DIV2              (ADC_CCR_PRESC_0)                                     /*!< ADC Asynchronous clock mode divided by 2 */
-#define ADC_CLOCK_ASYNC_DIV4              (ADC_CCR_PRESC_1)                                     /*!< ADC Asynchronous clock mode divided by 2 */
-#define ADC_CLOCK_ASYNC_DIV6              (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC Asynchronous clock mode divided by 2 */
-#define ADC_CLOCK_ASYNC_DIV8              (ADC_CCR_PRESC_2)                                     /*!< ADC Asynchronous clock mode divided by 2 */
-#define ADC_CLOCK_ASYNC_DIV10             (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)                   /*!< ADC Asynchronous clock mode divided by 2 */
-#define ADC_CLOCK_ASYNC_DIV12             (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1)                   /*!< ADC Asynchronous clock mode divided by 2 */
-#define ADC_CLOCK_ASYNC_DIV16             (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
-#define ADC_CLOCK_ASYNC_DIV32             (ADC_CCR_PRESC_3)                                     /*!< ADC Asynchronous clock mode divided by 2 */
-#define ADC_CLOCK_ASYNC_DIV64             (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC Asynchronous clock mode divided by 2 */
-#define ADC_CLOCK_ASYNC_DIV128            (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC Asynchronous clock mode divided by 2 */
-#define ADC_CLOCK_ASYNC_DIV256            (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
-
-#define ADC_CLOCK_SYNC_PCLK_DIV1         (ADC_CFGR2_CKMODE)    /*!< Synchronous clock mode divided by 1 
-                                                                               This configuration must be enabled only if PCLK has a 50%
-                                                                               duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
-                                                                               must by 50% duty cycle)*/
-#define ADC_CLOCK_SYNC_PCLK_DIV2         (ADC_CFGR2_CKMODE_0)  /*!< Synchronous clock mode divided by 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV4         (ADC_CFGR2_CKMODE_1)  /*!< Synchronous clock mode divided by 4 */
-
-/**                                                       
-  * @}
-  */ 
-
-/** @defgroup ADC_Resolution ADC Resolution
-  * @{
-  */
-#define ADC_RESOLUTION_12B      (0x00000000U)          /*!< ADC 12-bit resolution */
-#define ADC_RESOLUTION_10B      (ADC_CFGR1_RES_0)      /*!< ADC 10-bit resolution */
-#define ADC_RESOLUTION_8B       (ADC_CFGR1_RES_1)      /*!< ADC 8-bit resolution */
-#define ADC_RESOLUTION_6B       (ADC_CFGR1_RES)        /*!< ADC 6-bit resolution */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Data_align ADC conversion data alignment
-  * @{
-  */
-#define ADC_DATAALIGN_RIGHT      (0x00000000U)
-#define ADC_DATAALIGN_LEFT       (ADC_CFGR1_ALIGN)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_regular_external_trigger_edge ADC External Trigger Source Edge for Regular Group
-  * @{
-  */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000U)
-#define ADC_EXTERNALTRIGCONVEDGE_RISING         (ADC_CFGR1_EXTEN_0)         
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING        (ADC_CFGR1_EXTEN_1)
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  (ADC_CFGR1_EXTEN)
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_EOCSelection ADC EOC Selection
-  * @{
-  */ 
-#define ADC_EOC_SINGLE_CONV         (ADC_ISR_EOC)
-#define ADC_EOC_SEQ_CONV            (ADC_ISR_EOS)
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_Overrun ADC Overrun
-  * @{
-  */ 
-#define ADC_OVR_DATA_PRESERVED              (0x00000000U)
-#define ADC_OVR_DATA_OVERWRITTEN            (ADC_CFGR1_OVRMOD)
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_rank ADC rank
-  * @{
-  */
-#define ADC_RANK_CHANNEL_NUMBER                 (0x00001000U)  /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
-#define ADC_RANK_NONE                           (0x00001001U)  /*!< Disable the selected rank (selected channel) from sequencer */
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_channels ADC_Channels
-  * @{
-  */
-#define ADC_CHANNEL_0           (ADC_CHSELR_CHSEL0)
-#define ADC_CHANNEL_1           ((uint32_t)(ADC_CHSELR_CHSEL1) | ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_2           ((uint32_t)(ADC_CHSELR_CHSEL2) | ADC_CFGR1_AWDCH_1)
-#define ADC_CHANNEL_3           ((uint32_t)(ADC_CHSELR_CHSEL3)| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_4           ((uint32_t)(ADC_CHSELR_CHSEL4)| ADC_CFGR1_AWDCH_2)
-#define ADC_CHANNEL_5           ((uint32_t)(ADC_CHSELR_CHSEL5)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_6           ((uint32_t)(ADC_CHSELR_CHSEL6)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
-#define ADC_CHANNEL_7           ((uint32_t)(ADC_CHSELR_CHSEL7)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_8           ((uint32_t)(ADC_CHSELR_CHSEL8)| ADC_CFGR1_AWDCH_3)
-#define ADC_CHANNEL_9           ((uint32_t)(ADC_CHSELR_CHSEL9)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_10          ((uint32_t)(ADC_CHSELR_CHSEL10)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1)
-#define ADC_CHANNEL_11          ((uint32_t)(ADC_CHSELR_CHSEL11)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_12          ((uint32_t)(ADC_CHSELR_CHSEL12)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2)
-#define ADC_CHANNEL_13          ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_14          ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
-#define ADC_CHANNEL_15          ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
-#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
-#define ADC_CHANNEL_16          ((uint32_t)(ADC_CHSELR_CHSEL16)| ADC_CFGR1_AWDCH_4)
-#endif
-#define ADC_CHANNEL_17          ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_18          ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1)
-
-/* Internal channels */
-#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
-#define ADC_CHANNEL_VLCD         ADC_CHANNEL_16    
-#endif
-#define ADC_CHANNEL_VREFINT      ADC_CHANNEL_17
-#if defined(ADC_CCR_TSEN)
-#define ADC_CHANNEL_TEMPSENSOR   ADC_CHANNEL_18
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks
-  * @{
-  */
-#define ADC_CHANNEL_MASK        (0x0007FFFFU)
-#define ADC_CHANNEL_AWD_MASK    (0x7C000000U)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_sampling_times ADC Sampling Cycles
-  * @{
-  */
-#define ADC_SAMPLETIME_1CYCLE_5       (0x00000000U)                         /*!<  ADC sampling time 1.5 cycle */
-#define ADC_SAMPLETIME_3CYCLES_5      (ADC_SMPR_SMPR_0)                     /*!<  ADC sampling time 3.5 CYCLES */
-#define ADC_SAMPLETIME_7CYCLES_5      (ADC_SMPR_SMPR_1)                     /*!<  ADC sampling time 7.5 CYCLES */
-#define ADC_SAMPLETIME_12CYCLES_5     ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!<  ADC sampling time 12.5 CYCLES */
-#define ADC_SAMPLETIME_19CYCLES_5     (ADC_SMPR_SMPR_2)                     /*!<  ADC sampling time 19.5 CYCLES */
-#define ADC_SAMPLETIME_39CYCLES_5     ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!<  ADC sampling time 39.5 CYCLES */
-#define ADC_SAMPLETIME_79CYCLES_5     ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!<  ADC sampling time 79.5 CYCLES */
-#define ADC_SAMPLETIME_160CYCLES_5    (ADC_SMPR_SMPR)                       /*!<  ADC sampling time 160.5 CYCLES */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Scan_mode ADC Scan mode
-  * @{
-  */
-/* Note: Scan mode values must be compatible with other STM32 devices having  */
-/*       a configurable sequencer.                                            */
-/*       Scan direction setting values are defined by taking in account       */
-/*       already defined values for other STM32 devices:                      */
-/*         ADC_SCAN_DISABLE         (0x00000000U)                             */
-/*         ADC_SCAN_ENABLE          (0x00000001U)                             */
-/*       Scan direction forward is considered as default setting equivalent   */
-/*       to scan enable.                                                      */
-/*       Scan direction backward is considered as additional setting.         */
-/*       In case of migration from another STM32 device, the user will be     */
-/*       warned of change of setting choices with assert check.               */
-#define ADC_SCAN_DIRECTION_FORWARD        (0x00000001U)        /*!< Scan direction forward: from channel 0 to channel 18 */
-#define ADC_SCAN_DIRECTION_BACKWARD       (0x00000002U)        /*!< Scan direction backward: from channel 18 to channel 0 */
-
-#define ADC_SCAN_ENABLE         ADC_SCAN_DIRECTION_FORWARD             /* For compatibility with other STM32 devices */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio
-  * @{
-  */
-
-#define ADC_OVERSAMPLING_RATIO_2                    (0x00000000U)  /*!<  ADC Oversampling ratio 2x */
-#define ADC_OVERSAMPLING_RATIO_4                    (0x00000004U)  /*!<  ADC Oversampling ratio 4x */
-#define ADC_OVERSAMPLING_RATIO_8                    (0x00000008U)  /*!<  ADC Oversampling ratio 8x */
-#define ADC_OVERSAMPLING_RATIO_16                   (0x0000000CU)  /*!<  ADC Oversampling ratio 16x */
-#define ADC_OVERSAMPLING_RATIO_32                   (0x00000010U)  /*!<  ADC Oversampling ratio 32x */
-#define ADC_OVERSAMPLING_RATIO_64                   (0x00000014U)  /*!<  ADC Oversampling ratio 64x */
-#define ADC_OVERSAMPLING_RATIO_128                  (0x00000018U)  /*!<  ADC Oversampling ratio 128x */
-#define ADC_OVERSAMPLING_RATIO_256                  (0x0000001CU)  /*!<  ADC Oversampling ratio 256x */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift
-  * @{
-  */
-#define ADC_RIGHTBITSHIFT_NONE                       (0x00000000U)  /*!<  ADC No bit shift for oversampling */
-#define ADC_RIGHTBITSHIFT_1                          (0x00000020U)  /*!<  ADC 1 bit shift for oversampling */
-#define ADC_RIGHTBITSHIFT_2                          (0x00000040U)  /*!<  ADC 2 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_3                          (0x00000060U)  /*!<  ADC 3 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_4                          (0x00000080U)  /*!<  ADC 4 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_5                          (0x000000A0U)  /*!<  ADC 5 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_6                          (0x000000C0U)  /*!<  ADC 6 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_7                          (0x000000E0U)  /*!<  ADC 7 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_8                          (0x00000100U)  /*!<  ADC 8 bits shift for oversampling */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode
-  * @{
-  */
-#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER            (0x00000000U)  /*!<  ADC No bit shift for oversampling */
-#define ADC_TRIGGEREDMODE_MULTI_TRIGGER             (0x00000200U)  /*!<  ADC No bit shift for oversampling */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
-  * @{
-  */ 
-#define ADC_ANALOGWATCHDOG_NONE                     (0x00000000U)
-#define ADC_ANALOGWATCHDOG_SINGLE_REG               ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
-#define ADC_ANALOGWATCHDOG_ALL_REG                  ( ADC_CFGR1_AWDEN)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_conversion_type ADC Conversion Group
-  * @{
-  */ 
-#define ADC_REGULAR_GROUP                         ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))                                              
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Event_type ADC Event
-  * @{
-  */
-#define ADC_AWD_EVENT              (ADC_FLAG_AWD)
-#define ADC_OVR_EVENT              (ADC_FLAG_OVR)
-/**
-  * @}
-  */
-  
-/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
-  * @{
-  */
-#define ADC_IT_RDY           ADC_IER_ADRDYIE     /*!< ADC Ready (ADRDY) interrupt source */
-#define ADC_IT_EOSMP         ADC_IER_EOSMPIE     /*!< ADC End of Sampling interrupt source */
-#define ADC_IT_EOC           ADC_IER_EOCIE       /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IT_EOS           ADC_IER_EOSEQIE     /*!< ADC End of Regular sequence of Conversions interrupt source */
-#define ADC_IT_OVR           ADC_IER_OVRIE       /*!< ADC overrun interrupt source */
-#define ADC_IT_AWD           ADC_IER_AWDIE       /*!< ADC Analog watchdog 1 interrupt source */
-#define ADC_IT_EOCAL         ADC_IER_EOCALIE     /*!< ADC End of Calibration interrupt source */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_flags_definition ADC flags definition
-  * @{
-  */
-#define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
-#define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
-#define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
-#define ADC_FLAG_EOS           ADC_ISR_EOSEQ    /*!< ADC End of Regular sequence of Conversions flag */
-#define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
-#define ADC_FLAG_AWD           ADC_ISR_AWD      /*!< ADC Analog watchdog flag */
-#define ADC_FLAG_EOCAL         ADC_ISR_EOCAL    /*!< ADC Enf Of Calibration flag */
-
-
-#define ADC_FLAG_ALL    (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS |  \
-                         ADC_FLAG_OVR | ADC_FLAG_AWD   | ADC_FLAG_EOCAL)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
-  * @{
-  */
-/** @brief Reset ADC handle state
-  * @param  __HANDLE__ ADC handle
-  * @retval None
-  */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
-  do{                                                                          \
-     (__HANDLE__)->State = HAL_ADC_STATE_RESET;                               \
-     (__HANDLE__)->MspInitCallback = NULL;                                     \
-     (__HANDLE__)->MspDeInitCallback = NULL;                                   \
-    } while(0)
-#else
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-#endif
-
-/**
-  * @brief Enable the ADC peripheral
-  * @param __HANDLE__ ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
-
-/**
-  * @brief Verification of hardware constraints before ADC can be enabled
-  * @param __HANDLE__ ADC handle
-  * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
-  */
-#define ADC_ENABLING_CONDITIONS(__HANDLE__)           \
-       (( ( ((__HANDLE__)->Instance->CR) &                  \
-            (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | \
-             ADC_CR_ADDIS | ADC_CR_ADEN )                   \
-           ) == RESET                                       \
-        ) ? SET : RESET)
-
-/**
-  * @brief Disable the ADC peripheral
-  * @param __HANDLE__ ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE(__HANDLE__)                                          \
-  do{                                                                          \
-         (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS;                           \
-          __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
-  } while(0)
-    
-/**
-  * @brief Verification of hardware constraints before ADC can be disabled
-  * @param __HANDLE__ ADC handle
-  * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
-  */
-#define ADC_DISABLING_CONDITIONS(__HANDLE__)                             \
-       (( ( ((__HANDLE__)->Instance->CR) &                                     \
-            (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN   \
-        ) ? SET : RESET)
-         
-/**
-  * @brief Verification of ADC state: enabled or disabled
-  * @param __HANDLE__ ADC handle
-  * @retval SET (ADC enabled) or RESET (ADC disabled)
-  */
-#define ADC_IS_ENABLE(__HANDLE__)                                                    \
-       (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
-          ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
-        ) ? SET : RESET)
-         
-/**
-  * @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution.
-  * @param __HANDLE__ ADC handle
-  * @retval None
-  */
-#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
-/**
-  * @brief Test if conversion trigger of regular group is software start
-  *        or external trigger.
-  * @param __HANDLE__ ADC handle
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
-  (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
-
-
-
-/**
-  * @brief Check if no conversion on going on regular group
-  * @param __HANDLE__ ADC handle
-  * @retval SET (conversion is on going) or RESET (no conversion is on going)
-  */
-#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                          \
-  (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET                  \
-  ) ? RESET : SET)
-
-/**
-  * @brief Enable ADC continuous conversion mode.
-  * @param _CONTINUOUS_MODE_ Continuous mode.
-  * @retval None
-  */
-#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
-
-/**
-  * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
-  * @param _SCAN_MODE_ Scan conversion mode.
-  * @retval None
-  */
-#define ADC_SCANDIR(_SCAN_MODE_)                                   \
-  ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD)                           \
-    )? (ADC_CFGR1_SCANDIR) : (0x00000000U)                                      \
-  )
-
-/**
-  * @brief Configures the number of discontinuous conversions for the regular group channels.
-  * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions.
-  * @retval None
-  */
-#define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
-
-/**
-  * @brief Enable the ADC DMA continuous request.
-  * @param _DMAContReq_MODE_ DMA continuous request mode.
-  * @retval None
-  */
-#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U)
-
-/**
-  * @brief Enable the ADC Auto Delay.
-  * @param _AutoDelay_ Auto delay bit enable or disable.
-  * @retval None
-  */
-#define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U)
-
-/**
-  * @brief Enable the ADC LowPowerAutoPowerOff.
-  * @param _AUTOFF_ AutoOff bit enable or disable.
-  * @retval None
-  */
-#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U)
-
-/**
-  * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
-  * @param _Threshold_ Threshold value
-  * @retval None
-  */
-#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
-
-/**
-  * @brief Enable the ADC Low Frequency mode.
-  * @param _LOW_FREQUENCY_MODE_ Low Frequency mode.
-  * @retval None
-  */
-#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U)
-
-/**
-  * @brief Shift the offset in function of the selected ADC resolution. 
-  *        Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
-  *        If resolution 12 bits, no shift.
-  *        If resolution 10 bits, shift of 2 ranks on the right.
-  *        If resolution 8 bits, shift of 4 ranks on the right.
-  *        If resolution 6 bits, shift of 6 ranks on the right.
-  *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
-  * @param __HANDLE__ ADC handle.
-  * @param _Offset_ Value to be shifted
-  * @retval None
-  */
-#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
-        ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U))
-
-/**
-  * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
-  *        Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0
-  *        If resolution 12 bits, no shift.
-  *        If resolution 10 bits, shift of 2 ranks on the right.
-  *        If resolution 8 bits, shift of 4 ranks on the right.
-  *        If resolution 6 bits, shift of 6 ranks on the right.
-  *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
-  * @param __HANDLE__ ADC handle.
-  * @param _Threshold_ Value to be shifted
-  * @retval None
-  */
-#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
-        ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
-
-/**
-  * @brief Shift the value on the left, less significant are set to 0. 
-  * @param _Value_ Value to be shifted
-  * @param _Shift_ Number of shift to be done
-  * @retval None
-  */
-#define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_))
-
-
-/**
-  * @brief Enable the ADC end of conversion interrupt.
-  * @param __HANDLE__ ADC handle.
-  * @param __INTERRUPT__ ADC Interrupt.
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)  \
-  (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
-  * @brief Disable the ADC end of conversion interrupt.
-  * @param __HANDLE__ ADC handle.
-  * @param __INTERRUPT__ ADC interrupt.
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
-  (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
-  * @param __HANDLE__ ADC handle
-  * @param __INTERRUPT__ ADC interrupt source to check
-  *            @arg ...
-  *            @arg ...
-  * @retval State of interruption (TRUE or FALSE)
-  */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
-  (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief Clear the ADC's pending flags
-  * @param __HANDLE__ ADC handle.
-  * @param __FLAG__ ADC flag.
-  * @retval None
-  */
-/* Note: bit cleared bit by writing 1 */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-  (((__HANDLE__)->Instance->ISR) = (__FLAG__))
-
-/**
-  * @brief Get the selected ADC's flag status.
-  * @param __HANDLE__ ADC handle.
-  * @param __FLAG__ ADC flag.
-  * @retval None
-  */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
-  ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
-
-
-/**
-  * @brief Simultaneously clears and sets specific bits of the handle State
-  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
-  *        the first parameter is the ADC handle State, the second parameter is the
-  *        bit field to clear, the third and last parameter is the bit field to set.
-  * @retval None
-  */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
-  * @brief Clear ADC error code (set it to error code: "no error")
-  * @param __HANDLE__ ADC handle
-  * @retval None
-  */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
-  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-
-
-/**
-  * @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler
-  * @param __HANDLE__ ADC handle
-  * @retval None
-  */
-
-#define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__)                                       \
-  do{                                                                               \
-      if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) ||  \
-          (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) ||  \
-          (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4))    \
-      {                                                                             \
-        (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE);                       \
-        (__HANDLE__)->Instance->CFGR2 |=  (__HANDLE__)->Init.ClockPrescaler;        \
-      }                                                                             \
-      else                                                                          \
-      {                                                                             \
-        /* CKMOD bits must be reset */                                              \
-        (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE);                       \
-        ADC->CCR &= ~(ADC_CCR_PRESC);                                               \
-        ADC->CCR |=  (__HANDLE__)->Init.ClockPrescaler;                             \
-      }                                                                             \
-  } while(0)
-
-
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1  ) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2  ) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4  ) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6  ) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8  ) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
-                                       ((RESOLUTION) == ADC_RESOLUTION_10B) || \
-                                       ((RESOLUTION) == ADC_RESOLUTION_8B) || \
-                                       ((RESOLUTION) == ADC_RESOLUTION_6B))
-
-#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
-                                                ((RESOLUTION) == ADC_RESOLUTION_6B))
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
-                                  ((ALIGN) == ADC_DATAALIGN_LEFT))
-
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
-
-#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)   || \
-                                             ((EOC_SELECTION) == ADC_EOC_SEQ_CONV))
-
-#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
-                             ((OVR) == ADC_OVR_DATA_OVERWRITTEN))
-
-#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
-                               ((WATCHDOG) == ADC_RANK_NONE))
-
-#if defined (ADC_CHANNEL_VLCD)
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
-                                 ((CHANNEL) == ADC_CHANNEL_VREFINT)     || \
-                                 ((CHANNEL) == ADC_CHANNEL_VLCD))
-#elif defined (ADC_CHANNEL_TEMPSENSOR)
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
-                                 ((CHANNEL) == ADC_CHANNEL_VREFINT))
-#else
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_VREFINT))
-#endif
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5   ) || \
-                                  ((TIME) == ADC_SAMPLETIME_3CYCLES_5  ) || \
-                                  ((TIME) == ADC_SAMPLETIME_7CYCLES_5  ) || \
-                                  ((TIME) == ADC_SAMPLETIME_12CYCLES_5 ) || \
-                                  ((TIME) == ADC_SAMPLETIME_19CYCLES_5 ) || \
-                                  ((TIME) == ADC_SAMPLETIME_39CYCLES_5 ) || \
-                                  ((TIME) == ADC_SAMPLETIME_79CYCLES_5 ) || \
-                                  ((TIME) == ADC_SAMPLETIME_160CYCLES_5))
-
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
-                                     ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
-
-#define IS_ADC_OVERSAMPLING_RATIO(RATIO)          (((RATIO) == ADC_OVERSAMPLING_RATIO_2   ) || \
-                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_4   ) || \
-                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_8   ) || \
-                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_16  ) || \
-                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_32  ) || \
-                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_64  ) || \
-                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \
-                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
-
-#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT)               (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \
-                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_1   ) || \
-                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_2   ) || \
-                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_3   ) || \
-                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_4   ) || \
-                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_5   ) || \
-                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_6   ) || \
-                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_7   ) || \
-                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_8   ))
-
-#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE)     (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
-                                                      ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
-
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)     (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE      )   || \
-                                                   ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)   || \
-                                                   ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG   ))
-
-#define IS_ADC_CONVERSION_GROUP(CONVERSION)   ((CONVERSION) == ADC_REGULAR_GROUP)
-
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
-                                  ((EVENT) == ADC_OVR_EVENT))
-
-
-/** @defgroup ADC_range_verification ADC Range Verification
-  * in function of ADC resolution selected (12, 10, 8 or 6 bits)
-  * @{
-  */
-#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                           \
-   ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \
-    (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \
-    (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= (0x00FFU))) || \
-    (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= (0x003FU))))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
-  * @{
-  */
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Include ADC HAL Extended module */
-#include "stm32l0xx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group1
-  * @brief    Initialization and Configuration functions
-  * @{
-  */
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef    HAL_ADC_Init(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef    HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void                 HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void                 HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group2
-  * @brief    IO operation functions
-  * @{
-  */
-/* IO operation functions  *****************************************************/
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef    HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef    HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef    HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef    HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef    HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef    HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-
-/* Non-blocking mode: DMA */
-HAL_StatusTypeDef    HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef    HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t             HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
-void                 HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-void                 HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void                 HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void                 HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void                 HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions 
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef    HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef    HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
-/**
-  * @}
-  */
-
-/* Peripheral State functions *************************************************/
-/** @addtogroup ADC_Exported_Functions_Group4
-  * @{
-  */
-uint32_t             HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t             HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /*__STM32L0xx_HAL_ADC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h
deleted file mode 100644
index 0dd8cce5b0..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_adc_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of ADC HAL extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_ADC_EX_H
-#define __STM32L0xx_HAL_ADC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADCEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup ADCEx_Channel_Mode ADC Single Ended
-  * @{
-  */
-#define ADC_SINGLE_ENDED                        0x00000000U   /* dummy value */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_regular_external_trigger_source ADC External Trigger Source
-  * @{
-  */
-#define ADC_EXTERNALTRIGCONV_T6_TRGO            (0x00000000U)
-#define ADC_EXTERNALTRIGCONV_T21_CC2            (ADC_CFGR1_EXTSEL_0)
-#define ADC_EXTERNALTRIGCONV_T2_TRGO            (ADC_CFGR1_EXTSEL_1)
-#define ADC_EXTERNALTRIGCONV_T2_CC4             (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)
-#define ADC_EXTERNALTRIGCONV_T22_TRGO           (ADC_CFGR1_EXTSEL_2)
-#define ADC_EXTERNALTRIGCONV_T3_TRGO            (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1)
-#define ADC_EXTERNALTRIGCONV_EXT_IT11           (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)
-#define ADC_SOFTWARE_START                      (ADC_CFGR1_EXTSEL + 1U)
-
-/* ADC group regular external trigger TIM21_TRGO available only on            */
-/* STM32L0 devices categories: Cat.2, Cat.3, Cat.5                            */
-#if defined (STM32L031xx) || defined (STM32L041xx) || \
-    defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || \
-    defined (STM32L062xx) || defined (STM32L063xx) || \
-    defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
-    defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) || \
-    defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xB)
-#define ADC_EXTERNALTRIGCONV_T21_TRGO           (ADC_EXTERNALTRIGCONV_T22_TRGO)
-#endif
-
-/* ADC group regular external trigger TIM2_CC3 available only on              */
-/* STM32L0 devices categories: Cat.1, Cat.2, Cat.5                            */
-#if defined (STM32L011xx) || defined (STM32L021xx) || \
-    defined (STM32L031xx) || defined (STM32L041xx) || \
-    defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
-    defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) || \
-    defined (STM32L010x4) || defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xB)
-#define ADC_EXTERNALTRIGCONV_T2_CC3             (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0)
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_SYSCFG_internal_paths_flags_definition ADC SYSCFG internal paths Flags Definition
-  * @{
-  */
-#define ADC_FLAG_SENSOR         SYSCFG_CFGR3_VREFINT_RDYF
-#define ADC_FLAG_VREFINT        SYSCFG_VREFINT_ADC_RDYF
-/**
-  * @}
-  */
-   
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Macros ADCEx Private Macros
-  * @{
-  */
-
-#define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF)   ((SING_DIFF) == ADC_SINGLE_ENDED)
-
-/** @defgroup ADCEx_calibration_factor_length_verification ADC Calibration Factor Length Verification
-  * @{
-  */ 
-/**
-  * @brief Calibration factor length verification (7 bits maximum)
-  * @param _Calibration_Factor_: Calibration factor value
-  * @retval None
-  */
-#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= (0x7FU))
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_External_trigger_Source ADC External Trigger Source
-  * @{
-  */
-#if defined (STM32L031xx) || defined (STM32L041xx) || \
-    defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
-    defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) || \
-    defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xB)
-#define IS_ADC_EXTTRIG(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO  ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2  ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO  ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4   ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T21_TRGO ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC3   ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T3_TRGO  ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ) || \
-                              ((CONV) == ADC_SOFTWARE_START))
-#elif defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
-#define IS_ADC_EXTTRIG(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO  ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2  ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO  ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4   ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC3   ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T3_TRGO  ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ) || \
-                              ((CONV) == ADC_SOFTWARE_START))
-#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || \
-      defined (STM32L062xx) || defined (STM32L063xx)
-#define IS_ADC_EXTTRIG(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO  ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2  ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO  ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4   ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T21_TRGO ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_T3_TRGO  ) || \
-                              ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ) || \
-                              ((CONV) == ADC_SOFTWARE_START))
-#endif
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADCEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADCEx_Exported_Functions_Group1
-  * @{
-  */
-/* IO operation functions *****************************************************/
-
-/* ADC calibration */
-HAL_StatusTypeDef   HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
-uint32_t            HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
-HAL_StatusTypeDef   HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
-
-/* ADC VrefInt and Temperature sensor functions specific to this STM32 serie */
-HAL_StatusTypeDef   HAL_ADCEx_EnableVREFINT(void);
-void                HAL_ADCEx_DisableVREFINT(void);
-HAL_StatusTypeDef   HAL_ADCEx_EnableVREFINTTempSensor(void);
-void                HAL_ADCEx_DisableVREFINTTempSensor(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32L0xx_HAL_ADC_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp.h
deleted file mode 100644
index b13d795bcb..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp.h
+++ /dev/null
@@ -1,727 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_comp.h
-  * @author  MCD Application Team
-  * @brief   Header file of COMP HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_COMP_H
-#define __STM32L0xx_HAL_COMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup COMP
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup COMP_Exported_Types COMP Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  COMP Init structure definition  
-  */
-typedef struct
-{
-
-  uint32_t WindowMode;         /*!< Set window mode of a pair of comparators instances
-                                    (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
-                                    Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
-                                    This parameter can be a value of @ref COMP_WindowMode */
-
-  uint32_t Mode;               /*!< Set comparator operating mode to adjust power and speed.
-                                    Note: For the characteritics of comparator power modes
-                                          (propagation delay and power consumption), refer to device datasheet.
-                                    This parameter can be a value of @ref COMP_PowerMode */
-
-  uint32_t NonInvertingInput;  /*!< Set comparator input plus (non-inverting input).
-                                    This parameter can be a value of @ref COMP_InputPlus */
-
-  uint32_t InvertingInput;     /*!< Set comparator input minus (inverting input).
-                                    This parameter can be a value of @ref COMP_InputMinus */
-
-  uint32_t OutputPol;          /*!< Set comparator output polarity.
-                                    This parameter can be a value of @ref COMP_OutputPolarity */
-
-  uint32_t LPTIMConnection;    /*!< Set comparator output connection to LPTIM peripheral.
-                                    This parameter can be a value of @ref COMP_LPTIMConnection */
-
-  uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
-                                    This parameter can be a value of @ref COMP_EXTI_TriggerMode */
-
-}COMP_InitTypeDef;
-
-/**
-  * @brief  HAL COMP state machine: HAL COMP states definition
-  */
-#define COMP_STATE_BITFIELD_LOCK  (0x10U)
-typedef enum
-{
-  HAL_COMP_STATE_RESET             = 0x00U,                                             /*!< COMP not yet initialized                             */
-  HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
-  HAL_COMP_STATE_READY             = 0x01U,                                             /*!< COMP initialized and ready for use                   */
-  HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
-  HAL_COMP_STATE_BUSY              = 0x02U,                                             /*!< COMP is running                                      */
-  HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
-}HAL_COMP_StateTypeDef;
-
-/** 
-  * @brief  COMP Handle Structure definition
-  */
-typedef struct __COMP_HandleTypeDef
-{
-  COMP_TypeDef       *Instance;       /*!< Register base address    */
-  COMP_InitTypeDef   Init;            /*!< COMP required parameters */
-  HAL_LockTypeDef    Lock;            /*!< Locking object           */
-  __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
-  __IO uint32_t      ErrorCode;       /*!< COMP Error code */
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-  void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP trigger callback */
-  void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP Msp Init callback */
-  void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-} COMP_HandleTypeDef;
-
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL COMP Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_COMP_TRIGGER_CB_ID                = 0x00U,  /*!< COMP trigger callback ID */
-  HAL_COMP_MSPINIT_CB_ID                = 0x01U,  /*!< COMP Msp Init callback ID */
-  HAL_COMP_MSPDEINIT_CB_ID              = 0x02U   /*!< COMP Msp DeInit callback ID */
-} HAL_COMP_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL COMP Callback pointer definition
-  */
-typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
-
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup COMP_Exported_Constants COMP Exported Constants
-  * @{
-  */
-
-/** @defgroup COMP_Error_Code COMP Error Code
-  * @{
-  */
-#define HAL_COMP_ERROR_NONE             (0x00U)   /*!< No error */
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01U)   /*!< Invalid Callback error */
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_WindowMode COMP Window Mode
-  * @{
-  */
-#define COMP_WINDOWMODE_DISABLE                 (0x00000000U)          /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
-#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_COMP1WM)     /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_PowerMode COMP power mode
-  * @{
-  */
-/* Note: For the characteritics of comparator power modes                     */
-/*       (propagation delay and power consumption),                           */
-/*       refer to device datasheet.                                           */
-#define COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_COMP2SPEED)       /*!< COMP power mode to low power (indicated as "high speed" in reference manual) (only for COMP instance: COMP2) */
-#define COMP_POWERMODE_ULTRALOWPOWER   (0x00000000U)               /*!< COMP power mode to ultra low power (indicated as "low speed" in reference manual) (only for COMP instance: COMP2) */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
-  * @{
-  */
-#define COMP_INPUT_PLUS_IO1            (0x00000000U)                                      /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA3 for COMP2) */
-#define COMP_INPUT_PLUS_IO2            (COMP_CSR_COMP2INPSEL_0)                           /*!< Comparator input plus connected to IO2 (pin PB4 for COMP2) (only for COMP instance: COMP2) */
-#define COMP_INPUT_PLUS_IO3            (COMP_CSR_COMP2INPSEL_1)                           /*!< Comparator input plus connected to IO3 (pin PA5 for COMP2) (only for COMP instance: COMP2) */
-#define COMP_INPUT_PLUS_IO4            (COMP_CSR_COMP2INPSEL_0 | COMP_CSR_COMP2INPSEL_1)  /*!< Comparator input plus connected to IO4 (pin PB6 for COMP2) (only for COMP instance: COMP2) */
-#define COMP_INPUT_PLUS_IO5            (COMP_CSR_COMP2INPSEL_2)                           /*!< Comparator input plus connected to IO5 (pin PB7 for COMP2) (only for COMP instance: COMP2) */
-#if defined (STM32L011xx) || defined (STM32L021xx)
-#define COMP_INPUT_PLUS_IO6            (COMP_CSR_COMP2INPSEL_2 | COMP_CSR_COMP2INPSEL_0)  /*!< Comparator input plus connected to IO6 (pin PA7 for COMP2) (only for COMP instance: COMP2) (Available only on devices STM32L0 category 1) */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup COMP_InputMinus COMP input minus (inverting input)
-  * @{
-  */
-#define COMP_INPUT_MINUS_1_4VREFINT    (COMP_CSR_COMP2INNSEL_2                                                  ) /*!< Comparator input minus connected to 1/4 VREFINT (only for COMP instance: COMP2) */
-#define COMP_INPUT_MINUS_1_2VREFINT    (COMP_CSR_COMP2INNSEL_2 |                          COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to 1/2 VREFINT (only for COMP instance: COMP2) */
-#define COMP_INPUT_MINUS_3_4VREFINT    (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_1                         ) /*!< Comparator input minus connected to 3/4 VREFINT (only for COMP instance: COMP2) */
-#define COMP_INPUT_MINUS_VREFINT       (0x00000000U)                                                              /*!< Comparator input minus connected to VrefInt */
-#define COMP_INPUT_MINUS_DAC1_CH1      (                         COMP_CSR_COMP2INNSEL_1                         ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
-#define COMP_INPUT_MINUS_DAC1_CH2      (                         COMP_CSR_COMP2INNSEL_1 | COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
-#define COMP_INPUT_MINUS_IO1           (                                                  COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2) */
-#define COMP_INPUT_MINUS_IO2           (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_1 | COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to IO2 (pin PB3 for COMP2) (only for COMP instance: COMP2) */
-/**
-  * @}
-  */
-
-
-/** @defgroup COMP_LPTIMConnection COMP Low power timer connection definition
-  * @{
-  */
-
-#define COMP_LPTIMCONNECTION_DISABLED               (0x00000000U)    /*!< COMPx signal is gated */
-#define COMP_LPTIMCONNECTION_IN1_ENABLED            (0x00000001U)    /*!< COMPx signal is connected to LPTIM input 1 */
-#define COMP_LPTIMCONNECTION_IN2_ENABLED            (0x00000002U)    /*!< COMPx signal is connected to LPTIM input 2 */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_OutputPolarity COMP output Polarity
-  * @{
-  */
-#define COMP_OUTPUTPOL_NONINVERTED             (0x00000000U)                /*!< COMP output on GPIO isn't inverted */
-#define COMP_OUTPUTPOL_INVERTED                COMP_CSR_COMPxPOLARITY       /*!< COMP output on GPIO is inverted */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_OutputLevel COMP Output Level
-  * @{
-  */
-/* Note: Comparator output level values are fixed to "0" and "1",             */
-/* corresponding COMP register bit is managed by HAL function to match        */
-/* with these values (independently of bit position in register).             */
-
-/* When output polarity is not inverted, comparator output is low when
-   the input plus is at a lower voltage than the input minus */
-#define COMP_OUTPUT_LEVEL_LOW              (0x00000000U)
-/* When output polarity is not inverted, comparator output is high when
-   the input plus is at a higher voltage than the input minus */
-#define COMP_OUTPUT_LEVEL_HIGH             (0x00000001U)
-/**
-  * @}
-  */
-
-/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
-  * @{
-  */
-#define COMP_TRIGGERMODE_NONE                 (0x00000000U)                                    /*!< Comparator output triggering no External Interrupt Line */
-#define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
-#define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
-#define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
-#define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
-#define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
-#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup COMP_Exported_Macros COMP Exported Macros
-  * @{
-  */
-
-/** @defgroup COMP_Handle_Management  COMP Handle Management
-  * @{
-  */
-
-/** @brief  Reset COMP handle state.
-  * @param  __HANDLE__  COMP handle
-  * @retval None
-  */
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
-                                                     (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
-                                                     (__HANDLE__)->MspInitCallback = NULL;            \
-                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                    } while(0)
-#else
-#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
-#endif
-
-/**
-  * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
-  * @param __HANDLE__ COMP handle
-  * @retval None
-  */
-#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE) 
-
-/**
-  * @brief  Enable the specified comparator.
-  * @param  __HANDLE__  COMP handle
-  * @retval None
-  */
-#define __HAL_COMP_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN)
-
-/**
-  * @brief  Disable the specified comparator.
-  * @param  __HANDLE__  COMP handle
-  * @retval None
-  */
-#define __HAL_COMP_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN)
-
-/**
-  * @brief  Lock the specified comparator configuration.
-  * @note   Using this macro induce HAL COMP handle state machine being no
-  *         more in line with COMP instance state.
-  *         To keep HAL COMP handle state machine updated, it is recommended
-  *         to use function "HAL_COMP_Lock')".
-  * @param  __HANDLE__  COMP handle
-  * @retval None
-  */
-#define __HAL_COMP_LOCK(__HANDLE__)                SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxLOCK)
-
-/**
-  * @brief  Check whether the specified comparator is locked.
-  * @param  __HANDLE__  COMP handle
-  * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
-  */
-#define __HAL_COMP_IS_LOCKED(__HANDLE__)           (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxLOCK) == COMP_CSR_COMPxLOCK)
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Exti_Management  COMP external interrupt line management
-  * @{
-  */
-
-/**
-  * @brief  Enable the COMP1 EXTI line rising edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Disable the COMP1 EXTI line rising edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Enable the COMP1 EXTI line falling edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Disable the COMP1 EXTI line falling edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
-                                                               __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
-                                                               __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
-                                                             } while(0)
-
-/**
-  * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
-                                                               __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
-                                                               __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
-                                                             } while(0)
-
-/**
-  * @brief  Enable the COMP1 EXTI line in interrupt mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Disable the COMP1 EXTI line in interrupt mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Generate a software interrupt on the COMP1 EXTI line.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Enable the COMP1 EXTI line in event mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()           SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Disable the COMP1 EXTI line in event mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Check whether the COMP1 EXTI line flag is set.
-  * @retval RESET or SET
-  */
-#define __HAL_COMP_COMP1_EXTI_GET_FLAG()              READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Clear the COMP1 EXTI flag.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Enable the COMP2 EXTI line rising edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Disable the COMP2 EXTI line rising edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Enable the COMP2 EXTI line falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Disable the COMP2 EXTI line falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
-                                                               __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
-                                                               __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
-                                                             } while(0)
-
-/**
-  * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
-                                                               __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
-                                                               __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
-                                                             } while(0)
-
-/**
-  * @brief  Enable the COMP2 EXTI line in interrupt mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Disable the COMP2 EXTI line in interrupt mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Generate a software interrupt on the COMP2 EXTI line.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Enable the COMP2 EXTI line in event mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()           SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Disable the COMP2 EXTI line in event mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Check whether the COMP2 EXTI line flag is set.
-  * @retval RESET or SET
-  */
-#define __HAL_COMP_COMP2_EXTI_GET_FLAG()              READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Clear the COMP2 EXTI flag.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Private types -------------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup COMP_Private_Constants COMP Private Constants
-  * @{
-  */
-/** @defgroup COMP_ExtiLine COMP EXTI Lines
-  * @{
-  */
-#define COMP_EXTI_LINE_COMP1           (EXTI_IMR_IM21)  /*!< EXTI line 21 connected to COMP1 output */
-#define COMP_EXTI_LINE_COMP2           (EXTI_IMR_IM22)  /*!< EXTI line 22 connected to COMP2 output */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_ExtiLine COMP EXTI Lines
-  * @{
-  */
-#define COMP_EXTI_IT                        (0x01U)  /*!< EXTI line event with interruption */
-#define COMP_EXTI_EVENT                     (0x02U)  /*!< EXTI line event only (without interruption) */
-#define COMP_EXTI_RISING                    (0x10U)  /*!< EXTI line event on rising edge */
-#define COMP_EXTI_FALLING                   (0x20U)  /*!< EXTI line event on falling edge */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup COMP_Private_Macros COMP Private Macros
-  * @{
-  */
-
-/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators 
-  * @{
-  */
-/**
-  * @brief  Get the specified EXTI line for a comparator instance.
-  * @param  __INSTANCE__  specifies the COMP instance.
-  * @retval value of @ref COMP_ExtiLine
-  */
-#define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ?                 \
-                                             COMP_EXTI_LINE_COMP1 : COMP_EXTI_LINE_COMP2)
-/**
-  * @}
-  */
-
-/** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters
-  * @{
-  */
-#define IS_COMP_WINDOWMODE(__WINDOWMODE__)  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
-                                             ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )
-
-#define IS_COMP_POWERMODE(__POWERMODE__)    (((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
-                                             ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )
-
-#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
-
-#if defined (STM32L011xx) || defined (STM32L021xx)
-#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)                  \
-  (((__COMP_INSTANCE__) == COMP1)                                              \
-    ? (                                                                        \
-       (__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1                                 \
-      )                                                                        \
-      :                                                                        \
-      (                                                                        \
-          ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1)                            \
-       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2)                            \
-       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3)                            \
-       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO4)                            \
-       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO5)                            \
-       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO6)                            \
-      )                                                                        \
-  )
-#else
-#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)                  \
-  (((__COMP_INSTANCE__) == COMP1)                                              \
-    ? (                                                                        \
-       (__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1                                 \
-      )                                                                        \
-      :                                                                        \
-      (                                                                        \
-          ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1)                            \
-       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2)                            \
-       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3)                            \
-       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO4)                            \
-       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO5)                            \
-      )                                                                        \
-  )
-#endif
-
-#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)                \
-  (((__COMP_INSTANCE__) == COMP1)                                              \
-    ? (                                                                        \
-          ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)                      \
-       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)                     \
-       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)                     \
-       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)                          \
-      )                                                                        \
-      :                                                                        \
-      (                                                                        \
-          ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)                   \
-       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)                   \
-       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)                   \
-       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)                      \
-       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)                     \
-       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)                     \
-       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)                          \
-       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)                          \
-      )                                                                        \
-  )
-
-#define IS_COMP1_LPTIMCONNECTION(LPTIMCONNECTION)   (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \
-                                                     ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN1_ENABLED))
-
-#define IS_COMP2_LPTIMCONNECTION(LPTIMCONNECTION)   (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \
-                                                     ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN1_ENABLED) || \
-                                                     ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN2_ENABLED))
-
-#define IS_COMP2_LPTIMCONNECTION_RESTRICTED(LPTIMCONNECTION)   (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \
-                                                                ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN1_ENABLED))
-
-#define IS_COMP_OUTPUTPOL(POL)  (((POL) == COMP_OUTPUTPOL_NONINVERTED)  || \
-                                 ((POL) == COMP_OUTPUTPOL_INVERTED))
-
-#define IS_COMP_TRIGGERMODE(__TRIGGERMODE__) (((__TRIGGERMODE__) == COMP_TRIGGERMODE_NONE)                 || \
-                                              ((__TRIGGERMODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
-                                              ((__TRIGGERMODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
-                                              ((__TRIGGERMODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
-                                              ((__TRIGGERMODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
-                                              ((__TRIGGERMODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
-                                              ((__TRIGGERMODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING)   )
-
-
-#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
-                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Include COMP HAL Extended module */
-#include "stm32l0xx_hal_comp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup COMP_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup COMP_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
-void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
-void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
-
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* IO operation functions  *****************************************************/
-/** @addtogroup COMP_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
-void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup COMP_Exported_Functions_Group3
-  * @{
-  */
-HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
-uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
-/* Callback in interrupt mode */
-void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  **************************************************/
-/** @addtogroup COMP_Exported_Functions_Group4
-  * @{
-  */
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
-uint32_t              HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_COMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp_ex.h
deleted file mode 100644
index 179656b725..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp_ex.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_comp_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of COMP HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_COMP_EX_H
-#define __STM32L0xx_HAL_COMP_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !defined(STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup COMPEx COMPEx
-  * @{
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup COMPEx_Exported_Functions COMPEx Exported Functions
-  * @{
-  */
-
-/** @defgroup COMPEx_Exported_Functions_Group1 Extended COMP VREFINT setup functions
- * @{
- */
-/* COMP specific functions to manage VREFINT *************************************/
-void HAL_COMPEx_EnableVREFINT(void);
-void HAL_COMPEx_DisableVREFINT(void);
-   
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* #if !defined(STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_COMP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_conf_template.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_conf_template.h
deleted file mode 100644
index 5c30d3ce1b..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_conf_template.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration template file. 
-  *          This file should be copied to the application folder and renamed
-  *          to stm32l0xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_CONF_H
-#define __STM32L0xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-#define HAL_ADC_MODULE_ENABLED   
-#define HAL_COMP_MODULE_ENABLED 
-#define HAL_CRC_MODULE_ENABLED  
-#define HAL_CRYP_MODULE_ENABLED  
-#define HAL_DAC_MODULE_ENABLED   
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_EXTI_MODULE_ENABLED
-#define HAL_FIREWALL_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED   
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_LCD_MODULE_ENABLED 
-#define HAL_LPTIM_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED  
-#define HAL_RCC_MODULE_ENABLED 
-#define HAL_RNG_MODULE_ENABLED   
-#define HAL_RTC_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED   
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_TSC_MODULE_ENABLED   
-#define HAL_UART_MODULE_ENABLED 
-#define HAL_USART_MODULE_ENABLED 
-#define HAL_IRDA_MODULE_ENABLED 
-#define HAL_SMARTCARD_MODULE_ENABLED 
-#define HAL_SMBUS_MODULE_ENABLED 
-#define HAL_WWDG_MODULE_ENABLED  
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED 
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    (8000000U)         /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    (2097152U)         /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U)        /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator for USB (HSI48) value.
-  */
-#if !defined  (HSI48_VALUE) 
-#define HSI48_VALUE (48000000U)           /*!< Value of the Internal High Speed oscillator for USB in Hz.
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif /* HSI48_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (37000U)                 /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    (32768U)             /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-/**
-  * @brief Time out for LSE start up value in ms.
-  */
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)    /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-   
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((1U<<__NVIC_PRIO_BITS) - 1U)    /*!< tick interrupt priority */            
-#define  USE_RTOS                     0U     
-#define  PREFETCH_ENABLE              1U              
-#define  PREREAD_ENABLE               0U
-#define  BUFFER_CACHE_DISABLE         0U
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-
-/* ################## Register callback feature configuration ############### */
-/**
-  * @brief Set below the peripheral configuration  to "1U" to add the support
-  *        of HAL callback registration/deregistration feature for the HAL
-  *        driver(s). This allows user application to provide specific callback
-  *        functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
-  *        the default weak callback functions (see each stm32l0xx_hal_ppp.h file
-  *        for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
-  *        for each PPP peripheral).
-  */
-#define USE_HAL_ADC_REGISTER_CALLBACKS        0U
-#define USE_HAL_COMP_REGISTER_CALLBACKS       0U
-#define USE_HAL_DAC_REGISTER_CALLBACKS        0U
-#define USE_HAL_I2C_REGISTER_CALLBACKS        0U
-#define USE_HAL_I2S_REGISTER_CALLBACKS        0U
-#define USE_HAL_IRDA_REGISTER_CALLBACKS       0U
-#define USE_HAL_LPTIM_REGISTER_CALLBACKS      0U
-#define USE_HAL_PCD_REGISTER_CALLBACKS        0U
-#define USE_HAL_RNG_REGISTER_CALLBACKS        0U
-#define USE_HAL_RTC_REGISTER_CALLBACKS        0U
-#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U
-#define USE_HAL_SMBUS_REGISTER_CALLBACKS      0U
-#define USE_HAL_SPI_REGISTER_CALLBACKS        0U
-#define USE_HAL_TIM_REGISTER_CALLBACKS        0U
-#define USE_HAL_TSC_REGISTER_CALLBACKS        0U
-#define USE_HAL_UART_REGISTER_CALLBACKS       0U
-#define USE_HAL_USART_REGISTER_CALLBACKS      0U
-#define USE_HAL_WWDG_REGISTER_CALLBACKS       0U
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
- * Activated: CRC code is present inside driver
- * Deactivated: CRC code cleaned from driver
- */
-
-#define USE_SPI_CRC                   1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32l0xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-  
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32l0xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32l0xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32l0xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32l0xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32l0xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32l0xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32l0xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32l0xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32l0xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FIREWALL_MODULE_ENABLED
-  #include "stm32l0xx_hal_firewall.h"
-#endif /* HAL_FIREWALL_MODULE_ENABLED */
- 
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32l0xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l0xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32l0xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l0xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l0xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32l0xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-   
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l0xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32l0xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32l0xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l0xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l0xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
- #include "stm32l0xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l0xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l0xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l0xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l0xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32l0xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l0xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l0xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h
deleted file mode 100644
index 6ab043654a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h
+++ /dev/null
@@ -1,365 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_cortex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CORTEX HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_CORTEX_H
-#define __STM32L0xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX CORTEX
-  * @{
-  */ 
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
-  * @{
-  */
-typedef struct
-{
-  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
-
-  uint8_t                Enable;                /*!< Specifies the status of the region.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
-  uint8_t                Number;                /*!< Specifies the number of the region to protect.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
-
-  uint8_t                Size;                  /*!< Specifies the size of the region to protect.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
-  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
-                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
-  uint8_t                TypeExtField;          /*!< This parameter is NOT used but is kept to keep API unified through all families*/
-
-  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
-  uint8_t                DisableExec;           /*!< Specifies the instruction access status.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
-  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
-  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
-  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
-}MPU_Region_InitTypeDef;
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEx Exported Constants
-  * @{
-  */
-
-
-#define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__)  ((__PRIORITY__) < 0x10U)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x0)
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source
-  * @{
-  */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8    (0x00000000U)
-#define SYSTICK_CLKSOURCE_HCLK         (0x00000004U)
-#define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \
-                                       ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-/**
-  * @}
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
-  * @{
-  */
-#define  MPU_HFNMI_PRIVDEF_NONE      (0x00000000U)
-#define  MPU_HARDFAULT_NMI           (0x00000002U)
-#define  MPU_PRIVILEGED_DEFAULT      (0x00000004U)
-#define  MPU_HFNMI_PRIVDEF           (0x00000006U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
-  * @{
-  */
-#define  MPU_REGION_ENABLE           ((uint8_t)0x01)
-#define  MPU_REGION_DISABLE          ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
-  * @{
-  */
-#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
-#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
-  * @{
-  */
-#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
-  * @{
-  */
-#define  MPU_ACCESS_CACHEABLE        ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_CACHEABLE    ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
-  * @{
-  */
-#define  MPU_ACCESS_BUFFERABLE       ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_BUFFERABLE   ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
-  * @{
-  */
-#define   MPU_REGION_SIZE_32B        ((uint8_t)0x04)
-#define   MPU_REGION_SIZE_64B        ((uint8_t)0x05)
-#define   MPU_REGION_SIZE_128B       ((uint8_t)0x06)
-#define   MPU_REGION_SIZE_256B       ((uint8_t)0x07)
-#define   MPU_REGION_SIZE_512B       ((uint8_t)0x08)
-#define   MPU_REGION_SIZE_1KB        ((uint8_t)0x09)
-#define   MPU_REGION_SIZE_2KB        ((uint8_t)0x0A)
-#define   MPU_REGION_SIZE_4KB        ((uint8_t)0x0B)
-#define   MPU_REGION_SIZE_8KB        ((uint8_t)0x0C)
-#define   MPU_REGION_SIZE_16KB       ((uint8_t)0x0D)
-#define   MPU_REGION_SIZE_32KB       ((uint8_t)0x0E)
-#define   MPU_REGION_SIZE_64KB       ((uint8_t)0x0F)
-#define   MPU_REGION_SIZE_128KB      ((uint8_t)0x10)
-#define   MPU_REGION_SIZE_256KB      ((uint8_t)0x11)
-#define   MPU_REGION_SIZE_512KB      ((uint8_t)0x12)
-#define   MPU_REGION_SIZE_1MB        ((uint8_t)0x13)
-#define   MPU_REGION_SIZE_2MB        ((uint8_t)0x14)
-#define   MPU_REGION_SIZE_4MB        ((uint8_t)0x15)
-#define   MPU_REGION_SIZE_8MB        ((uint8_t)0x16)
-#define   MPU_REGION_SIZE_16MB       ((uint8_t)0x17)
-#define   MPU_REGION_SIZE_32MB       ((uint8_t)0x18)
-#define   MPU_REGION_SIZE_64MB       ((uint8_t)0x19)
-#define   MPU_REGION_SIZE_128MB      ((uint8_t)0x1A)
-#define   MPU_REGION_SIZE_256MB      ((uint8_t)0x1B)
-#define   MPU_REGION_SIZE_512MB      ((uint8_t)0x1C)
-#define   MPU_REGION_SIZE_1GB        ((uint8_t)0x1D)
-#define   MPU_REGION_SIZE_2GB        ((uint8_t)0x1E)
-#define   MPU_REGION_SIZE_4GB        ((uint8_t)0x1F)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
-  * @{
-  */
-#define  MPU_REGION_NO_ACCESS        ((uint8_t)0x00)
-#define  MPU_REGION_PRIV_RW          ((uint8_t)0x01)
-#define  MPU_REGION_PRIV_RW_URO      ((uint8_t)0x02)
-#define  MPU_REGION_FULL_ACCESS      ((uint8_t)0x03)
-#define  MPU_REGION_PRIV_RO          ((uint8_t)0x05)
-#define  MPU_REGION_PRIV_RO_URO      ((uint8_t)0x06)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
-  * @{
-  */
-#define  MPU_REGION_NUMBER0          ((uint8_t)0x00)
-#define  MPU_REGION_NUMBER1          ((uint8_t)0x01)
-#define  MPU_REGION_NUMBER2          ((uint8_t)0x02)
-#define  MPU_REGION_NUMBER3          ((uint8_t)0x03)
-#define  MPU_REGION_NUMBER4          ((uint8_t)0x04)
-#define  MPU_REGION_NUMBER5          ((uint8_t)0x05)
-#define  MPU_REGION_NUMBER6          ((uint8_t)0x06)
-#define  MPU_REGION_NUMBER7          ((uint8_t)0x07)
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-
-/**
-  * @}
-  */  
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-  
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 
- *  @brief    Initialization and Configuration functions
- * @{
-  */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
-  * @}
-  */
-  
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- *  @brief   Cortex control functions
- * @{
- */
- 
-uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-#if (__MPU_PRESENT == 1U)
-void HAL_MPU_Enable(uint32_t MPU_Control);
-void HAL_MPU_Disable(void);
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-  
-  /**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
-                                     ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
-                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
-                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_256B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FFU)
-#endif /* __MPU_PRESENT */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_CORTEX_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc.h
deleted file mode 100644
index 91442483cb..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc.h
+++ /dev/null
@@ -1,345 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_crc.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_CRC_H
-#define STM32L0xx_HAL_CRC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CRC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CRC_Exported_Types CRC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  CRC HAL State Structure definition
-  */
-typedef enum
-{
-  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
-  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
-  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
-  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
-  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
-} HAL_CRC_StateTypeDef;
-
-/**
-  * @brief CRC Init Structure definition
-  */
-typedef struct
-{
-  uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
-                                            If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
-                                            X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
-                                            X^4 + X^2+ X +1.
-                                            In that case, there is no need to set GeneratingPolynomial field.
-                                            If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
-                                            CRCLength fields must be set. */
-
-  uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
-                                           If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
-                                           0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
-                                           otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
-
-  uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
-                                           respectively equal to 7, 8, 16 or 32. This field is written in normal,
-                                           representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
-                                           is written 0x65. No need to specify it if DefaultPolynomialUse is set to
-                                            DEFAULT_POLYNOMIAL_ENABLE.   */
-
-  uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
-                                           Value can be either one of
-                                           @arg @ref CRC_POLYLENGTH_32B                  (32-bit CRC),
-                                           @arg @ref CRC_POLYLENGTH_16B                  (16-bit CRC),
-                                           @arg @ref CRC_POLYLENGTH_8B                   (8-bit CRC),
-                                           @arg @ref CRC_POLYLENGTH_7B                   (7-bit CRC). */
-
-  uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
-                                           is set to DEFAULT_INIT_VALUE_ENABLE.   */
-
-  uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
-                                           Can be either one of the following values
-                                           @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion
-                                           @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D
-                                           becomes 0x58D43CB2
-                                           @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion,
-                                           0x1A2B3C4D becomes 0xD458B23C
-                                           @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D
-                                           becomes 0xB23CD458 */
-
-  uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
-                                            Can be either
-                                            @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion,
-                                            @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted
-                                             into 0x22CC4488 */
-} CRC_InitTypeDef;
-
-/**
-  * @brief  CRC Handle Structure definition
-  */
-typedef struct
-{
-  CRC_TypeDef                 *Instance;   /*!< Register base address        */
-
-  CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
-
-  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
-
-  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
-
-  uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
-                                            Can be either
-                                            @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes
-                                            (8-bit data)
-                                            @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of
-                                            half-words (16-bit data)
-                                            @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words
-                                            (32-bit data)
-
-                                          Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
-                                          error must occur if InputBufferFormat is not one of the three values listed
-                                          above  */
-} CRC_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Constants CRC Exported Constants
-  * @{
-  */
-
-/** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
-  * @{
-  */
-#define DEFAULT_CRC32_POLY      0x04C11DB7U  /*!<  X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
-  * @{
-  */
-#define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU  /*!< Initial CRC default value */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
-  * @{
-  */
-#define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)  /*!< Enable default generating polynomial 0x04C11DB7  */
-#define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)  /*!< Disable default generating polynomial 0x04C11DB7 */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
-  * @{
-  */
-#define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U) /*!< Enable initial CRC default value  */
-#define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U) /*!< Disable initial CRC default value */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
-  * @{
-  */
-#define CRC_POLYLENGTH_32B                  0x00000000U        /*!< Resort to a 32-bit long generating polynomial */
-#define CRC_POLYLENGTH_16B                  CRC_CR_POLYSIZE_0  /*!< Resort to a 16-bit long generating polynomial */
-#define CRC_POLYLENGTH_8B                   CRC_CR_POLYSIZE_1  /*!< Resort to a 8-bit long generating polynomial  */
-#define CRC_POLYLENGTH_7B                   CRC_CR_POLYSIZE    /*!< Resort to a 7-bit long generating polynomial  */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
-  * @{
-  */
-#define HAL_CRC_LENGTH_32B     32U          /*!< 32-bit long CRC */
-#define HAL_CRC_LENGTH_16B     16U          /*!< 16-bit long CRC */
-#define HAL_CRC_LENGTH_8B       8U          /*!< 8-bit long CRC  */
-#define HAL_CRC_LENGTH_7B       7U          /*!< 7-bit long CRC  */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
-  * @{
-  */
-/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
- * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
- * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
- * the CRC APIs to provide a correct result */
-#define CRC_INPUTDATA_FORMAT_UNDEFINED             0x00000000U  /*!< Undefined input data format    */
-#define CRC_INPUTDATA_FORMAT_BYTES                 0x00000001U  /*!< Input data in byte format      */
-#define CRC_INPUTDATA_FORMAT_HALFWORDS             0x00000002U  /*!< Input data in half-word format */
-#define CRC_INPUTDATA_FORMAT_WORDS                 0x00000003U  /*!< Input data in word format      */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CRC_Exported_Macros CRC Exported Macros
-  * @{
-  */
-
-/** @brief Reset CRC handle state.
-  * @param  __HANDLE__ CRC handle.
-  * @retval None
-  */
-#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
-
-/**
-  * @brief  Reset CRC Data Register.
-  * @param  __HANDLE__ CRC handle
-  * @retval None
-  */
-#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
-
-/**
-  * @brief  Set CRC INIT non-default value
-  * @param  __HANDLE__ CRC handle
-  * @param  __INIT__ 32-bit initial value
-  * @retval None
-  */
-#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
-
-/**
-  * @brief Store data in the Independent Data (ID) register.
-  * @param __HANDLE__ CRC handle
-  * @param __VALUE__  Value to be stored in the ID register
-  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
-  * @retval None
-  */
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
-
-/**
-  * @brief Return the data stored in the Independent Data (ID) register.
-  * @param __HANDLE__ CRC handle
-  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
-  * @retval Value of the ID register
-  */
-#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
-/**
-  * @}
-  */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup  CRC_Private_Macros CRC Private Macros
-  * @{
-  */
-
-#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
-                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
-
-#define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
-                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
-
-#define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \
-                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \
-                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \
-                                       ((LENGTH) == CRC_POLYLENGTH_7B))
-
-#define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \
-                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
-                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
-
-/**
-  * @}
-  */
-
-/* Include CRC HAL Extended module */
-#include "stm32l0xx_hal_crc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions ***********************************************/
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
-  * @{
-  */
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-/**
-  * @}
-  */
-
-/* Peripheral State and Error functions ***************************************/
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
-  * @{
-  */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc_ex.h
deleted file mode 100644
index 89828880d2..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc_ex.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_crc_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRC HAL extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_CRC_EX_H
-#define STM32L0xx_HAL_CRC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CRCEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
-  * @{
-  */
-#define CRC_INPUTDATA_INVERSION_NONE               0x00000000U     /*!< No input data inversion            */
-#define CRC_INPUTDATA_INVERSION_BYTE               CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion     */
-#define CRC_INPUTDATA_INVERSION_HALFWORD           CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
-#define CRC_INPUTDATA_INVERSION_WORD               CRC_CR_REV_IN   /*!< Word-wise input data inversion     */
-/**
-  * @}
-  */
-
-/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
-  * @{
-  */
-#define CRC_OUTPUTDATA_INVERSION_DISABLE         0x00000000U       /*!< No output data inversion       */
-#define CRC_OUTPUTDATA_INVERSION_ENABLE          CRC_CR_REV_OUT    /*!< Bit-wise output data inversion */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Set CRC output reversal
-  * @param  __HANDLE__ CRC handle
-  * @retval None
-  */
-#define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
-
-/**
-  * @brief  Unset CRC output reversal
-  * @param  __HANDLE__ CRC handle
-  * @retval None
-  */
-#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
-
-/**
-  * @brief  Set CRC non-default polynomial
-  * @param  __HANDLE__ CRC handle
-  * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
-  * @retval None
-  */
-#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
-  * @{
-  */
-
-#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
-                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
-                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
-                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
-
-#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
-                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CRCEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CRCEx_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
-HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
-HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_CRC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp.h
deleted file mode 100644
index 06a86a6967..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp.h
+++ /dev/null
@@ -1,411 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_cryp.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRYP HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_CRYP_H
-#define __STM32L0xx_HAL_CRYP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-   
-#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CRYP CRYP
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup CRYP_Exported_Types CRYP Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  CRYP Configuration Structure definition  
-  */
-typedef struct
-{  
-  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
-                             This parameter can be a value of @ref CRYP_Data_Type */
-  
-  uint8_t* pKey;        /*!< The key used for encryption/decryption */
-  
-  uint8_t* pInitVect;   /*!< The initialization vector used also as initialization
-                             counter in CTR mode */
-  
-}CRYP_InitTypeDef;
-
-/** 
-  * @brief HAL CRYP State structures definition  
-  */ 
-typedef enum
-{
-  HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */
-  HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */
-  HAL_CRYP_STATE_BUSY              = 0x02U,  /*!< CRYP internal processing is ongoing   */
-  HAL_CRYP_STATE_TIMEOUT           = 0x03U,  /*!< CRYP timeout state                    */
-  HAL_CRYP_STATE_ERROR             = 0x04U   /*!< CRYP error state                      */ 
-    
-}HAL_CRYP_STATETypeDef;
-
-/** 
-  * @brief HAL CRYP phase structures definition  
-  */ 
-typedef enum
-{
-  HAL_CRYP_PHASE_READY             = 0x01U,    /*!< CRYP peripheral is ready for initialization. */
-  HAL_CRYP_PHASE_PROCESS           = 0x02U,    /*!< CRYP peripheral is in processing phase */
-}HAL_PhaseTypeDef;
-
-/** 
-  * @brief  CRYP handle Structure definition  
-  */ 
-typedef struct
-{
-  AES_TypeDef                 *Instance;        /*!< Register base address        */
-
-  CRYP_InitTypeDef            Init;             /*!< CRYP required parameters */
-
-  uint8_t                     *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
-  uint8_t                     *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
-  __IO uint16_t               CrypInCount;      /*!< Counter of inputed data */
-
-  __IO uint16_t               CrypOutCount;     /*!< Counter of outputed data */
-
-  HAL_StatusTypeDef           Status;           /*!< CRYP peripheral status */
-
-  HAL_PhaseTypeDef            Phase;            /*!< CRYP peripheral phase */
-
-  DMA_HandleTypeDef           *hdmain;          /*!< CRYP In DMA handle parameters */
-
-  DMA_HandleTypeDef           *hdmaout;         /*!< CRYP Out DMA handle parameters */
-
-  HAL_LockTypeDef             Lock;             /*!< CRYP locking object */
-
-  __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
-
-}CRYP_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
-  * @{
-  */
-
-/** @defgroup CRYP_Data_Type CRYP Data Type
-  * @{
-  */
-#define CRYP_DATATYPE_32B         (0x00000000U)
-#define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0
-#define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1
-#define CRYP_DATATYPE_1B          AES_CR_DATATYPE
-
-#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \
-                                    ((DATATYPE) == CRYP_DATATYPE_16B) || \
-                                    ((DATATYPE) == CRYP_DATATYPE_8B)  || \
-                                    ((DATATYPE) == CRYP_DATATYPE_1B))  
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_AlgoModeDirection CRYP Algo Mode Direction
-  * @{
-  */ 
-#define CRYP_CR_ALGOMODE_DIRECTION              (uint32_t)(AES_CR_MODE|AES_CR_CHMOD)
-
-#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT        (0x00000000U)
-#define CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT  (AES_CR_MODE)
-#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT        (AES_CR_CHMOD_0)
-#define CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT  ((uint32_t)(AES_CR_CHMOD_0|AES_CR_MODE))
-#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT        (AES_CR_CHMOD_1)
-#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT        ((uint32_t)(AES_CR_CHMOD_1 | AES_CR_MODE_1))
-/**
-  * @}
-  */
-  
-/** @defgroup CRYP_AES_Interrupts AES Interrupts
-  * @{
-  */ 
-#define CRYP_IT_CC                          AES_CR_CCIE  /*!< Computation Complete interrupt */
-#define CRYP_IT_ERR                         AES_CR_ERRIE /*!< Error interrupt                */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup CRYP_AES_Flags AES Flags
-  * @{
-  */ 
-#define CRYP_FLAG_CCF                       AES_SR_CCF    /*!< Computation Complete Flag */
-#define CRYP_FLAG_RDERR                     AES_SR_RDERR  /*!< Read Error Flag           */
-#define CRYP_FLAG_WRERR                     AES_SR_WRERR  /*!< Write Error Flag          */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup CRYP_AES_Clear_Flags AES Clear Flags
-  * @{
-  */ 
-#define CRYP_CLEARFLAG_CCF                       AES_CR_CCFC   /*!< Computation Complete Flag Clear */
-#define CRYP_CLEARFLAG_RDERR                     AES_CR_ERRC   /*!< Read Error Clear           */
-#define CRYP_CLEARFLAG_WRERR                     AES_CR_ERRC   /*!< Write Error Clear          */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
-  * @{
-  */
-
-/** @brief Reset CRYP handle state
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @retval None
-  */
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
-
-/**
-  * @brief  Enable/Disable the CRYP peripheral.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @retval None
-  */
-#define __HAL_CRYP_ENABLE(__HANDLE__)                   SET_BIT((__HANDLE__)->Instance->CR, AES_CR_EN)
-#define __HAL_CRYP_DISABLE(__HANDLE__)                  CLEAR_BIT((__HANDLE__)->Instance->CR, AES_CR_EN)
-
-/**
-  * @brief  Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,...
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __MODE__ The algorithm mode.
-  * @retval None
-  */
-#define __HAL_CRYP_SET_MODE(__HANDLE__,__MODE__)             SET_BIT((__HANDLE__)->Instance->CR, (__MODE__))
-
-
-/** @brief  Check whether the specified CRYP flag is set or not.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CRYP_FLAG_CCF   : Computation Complete Flag
-  *            @arg CRYP_FLAG_RDERR : Read Error Flag
-  *            @arg CRYP_FLAG_WRERR : Write Error Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_CRYP_GET_FLAG(__HANDLE__,__FLAG__)         (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the CRYP pending flag.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *         This parameter can be one of the following values:
-  *            @arg CRYP_CLEARFLAG_CCF   : Computation Complete Clear Flag
-  *            @arg CRYP_CLEARFLAG_RDERR : Read Error Clear
-  *            @arg CRYP_CLEARFLAG_WRERR : Write Error Clear
-  * @retval None
-  */
-#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__)   SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
-
-/**
-  * @brief  Enable the CRYP interrupt.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __INTERRUPT__ CRYP Interrupt.
-  * @retval None
-  */
-#define __HAL_CRYP_ENABLE_IT(__HANDLE__,__INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the CRYP interrupt.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __INTERRUPT__ CRYP interrupt.
-  * @retval None
-  */
-#define __HAL_CRYP_DISABLE_IT(__HANDLE__,__INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-/** @brief  Checks if the specified CRYP interrupt source is enabled or disabled.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param __INTERRUPT__ CRYP interrupt source to check
-  *         This parameter can be one of the following values:
-  *            @arg CRYP_IT_CC   : Computation Complete interrupt
-  *            @arg CRYP_IT_ERR : Error interrupt (used for RDERR and WRERR)
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
-    (( ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)       \
-     )? SET : RESET                                         \
-    )
-         
-/** @brief  Clear the CRYP pending IT.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __IT__ specifies the IT to clear.
-  *         This parameter can be one of the following values:
-  *            @arg CRYP_CLEARFLAG_CCF   : Computation Complete Clear Flag
-  *            @arg CRYP_CLEARFLAG_RDERR : Read Error Clear
-  *            @arg CRYP_CLEARFLAG_WRERR : Write Error Clear
-  * @retval None
-  */
-#define __HAL_CRYP_CLEAR_IT(__HANDLE__, __IT__) SET_BIT((__HANDLE__)->Instance->CR, (__IT__))
-
-/**
-  * @}
-  */
-
-/* Include CRYP HAL Extension module */
-#include "stm32l0xx_hal_cryp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
-  * @{
-  */
-
-/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions *********************************/
-HAL_StatusTypeDef     HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef     HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
-
-/* MSP functions  *************************************************************/
-void                  HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
-void                  HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/** @defgroup CRYP_Exported_Functions_Group2  AES processing functions
-  * @{
-  */
-
-/* AES encryption/decryption using polling  ***********************************/
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* AES encryption/decryption using interrupt  *********************************/
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* AES encryption/decryption using DMA  ***************************************/
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup CRYP_Exported_Functions_Group3 DMA callback functions
-  * @{
-  */
-
-/* CallBack functions  ********************************************************/
-void                  HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
-void                  HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
-void                  HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
-  * @{
-  */
-
-/* Processing functions  ********************************************************/
-void                  HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions
-  * @{
-  */
-
-/* Peripheral State functions  **************************************************/
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Define the private group ***********************************/
-/**************************************************************/
-/** @defgroup CRYP_Private CRYP Private
-  * @{
-  */
-/**
-  * @}
-  */
-/**************************************************************/
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#endif /* STM32L021xx || STM32L041xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_CRYP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp_ex.h
deleted file mode 100644
index c43dcac011..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp_ex.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_cryp_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRYPEx HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_CRYP_EX_H
-#define __STM32L0xx_HAL_CRYP_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-   
-#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CRYPEx CRYPEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/* Exported constants --------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
-  * @{
-  */
-
-/** @defgroup CRYPEx_Exported_Functions_Group1 Extended features functions
-  * @{
-  */
-
-/* CallBack functions  ********************************************************/
-void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#endif /* STM32L021xx || STM32L041xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_CRYP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac.h
deleted file mode 100644
index dd1dbcf69b..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac.h
+++ /dev/null
@@ -1,486 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_dac.h
-  * @author  MCD Application Team
-  * @brief   Header file of DAC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_DAC_H
-#define __STM32L0xx_HAL_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-   
-#if !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) && !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
-   
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DAC DAC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Types DAC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-typedef enum
-{
-  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
-  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
-  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
-  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
-  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
- 
-}HAL_DAC_StateTypeDef;
- 
-/** 
-  * @brief  DAC handle Structure definition  
-  */ 
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-typedef struct __DAC_HandleTypeDef
-#else
-typedef struct
-#endif
-{
-  DAC_TypeDef                 *Instance;     /*!< Register base address             */
-
-  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
-
-  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
-
-  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
-
-#if defined (DAC_CHANNEL2_SUPPORT)
-  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */ 
-#endif
-
-  __IO uint32_t               ErrorCode;     /*!< DAC Error code                   */
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  void (* ConvCpltCallbackCh1)            (struct __DAC_HandleTypeDef *hdac);
-  void (* ConvHalfCpltCallbackCh1)        (struct __DAC_HandleTypeDef *hdac);
-  void (* ErrorCallbackCh1)               (struct __DAC_HandleTypeDef *hdac);
-  void (* DMAUnderrunCallbackCh1)         (struct __DAC_HandleTypeDef *hdac);
-  void (* ConvCpltCallbackCh2)            (struct __DAC_HandleTypeDef* hdac);
-  void (* ConvHalfCpltCallbackCh2)        (struct __DAC_HandleTypeDef* hdac);
-  void (* ErrorCallbackCh2)               (struct __DAC_HandleTypeDef* hdac);
-  void (* DMAUnderrunCallbackCh2)         (struct __DAC_HandleTypeDef* hdac); 
-
-  void (* MspInitCallback)                (struct __DAC_HandleTypeDef *hdac);
-  void (* MspDeInitCallback )             (struct __DAC_HandleTypeDef *hdac); 
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 
-
-}DAC_HandleTypeDef;
-
-/** 
-  * @brief   DAC Configuration regular Channel structure definition
-  */
-typedef struct
-{
-  uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.
-                                   This parameter can be a value of @ref DAC_trigger_selection */
-
-  uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                   This parameter can be a value of @ref DAC_output_buffer */
-
-}DAC_ChannelConfTypeDef;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL DAC Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_DAC_CH1_COMPLETE_CB_ID                 = 0x00U,  /*!< DAC CH1 Complete Callback ID      */
-  HAL_DAC_CH1_HALF_COMPLETE_CB_ID            = 0x01U,  /*!< DAC CH1 half Complete Callback ID */
-  HAL_DAC_CH1_ERROR_ID                       = 0x02U,  /*!< DAC CH1 error Callback ID         */
-  HAL_DAC_CH1_UNDERRUN_CB_ID                 = 0x03U,  /*!< DAC CH1 underrun Callback ID      */
-  HAL_DAC_CH2_COMPLETE_CB_ID                 = 0x04U,  /*!< DAC CH2 Complete Callback ID      */
-  HAL_DAC_CH2_HALF_COMPLETE_CB_ID            = 0x05U,  /*!< DAC CH2 half Complete Callback ID */
-  HAL_DAC_CH2_ERROR_ID                       = 0x06U,  /*!< DAC CH2 error Callback ID         */
-  HAL_DAC_CH2_UNDERRUN_CB_ID                 = 0x07U,  /*!< DAC CH2 underrun Callback ID      */
-  HAL_DAC_MSP_INIT_CB_ID                     = 0x08U,  /*!< DAC MspInit Callback ID           */
-  HAL_DAC_MSP_DEINIT_CB_ID                   = 0x09U,  /*!< DAC MspDeInit Callback ID         */
-  HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
-}HAL_DAC_CallbackIDTypeDef;                            
-                                                       
-/**
-  * @brief  HAL DAC Callback pointer definition
-  */
-typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
-  * @{
-  */  
-
-/** @defgroup DAC_Error_Code DAC Error Code
-  * @{
-  */
-#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DMA underrun error   */
-#if defined (DAC_CHANNEL2_SUPPORT)
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DMA underrun error   */
-#endif
-#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_trigger_selection DAC trigger selection
-  * @{
-  */
-#define DAC_TRIGGER_NONE       (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T6_TRGO    (                                                              DAC_CR_TEN1)  /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T21_TRGO   ((uint32_t)(                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM21 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T2_TRGO    ((uint32_t)(DAC_CR_TSEL1_2 |                                   DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9    ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 |                  DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE   ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#if defined (DAC_CHANNEL2_SUPPORT)
-#define DAC_TRIGGER_T3_TRGO    ((uint32_t)(                                  DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3  TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_CH3     ((uint32_t)(                 DAC_CR_TSEL1_1 |                  DAC_CR_TEN1)) /*!< TIM3  CH3  selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO    ((uint32_t)(DAC_CR_TSEL1_2 |                  DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM7  TRGO selected as external conversion trigger for DAC channel */
-#endif
-
-#if defined (DAC_CHANNEL2_SUPPORT)
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_T3_TRGO)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_T3_CH3)     || \
-                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_T21_TRGO)   || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#else
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_T21_TRGO)   || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#endif /* DAC_CHANNEL2_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_output_buffer DAC output buffer
-  * @{
-  */
-#define DAC_OUTPUTBUFFER_ENABLE            (0x00000000U)
-#define DAC_OUTPUTBUFFER_DISABLE           (DAC_CR_BOFF1)
-
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
-                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Channel_selection DAC Channel selection
-  * @{
-  */
-#define DAC_CHANNEL_1                      (0x00000000U)
-#if defined (DAC_CHANNEL2_SUPPORT)
-#define DAC_CHANNEL_2                      (0x00000010U)
-#endif
-
-#if defined (DAC_CHANNEL2_SUPPORT)
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
-                                 ((CHANNEL) == DAC_CHANNEL_2))
-#else
-#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data_alignement DAC data alignement
-  * @{
-  */
-#define DAC_ALIGN_12B_R                    (0x00000000U)
-#define DAC_ALIGN_12B_L                    (0x00000004U)
-#define DAC_ALIGN_8B_R                     (0x00000008U)
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
-                             ((ALIGN) == DAC_ALIGN_12B_L) || \
-                             ((ALIGN) == DAC_ALIGN_8B_R))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data DAC data
-  * @{
-  */
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
-/**
-  * @}
-  */
-
-/** @defgroup DAC_flags_definition DAC flags definition
-  * @{
-  */ 
-#define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)
-#if defined (DAC_CHANNEL2_SUPPORT)
-#define DAC_FLAG_DMAUDR2                   (DAC_SR_DMAUDR2)   
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_IT_definition DAC IT definition
-  * @{
-  */ 
-#define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)
-#if defined (DAC_CHANNEL2_SUPPORT)
-#define DAC_IT_DMAUDR2                   (DAC_SR_DMAUDR2)   
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
-  * @{
-  */
-
-/** @brief Reset DAC handle state
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @retval None
-  */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
-                                                                 (__HANDLE__)->State = HAL_DAC_STATE_RESET; \
-                                                                 (__HANDLE__)->MspInitCallback = NULL;       \
-                                                                 (__HANDLE__)->MspDeInitCallback = NULL;     \
-                                                               } while(0)
-#else
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/** @brief Enable the DAC channel
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __DAC_CHANNEL__ specifies the DAC channel
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \
-SET_BIT((__HANDLE__)->Instance->CR, (DAC_CR_EN1 << (__DAC_CHANNEL__)))
-
-/** @brief Disable the DAC channel
-  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __DAC_CHANNEL__ specifies the DAC channel.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \
-CLEAR_BIT((__HANDLE__)->Instance->CR, (DAC_CR_EN1 << (__DAC_CHANNEL__)))
-
-  
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
-SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-
-/** @brief Disable the DAC interrupt
-  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __INTERRUPT__ specifies the DAC interrupt.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
-CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-/** @brief  Check whether the specified DAC interrupt source is enabled or not.
-  * @param __HANDLE__ DAC handle
-  * @param __INTERRUPT__ DAC interrupt source to check
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (STM32L072xx STM32L073xx STM32L082xx STM32L083xx only)
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
-(((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief  Get the selected DAC's flag status.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __FLAG__ specifies the FLAG.
-  * @retval None
-  */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__)  \
-((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the DAC's flag.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __FLAG__ specifies the FLAG.
-  * @retval None
-  */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-(((__HANDLE__)->Instance->SR) = (__FLAG__))
-
-/**
-  * @}
-  */ 
-
-/* Private macro ------------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Macros DAC Private Macros
-  * @{
-  */
-
-/** @brief Set DHR12R1 alignment
-  * @param  __ALIGNMENT__ specifies the DAC alignement
-  * @retval None
-  */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
-
-/** @brief  Set DHR12R2 alignment
-  * @param  __ALIGNMENT__ specifies the DAC alignement
-  * @retval None
-  */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
-
-/** @brief  Set DHR12RD alignment
-  * @param  __ALIGNMENT__ specifies the DAC alignement
-  * @retval None
-  */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
-
-/** @brief Enable the DAC interrupt
-  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __INTERRUPT__ specifies the DAC interrupt.
-  * @retval None
-  */
-  
-/**
-  * @}
-  */ 
-
-
-/* Include DAC HAL Extension module */
-#include "stm32l0xx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Functions DAC Exported Functions
-  * @{
-  */
-
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */ 
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/* DAC callback registering/unregistering */
-HAL_StatusTypeDef     HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId, pDAC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
-  * @{
-  */
-/* Peripheral State functions ***************************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* !STM32L010xB && !STM32L010x8 && !STM32L010x6 && !STM32L010x4 && !STM32L011xx && !STM32L021xx && !STM32L031xx && !STM32L041xx && !STM32L071xx && !STM32L081xx*/
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32L0xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac_ex.h
deleted file mode 100644
index 202a7bdea6..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac_ex.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_dac_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of DAC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_DAC_EX_H
-#define __STM32L0xx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !defined(STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) && !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
-   
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DACEx DACEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-   
-/* Exported constants --------------------------------------------------------*/
-  
-/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
-  * @{
-  */ 
-   
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
-  * @{
-  */
-#define DAC_LFSRUNMASK_BIT0                (0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0             (DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0             (DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0             (DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1            (0x00000000U) /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3            (DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7            (DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31           (DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/  
-
-/* Exported functions --------------------------------------------------------*/  
-
-/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
-  * @{
-  */
-
-/** @defgroup DACEx_Exported_Functions_Group1  Extended features functions
-  * @{
-  */
-/* Extension features functions ***********************************************/
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-
-#if defined (DAC_CHANNEL2_SUPPORT)
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Define the private group ***********************************/
-/**************************************************************/
-/** @defgroup DACEx_Private DACEx Private
-  * @{
-  */
-/**
-  * @}
-  */
-/**************************************************************/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* !STM32L010xB && !STM32L010x8 && !STM32L010x6 && !STM32L010x4 && !STM32L011xx && !STM32L021xx && !STM32L031xx && !STM32L041xx && !STM32L051xx && !STM32L071xx && !STM32L081xx*/
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32L0xx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h
deleted file mode 100644
index d042768fac..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_def.h
-  * @author  MCD Application Team
-  * @brief   This file contains HAL common defines, enumeration, macros and
-  *          structures definitions.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_DEF
-#define __STM32L0xx_HAL_DEF
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-#include "Legacy/stm32_hal_legacy.h"
-#include <stddef.h>
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  HAL Status structures definition
-  */
-typedef enum
-{
-  HAL_OK       = 0x00U,
-  HAL_ERROR    = 0x01U,
-  HAL_BUSY     = 0x02U,
-  HAL_TIMEOUT  = 0x03U
-} HAL_StatusTypeDef;
-
-/**
-  * @brief  HAL Lock structures definition
-  */
-typedef enum
-{
-  HAL_UNLOCKED = 0x00U,
-  HAL_LOCKED   = 0x01U
-} HAL_LockTypeDef;
-
-/* Exported macro ------------------------------------------------------------*/
-
-#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
-
-#define HAL_MAX_DELAY      0xFFFFFFFFU
-
-#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
-#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)             \
-                        do{                                                    \
-                            (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
-                            (__DMA_HANDLE__).Parent = (__HANDLE__);             \
-                          } while(0)
-
-/** @brief Reset the Handle's State field.
-  * @param __HANDLE__: specifies the Peripheral Handle.
-  * @note  This macro can be used for the following purpose:
-  *          - When the Handle is declared as local variable; before passing it as parameter
-  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
-  *            to set to 0 the Handle's "State" field.
-  *            Otherwise, "State" field may have any random value and the first time the function
-  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
-  *            (i.e. HAL_PPP_MspInit() will not be executed).
-  *          - When there is a need to reconfigure the low level hardware: instead of calling
-  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
-  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
-  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
-  * @retval None
-  */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
-
-#if (USE_RTOS == 1)
-
-  /* Reserved for future use */
-  #error "USE_RTOS should be 0 in the current HAL release"
-
-#else
-  #define __HAL_LOCK(__HANDLE__)                                               \
-                                do{                                            \
-                                    if((__HANDLE__)->Lock == HAL_LOCKED)       \
-                                    {                                          \
-                                       return HAL_BUSY;                        \
-                                    }                                          \
-                                    else                                       \
-                                    {                                          \
-                                       (__HANDLE__)->Lock = HAL_LOCKED;        \
-                                    }                                          \
-                                  }while (0)
-
-  #define __HAL_UNLOCK(__HANDLE__)                                             \
-                                  do{                                          \
-                                      (__HANDLE__)->Lock = HAL_UNLOCKED;       \
-                                    }while (0)
-#endif /* USE_RTOS */
-
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
-  #ifndef __weak
-    #define __weak  __attribute__((weak))
-  #endif
-  #ifndef __packed
-    #define __packed  __attribute__((packed))
-  #endif
-#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
-  #ifndef __weak
-    #define __weak   __attribute__((weak))
-  #endif /* __weak */
-  #ifndef __packed
-    #define __packed __attribute__((__packed__))
-  #endif /* __packed */
-
-  #define __NOINLINE __attribute__ ( (noinline) )
-
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
-  #ifndef __ALIGN_BEGIN
-    #define __ALIGN_BEGIN
-  #endif
-  #ifndef __ALIGN_END
-    #define __ALIGN_END      __attribute__ ((aligned (4)))
-  #endif
-#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
-  #ifndef __ALIGN_END
-    #define __ALIGN_END    __attribute__ ((aligned (4)))
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN
-    #define __ALIGN_BEGIN
-  #endif /* __ALIGN_BEGIN */
-#else
-  #ifndef __ALIGN_END
-    #define __ALIGN_END
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN
-    #if defined   (__CC_ARM)      /* ARM Compiler V5*/
-      #define __ALIGN_BEGIN    __align(4)
-    #elif defined (__ICCARM__)    /* IAR Compiler */
-      #define __ALIGN_BEGIN
-    #endif /* __CC_ARM */
-  #endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-/**
-  * @brief  __RAM_FUNC definition
-  */
-#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-/* ARM Compiler V4/V5 and V6
-   --------------------------
-   RAM functions are defined using the toolchain options.
-   Functions that are executed in RAM should reside in a separate source module.
-   Using the 'Options for File' dialog you can simply change the 'Code / Const'
-   area of a module to a memory space in physical RAM.
-   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
-   dialog.
-*/
-#define __RAM_FUNC
-
-#define __NOINLINE __attribute__ ( (noinline) )
-
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc".
-*/
-#define __RAM_FUNC __ramfunc
-
-#define __NOINLINE _Pragma("optimize = no_inline")
-
-#elif defined   (  __GNUC__  )
-/* GNU Compiler
-   ------------
-  RAM functions are defined using a specific toolchain attribute
-   "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC  __attribute__((section(".RamFunc")))
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32L0xx_HAL_DEF */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h
deleted file mode 100644
index af5ef58428..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h
+++ /dev/null
@@ -1,675 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_dma.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_DMA_H
-#define STM32L0xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMA_Exported_Types DMA Exported Types
-  * @{
-  */
-
-/**
-  * @brief  DMA Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
-                                           This parameter can be a value of @ref DMA_request */
-
-  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
-                                           from memory to memory or from peripheral to memory.
-                                           This parameter can be a value of @ref DMA_Data_transfer_direction */
-
-  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
-                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
-  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
-                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
-  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
-                                           This parameter can be a value of @ref DMA_Peripheral_data_size */
-
-  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
-                                           This parameter can be a value of @ref DMA_Memory_data_size */
-
-  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
-                                           This parameter can be a value of @ref DMA_mode
-                                           @note The circular buffer mode cannot be used if the memory-to-memory
-                                                 data transfer is configured on the selected Channel */
-
-  uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
-                                           This parameter can be a value of @ref DMA_Priority_level */
-} DMA_InitTypeDef;
-
-/**
-  * @brief  HAL DMA State structures definition
-  */
-typedef enum
-{
-  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
-  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
-  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
-  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                      */
-}HAL_DMA_StateTypeDef;
-
-/**
-  * @brief  HAL DMA Error Code structure definition
-  */
-typedef enum
-{
-  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
-  HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
-}HAL_DMA_LevelCompleteTypeDef;
-
-
-/**
-  * @brief  HAL DMA Callback ID structure definition
-  */
-typedef enum
-{
-  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
-  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
-  HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
-  HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
-  HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */
-}HAL_DMA_CallbackIDTypeDef;
-
-/**
-  * @brief  DMA handle Structure definition
-  */
-typedef struct __DMA_HandleTypeDef
-{
-  DMA_Channel_TypeDef    *Instance;                                                  /*!< Register base address                */
-
-  DMA_InitTypeDef       Init;                                                        /*!< DMA communication parameters         */
-
-  HAL_LockTypeDef       Lock;                                                        /*!< DMA locking object                   */
-
-  __IO HAL_DMA_StateTypeDef  State;                                                  /*!< DMA transfer state                   */
-
-  void                  *Parent;                                                     /*!< Parent object state                  */
-
-  void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback       */
-
-  void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback  */
-
-  void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback          */
-
-  void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer abort callback          */
-
-  __IO uint32_t          ErrorCode;                                                  /*!< DMA Error code                       */
-
-  DMA_TypeDef            *DmaBaseAddress;                                            /*!< DMA Channel Base Address             */
-
-  uint32_t               ChannelIndex;                                               /*!< DMA Channel Index                    */
-
-}DMA_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
-  * @{
-  */
-
-/** @defgroup DMA_Error_Code DMA Error Code
-  * @{
-  */
-#define HAL_DMA_ERROR_NONE                 0x00000000U    /*!< No error                                */
-#define HAL_DMA_ERROR_TE                   0x00000001U    /*!< Transfer error                          */
-#define HAL_DMA_ERROR_NO_XFER              0x00000004U    /*!< Abort requested with no Xfer ongoing    */
-#define HAL_DMA_ERROR_TIMEOUT              0x00000020U    /*!< Timeout error                           */
-#define HAL_DMA_ERROR_NOT_SUPPORTED        0x00000100U    /*!< Not supported mode                      */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_request DMA request
-  * @{
-  */
-
-#if defined (STM32L010x4) || defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xC)
-
-#define DMA_REQUEST_0                     0U
-#define DMA_REQUEST_1                     1U
-#define DMA_REQUEST_4                     4U
-#define DMA_REQUEST_5                     5U
-#define DMA_REQUEST_6                     6U
-#define DMA_REQUEST_8                     8U
-
-#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
-                                     ((REQUEST) == DMA_REQUEST_1) || \
-                                     ((REQUEST) == DMA_REQUEST_4) || \
-                                     ((REQUEST) == DMA_REQUEST_5) || \
-                                     ((REQUEST) == DMA_REQUEST_6) || \
-                                     ((REQUEST) == DMA_REQUEST_8))
-
-/* STM32L010x4 || STM32L010x6 || STM32L010x8 || STM32L010xC */
-
-#elif defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-
-#define DMA_REQUEST_0                     0U
-#define DMA_REQUEST_1                     1U
-#define DMA_REQUEST_2                     2U
-#define DMA_REQUEST_3                     3U
-#define DMA_REQUEST_4                     4U
-#define DMA_REQUEST_5                     5U
-#define DMA_REQUEST_6                     6U
-#define DMA_REQUEST_7                     7U
-#define DMA_REQUEST_8                     8U
-#define DMA_REQUEST_9                     9U
-#define DMA_REQUEST_10                   10U
-#define DMA_REQUEST_11                   11U  /* AES product only */
-#define DMA_REQUEST_12                   12U
-#define DMA_REQUEST_13                   13U
-#define DMA_REQUEST_14                   14U
-#define DMA_REQUEST_15                   15U
-
-#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
-                                     ((REQUEST) == DMA_REQUEST_1) || \
-                                     ((REQUEST) == DMA_REQUEST_2) || \
-                                     ((REQUEST) == DMA_REQUEST_3) || \
-                                     ((REQUEST) == DMA_REQUEST_4) || \
-                                     ((REQUEST) == DMA_REQUEST_5) || \
-                                     ((REQUEST) == DMA_REQUEST_6) || \
-                                     ((REQUEST) == DMA_REQUEST_7) || \
-                                     ((REQUEST) == DMA_REQUEST_8) || \
-                                     ((REQUEST) == DMA_REQUEST_9) || \
-                                     ((REQUEST) == DMA_REQUEST_10) || \
-                                     ((REQUEST) == DMA_REQUEST_11) || \
-                                     ((REQUEST) == DMA_REQUEST_12) || \
-                                     ((REQUEST) == DMA_REQUEST_13) || \
-                                     ((REQUEST) == DMA_REQUEST_14) || \
-                                     ((REQUEST) == DMA_REQUEST_15))
-
-/* (STM32L021xx) || (STM32L041xx) || (STM32L062xx) || (STM32L063xx) || (STM32L081xx) || (STM32L082xx) || (STM32L083xx) */
-
-#else
-
-#define DMA_REQUEST_0                     0U
-#define DMA_REQUEST_1                     1U
-#define DMA_REQUEST_2                     2U
-#define DMA_REQUEST_3                     3U
-#define DMA_REQUEST_4                     4U
-#define DMA_REQUEST_5                     5U
-#define DMA_REQUEST_6                     6U
-#define DMA_REQUEST_7                     7U
-#define DMA_REQUEST_8                     8U
-#define DMA_REQUEST_9                     9U
-#define DMA_REQUEST_10                   10U
-#define DMA_REQUEST_12                   12U
-#define DMA_REQUEST_13                   13U
-#define DMA_REQUEST_14                   14U
-#define DMA_REQUEST_15                   15U
-
-#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
-                                     ((REQUEST) == DMA_REQUEST_1) || \
-                                     ((REQUEST) == DMA_REQUEST_2) || \
-                                     ((REQUEST) == DMA_REQUEST_3) || \
-                                     ((REQUEST) == DMA_REQUEST_4) || \
-                                     ((REQUEST) == DMA_REQUEST_5) || \
-                                     ((REQUEST) == DMA_REQUEST_6) || \
-                                     ((REQUEST) == DMA_REQUEST_7) || \
-                                     ((REQUEST) == DMA_REQUEST_8) || \
-                                     ((REQUEST) == DMA_REQUEST_9) || \
-                                     ((REQUEST) == DMA_REQUEST_10) || \
-                                     ((REQUEST) == DMA_REQUEST_12) || \
-                                     ((REQUEST) == DMA_REQUEST_13) || \
-                                     ((REQUEST) == DMA_REQUEST_14) || \
-                                     ((REQUEST) == DMA_REQUEST_15))
-
-#endif /* (STM32L031xx) || (STM32L051xx) || (STM32L052xx) || (STM32L053xx) || (STM32L071xx) || (STM32L072xx) || (STM32L073xx) */
-
-
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
-  * @{
-  */
-#define DMA_PERIPH_TO_MEMORY         0x00000000U        /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH         DMA_CCR_DIR        /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY         DMA_CCR_MEM2MEM    /*!< Memory to memory direction     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
-  * @{
-  */
-#define DMA_PINC_ENABLE              DMA_CCR_PINC  /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE             0x00000000U   /*!< Peripheral increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
-  * @{
-  */
-#define DMA_MINC_ENABLE              DMA_CCR_MINC   /*!< Memory increment mode Enable  */
-#define DMA_MINC_DISABLE             0x00000000U    /*!< Memory increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
-  * @{
-  */
-#define DMA_PDATAALIGN_BYTE          0x00000000U     /*!< Peripheral data alignment : Byte     */
-#define DMA_PDATAALIGN_HALFWORD      DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
-#define DMA_PDATAALIGN_WORD          DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
-  * @{
-  */
-#define DMA_MDATAALIGN_BYTE          0x00000000U     /*!< Memory data alignment : Byte     */
-#define DMA_MDATAALIGN_HALFWORD      DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
-#define DMA_MDATAALIGN_WORD          DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_mode DMA mode
-  * @{
-  */
-#define DMA_NORMAL                   0x00000000U     /*!< Normal mode                  */
-#define DMA_CIRCULAR                 DMA_CCR_CIRC    /*!< Circular mode                */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Priority_level DMA Priority level
-  * @{
-  */
-#define DMA_PRIORITY_LOW             0x00000000U      /*!< Priority level : Low       */
-#define DMA_PRIORITY_MEDIUM          DMA_CCR_PL_0     /*!< Priority level : Medium    */
-#define DMA_PRIORITY_HIGH            DMA_CCR_PL_1     /*!< Priority level : High      */
-#define DMA_PRIORITY_VERY_HIGH       DMA_CCR_PL       /*!< Priority level : Very_High */
-/**
-  * @}
-  */
-
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
-  * @{
-  */
-#define DMA_IT_TC                         DMA_CCR_TCIE
-#define DMA_IT_HT                         DMA_CCR_HTIE
-#define DMA_IT_TE                         DMA_CCR_TEIE
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
-  * @{
-  */
-#define DMA_FLAG_GL1                      DMA_ISR_GIF1
-#define DMA_FLAG_TC1                      DMA_ISR_TCIF1
-#define DMA_FLAG_HT1                      DMA_ISR_HTIF1
-#define DMA_FLAG_TE1                      DMA_ISR_TEIF1
-#define DMA_FLAG_GL2                      DMA_ISR_GIF2
-#define DMA_FLAG_TC2                      DMA_ISR_TCIF2
-#define DMA_FLAG_HT2                      DMA_ISR_HTIF2
-#define DMA_FLAG_TE2                      DMA_ISR_TEIF2
-#define DMA_FLAG_GL3                      DMA_ISR_GIF3
-#define DMA_FLAG_TC3                      DMA_ISR_TCIF3
-#define DMA_FLAG_HT3                      DMA_ISR_HTIF3
-#define DMA_FLAG_TE3                      DMA_ISR_TEIF3
-#define DMA_FLAG_GL4                      DMA_ISR_GIF4
-#define DMA_FLAG_TC4                      DMA_ISR_TCIF4
-#define DMA_FLAG_HT4                      DMA_ISR_HTIF4
-#define DMA_FLAG_TE4                      DMA_ISR_TEIF4
-#define DMA_FLAG_GL5                      DMA_ISR_GIF5
-#define DMA_FLAG_TC5                      DMA_ISR_TCIF5
-#define DMA_FLAG_HT5                      DMA_ISR_HTIF5
-#define DMA_FLAG_TE5                      DMA_ISR_TEIF5
-#define DMA_FLAG_GL6                      DMA_ISR_GIF6
-#define DMA_FLAG_TC6                      DMA_ISR_TCIF6
-#define DMA_FLAG_HT6                      DMA_ISR_HTIF6
-#define DMA_FLAG_TE6                      DMA_ISR_TEIF6
-#define DMA_FLAG_GL7                      DMA_ISR_GIF7
-#define DMA_FLAG_TC7                      DMA_ISR_TCIF7
-#define DMA_FLAG_HT7                      DMA_ISR_HTIF7
-#define DMA_FLAG_TE7                      DMA_ISR_TEIF7
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup DMA_Exported_Macros DMA Exported Macros
-  * @{
-  */
-
-/** @brief  Reset DMA handle state
-  * @param  __HANDLE__ DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
-  * @brief  Enable the specified DMA Channel.
-  * @param  __HANDLE__ DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
-
-/**
-  * @brief  Disable the specified DMA Channel.
-  * @param  __HANDLE__ DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
-
-
-/* Interrupt & Flag management */
-
-/**
-  * @brief  Return the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer complete flag index.
-  */
-
-#if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- DMA_FLAG_TC5)
-#else
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
-   DMA_FLAG_TC7)
-#endif
-/**
-  * @brief  Return the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified half transfer complete flag index.
-  */
-#if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- DMA_FLAG_HT5)
-#else
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
-   DMA_FLAG_HT7)
-#endif
-/**
-  * @brief  Returns the current DMA Channel transfer error flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- DMA_FLAG_TE5)
-#else
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
-   DMA_FLAG_TE7)
-#endif
-/**
-  * @brief  Returns the current DMA Channel Global interrupt flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
-   DMA_ISR_GIF5)
-#else
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
-   DMA_ISR_GIF7)
-#endif
-/**
-  * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__ Get the specified flag.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCIFx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEIFx:  Transfer error flag
-  *            @arg DMA_ISR_GIFx: Global interrupt flag
-  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
-
-/**
-  * @brief  Clears the DMA Channel pending flags.
-  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *            @arg DMA_FLAG_GLx:  Global interrupt flag
-  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
-  * @retval None
-  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
-
-/**
-  * @brief  Enable the specified DMA Channel interrupts.
-  * @param  __HANDLE__ DMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified DMA Channel interrupts.
-  * @param  __HANDLE__ DMA handle
-  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
-  * @param  __HANDLE__ DMA handle
-  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval The state of DMA_IT (SET or RESET).
-  */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
-
-/**
-  * @brief  Return the number of remaining data units in the current DMA Channel transfer.
-  * @param  __HANDLE__ DMA handle
-  * @retval The number of remaining data units in the current DMA Channel transfer.
-  */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DMA_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Define the private group ***********************************/
-/**************************************************************/
-/** @defgroup DMA_Private DMA Private
-  * @{
-  */
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
-                                            ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
-                                        ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
-                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
-                                           ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
-                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
-                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
-                           ((MODE) == DMA_CIRCULAR))
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
-                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
-                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
-                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-
-/**
-  * @}
-  */
-/**************************************************************/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h
deleted file mode 100644
index e687b177a9..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_exti.h
-  * @author  MCD Application Team
-  * @brief   Header file of EXTI LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_EXTI_H
-#define __STM32L0xx_HAL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup EXTI EXTI
-  * @brief EXTI HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Types EXTI Exported Types
-  * @{
-  */
-typedef enum
-{
-  HAL_EXTI_COMMON_CB_ID          = 0x00U,
-  HAL_EXTI_RISING_CB_ID          = 0x01U,
-  HAL_EXTI_FALLING_CB_ID         = 0x02U,
-} EXTI_CallbackIDTypeDef;
-
-
-/**
-  * @brief  EXTI Handle structure definition
-  */
-typedef struct
-{
-  uint32_t Line;                    /*!<  Exti line number */
-  void (* PendingCallback)(void);   /*!<  Exti pending callback */
-} EXTI_HandleTypeDef;
-
-/**
-  * @brief  EXTI Configuration structure definition
-  */
-typedef struct
-{
-  uint32_t Line;      /*!< The Exti line to be configured. This parameter
-                           can be a value of @ref EXTI_Line */
-  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
-                           This parameter can be a combination of @ref EXTI_Mode */
-  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
-                           can be a value of @ref EXTI_Trigger */
-  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
-                           This parameter is only possible for line 0 to 15. It
-                           can be a value of @ref EXTI_GPIOSel */
-} EXTI_ConfigTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
-  * @{
-  */
-
-/** @defgroup EXTI_Line  EXTI Line
-  * @{
-  */
-
-
-#define EXTI_LINE_0                        (EXTI_GPIO       | 0x00u)    /*!< External interrupt line 0 */
-#define EXTI_LINE_1                        (EXTI_GPIO       | 0x01u)    /*!< External interrupt line 1 */
-#define EXTI_LINE_2                        (EXTI_GPIO       | 0x02u)    /*!< External interrupt line 2 */
-#define EXTI_LINE_3                        (EXTI_GPIO       | 0x03u)    /*!< External interrupt line 3 */
-#define EXTI_LINE_4                        (EXTI_GPIO       | 0x04u)    /*!< External interrupt line 4 */
-#define EXTI_LINE_5                        (EXTI_GPIO       | 0x05u)    /*!< External interrupt line 5 */
-#define EXTI_LINE_6                        (EXTI_GPIO       | 0x06u)    /*!< External interrupt line 6 */
-#define EXTI_LINE_7                        (EXTI_GPIO       | 0x07u)    /*!< External interrupt line 7 */
-#define EXTI_LINE_8                        (EXTI_GPIO       | 0x08u)    /*!< External interrupt line 8 */
-#define EXTI_LINE_9                        (EXTI_GPIO       | 0x09u)    /*!< External interrupt line 9 */
-#define EXTI_LINE_10                       (EXTI_GPIO       | 0x0Au)    /*!< External interrupt line 10 */
-#define EXTI_LINE_11                       (EXTI_GPIO       | 0x0Bu)    /*!< External interrupt line 11 */
-#define EXTI_LINE_12                       (EXTI_GPIO       | 0x0Cu)    /*!< External interrupt line 12 */
-#define EXTI_LINE_13                       (EXTI_GPIO       | 0x0Du)    /*!< External interrupt line 13 */
-#define EXTI_LINE_14                       (EXTI_GPIO       | 0x0Eu)    /*!< External interrupt line 14 */
-#define EXTI_LINE_15                       (EXTI_GPIO       | 0x0Fu)    /*!< External interrupt line 15 */
-#if defined(EXTI_IMR_IM16)
-#define EXTI_LINE_16                       (EXTI_CONFIG     | 0x10u)    /*!< External interrupt line 16 Connected to the PVD Output */
-#else
-#define EXTI_LINE_16                       (EXTI_RESERVED   | 0x10u)    /*!< No interrupt supported in this line */
-#endif /* EXTI_IMR_IM16 */
-#define EXTI_LINE_17                       (EXTI_CONFIG     | 0x11u)    /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#if defined(EXTI_IMR_IM18)
-#define EXTI_LINE_18                       (EXTI_DIRECT     | 0x12u)    /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */
-#else
-#define EXTI_LINE_18                       (EXTI_RESERVED   | 0x12u)    /*!< No interrupt supported in this line */
-#endif /* EXTI_IMR_IM18 */
-#define EXTI_LINE_19                       (EXTI_CONFIG     | 0x13u)    /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events or CSS_LSE */
-#define EXTI_LINE_20                       (EXTI_CONFIG     | 0x14u)    /*!< External interrupt line 20 Connected to the RTC wakeup timer */
-#if defined(EXTI_IMR_IM21)
-#define EXTI_LINE_21                       (EXTI_CONFIG     | 0x15u)    /*!< External interrupt line 21 Connected to the Comparator 1 output */
-#else
-#define EXTI_LINE_21                       (EXTI_RESERVED   | 0x15u)    /*!< No interrupt supported in this line */
-#endif /* EXTI_IMR_IM21 */
-#if defined(EXTI_IMR_IM22)
-#define EXTI_LINE_22                       (EXTI_CONFIG     | 0x16u)    /*!< External interrupt line 22 Connected to the Comparator 2 output */
-#else
-#define EXTI_LINE_22                       (EXTI_RESERVED   | 0x16u)    /*!< No interrupt supported in this line */
-#endif /* EXTI_IMR_IM22 */
-#define EXTI_LINE_23                       (EXTI_DIRECT     | 0x17u)    /*!< External interrupt line 23 Connected to the internal I2C1 wakeup event */
-#if defined(EXTI_IMR_IM24)
-#define EXTI_LINE_24                       (EXTI_DIRECT     | 0x18u)    /*!< External interrupt line 24 Connected to the internal I2C3 wakeup event */
-#else
-#define EXTI_LINE_24                       (EXTI_RESERVED   | 0x18u)    /*!< No interrupt supported in this line */
-#endif /* EXTI_IMR_IM24 */
-#if defined(EXTI_IMR_IM25)
-#define EXTI_LINE_25                       (EXTI_DIRECT     | 0x19u)    /*!< External interrupt line 25 Connected to the internal USART1 wakeup event */
-#else
-#define EXTI_LINE_25                       (EXTI_RESERVED   | 0x19u)    /*!< No interrupt supported in this line */
-#endif /* EXTI_IMR_IM25 */
-#define EXTI_LINE_26                       (EXTI_DIRECT     | 0x1Au)    /*!< External interrupt line 26 Connected to the internal USART2 wakeup event */
-#define EXTI_LINE_27                       (EXTI_RESERVED   | 0x1Bu)    /*!< No interrupt supported in this line */
-#define EXTI_LINE_28                       (EXTI_DIRECT     | 0x1Cu)    /*!< External interrupt line 28 Connected to the LPUART1 Wakeup event */
-#define EXTI_LINE_29                       (EXTI_DIRECT     | 0x1Du)    /*!< External interrupt line 29 Connected to the LPTIM1 Wakeup event */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Mode  EXTI Mode
-  * @{
-  */
-#define EXTI_MODE_NONE                      0x00000000u
-#define EXTI_MODE_INTERRUPT                 0x00000001u
-#define EXTI_MODE_EVENT                     0x00000002u
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Trigger  EXTI Trigger
-  * @{
-  */
-#define EXTI_TRIGGER_NONE                   0x00000000u
-#define EXTI_TRIGGER_RISING                 0x00000001u
-#define EXTI_TRIGGER_FALLING                0x00000002u
-#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
-  * @brief
-  * @{
-  */
-#define EXTI_GPIOA                          0x00000000u
-#define EXTI_GPIOB                          0x00000001u
-#define EXTI_GPIOC                          0x00000002u
-#if defined (GPIOD)
-#define EXTI_GPIOD                          0x00000003u
-#endif /* GPIOD*/
-#if defined (GPIOE)
-#define EXTI_GPIOE                          0x00000004u
-#endif /* GPIOE*/
-#if defined (GPIOH)
-#define EXTI_GPIOH                          0x00000007u
-#endif /* GPIOH*/
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
-  * @{
-  */
-/**
-  * @brief  EXTI Line property definition
-  */
-#define EXTI_PROPERTY_SHIFT                  24u
-#define EXTI_DIRECT                         (0x01uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
-#define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
-
-/**
-  * @brief  EXTI bit usage
-  */
-#define EXTI_PIN_MASK                       0x0000001Fu
-
-/**
-  * @brief  EXTI Mask for interrupt & event mode
-  */
-#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
-
-/**
-  * @brief  EXTI Mask for trigger possibilities
-  */
-#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-
-/**
-  * @brief  EXTI Line number
-  */
-#define EXTI_LINE_NB                        30u
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup EXTI_Private_Macros EXTI Private Macros
-  * @{
-  */
-#define IS_EXTI_LINE(__EXTI_LINE__)          ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
-                                             ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)              || \
-                                              (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))               && \
-                                              (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
-
-#define IS_EXTI_MODE(__EXTI_LINE__)          ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
-                                              (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
-
-#define IS_EXTI_TRIGGER(__EXTI_LINE__)       (((__EXTI_LINE__)  & ~EXTI_TRIGGER_MASK) == 0x00u)
-
-#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__)  ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
-
-#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
-
-#if !defined (GPIOH)
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC))
-#elif !defined (GPIOD)
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOH))
-#elif !defined (GPIOE)
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOD) || \
-                                         ((__PORT__) == EXTI_GPIOH))
-#else
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOD) || \
-                                         ((__PORT__) == EXTI_GPIOE) || \
-                                         ((__PORT__) == EXTI_GPIOH))
-#endif /* GPIOH */
-
-#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16u)
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
-  * @brief    EXTI Exported Functions
-  * @{
-  */
-
-/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
-  * @brief    Configuration functions
-  * @{
-  */
-/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
-  * @brief    IO operation functions
-  * @{
-  */
-/* IO operation functions *****************************************************/
-void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
-uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_EXTI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_firewall.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_firewall.h
deleted file mode 100644
index adbfb7649c..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_firewall.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_firewall.h
-  * @author  MCD Application Team
-  * @brief   Header file of FIREWALL HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_FIREWALL_H
-#define __STM32L0xx_HAL_FIREWALL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) && !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FIREWALL  FIREWALL
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FIREWALL_Exported_Types FIREWALL Exported Types
-  * @{
-  */
-
-/**
-  * @brief FIREWALL Initialization Structure definition
-  */
-typedef struct
-{
-  uint32_t CodeSegmentStartAddress;        /*!< Protected code segment start address. This value is 24-bit long, the 8 LSB bits are
-                                                reserved and forced to 0 in order to allow a 256-byte granularity. */
-
-  uint32_t CodeSegmentLength;              /*!< Protected code segment length in bytes. This value is 22-bit long, the 8 LSB bits are
-                                                reserved and forced to 0 for the length to be a multiple of 256 bytes. */
-
-  uint32_t NonVDataSegmentStartAddress;    /*!< Protected non-volatile data segment start address. This value is 24-bit long, the 8 LSB
-                                                bits are reserved and forced to 0 in order to allow a 256-byte granularity. */
-
-  uint32_t NonVDataSegmentLength;          /*!< Protected non-volatile data segment length in bytes. This value is 22-bit long, the 8 LSB
-                                                bits are reserved and forced to 0 for the length to be a multiple of 256 bytes. */
-
-  uint32_t VDataSegmentStartAddress;       /*!< Protected volatile data segment start address. This value is 17-bit long, the 6 LSB bits
-                                                are reserved and forced to 0 in order to allow a 64-byte granularity. */
-
-  uint32_t VDataSegmentLength;             /*!< Protected volatile data segment length in bytes. This value is 17-bit long, the 6 LSB
-                                                bits are reserved and forced to 0 for the length to be a multiple of 64 bytes. */
-
-  uint32_t VolatileDataExecution;          /*!< Set VDE bit specifying whether or not the volatile data segment can be executed.
-                                                 When VDS = 1 (set by parameter VolatileDataShared), VDE bit has no meaning.
-                                                This parameter can be a value of @ref FIREWALL_VolatileData_Executable */
-
-  uint32_t VolatileDataShared;             /*!< Set VDS bit in specifying whether or not the volatile data segment can be shared with a
-                                                non-protected application code.
-                                                This parameter can be a value of @ref FIREWALL_VolatileData_Shared */
-
-}FIREWALL_InitTypeDef;
-
-
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FIREWALL_Exported_Constants FIREWALL Exported Constants
-  * @{
-  */
-
-/** @defgroup FIREWALL_VolatileData_Executable   FIREWALL volatile data segment execution status
-  * @{
-  */
-#define FIREWALL_VOLATILEDATA_NOT_EXECUTABLE                 (0x0000U)
-#define FIREWALL_VOLATILEDATA_EXECUTABLE                     FW_CR_VDE
-/**
-  * @}
-  */
-
-/** @defgroup FIREWALL_VolatileData_Shared  FIREWALL volatile data segment share status
-  * @{
-  */
-#define FIREWALL_VOLATILEDATA_NOT_SHARED                (0x0000U)
-#define FIREWALL_VOLATILEDATA_SHARED                    FW_CR_VDS
-/**
-  * @}
-  */
-
-/** @defgroup FIREWALL_Pre_Arm FIREWALL pre arm status
-  * @{
-  */
-#define FIREWALL_PRE_ARM_RESET                 (0x0000U)
-#define FIREWALL_PRE_ARM_SET                   FW_CR_FPA
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup FIREWALL_Private
-  * @{
-  */
-#define IS_FIREWALL_CODE_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
-#define IS_FIREWALL_CODE_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
-
-#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
-#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
-
-#define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= SRAM_BASE) && ((ADDRESS) < (SRAM_BASE + SRAM_SIZE_MAX)))
-#define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (SRAM_BASE + SRAM_SIZE_MAX))
-
-
-#define IS_FIREWALL_VOLATILEDATA_SHARE(SHARE) (((SHARE) == FIREWALL_VOLATILEDATA_NOT_SHARED) || \
-                                               ((SHARE) == FIREWALL_VOLATILEDATA_SHARED))
-
-#define IS_FIREWALL_VOLATILEDATA_EXECUTE(EXECUTE) (((EXECUTE) == FIREWALL_VOLATILEDATA_NOT_EXECUTABLE) || \
-                                                   ((EXECUTE) == FIREWALL_VOLATILEDATA_EXECUTABLE))
-/**
-  * @}
-  */
-
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup FIREWALL_Exported_Macros FIREWALL Exported Macros
-  * @{
-  */
-
-/** @brief  Check whether the FIREWALL is enabled or not.
-  * @retval FIREWALL enabling status (TRUE or FALSE).
-  */
-#define  __HAL_FIREWALL_IS_ENABLED()  HAL_IS_BIT_CLR(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN)
-
-
-/** @brief Enable FIREWALL pre arm.
-  * @note When FPA bit is set, any code executed outside the protected segment
-  *       closes the Firewall, otherwise it generates a system reset.
-  * @note This macro provides the same service as HAL_FIREWALL_EnablePreArmFlag() API
-  *       but can be executed inside a code area protected by the Firewall.
-  * @note This macro can be executed whatever the Firewall state (opened or closed) when
-  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
-  *       0, that is, when the non volatile data segment is defined), the macro can be
-  *       executed only when the Firewall is opened.
-  */
-#define __HAL_FIREWALL_PREARM_ENABLE()                                                 \
-             do {                                                                      \
-                  __IO uint32_t tmpreg;                                                \
-                  SET_BIT(FIREWALL->CR, FW_CR_FPA) ;                                   \
-                  /* Read bit back to ensure it is taken into account by Peripheral */ \
-                  /* (introduce proper delay inside macro execution) */                \
-                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ;                         \
-                  UNUSED(tmpreg);                                                      \
-                } while(0)
-
-
-
-/** @brief Disable FIREWALL pre arm.
-  * @note When FPA bit is set, any code executed outside the protected segment
-  *       closes the Firewall, otherwise, it generates a system reset.
-  * @note This macro provides the same service as HAL_FIREWALL_DisablePreArmFlag() API
-  *       but can be executed inside a code area protected by the Firewall.
-  * @note This macro can be executed whatever the Firewall state (opened or closed) when
-  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
-  *       0, that is, when the non volatile data segment is defined), the macro can be
-  *       executed only when the Firewall is opened.
-  */
-#define __HAL_FIREWALL_PREARM_DISABLE()                                                \
-             do {                                                                      \
-                  __IO uint32_t tmpreg;                                                \
-                  CLEAR_BIT(FIREWALL->CR, FW_CR_FPA) ;                                 \
-                  /* Read bit back to ensure it is taken into account by Peripheral */ \
-                  /* (introduce proper delay inside macro execution) */                \
-                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ;                         \
-                  UNUSED(tmpreg);                                                      \
-                } while(0)
-
-/** @brief Enable volatile data sharing in setting VDS bit.
-  * @note When VDS bit is set, the volatile data segment is shared with non-protected
-  *       application code. It can be accessed whatever the Firewall state (opened or closed).
-  * @note This macro can be executed inside a code area protected by the Firewall.
-  * @note This macro can be executed whatever the Firewall state (opened or closed) when
-  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
-  *       0, that is, when the non volatile data segment is defined), the macro can be
-  *       executed only when the Firewall is opened.
-  */
-#define __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE()                                    \
-             do {                                                                      \
-                  __IO uint32_t tmpreg;                                                \
-                  SET_BIT(FIREWALL->CR, FW_CR_VDS) ;                                   \
-                  /* Read bit back to ensure it is taken into account by Peripheral */ \
-                  /* (introduce proper delay inside macro execution) */                \
-                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ;                         \
-                  UNUSED(tmpreg);                                                      \
-                } while(0)
-
-/** @brief Disable volatile data sharing in resetting VDS bit.
-  * @note When VDS bit is reset, the volatile data segment is not shared and cannot be
-  *       hit by a non protected executable code when the Firewall is closed. If it is
-  *       accessed in such a condition, a system reset is generated by the Firewall.
-  * @note This macro can be executed inside a code area protected by the Firewall.
-  * @note This macro can be executed whatever the Firewall state (opened or closed) when
-  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
-  *       0, that is, when the non volatile data segment is defined), the macro can be
-  *       executed only when the Firewall is opened.
-  */
-#define __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE()                                   \
-             do {                                                                      \
-                  __IO uint32_t tmpreg;                                                \
-                  CLEAR_BIT(FIREWALL->CR, FW_CR_VDS) ;                                 \
-                  /* Read bit back to ensure it is taken into account by Peripheral */ \
-                  /* (introduce proper delay inside macro execution) */                \
-                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ;                         \
-                  UNUSED(tmpreg);                                                      \
-                } while(0)
-
-/** @brief Enable volatile data execution in setting VDE bit.
-  * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be
-  *       executed whatever the VDE bit value.
-  * @note When VDE bit is set (with VDS = 0), the volatile data segment is executable. When
-  *       the Firewall call is closed, a "call gate" entry procedure is required to open
-  *       first the Firewall.
-  * @note This macro can be executed inside a code area protected by the Firewall.
-  * @note This macro can be executed whatever the Firewall state (opened or closed) when
-  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
-  *       0, that is, when the non volatile data segment is defined), the macro can be
-  *       executed only when the Firewall is opened.
-  */
-#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE()                                 \
-             do {                                                                      \
-                  __IO uint32_t tmpreg;                                                \
-                  SET_BIT(FIREWALL->CR, FW_CR_VDE) ;                                   \
-                  /* Read bit back to ensure it is taken into account by Peripheral */ \
-                  /* (introduce proper delay inside macro execution) */                \
-                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ;                         \
-                  UNUSED(tmpreg);                                                      \
-                } while(0)
-
-/** @brief Disable volatile data execution in resetting VDE bit.
-  * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be
-  *       executed whatever the VDE bit value.
-  * @note When VDE bit is reset (with VDS = 0), the volatile data segment cannot  be executed.
-  * @note This macro can be executed inside a code area protected by the Firewall.
-  * @note This macro can be executed whatever the Firewall state (opened or closed) when
-  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
-  *       0, that is, when the non volatile data segment is defined), the macro can be
-  *       executed only when the Firewall is opened.
-  */
-#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE()                                \
-             do {                                                                      \
-                  __IO uint32_t tmpreg;                                                \
-                  CLEAR_BIT(FIREWALL->CR, FW_CR_VDE) ;                                 \
-                  /* Read bit back to ensure it is taken into account by Peripheral */ \
-                  /* (introduce proper delay inside macro execution) */                \
-                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ;                         \
-                  UNUSED(tmpreg);                                                      \
-                } while(0)
-
-
-/** @brief Check whether or not the volatile data segment is shared.
-  * @note This macro can be executed inside a code area protected by the Firewall.
-  * @note This macro can be executed whatever the Firewall state (opened or closed) when
-  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
-  *       0, that is, when the non volatile data segment is defined), the macro can be
-  *       executed only when the Firewall is opened.
-  * @retval VDS bit setting status (TRUE or FALSE).
-  */
-#define __HAL_FIREWALL_GET_VOLATILEDATA_SHARED() ((FIREWALL->CR & FW_CR_VDS) == FW_CR_VDS)
-
-/** @brief Check whether or not the volatile data segment is declared executable.
-  * @note This macro can be executed inside a code area protected by the Firewall.
-  * @note This macro can be executed whatever the Firewall state (opened or closed) when
-  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
-  *       0, that is, when the non volatile data segment is defined), the macro can be
-  *       executed only when the Firewall is opened.
-  * @retval VDE bit setting status (TRUE or FALSE).
-  */
-#define __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION() ((FIREWALL->CR & FW_CR_VDE) == FW_CR_VDE)
-
-/** @brief Check whether or not the Firewall pre arm bit is set.
-  * @note This macro can be executed inside a code area protected by the Firewall.
-  * @note This macro can be executed whatever the Firewall state (opened or closed) when
-  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
-  *       0, that is, when the non volatile data segment is defined), the macro can be
-  *       executed only when the Firewall is opened.
-  * @retval FPA bit setting status (TRUE or FALSE).
-  */
-#define __HAL_FIREWALL_GET_PREARM() ((FIREWALL->CR & FW_CR_FPA) == FW_CR_FPA)
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup FIREWALL_Exported_Functions FIREWALL Exported Functions
-  * @{
-  */
-
-/** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions
-  * @brief    Initialization and Configuration Functions
-  * @{
-  */
-
-/* Initialization functions  ********************************/
-HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init);
-void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config);
-void HAL_FIREWALL_EnableFirewall(void);
-void HAL_FIREWALL_EnablePreArmFlag(void);
-void HAL_FIREWALL_DisablePreArmFlag(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Define the private group ***********************************/
-/**************************************************************/
-/** @defgroup FIREWALL_Private FIREWALL Private
-  * @{
-  */
-/**
-  * @}
-  */
-/**************************************************************/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-#endif /* #if !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) && !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_FIREWALL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h
deleted file mode 100644
index 8fa4b9124c..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h
+++ /dev/null
@@ -1,378 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_flash.h
-  * @author  MCD Application Team
-  * @brief   Header file of Flash HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_FLASH_H
-#define __STM32L0xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */
-
-/** @addtogroup FLASH_Private_Constants
-  * @{
-  */
-#define FLASH_TIMEOUT_VALUE      (50000U) /* 50 s */
-#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Private_Macros
-  * @{
-  */
-
-#define IS_FLASH_TYPEPROGRAM(_VALUE_)   ((_VALUE_) == FLASH_TYPEPROGRAM_WORD)
-
-#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
-                                       ((__LATENCY__) == FLASH_LATENCY_1))
-
-/**
-  * @}
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
-  * @{
-  */
-
-/**
-  * @brief  FLASH Procedure structure definition
-  */
-typedef enum
-{
-  FLASH_PROC_NONE              = 0,
-  FLASH_PROC_PAGEERASE         = 1,
-  FLASH_PROC_PROGRAM           = 2,
-} FLASH_ProcedureTypeDef;
-
-/**
-  * @brief  FLASH handle Structure definition
-  */
-typedef struct
-{
-  __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
-
-  __IO uint32_t               NbPagesToErase;   /*!< Internal variable to save the remaining sectors to erase in IT context*/
-
-  __IO uint32_t               Address;          /*!< Internal variable to save address selected for program or erase */
-
-  __IO uint32_t               Page;             /*!< Internal variable to define the current page which is erasing */
-
-  HAL_LockTypeDef             Lock;             /*!< FLASH locking object                */
-
-  __IO uint32_t               ErrorCode;        /*!< FLASH error code
-                                                     This parameter can be a value of @ref FLASH_Error_Codes  */
-} FLASH_ProcessTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
-  * @{
-  */
-
-/** @defgroup FLASH_Error_Codes FLASH Error Codes
-  * @{
-  */
-
-#define HAL_FLASH_ERROR_NONE      0x00U  /*!< No error */
-#define HAL_FLASH_ERROR_PGA       0x01U  /*!< Programming alignment error */
-#define HAL_FLASH_ERROR_WRP       0x02U  /*!< Write protection error */
-#define HAL_FLASH_ERROR_OPTV      0x04U  /*!< Option validity error */
-#define HAL_FLASH_ERROR_SIZE      0x08U  /*!<  */
-#define HAL_FLASH_ERROR_RD        0x10U  /*!< Read protected error */
-#define HAL_FLASH_ERROR_FWWERR    0x20U  /*!< FLASH Write or Erase operation aborted */
-#define HAL_FLASH_ERROR_NOTZERO   0x40U  /*!< FLASH Write operation is done in a not-erased region */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Page_Size FLASH size information
-  * @{
-  */
-
-#define FLASH_SIZE                (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFF) * 1024U)
-#define FLASH_PAGE_SIZE           (128U)  /*!< FLASH Page Size in bytes */
-
-#define FLASH_END                 (FLASH_BASE + FLASH_SIZE - 1)    /*!< FLASH end address in the alias region */
-
-#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define FLASH_BANK2_BASE          (FLASH_BASE + (FLASH_SIZE >> 1)) /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END           (FLASH_BANK2_BASE - 1)           /*!< Program end FLASH BANK1 address */
-#define FLASH_BANK2_END           (FLASH_END)                      /*!< Program end FLASH BANK2 address */
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Type_Program FLASH Type Program
-  * @{
-  */
-#define FLASH_TYPEPROGRAM_WORD       (0x02U)  /*!<Program a word (32-bit) at a specified address.*/
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Latency FLASH Latency
-  * @{
-  */
-#define FLASH_LATENCY_0            (0x00000000U)    /*!< FLASH Zero Latency cycle */
-#define FLASH_LATENCY_1            FLASH_ACR_LATENCY         /*!< FLASH One Latency cycle */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Interrupts FLASH Interrupts
-  * @{
-  */
-
-#define FLASH_IT_EOP               FLASH_PECR_EOPIE  /*!< End of programming interrupt source */
-#define FLASH_IT_ERR               FLASH_PECR_ERRIE  /*!< Error interrupt source */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Flags FLASH Flags
-  * @{
-  */
-
-#define FLASH_FLAG_BSY             FLASH_SR_BSY        /*!< FLASH Busy flag */
-#define FLASH_FLAG_EOP             FLASH_SR_EOP        /*!< FLASH End of Programming flag */
-#define FLASH_FLAG_ENDHV           FLASH_SR_HVOFF      /*!< FLASH End of High Voltage flag */
-#define FLASH_FLAG_READY           FLASH_SR_READY      /*!< FLASH Ready flag after low power mode */
-#define FLASH_FLAG_WRPERR          FLASH_SR_WRPERR     /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_PGAERR          FLASH_SR_PGAERR     /*!< FLASH Programming Alignment error flag */
-#define FLASH_FLAG_SIZERR          FLASH_SR_SIZERR     /*!< FLASH Size error flag  */
-#define FLASH_FLAG_OPTVERR         FLASH_SR_OPTVERR    /*!< FLASH Option Validity error flag  */
-#define FLASH_FLAG_RDERR           FLASH_SR_RDERR      /*!< FLASH Read protected error flag */
-#define FLASH_FLAG_FWWERR          FLASH_SR_FWWERR     /*!< FLASH Write or Errase operation aborted */
-#define FLASH_FLAG_NOTZEROERR      FLASH_SR_NOTZEROERR /*!< FLASH Read protected error flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Keys FLASH Keys
-  * @{
-  */
-
-#define FLASH_PDKEY1               (0x04152637U) /*!< Flash power down key1 */
-#define FLASH_PDKEY2               (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
-                                                    to unlock the RUN_PD bit in FLASH_ACR */
-
-#define FLASH_PEKEY1               (0x89ABCDEFU) /*!< Flash program erase key1 */
-#define FLASH_PEKEY2               (0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2
-                                                     to unlock the write access to the FLASH_PECR register and
-                                                     data EEPROM */
-
-#define FLASH_PRGKEY1              (0x8C9DAEBFU) /*!< Flash program memory key1 */
-#define FLASH_PRGKEY2              (0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2
-                                                     to unlock the program memory */
-
-#define FLASH_OPTKEY1              (0xFBEAD9C8U) /*!< Flash option key1 */
-#define FLASH_OPTKEY2              (0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to
-                                                              unlock the write access to the option byte block */
-/**
-  * @}
-  */
-
-/* CMSIS_Legacy */
-
-#if defined ( __ICCARM__ )
-#define InterruptType_ACTLR_DISMCYCINT_Msk         IntType_ACTLR_DISMCYCINT_Msk
-#endif
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
- *  @brief macros to control FLASH features
- *  @{
- */
-
-
-/** @defgroup FLASH_Interrupt FLASH Interrupts
- *  @brief macros to handle FLASH interrupts
- * @{
- */
-
-/**
-  * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__  FLASH interrupt
-  *         This parameter can be any combination of the following values:
-  *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
-  *     @arg @ref FLASH_IT_ERR Error Interrupt
-  * @retval none
-  */
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  SET_BIT((FLASH->PECR), (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__  FLASH interrupt
-  *         This parameter can be any combination of the following values:
-  *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
-  *     @arg @ref FLASH_IT_ERR Error Interrupt
-  * @retval none
-  */
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT((FLASH->PECR), (uint32_t)(__INTERRUPT__))
-
-/**
-  * @brief  Get the specified FLASH flag status.
-  * @param  __FLAG__ specifies the FLASH flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref FLASH_FLAG_BSY         FLASH Busy flag
-  *            @arg @ref FLASH_FLAG_EOP         FLASH End of Operation flag
-  *            @arg @ref FLASH_FLAG_ENDHV       FLASH End of High Voltage flag
-  *            @arg @ref FLASH_FLAG_READY       FLASH Ready flag after low power mode
-  *            @arg @ref FLASH_FLAG_PGAERR      FLASH Programming Alignment error flag
-  *            @arg @ref FLASH_FLAG_SIZERR      FLASH Size error flag
-  *            @arg @ref FLASH_FLAG_OPTVERR     FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx)
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read protected error flag
-  *            @arg @ref FLASH_FLAG_WRPERR      FLASH Write protected error flag
-  *            @arg @ref FLASH_FLAG_FWWERR      FLASH Fetch While Write Error flag
-  *            @arg @ref FLASH_FLAG_NOTZEROERR  Not Zero area error flag
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_FLASH_GET_FLAG(__FLAG__)   (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clear the specified FLASH flag.
-  * @param  __FLAG__ specifies the FLASH flags to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref FLASH_FLAG_EOP         FLASH End of Operation flag
-  *            @arg @ref FLASH_FLAG_PGAERR      FLASH Programming Alignment error flag
-  *            @arg @ref FLASH_FLAG_SIZERR      FLASH Size error flag
-  *            @arg @ref FLASH_FLAG_OPTVERR     FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx)
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read protected error flag
-  *            @arg @ref FLASH_FLAG_WRPERR      FLASH Write protected error flag
-  *            @arg @ref FLASH_FLAG_FWWERR      FLASH Fetch While Write Error flag
-  *            @arg @ref FLASH_FLAG_NOTZEROERR  Not Zero area error flag
-  * @retval none
-  */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   ((FLASH->SR) = (__FLAG__))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Include FLASH HAL Extended module */
-#include "stm32l0xx_hal_flash_ex.h"
-#include "stm32l0xx_hal_flash_ramfunc.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group1
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
-
-/* FLASH IRQ handler function */
-void       HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */
-void       HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void       HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-uint32_t HAL_FLASH_GetError(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private function -------------------------------------------------*/
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-HAL_StatusTypeDef       FLASH_WaitForLastOperation(uint32_t Timeout);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_FLASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h
deleted file mode 100644
index a971a42d72..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h
+++ /dev/null
@@ -1,811 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_flash_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of Flash HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_FLASH_EX_H
-#define __STM32L0xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASHEx
-  * @{
-  */
-
-/** @addtogroup FLASHEx_Private_Constants
-  * @{
-  */
-#define FLASH_SIZE_DATA_REGISTER   FLASHSIZE_BASE
-
-#define FLASH_NBPAGES_MAX (FLASH_SIZE / FLASH_PAGE_SIZE)
-
-#define WRP_MASK_LOW                 (0x0000FFFFU)
-#define WRP_MASK_HIGH                (0xFFFF0000U)
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASHEx_Private_Macros
-  * @{
-  */
-
-#define IS_FLASH_TYPEERASE(__VALUE__)   (((__VALUE__) == FLASH_TYPEERASE_PAGES))
-
-#define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP  | OPTIONBYTE_RDP | \
-                                                  OPTIONBYTE_USER | OPTIONBYTE_BOR | OPTIONBYTE_BOOT_BIT1)))
-
-#define IS_WRPSTATE(__VALUE__)          (((__VALUE__) == OB_WRPSTATE_DISABLE) || \
-                                         ((__VALUE__) == OB_WRPSTATE_ENABLE))
-
-#define IS_OB_WRP(__PAGE__)             (((__PAGE__) != 0x0000000U))
-
-#define IS_OB_RDP(__LEVEL__)            (((__LEVEL__) == OB_RDP_LEVEL_0) ||\
-                                         ((__LEVEL__) == OB_RDP_LEVEL_1) ||\
-                                         ((__LEVEL__) == OB_RDP_LEVEL_2))
-
-#define IS_OB_BOR_LEVEL(__LEVEL__)      (((__LEVEL__) == OB_BOR_OFF)     || \
-                                         ((__LEVEL__) == OB_BOR_LEVEL1)  || \
-                                         ((__LEVEL__) == OB_BOR_LEVEL2)  || \
-                                         ((__LEVEL__) == OB_BOR_LEVEL3)  || \
-                                         ((__LEVEL__) == OB_BOR_LEVEL4)  || \
-                                         ((__LEVEL__) == OB_BOR_LEVEL5))
-
-#define IS_OB_IWDG_SOURCE(__SOURCE__)   (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))
-
-#define IS_OB_STOP_SOURCE(__SOURCE__)   (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))
-
-#define IS_OB_STDBY_SOURCE(__SOURCE__)  (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
-
-#if defined(FLASH_OPTR_WPRMOD) && defined(FLASH_OPTR_BFB2)
-
-#define IS_OBEX(__VALUE__)              (((__VALUE__) <= (OPTIONBYTE_PCROP | OPTIONBYTE_BOOTCONFIG)) && ((__VALUE__) != 0U))
-
-#elif defined(FLASH_OPTR_WPRMOD) && !defined(FLASH_OPTR_BFB2)
-
-#define IS_OBEX(__VALUE__)              ((__VALUE__) == OPTIONBYTE_PCROP)
-
-#elif !defined(FLASH_OPTR_WPRMOD) && defined(FLASH_OPTR_BFB2)
-
-#define IS_OBEX(__VALUE__)              ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)
-
-#endif /* FLASH_OPTR_WPRMOD && FLASH_OPTR_BFB2 */
-
-#if defined(FLASH_OPTR_WPRMOD)
-
-#define IS_PCROPSTATE(__VALUE__)        (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \
-                                         ((__VALUE__) == OB_PCROP_STATE_ENABLE))
-
-#define IS_OB_PCROP(__PAGE__)           (((__PAGE__) != 0x0000000U))
-#endif /* FLASH_OPTR_WPRMOD */
-
-#if defined(FLASH_OPTR_BFB2)
-
-#define IS_OB_BOOT_BANK(__BANK__)     (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
-
-#endif /* FLASH_OPTR_BFB2 */
-
-#define IS_OB_BOOT1(__BOOT_BIT1__)  (((__BOOT_BIT1__) == OB_BOOT_BIT1_RESET) || ((__BOOT_BIT1__) == OB_BOOT_BIT1_SET))
-#define IS_TYPEPROGRAMDATA(__VALUE__)   (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE)     || \
-                                         ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
-                                         ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD))
-
-
-/** @defgroup FLASHEx_Address FLASHEx Address
-  * @{
-  */
-
-#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-
-#define IS_FLASH_DATA_ADDRESS(__ADDRESS__)          (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END))
-#define IS_FLASH_DATA_BANK1_ADDRESS(__ADDRESS__)    (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK1_END))
-#define IS_FLASH_DATA_BANK2_ADDRESS(__ADDRESS__)    (((__ADDRESS__) >= DATA_EEPROM_BANK2_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END))
-#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__)       (((__ADDRESS__) >= FLASH_BASE)       && ((__ADDRESS__) <  (FLASH_BASE + FLASH_SIZE)))
-#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE)       && ((__ADDRESS__) <  (FLASH_BASE + (FLASH_SIZE >> 1))))
-#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <  (FLASH_BASE + FLASH_SIZE)))
-#else
-#define IS_FLASH_DATA_ADDRESS(__ADDRESS__)          (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_END))
-#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__)       (((__ADDRESS__) >= FLASH_BASE)       && ((__ADDRESS__) <  (FLASH_BASE + FLASH_SIZE)))
-#endif
-
-#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  FLASH Erase structure definition
-  */
-typedef struct
-{
-  uint32_t TypeErase;   /*!< TypeErase: Page Erase only.
-                             This parameter can be a value of @ref FLASHEx_Type_Erase */
-
-  uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased
-                             This parameter must be a value belonging to FLASH Programm address (depending on the devices)  */
-
-  uint32_t NbPages;     /*!< NbPages: Number of pages to be erased.
-                             This parameter must be a value between 1 and (max number of pages - value of Initial page)*/
-
-} FLASH_EraseInitTypeDef;
-
-/**
-  * @brief  FLASH Option Bytes PROGRAM structure definition
-  */
-typedef struct
-{
-  uint32_t  OptionType;       /*!< OptionType: Option byte to be configured.
-                                   This parameter can be a value of @ref FLASHEx_Option_Type */
-
-  uint32_t  WRPState;         /*!< WRPState: Write protection activation or deactivation.
-                                   This parameter can be a value of @ref FLASHEx_WRP_State */
-
-  uint32_t WRPSector;         /*!< WRPSector: This bitfield specifies the sector (s) which are write protected.
-                                   This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection */
-
-#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
-  uint32_t WRPSector2;        /*!< WRPSector2 : This bitfield specifies the sector(s) upper Sector31 which are write protected.
-                                   This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */
-#endif
-
-  uint8_t   RDPLevel;         /*!< RDPLevel: Set the read protection level.
-                                   This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
-
-  uint8_t   BORLevel;         /*!< BORLevel: Set the BOR Level.
-                                   This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */
-
-  uint8_t   USERConfig;       /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-                                   This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog,
-                                   @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
-
-  uint8_t BOOTBit1Config;     /*!< BOOT1Config: Together with input pad Boot0, this bit selects the boot source, flash, ram or system memory
-                                   This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOTBit1 */
-} FLASH_OBProgramInitTypeDef;
-
-#if defined(FLASH_OPTR_WPRMOD) || defined(FLASH_OPTR_BFB2)
-/**
-  * @brief  FLASH Advanced Option Bytes Program structure definition
-  */
-typedef struct
-{
-  uint32_t OptionType;          /*!< OptionType: Option byte to be configured for extension .
-                                     This parameter can be a value of @ref FLASHEx_OptionAdv_Type */
-
-#if defined(FLASH_OPTR_WPRMOD)
-  uint32_t PCROPState;          /*!< PCROPState: PCROP activation or deactivation.
-                                     This parameter can be a value of @ref FLASHEx_PCROP_State */
-
-  uint32_t PCROPSector;        /*!< PCROPSector : This bitfield specifies the sector(s) which are read/write protected.
-                                    This parameter can be a combination of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
-
-#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-  uint32_t PCROPSector2;       /*!< PCROPSector : This bitfield specifies the sector(s) upper Sector31 which are read/write protected.
-                                    This parameter can be a combination of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */
-#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
-#endif /* FLASH_OPTR_WPRMOD */
-
-#if defined(FLASH_OPTR_BFB2)
-  uint16_t BootConfig;          /*!< BootConfig: specifies Option bytes for boot config
-                                     This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */
-#endif /* FLASH_OPTR_BFB2*/
-} FLASH_AdvOBProgramInitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* FLASH_OPTR_WPRMOD || FLASH_OPTR_BFB2 */
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
-  * @{
-  */
-
-/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
-  * @{
-  */
-#define FLASH_TYPEERASE_PAGES           (0x00U)  /*!<Page erase only*/
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Type FLASHEx Option Type
-  * @{
-  */
-#define OPTIONBYTE_WRP            (0x01U)  /*!<WRP option byte configuration*/
-#define OPTIONBYTE_RDP            (0x02U)  /*!<RDP option byte configuration*/
-#define OPTIONBYTE_USER           (0x04U)  /*!<USER option byte configuration*/
-#define OPTIONBYTE_BOR            (0x08U)  /*!<BOR option byte configuration*/
-#define OPTIONBYTE_BOOT_BIT1      (0x10U)  /*!< BOOT PIN1 option byte configuration*/
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_WRP_State FLASHEx WRP State
-  * @{
-  */
-#define OB_WRPSTATE_DISABLE        (0x00U)  /*!<Disable the write protection of the desired sectors*/
-#define OB_WRPSTATE_ENABLE         (0x01U)  /*!<Enable the write protection of the desired sectors*/
-
-/**
-  * @}
-  */
-
-#if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx)
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
-  * @{
-  */
-#define OB_WRP_Pages0to31          (0x00000001U) /* Write protection of Sector0 */
-#define OB_WRP_Pages32to63         (0x00000002U) /* Write protection of Sector1 */
-#define OB_WRP_Pages64to95         (0x00000004U) /* Write protection of Sector2 */
-#define OB_WRP_Pages96to127        (0x00000008U) /* Write protection of Sector3 */
-#define OB_WRP_Pages128to159       (0x00000010U) /* Write protection of Sector4 */
-#define OB_WRP_Pages160to191       (0x00000020U) /* Write protection of Sector5 */
-#define OB_WRP_Pages192to223       (0x00000040U) /* Write protection of Sector6 */
-#define OB_WRP_Pages224to255       (0x00000080U) /* Write protection of Sector7 */
-#define OB_WRP_AllPages            (0x000000FFU) /*!< Write protection of all Sectors */
-/**
-  * @}
-  */
-#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx)
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
-  * @{
-  */
-#define OB_WRP_Pages0to31          (0x00000001U) /* Write protection of Sector0 */
-#define OB_WRP_Pages32to63         (0x00000002U) /* Write protection of Sector1 */
-#define OB_WRP_Pages64to95         (0x00000004U) /* Write protection of Sector2 */
-#define OB_WRP_Pages96to127        (0x00000008U) /* Write protection of Sector3 */
-#define OB_WRP_Pages128to159       (0x00000010U) /* Write protection of Sector4 */
-#define OB_WRP_Pages160to191       (0x00000020U) /* Write protection of Sector5 */
-#define OB_WRP_Pages192to223       (0x00000040U) /* Write protection of Sector6 */
-#define OB_WRP_Pages224to255       (0x00000080U) /* Write protection of Sector7 */
-#define OB_WRP_Pages256to287       (0x00000100U) /* Write protection of Sector8 */
-#define OB_WRP_Pages288to319       (0x00000200U) /* Write protection of Sector9 */
-#define OB_WRP_Pages320to351       (0x00000400U) /* Write protection of Sector10 */
-#define OB_WRP_Pages352to383       (0x00000800U) /* Write protection of Sector11 */
-#define OB_WRP_Pages384to415       (0x00001000U) /* Write protection of Sector12 */
-#define OB_WRP_Pages416to447       (0x00002000U) /* Write protection of Sector13 */
-#define OB_WRP_Pages448to479       (0x00004000U) /* Write protection of Sector14 */
-#define OB_WRP_Pages480to511       (0x00008000U) /* Write protection of Sector15 */
-#define OB_WRP_AllPages            (0x0000FFFFU) /*!< Write protection of all Sectors */
-/**
-  * @}
-  */
-
-#elif defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write ProtectionP
-  * @{
-  */
-#define OB_WRP_Pages0to31          (0x00000001U) /* Write protection of Sector0 */
-#define OB_WRP_Pages32to63         (0x00000002U) /* Write protection of Sector1 */
-#define OB_WRP_Pages64to95         (0x00000004U) /* Write protection of Sector2 */
-#define OB_WRP_Pages96to127        (0x00000008U) /* Write protection of Sector3 */
-#define OB_WRP_Pages128to159       (0x00000010U) /* Write protection of Sector4 */
-#define OB_WRP_Pages160to191       (0x00000020U) /* Write protection of Sector5 */
-#define OB_WRP_Pages192to223       (0x00000040U) /* Write protection of Sector6 */
-#define OB_WRP_Pages224to255       (0x00000080U) /* Write protection of Sector7 */
-#define OB_WRP_Pages256to287       (0x00000100U) /* Write protection of Sector8 */
-#define OB_WRP_Pages288to319       (0x00000200U) /* Write protection of Sector9 */
-#define OB_WRP_Pages320to351       (0x00000400U) /* Write protection of Sector10 */
-#define OB_WRP_Pages352to383       (0x00000800U) /* Write protection of Sector11 */
-#define OB_WRP_Pages384to415       (0x00001000U) /* Write protection of Sector12 */
-#define OB_WRP_Pages416to447       (0x00002000U) /* Write protection of Sector13 */
-#define OB_WRP_Pages448to479       (0x00004000U) /* Write protection of Sector14 */
-#define OB_WRP_Pages480to511       (0x00008000U) /* Write protection of Sector15 */
-#define OB_WRP_Pages512to543       (0x00010000U) /* Write protection of Sector16 */
-#define OB_WRP_Pages544to575       (0x00020000U) /* Write protection of Sector17 */
-#define OB_WRP_Pages576to607       (0x00040000U) /* Write protection of Sector18 */
-#define OB_WRP_Pages608to639       (0x00080000U) /* Write protection of Sector19 */
-#define OB_WRP_Pages640to671       (0x00100000U) /* Write protection of Sector20 */
-#define OB_WRP_Pages672to703       (0x00200000U) /* Write protection of Sector21 */
-#define OB_WRP_Pages704to735       (0x00400000U) /* Write protection of Sector22 */
-#define OB_WRP_Pages736to767       (0x00800000U) /* Write protection of Sector23 */
-#define OB_WRP_Pages768to799       (0x01000000U) /* Write protection of Sector24 */
-#define OB_WRP_Pages800to831       (0x02000000U) /* Write protection of Sector25 */
-#define OB_WRP_Pages832to863       (0x04000000U) /* Write protection of Sector26 */
-#define OB_WRP_Pages864to895       (0x08000000U) /* Write protection of Sector27 */
-#define OB_WRP_Pages896to927       (0x10000000U) /* Write protection of Sector28 */
-#define OB_WRP_Pages928to959       (0x20000000U) /* Write protection of Sector29 */
-#define OB_WRP_Pages960to991       (0x40000000U) /* Write protection of Sector30 */
-#define OB_WRP_Pages992to1023      (0x80000000U) /* Write protection of Sector31 */
-#define OB_WRP_AllPages            (0xFFFFFFFFU) /*!<Write  protection of all Sectors */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASH Option Bytes Write Protection
-  * @{
-  */
-#define OB_WRP2_Pages1024to1055    (0x00000001U) /* Write protection of Sector32 */
-#define OB_WRP2_Pages1056to1087    (0x00000002U) /* Write protection of Sector33 */
-#define OB_WRP2_Pages1088to1119    (0x00000004U) /* Write protection of Sector34 */
-#define OB_WRP2_Pages1120to1151    (0x00000008U) /* Write protection of Sector35 */
-#define OB_WRP2_Pages1152to1183    (0x00000010U) /* Write protection of Sector36 */
-#define OB_WRP2_Pages1184to1215    (0x00000020U) /* Write protection of Sector37 */
-#define OB_WRP2_Pages1216to1247    (0x00000040U) /* Write protection of Sector38 */
-#define OB_WRP2_Pages1248to1279    (0x00000080U) /* Write protection of Sector39 */
-#define OB_WRP2_Pages1280to1311    (0x00000100U) /* Write protection of Sector40 */
-#define OB_WRP2_Pages1312to1343    (0x00000200U) /* Write protection of Sector41 */
-#define OB_WRP2_Pages1344to1375    (0x00000400U) /* Write protection of Sector42 */
-#define OB_WRP2_Pages1376to1407    (0x00000800U) /* Write protection of Sector43 */
-#define OB_WRP2_Pages1408to1439    (0x00001000U) /* Write protection of Sector44 */
-#define OB_WRP2_Pages1440to1471    (0x00002000U) /* Write protection of Sector45 */
-#define OB_WRP2_Pages1472to1503    (0x00004000U) /* Write protection of Sector46 */
-#define OB_WRP2_Pages1504to1535    (0x00008000U) /* Write protection of Sector47 */
-#define OB_WRP2_AllPages           (0x0000FFFFU) /*!< Write protection of all Sectors WRP2 */
-/**
-  * @}
-  */
-#endif /* STM32L071xx || STM32L072xx || (STM32L073xx) || (STM32L081xx) || (STM32L082xx) || (STM32L083xx) */
-
-/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
-  * @{
-  */
-#define OB_RDP_LEVEL_0         ((uint8_t)0xAA)
-#define OB_RDP_LEVEL_1         ((uint8_t)0xBB)
-#define OB_RDP_LEVEL_2         ((uint8_t)0xCC) /* Warning: When enabling read protection level 2
-                                                it is no more possible to go back to level 1 or 0 */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level
-  * @{
-  */
-
-#define OB_BOR_OFF       ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD
-                                             power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
-#define OB_BOR_LEVEL1    ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply    */
-#define OB_BOR_LEVEL2    ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply    */
-#define OB_BOR_LEVEL3    ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply    */
-#define OB_BOR_LEVEL4    ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply  */
-#define OB_BOR_LEVEL5    ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply    */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog
-  * @{
-  */
-
-#define OB_IWDG_SW                     ((uint8_t)0x10)  /*!< Software WDG selected */
-#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware WDG selected */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP
-  * @{
-  */
-
-#define OB_STOP_NORST                  ((uint8_t)0x20) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY
-  * @{
-  */
-
-#define OB_STDBY_NORST                 ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-
-/**
-  * @}
-  */
-
-#if defined(FLASH_OPTR_WPRMOD)
-
-/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
-  * @{
-  */
-
-#define OPTIONBYTE_PCROP        (0x01U)  /*!<PCROP option byte configuration*/
-
-/**
-  * @}
-  */
-
-#endif /* FLASH_OPTR_WPRMOD */
-
-#if defined(FLASH_OPTR_BFB2)
-
-/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
-  * @{
-  */
-
-#define OPTIONBYTE_BOOTCONFIG   (0x02U)  /*!<BOOTConfig option byte configuration*/
-
-/**
-  * @}
-  */
-
-#endif /* FLASH_OPTR_BFB2 */
-
-#if defined(FLASH_OPTR_WPRMOD)
-
-/** @defgroup  FLASHEx_PCROP_State FLASHEx PCROP State
-  * @{
-  */
-#define OB_PCROP_STATE_DISABLE        (0x00U)  /*!<Disable PCROP for selected sectors */
-#define OB_PCROP_STATE_ENABLE         (0x01U)  /*!<Enable PCROP for selected sectors */
-
-/**
-  * @}
-  */
-
-/** @defgroup  FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode
-  * @{
-  */
-#define OB_PCROP_DESELECTED     ((uint16_t)0x0000)            /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */
-#define OB_PCROP_SELECTED       ((uint16_t)FLASH_OPTR_WPRMOD)  /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i   */
-
-/**
-  * @}
-  */
-#endif /* FLASH_OPTR_WPRMOD */
-
-#if defined (STM32L011xx) || defined (STM32L021xx) ||  defined (STM32L031xx) || defined (STM32L041xx)
-/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection
-  * @{
-  */
-#define OB_PCROP_Pages0to31          (0x00000001U) /* PC Read/Write protection of Sector0 */
-#define OB_PCROP_Pages32to63         (0x00000002U) /* PC Read/Write protection of Sector1 */
-#define OB_PCROP_Pages64to95         (0x00000004U) /* PC Read/Write protection of Sector2 */
-#define OB_PCROP_Pages96to127        (0x00000008U) /* PC Read/Write protection of Sector3 */
-#define OB_PCROP_Pages128to159       (0x00000010U) /* PC Read/Write protection of Sector4 */
-#define OB_PCROP_Pages160to191       (0x00000020U) /* PC Read/Write protection of Sector5 */
-#define OB_PCROP_Pages192to223       (0x00000040U) /* PC Read/Write protection of Sector6 */
-#define OB_PCROP_Pages224to255       (0x00000080U) /* PC Read/Write protection of Sector7 */
-#define OB_PCROP_AllPages            (0x000000FFU) /*!< PC Read/Write protection of all Sectors */
-/**
-  * @}
-  */
-#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx)
-/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection
-  * @{
-  */
-#define OB_PCROP_Pages0to31          (0x00000001U) /* PC Read/Write protection of Sector0 */
-#define OB_PCROP_Pages32to63         (0x00000002U) /* PC Read/Write protection of Sector1 */
-#define OB_PCROP_Pages64to95         (0x00000004U) /* PC Read/Write protection of Sector2 */
-#define OB_PCROP_Pages96to127        (0x00000008U) /* PC Read/Write protection of Sector3 */
-#define OB_PCROP_Pages128to159       (0x00000010U) /* PC Read/Write protection of Sector4 */
-#define OB_PCROP_Pages160to191       (0x00000020U) /* PC Read/Write protection of Sector5 */
-#define OB_PCROP_Pages192to223       (0x00000040U) /* PC Read/Write protection of Sector6 */
-#define OB_PCROP_Pages224to255       (0x00000080U) /* PC Read/Write protection of Sector7 */
-#define OB_PCROP_Pages256to287       (0x00000100U) /* PC Read/Write protection of Sector8 */
-#define OB_PCROP_Pages288to319       (0x00000200U) /* PC Read/Write protection of Sector9 */
-#define OB_PCROP_Pages320to351       (0x00000400U) /* PC Read/Write protection of Sector10 */
-#define OB_PCROP_Pages352to383       (0x00000800U) /* PC Read/Write protection of Sector11 */
-#define OB_PCROP_Pages384to415       (0x00001000U) /* PC Read/Write protection of Sector12 */
-#define OB_PCROP_Pages416to447       (0x00002000U) /* PC Read/Write protection of Sector13 */
-#define OB_PCROP_Pages448to479       (0x00004000U) /* PC Read/Write protection of Sector14 */
-#define OB_PCROP_Pages480to511       (0x00008000U) /* PC Read/Write protection of Sector15 */
-#define OB_PCROP_AllPages            (0x0000FFFFU) /*!< PC Read/Write protection of all Sectors */
-/**
-  * @}
-  */
-#endif
-
-#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC Read/Write Protection
-  * @{
-  */
-#define OB_PCROP_Pages0to31          (0x00000001U) /* PC Read/Write protection of Sector0 */
-#define OB_PCROP_Pages32to63         (0x00000002U) /* PC Read/Write protection of Sector1 */
-#define OB_PCROP_Pages64to95         (0x00000004U) /* PC Read/Write protection of Sector2 */
-#define OB_PCROP_Pages96to127        (0x00000008U) /* PC Read/Write protection of Sector3 */
-#define OB_PCROP_Pages128to159       (0x00000010U) /* PC Read/Write protection of Sector4 */
-#define OB_PCROP_Pages160to191       (0x00000020U) /* PC Read/Write protection of Sector5 */
-#define OB_PCROP_Pages192to223       (0x00000040U) /* PC Read/Write protection of Sector6 */
-#define OB_PCROP_Pages224to255       (0x00000080U) /* PC Read/Write protection of Sector7 */
-#define OB_PCROP_Pages256to287       (0x00000100U) /* PC Read/Write protection of Sector8 */
-#define OB_PCROP_Pages288to319       (0x00000200U) /* PC Read/Write protection of Sector9 */
-#define OB_PCROP_Pages320to351       (0x00000400U) /* PC Read/Write protection of Sector10 */
-#define OB_PCROP_Pages352to383       (0x00000800U) /* PC Read/Write protection of Sector11 */
-#define OB_PCROP_Pages384to415       (0x00001000U) /* PC Read/Write protection of Sector12 */
-#define OB_PCROP_Pages416to447       (0x00002000U) /* PC Read/Write protection of Sector13 */
-#define OB_PCROP_Pages448to479       (0x00004000U) /* PC Read/Write protection of Sector14 */
-#define OB_PCROP_Pages480to511       (0x00008000U) /* PC Read/Write protection of Sector15 */
-#define OB_PCROP_Pages512to543       (0x00010000U) /* PC Read/Write protection of Sector16 */
-#define OB_PCROP_Pages544to575       (0x00020000U) /* PC Read/Write protection of Sector17 */
-#define OB_PCROP_Pages576to607       (0x00040000U) /* PC Read/Write protection of Sector18 */
-#define OB_PCROP_Pages608to639       (0x00080000U) /* PC Read/Write protection of Sector19 */
-#define OB_PCROP_Pages640to671       (0x00100000U) /* PC Read/Write protection of Sector20 */
-#define OB_PCROP_Pages672to703       (0x00200000U) /* PC Read/Write protection of Sector21 */
-#define OB_PCROP_Pages704to735       (0x00400000U) /* PC Read/Write protection of Sector22 */
-#define OB_PCROP_Pages736to767       (0x00800000U) /* PC Read/Write protection of Sector23 */
-#define OB_PCROP_Pages768to799       (0x01000000U) /* PC Read/Write protection of Sector24 */
-#define OB_PCROP_Pages800to831       (0x02000000U) /* PC Read/Write protection of Sector25 */
-#define OB_PCROP_Pages832to863       (0x04000000U) /* PC Read/Write protection of Sector26 */
-#define OB_PCROP_Pages864to895       (0x08000000U) /* PC Read/Write protection of Sector27 */
-#define OB_PCROP_Pages896to927       (0x10000000U) /* PC Read/Write protection of Sector28 */
-#define OB_PCROP_Pages928to959       (0x20000000U) /* PC Read/Write protection of Sector29 */
-#define OB_PCROP_Pages960to991       (0x40000000U) /* PC Read/Write protection of Sector30 */
-#define OB_PCROP_Pages992to1023      (0x80000000U) /* PC Read/Write protection of Sector31 */
-#define OB_PCROP_AllPages            (0xFFFFFFFFU) /*!<PC Read/Write  protection of all Sectors */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASH Option Bytes PC Read/Write Protection (Sector 2)
-  * @{
-  */
-#define OB_PCROP2_Pages1024to1055    (0x00000001U) /* PC Read/Write protection of Sector32 */
-#define OB_PCROP2_Pages1056to1087    (0x00000002U) /* PC Read/Write protection of Sector33 */
-#define OB_PCROP2_Pages1088to1119    (0x00000004U) /* PC Read/Write protection of Sector34 */
-#define OB_PCROP2_Pages1120to1151    (0x00000008U) /* PC Read/Write protection of Sector35 */
-#define OB_PCROP2_Pages1152to1183    (0x00000010U) /* PC Read/Write protection of Sector36 */
-#define OB_PCROP2_Pages1184to1215    (0x00000020U) /* PC Read/Write protection of Sector37 */
-#define OB_PCROP2_Pages1216to1247    (0x00000040U) /* PC Read/Write protection of Sector38 */
-#define OB_PCROP2_Pages1248to1279    (0x00000080U) /* PC Read/Write protection of Sector39 */
-#define OB_PCROP2_Pages1280to1311    (0x00000100U) /* PC Read/Write protection of Sector40 */
-#define OB_PCROP2_Pages1312to1343    (0x00000200U) /* PC Read/Write protection of Sector41 */
-#define OB_PCROP2_Pages1344to1375    (0x00000400U) /* PC Read/Write protection of Sector42 */
-#define OB_PCROP2_Pages1376to1407    (0x00000800U) /* PC Read/Write protection of Sector43 */
-#define OB_PCROP2_Pages1408to1439    (0x00001000U) /* PC Read/Write protection of Sector44 */
-#define OB_PCROP2_Pages1440to1471    (0x00002000U) /* PC Read/Write protection of Sector45 */
-#define OB_PCROP2_Pages1472to1503    (0x00004000U) /* PC Read/Write protection of Sector46 */
-#define OB_PCROP2_Pages1504to1535    (0x00008000U) /* PC Read/Write protection of Sector47 */
-#define OB_PCROP2_AllPages           (0x0000FFFFU) /*!< PC Read/Write protection of all Sectors PCROP2 */
-/**
-  * @}
-  */
-#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
-
-/** @defgroup FLASHEx_Option_Bytes_BOOTBit1 FLASH Option Bytes BOOT Bit1 Setup
-  * @{
-  */
-#define OB_BOOT_BIT1_RESET      (uint8_t)(0x00) /*!< BOOT Bit 1 Reset */
-#define OB_BOOT_BIT1_SET        (uint8_t)(0x01) /*!< BOOT Bit 1 Set */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
-  * @{
-  */
-#define FLASH_TYPEPROGRAMDATA_BYTE            (0x00U)  /*!<Program byte (8-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAMDATA_HALFWORD        (0x01U)  /*!<Program a half-word (16-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAMDATA_WORD            (0x02U)  /*!<Program a word (32-bit) at a specified address.*/
-
-/**
-  * @}
-  */
-
-#if defined(FLASH_OPTR_BFB2)
-
-/** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT
-  * @{
-  */
-
-#define OB_BOOT_BANK1                 ((uint8_t)0x00) /*!<  At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
-                                                            and this parameter is selected the device will boot from Bank 1 (Default)*/
-#define OB_BOOT_BANK2                 ((uint8_t)(FLASH_OPTR_BFB2 >> 16)) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
-                                                            and this parameter is selected the device will boot from Bank 2 */
-
-/**
-  * @}
-  */
-#endif /* FLASH_OPTR_BFB2 */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
- *  @{
- */
-
-/**
-  * @brief  Set the FLASH Latency.
-  * @param  __LATENCY__ FLASH Latency
-  *          This parameter can be one of the following values:
-  *            @arg @ref FLASH_LATENCY_0  FLASH Zero Latency cycle
-  *            @arg @ref FLASH_LATENCY_1  FLASH One Latency cycle
-  * @retval none
-  */
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
-                  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
-
-/**
-  * @brief  Get the FLASH Latency.
-  * @retval FLASH Latency
-  *          This parameter can be one of the following values:
-  *            @arg @ref FLASH_LATENCY_0  FLASH Zero Latency cycle
-  *            @arg @ref FLASH_LATENCY_1  FLASH One Latency cycle
-  */
-#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
-
-/**
-  * @brief  Enable the FLASH prefetch buffer.
-  * @retval none
-  */
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()      SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
-
-/**
-  * @brief  Disable the FLASH prefetch buffer.
-  * @retval none
-  */
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()     CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
-
-/**
-  * @brief  Enable the FLASH Buffer cache.
-  * @retval none
-  */
-#define __HAL_FLASH_BUFFER_CACHE_ENABLE()         CLEAR_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF)
-
-/**
-  * @brief  Disable the FLASH Buffer cache.
-  * @retval none
-  */
-#define __HAL_FLASH_BUFFER_CACHE_DISABLE()        SET_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF)
-
-/**
-  * @brief  Enable the FLASH preread buffer.
-  * @retval none
-  */
-#define __HAL_FLASH_PREREAD_BUFFER_ENABLE()       SET_BIT((FLASH->ACR), FLASH_ACR_PRE_READ)
-
-/**
-  * @brief  Disable the FLASH preread buffer.
-  * @retval none
-  */
-#define __HAL_FLASH_PREREAD_BUFFER_DISABLE()      CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRE_READ)
-
-/**
-  * @brief  Enable the FLASH power down during Sleep mode
-  * @retval none
-  */
-#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE()      SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
-
-/**
-  * @brief  Disable the FLASH power down during Sleep mode
-  * @retval none
-  */
-#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE()     CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
-
-/**
-  * @brief  Enable the Flash Run power down mode.
-  * @note   Writing this bit  to 0 this bit, automatically the keys are
-  *         loss and a new unlock sequence is necessary to re-write it to 1.
-  */
-#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1;    \
-                                             FLASH->PDKEYR = FLASH_PDKEY2;    \
-                                             SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD);  \
-                                           } while (0)
-
-/**
-  * @brief  Disable the Flash Run power down mode.
-  * @note   Writing this bit to 0 this bit, automatically the keys are
-  *         loss and a new unlock sequence is necessary to re-write it to 1.
-  */
-#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1;    \
-                                              FLASH->PDKEYR = FLASH_PDKEY2;    \
-                                             CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD);  \
-                                            } while (0)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup FLASHEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group2
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-
-#if defined(FLASH_OPTR_WPRMOD) || defined(FLASH_OPTR_BFB2)
-
-HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
-void              HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
-
-#endif /* FLASH_OPTR_WPRMOD || FLASH_OPTR_BFB2 */
-
-#if defined(FLASH_OPTR_WPRMOD)
-
-HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
-HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
-
-#endif /* FLASH_OPTR_WPRMOD */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group3
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void);
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void);
-
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address);
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
-void              HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void);
-void              HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_FLASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h
deleted file mode 100644
index f97c31862e..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_flash_ramfunc.h
-  * @author  MCD Application Team
-  * @brief   Header file of FLASH RAMFUNC driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_FLASH_RAMFUNC_H
-#define __STM32L0xx_FLASH_RAMFUNC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH_RAMFUNC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions
-  * @{
-  */
-
-/*
-  * @brief  FLASH memory functions that should be executed from internal SRAM.
-  *         These functions are defined inside the "stm32l0xx_hal_flash_ramfunc.c"
-  *         file.
-  */
-  
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
-  * @{
-  */
-
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group2
-  * @{
-  */
-
-#if defined(FLASH_PECR_PARALLBANK)
-
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);
-
-#endif /* FLASH_PECR_PARALLBANK */
-
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group3
-  * @{
-  */
-__RAM_FUNC  HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t *Error);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_FLASH_RAMFUNC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h
deleted file mode 100644
index 9e6eb78c8f..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_gpio.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_GPIO_H
-#define __STM32L0xx_HAL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIO GPIO
-  * @{
-  */
-/******************************************************************************/
-/* Exported types ------------------------------------------------------------*/
-/******************************************************************************/
-
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
-  * @{
-  */
-
-/** @defgroup GPIO_Init_Configuration GPIO init configuration structure
-  * @{
-  */
-/**
-  * @brief   GPIO Init structure definition
-  */
-typedef struct
-{
-  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
-                           This parameter can be a combination of @ref GPIO_pins_define */
-
-  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref GPIO_mode_define */
-
-  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
-                           This parameter can be a value of @ref GPIO_pull_define */
-
-  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
-                           This parameter can be a value of @ref GPIO_speed_define */
-
-  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
-                            This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
-} GPIO_InitTypeDef;
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_SetReset_Definition  GPIO set reset definition
-  * @{
-  */
-/**
-  * @brief  GPIO Bit SET and Bit RESET enumeration
-  */
-typedef enum
-{
-  GPIO_PIN_RESET = 0U,
-  GPIO_PIN_SET
-} GPIO_PinState;
-/**
-  * @}
-  */
-
-
-#define IS_GPIO_PIN_ACTION(__ACTION__) (((__ACTION__) == GPIO_PIN_RESET) || ((__ACTION__) == GPIO_PIN_SET))
-
-/**
-  * @}
-  */
-/******************************************************************************/
-/* Exported constants --------------------------------------------------------*/
-/******************************************************************************/
-
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-
-/** @defgroup GPIO_pins_define Pin definition
-  * @{
-  */
-#define GPIO_PIN_0                 (0x0001U)  /* Pin 0 selected    */
-#define GPIO_PIN_1                 (0x0002U)  /* Pin 1 selected    */
-#define GPIO_PIN_2                 (0x0004U)  /* Pin 2 selected    */
-#define GPIO_PIN_3                 (0x0008U)  /* Pin 3 selected    */
-#define GPIO_PIN_4                 (0x0010U)  /* Pin 4 selected    */
-#define GPIO_PIN_5                 (0x0020U)  /* Pin 5 selected    */
-#define GPIO_PIN_6                 (0x0040U)  /* Pin 6 selected    */
-#define GPIO_PIN_7                 (0x0080U)  /* Pin 7 selected    */
-#define GPIO_PIN_8                 (0x0100U)  /* Pin 8 selected    */
-#define GPIO_PIN_9                 (0x0200U)  /* Pin 9 selected    */
-#define GPIO_PIN_10                (0x0400U)  /* Pin 10 selected   */
-#define GPIO_PIN_11                (0x0800U)  /* Pin 11 selected   */
-#define GPIO_PIN_12                (0x1000U)  /* Pin 12 selected   */
-#define GPIO_PIN_13                (0x2000U)  /* Pin 13 selected   */
-#define GPIO_PIN_14                (0x4000U)  /* Pin 14 selected   */
-#define GPIO_PIN_15                (0x8000U)  /* Pin 15 selected   */
-#define GPIO_PIN_All               (0xFFFFU)  /* All pins selected */
-/**
-  * @}
-  */
-
-#define GPIO_PIN_MASK              (0x0000FFFFU) /* PIN mask for assert test */
-#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
-                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
-
-/** @defgroup GPIO_mode_define Mode definition
-  * @brief GPIO Configuration Mode
-  *        Elements values convention: 0x00WX00YZ
-  *           - W  : EXTI trigger detection on 3 bits
-  *           - X  : EXTI mode (IT or Event) on 2 bits
-  *           - Y  : Output type (Push Pull or Open Drain) on 1 bit
-  *           - Z  : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
-  * @{
-  */ 
-#define  GPIO_MODE_INPUT                        MODE_INPUT                                                  /*!< Input Floating Mode                   */
-#define  GPIO_MODE_OUTPUT_PP                    (MODE_OUTPUT | OUTPUT_PP)                                   /*!< Output Push Pull Mode                 */
-#define  GPIO_MODE_OUTPUT_OD                    (MODE_OUTPUT | OUTPUT_OD)                                   /*!< Output Open Drain Mode                */
-#define  GPIO_MODE_AF_PP                        (MODE_AF | OUTPUT_PP)                                       /*!< Alternate Function Push Pull Mode     */
-#define  GPIO_MODE_AF_OD                        (MODE_AF | OUTPUT_OD)                                       /*!< Alternate Function Open Drain Mode    */
-
-#define  GPIO_MODE_ANALOG                       MODE_ANALOG                                                 /*!< Analog Mode  */
-    
-#define  GPIO_MODE_IT_RISING                    (MODE_INPUT | EXTI_IT | TRIGGER_RISING)                     /*!< External Interrupt Mode with Rising edge trigger detection          */
-#define  GPIO_MODE_IT_FALLING                   (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)                    /*!< External Interrupt Mode with Falling edge trigger detection         */
-#define  GPIO_MODE_IT_RISING_FALLING            (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
- 
-#define  GPIO_MODE_EVT_RISING                   (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)                     /*!< External Event Mode with Rising edge trigger detection             */
-#define  GPIO_MODE_EVT_FALLING                  (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)                    /*!< External Event Mode with Falling edge trigger detection            */
-#define  GPIO_MODE_EVT_RISING_FALLING           (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Event Mode with Rising/Falling edge trigger detection     */
-
-/**
-  * @}
-  */
-
-#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT)              ||\
-                                ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
-                                ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
-                                ((__MODE__) == GPIO_MODE_AF_PP)              ||\
-                                ((__MODE__) == GPIO_MODE_AF_OD)              ||\
-                                ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
-                                ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
-                                ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
-                                ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
-                                ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
-                                ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
-                                ((__MODE__) == GPIO_MODE_ANALOG))
-
-
-/** @defgroup GPIO_speed_define Speed definition
-  * @brief GPIO Output Maximum frequency
-  * @{
-  */
-#define  GPIO_SPEED_FREQ_LOW              (0x00000000U)  /*!< range up to 0.4 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_MEDIUM           (0x00000001U)  /*!< range 0.4 MHz to 2 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_HIGH             (0x00000002U)  /*!< range   2 MHz to 10 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_VERY_HIGH        (0x00000003U)  /*!< range  10 MHz to 35 MHz, please refer to the product datasheet */
-
-/**
-  * @}
-  */
-
-#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW     )  || ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM     ) || \
-                                  ((__SPEED__) == GPIO_SPEED_FREQ_HIGH  ) || ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
-
-
-/** @defgroup GPIO_pull_define Pull definition
-  * @brief GPIO Pull-Up or Pull-Down Activation
-  * @{
-  */
-#define  GPIO_NOPULL        (0x00000000U)   /*!< No Pull-up or Pull-down activation  */
-#define  GPIO_PULLUP        (0x00000001U)   /*!< Pull-up activation                  */
-#define  GPIO_PULLDOWN      (0x00000002U)   /*!< Pull-down activation                */
-
-/**
-  * @}
-  */
-
-#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) || ((__PULL__) == GPIO_PULLUP) || \
-                                ((__PULL__) == GPIO_PULLDOWN))
-
-
-/**
-  * @}
-  */
-/******************************************************************************/
-/* Exported macro ------------------------------------------------------------*/
-/******************************************************************************/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macro GPIO Exported Macros
-  * @{
-  */
-/**
-  * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
-  *         This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
-  * @brief  Clears the EXTI's line pending flags.
-  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Checks whether the specified EXTI line is asserted or not.
-  * @param  __EXTI_LINE__ specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
-  * @brief  Clears the EXTI's line pending bits.
-  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
-  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__ specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-
-/**
-  * @}
-  */
-/* Include GPIO HAL Extension module */
-#include "stm32l0xx_hal_gpio_ex.h"
-
-/******************************************************************************/
-/* Exported functions --------------------------------------------------------*/
-/******************************************************************************/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions *******************************/
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @{
- */
-void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
-/**
-  * @}
-  */
-
-/* IO operation functions *******************************************************/
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
- *  @{
- */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void          HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void          HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void          HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void          HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Define the private group ***********************************/
-/**************************************************************/
-/** @defgroup GPIO_Private GPIO Private
-  * @{
-  */
-#define GPIO_MODE_Pos                           0U
-#define GPIO_MODE                               (0x3UL << GPIO_MODE_Pos)
-#define MODE_INPUT                              (0x0UL << GPIO_MODE_Pos)
-#define MODE_OUTPUT                             (0x1UL << GPIO_MODE_Pos)
-#define MODE_AF                                 (0x2UL << GPIO_MODE_Pos)
-#define MODE_ANALOG                             (0x3UL << GPIO_MODE_Pos)
-#define OUTPUT_TYPE_Pos                         4U
-#define OUTPUT_TYPE                             (0x1UL << OUTPUT_TYPE_Pos)
-#define OUTPUT_PP                               (0x0UL << OUTPUT_TYPE_Pos)
-#define OUTPUT_OD                               (0x1UL << OUTPUT_TYPE_Pos)
-#define EXTI_MODE_Pos                           16U
-#define EXTI_MODE                               (0x3UL << EXTI_MODE_Pos)
-#define EXTI_IT                                 (0x1UL << EXTI_MODE_Pos)
-#define EXTI_EVT                                (0x2UL << EXTI_MODE_Pos)
-#define TRIGGER_MODE_Pos                         20U
-#define TRIGGER_MODE                            (0x7UL << TRIGGER_MODE_Pos)
-#define TRIGGER_RISING                          (0x1UL << TRIGGER_MODE_Pos)
-#define TRIGGER_FALLING                         (0x2UL << TRIGGER_MODE_Pos)
-/**
-  * @}
-  */
-/**************************************************************/
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h
deleted file mode 100644
index c53329117a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h
+++ /dev/null
@@ -1,2505 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_gpio_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_GPIO_EX_H
-#define __STM32L0xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIOEx GPIOEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
-  * @{
-  */
-
-
-/*----------------------------------------------------------------------------*/
-/*------------------------- STM32L083xx/STM32L073xx---------------------------*/
-/*----------------------------------------------------------------------------*/
-
-#if defined (STM32L083xx) || defined (STM32L073xx)
-
-/* The table below gives an overview of the different alternate functions per port.
- * For more details refer yourself to the product data sheet.
- *
- */
-
-/*     |   AF0  |   AF1  |   AF2  |   AF3  |   AF4  |   AF5  |   AF6  |   AF7  |
- *______________________________________________________________________________
- * PA0 |        |        |TIM2_C1 |TSC     |USART2  |TIM2_TR |USART4  |COMP1   |
- * PA1 |EVENTOUT|LCD     |TIM2_C2 |TSC     |USART2  |TIM21_TR|USART4  |        |
- * PA2 |TIM21_C1|LCD     |TIM2_C3 |TSC     |USART2  |        |LPUART1 |COMP2   |
- * PA3 |TIM21_C2|LCD     |TIM2_C4 |TSC     |USART2  |        |LPUART1 |        |
- * PA4 |SPI1    |        |        |TSC     |USART2  |TIM22_TR|        |        |
- * PA5 |SPI1    |        |TIM2_TR |TSC     |        |TIM2_C1 |        |        |
- * PA6 |SPI1    |LCD     |TIM3_C1 |TSC     |LPUART1 |TIM22_C1|EVENTOUT|COMP1   |
- * PA7 |SPI1    |LCD     |TIM3_C2 |TSC     |        |TIM22_C2|EVENTOUT|COMP2   |
- * PA8 |MCO     |LCD     |USB     |EVENTOUT|USART1  |        |        |I2C3    |
- * PA9 |MCO     |LCD     |        |TSC     |USART1  |        |I2C1    |I2C3    |
- * PA10|        |LCD     |        |TSC     |USART1  |        |I2C1    |        |
- * PA11|SPI1    |        |EVENTOUT|TSC     |USART1  |        |I2C2    |COMP1   |
- * PA12|SPI1    |        |EVENTOUT|TSC     |USART1  |        |I2C2    |COMP2   |
- * PA13|SWDIO   |        |USB     |        |        |        |LPUART1 |        |
- * PA14|SWCLK   |        |        |        |USART2  |        |LPUART1 |        |
- * PA15|SPI1    |LCD     |TIM2_TR |EVENTOUT|USART2  |TIM2_C1 |USART4  |        |
- *______________________________________________________________________________
- * PB0 |EVENTOUT|LCD     |TIM3_C3 |TSC     |        |        |        |        |
- * PB1 |        |LCD     |TIM3_C4 |TSC     |LPUART1 |        |        |        |
- * PB2 |        |        |LPTIM1_O|TSC     |        |        |        |I2C3    |
- * PB3 |SPI1    |LCD     |TIM2_C2 |TSC     |EVENTOUT|USART1  |USART5  |        |
- * PB4 |SPI1    |LCD     |TIM3_C1 |TSC     |TIM22_C1|USART1  |USART5  |I2C3    |
- * PB5 |SPI1    |LCD     |LPTIM1_I|I2C1    |TIM3_C2 |USART1  |USART5  |        |
- *     |        |        |        |        |TIM22_C2|        |        |        |
- * PB6 |USART1  |I2C1    |LPTIM1_T|TSC     |        |        |        |        |
- * PB7 |USART1  |I2C1    |LPTIM1_I|TSC     |        |        |USART4  |        |
- * PB8 |        |LCD     |        |TSC     |I2C1    |        |        |        |
- * PB9 |        |LCD     |EVENTOUT|        |I2C1    |SPI2    |        |        |
- * PB10|        |LCD     |TIM2_C3 |TSC     |LPUART1 |SPI2    |I2C2    |LPUART1 |
- * PB11|EVENTOUT|LCD     |TIM2_C4 |TSC     |LPUART1 |        |I2C2    |LPUART1 |
- * PB12|SPI2    |LCD     |LPUART1 |TSC     |        |I2C2    |EVENTOUT|        |
- * PB13|SPI2    |LCD     |MCO     |TSC     |LPUART1 |I2C2    |TIM21_C1|        |
- * PB14|SPI2    |LCD     |RTC     |TSC     |LPUART1 |I2C2    |TIM21_C2|        |
- * PB15|SPI2    |LCD     |RTC     |        |        |        |        |        |
- *______________________________________________________________________________
- * PC0 |LPTIM1_I|LCD     |EVENTOUT|TSC     |        |        |LPUART1 |I2C3    |
- * PC1 |LPTIM1_O|LCD     |EVENTOUT|TSC     |        |        |LPUART1 |I2C3    |
- * PC2 |LPTIM1_I|LCD     |SPI2    |TSC     |        |        |        |        |
- * PC3 |LPTIM1_T|LCD     |SPI2    |TSC     |        |        |        |        |
- * PC4 |EVENTOUT|LCD     |LPUART1 |        |        |        |        |        |
- * PC5 |        |LCD     |LPUART1 |TSC     |        |        |        |        |
- * PC6 |TIM22_C1|LCD     |TIM3_C1 |TSC     |        |        |        |        |
- * PC7 |TIM22_C2|LCD     |TIM3_C2 |TSC     |        |        |        |        |
- * PC8 |TIM22_TR|LCD     |TIM3_C3 |TSC     |        |        |        |        |
- * PC9 |TIM21_TR|LCD     |USB     |TSC     |        |        |        |I2C3    |
- *     |        |        |TIM3_C4 |        |        |        |        |        |
- * PC10|LPUART1 |LCD     |        |        |        |        |USART4  |        |
- * PC11|LPUART1 |LCD     |        |        |        |        |USART4  |        |
- * PC12|        |LCD     |USART5  |        |        |        |USART4  |        |
- * PC13|        |        |        |        |        |        |        |        |
- * PC14|        |        |        |        |        |        |        |        |
- * PC15|        |        |        |        |        |        |        |        |
- *______________________________________________________________________________
- * PD0 |TIM21_C1|SPI2    |        |        |        |        |        |        |
- * PD1 |        |SPI2    |        |        |        |        |        |        |
- * PD2 |LPUART1 |LCD     |TIM3_TR |        |        |        |USART5  |        |
- * PD3 |USART2  |LCD     |SPI2    |        |        |        |        |        |
- * PD4 |USART2  |SPI2    |        |        |        |        |        |        |
- * PD5 |USART2  |        |        |        |        |        |        |        |
- * PD6 |USART2  |        |        |        |        |        |        |        |
- * PD7 |USART2  |TIM21_C2|        |        |        |        |        |        |
- * PD8 |LPUART1 |LCD     |        |        |        |        |        |        |
- * PD9 |LPUART1 |LCD     |        |        |        |        |        |        |
- * PD10|        |LCD     |        |        |        |        |        |        |
- * PD11|LPUART1 |LCD     |        |        |        |        |        |        |
- * PD12|LPUART1 |LCD     |        |        |        |        |        |        |
- * PD13|        |LCD     |        |        |        |        |        |        |
- * PD14|        |LCD     |        |        |        |        |        |        |
- * PD15|USB     |LCD     |        |        |        |        |        |        |
- *______________________________________________________________________________
- * PE0 |        |LCD     |EVENTOUT|        |        |        |        |        |
- * PE1 |        |LCD     |EVENTOUT|        |        |        |        |        |
- * PE2 |        |LCD     |TIM3_TR |        |        |        |        |        |
- * PE3 |TIM22_C1|LCD     |TIM3_C1 |        |        |        |        |        |
- * PE4 |TIM22_C2|        |TIM3_C2 |        |        |        |        |        |
- * PE5 |TIM21_C1|        |TIM3_C3 |        |        |        |        |        |
- * PE6 |TIM21_C2|        |TIM3_C4 |        |        |        |        |        |
- * PE7 |        |LCD     |        |        |        |        |USART5  |        |
- * PE8 |        |LCD     |        |        |        |        |USART4  |        |
- * PE9 |TIM2_C1 |LCD     |TIM2_TR |        |        |        |USART4  |        |
- * PE10|TIM2_C2 |LCD     |        |        |        |        |USART5  |        |
- * PE11|TIM2_C3 |        |        |        |        |        |USART5  |        |
- * PE12|TIM2_C4 |        |SPI1    |        |        |        |        |        |
- * PE13|        |LCD     |SPI1    |        |        |        |        |        |
- * PE14|        |LCD     |SPI1    |        |        |        |        |        |
- * PE15|        |LCD     |SPI1    |        |        |        |        |        |
- *______________________________________________________________________________
- * PH0 |USB     |        |        |        |        |        |        |        |
- * PH1 |        |        |        |        |        |        |        |        |
- * PH9 |        |        |        |        |        |        |        |        |
- * PH10|        |        |        |        |        |        |        |        |
- *
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
- * @{
-   */
-
-/*
- * Alternate function AF0
- */
-#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF0_TIM21         ((uint8_t)0x00U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF0_SPI1          ((uint8_t)0x00U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF0_SWDIO         ((uint8_t)0x00U)  /* SWDIO Alternate Function mapping    */
-#define GPIO_AF0_SWCLK         ((uint8_t)0x00U)  /* SWCLK Alternate Function mapping    */
-#define GPIO_AF0_USART1        ((uint8_t)0x00U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF0_SPI2          ((uint8_t)0x00U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF0_LPTIM1        ((uint8_t)0x00U)  /* LPTIM1 Alternate Function mapping   */
-#define GPIO_AF0_TIM22         ((uint8_t)0x00U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF0_LPUART1       ((uint8_t)0x00U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF0_USART2        ((uint8_t)0x00U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF0_TIM2          ((uint8_t)0x00U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF0_USB           ((uint8_t)0x00U)  /* USB Alternate Function mapping      */
-/**
-  *
-  */
-
-/*
- * Alternate function AF1
- */
-#define GPIO_AF1_I2C1          ((uint8_t)0x01U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF1_SPI2          ((uint8_t)0x01U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF1_TIM21         ((uint8_t)0x01U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF1_LCD           ((uint8_t)0x01U)  /* LCD Alternate Function mapping      */
-/**
-  *
-  */
-
-/*
- * Alternate function AF2
- */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping     */
-#define GPIO_AF2_EVENTOUT      ((uint8_t)0x02U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF2_LPTIM1        ((uint8_t)0x02U)  /* LPTIM1 Alternate Function mapping   */
-#define GPIO_AF2_LPUART1       ((uint8_t)0x02U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF2_MCO           ((uint8_t)0x02U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF2_RTC           ((uint8_t)0x02U)  /* RTC Alternate Function mapping      */
-#define GPIO_AF2_SPI2          ((uint8_t)0x02U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF2_USART5        ((uint8_t)0x02U)  /* USART5 Alternate Function mapping   */
-#define GPIO_AF2_SPI1          ((uint8_t)0x02U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF2_USB           ((uint8_t)0x00U)  /* USB Alternate Function mapping      */
-/**
-  *
-  */
-
-/*
- * Alternate function AF3
- */
-#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF3_I2C1          ((uint8_t)0x03U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC  Alternate Function mapping     */
-/**
-  *
-  */
-
-/*
- * Alternate function AF4
- */
-#define GPIO_AF4_USART2          ((uint8_t)0x04U)  /* USART2 Alternate Function mapping  */
-#define GPIO_AF4_LPUART1         ((uint8_t)0x04U)  /* LPUART1 Alternate Function mapping */
-#define GPIO_AF4_USART1          ((uint8_t)0x04U)  /* USART1 Alternate Function mapping  */
-#define GPIO_AF4_EVENTOUT        ((uint8_t)0x04U)  /* EVENTOUT Alternate Function mapping*/
-#define GPIO_AF4_TIM22           ((uint8_t)0x04U)  /* TIM22 Alternate Function mapping   */
-#define GPIO_AF4_TIM3            ((uint8_t)0x04U)  /* TIM3 Alternate Function mapping    */
-#define GPIO_AF4_I2C1            ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF5
- */
-#define GPIO_AF5_TIM2          ((uint8_t)0x05U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF5_TIM21         ((uint8_t)0x05U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF5_TIM22         ((uint8_t)0x05U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF5_USART1        ((uint8_t)0x05U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF5_I2C2          ((uint8_t)0x05U)  /* I2C2 Alternate Function mapping     */
-/**
-  *
-  */
-
-/*
- * Alternate function AF6
- */
-
-#define GPIO_AF6_USART4        ((uint8_t)0x06U)  /* USART4 Alternate Function mapping   */
-#define GPIO_AF6_LPUART1       ((uint8_t)0x06U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF6_EVENTOUT      ((uint8_t)0x06U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF6_I2C1          ((uint8_t)0x06U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF6_I2C2          ((uint8_t)0x06U)  /* I2C2 Alternate Function mapping     */
-#define GPIO_AF6_USART5        ((uint8_t)0x06U)  /* USART5 Alternate Function mapping   */
-#define GPIO_AF6_TIM21         ((uint8_t)0x06U)  /* TIM21 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF7
- */
-#define GPIO_AF7_COMP1        ((uint8_t)0x07U)  /* COMP1 Alternate Function mapping     */
-#define GPIO_AF7_COMP2        ((uint8_t)0x07U)  /* COMP2 Alternate Function mapping     */
-#define GPIO_AF7_I2C3         ((uint8_t)0x07U)  /* I2C3 Alternate Function mapping      */
-#define GPIO_AF7_LPUART1      ((uint8_t)0x07U)  /* LPUART1 Alternate Function mapping   */
-/**
-  *
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private  GPIOEx Private
-  * @{
-  */
-/**
-  *  IS_GPIO_AF macro definition
-  */
-#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
-
-/**
-  * @}
-  */
-#endif /* (STM32L083xx) || (STM32L073xx) */
-
-/*----------------------------------------------------------------------------*/
-/*------------------------- STM32L082xx and STM32L072xx-----------------------*/
-/*----------------------------------------------------------------------------*/
-#if defined (STM32L082xx) || defined (STM32L072xx)
-
-/* The table below gives an overview of the different alternate functions per port.
- * For more details refer yourself to the product data sheet.
- */
-
-
-/*     |   AF0  |   AF1  |   AF2  |   AF3  |   AF4  |   AF5  |   AF6  |   AF7  |
- *______________________________________________________________________________
- * PA0 |        |        |TIM2_C1 |TSC     |USART2  |TIM2_TR |USART4  |COMP1   |
- * PA1 |EVENTOUT|        |TIM2_C2 |TSC     |USART2  |TIM21_TR|USART4  |        |
- * PA2 |TIM21_C1|        |TIM2_C3 |TSC     |USART2  |        |LPUART1 |COMP2   |
- * PA3 |TIM21_C2|        |TIM2_C4 |TSC     |USART2  |        |LPUART1 |        |
- * PA4 |SPI1    |        |        |TSC     |USART2  |TIM22_TR|        |        |
- * PA5 |SPI1    |        |TIM2_TR |TSC     |        |TIM2_C1 |        |        |
- * PA6 |SPI1    |        |TIM3_C1 |TSC     |LPUART1 |TIM22_C1|EVENTOUT|COMP1   |
- * PA7 |SPI1    |        |TIM3_C2 |TSC     |        |TIM22_C2|EVENTOUT|COMP2   |
- * PA8 |MCO     |        |USB     |EVENTOUT|USART1  |        |        |I2C3    |
- * PA9 |MCO     |        |        |TSC     |USART1  |        |I2C1    |I2C3    |
- * PA10|        |        |        |TSC     |USART1  |        |I2C1    |        |
- * PA11|SPI1    |        |EVENTOUT|TSC     |USART1  |        |I2C2    |COMP1   |
- * PA12|SPI1    |        |EVENTOUT|TSC     |USART1  |        |I2C2    |COMP2   |
- * PA13|SWDIO   |        |USB     |        |        |        |LPUART1 |        |
- * PA14|SWCLK   |        |        |        |USART2  |        |LPUART1 |        |
- * PA15|SPI1    |        |TIM2_TR |EVENTOUT|USART2  |TIM2_C1 |USART4  |        |
- *______________________________________________________________________________
- * PB0 |EVENTOUT|        |TIM3_C3 |TSC     |        |        |        |        |
- * PB1 |        |        |TIM3_C4 |TSC     |LPUART1 |        |        |        |
- * PB2 |        |        |LPTIM1_O|TSC     |        |        |        |I2C3    |
- * PB3 |SPI1    |        |TIM2_C2 |TSC     |EVENTOUT|USART1  |USART5  |        |
- * PB4 |SPI1    |        |TIM3_C1 |TSC     |TIM22_C1|USART1  |USART5  |I2C3    |
- * PB5 |SPI1    |        |LPTIM1_I|I2C1    |TIM3_C2 |USART1  |USART5  |        |
- *     |        |        |        |        |TIM22_C2|        |        |        |
- * PB6 |USART1  |I2C1    |LPTIM1_T|TSC     |        |        |        |        |
- * PB7 |USART1  |I2C1    |LPTIM1_I|TSC     |        |        |USART4  |        |
- * PB8 |        |        |        |TSC     |I2C1    |        |        |        |
- * PB9 |        |        |EVENTOUT|        |I2C1    |SPI2    |        |        |
- * PB10|        |        |TIM2_C3 |TSC     |LPUART1 |SPI2    |I2C2    |LPUART1 |
- * PB11|EVENTOUT|        |TIM2_C4 |TSC     |LPUART1 |        |I2C2    |LPUART1 |
- * PB12|SPI2    |        |LPUART1 |TSC     |        |I2C2    |EVENTOUT|        |
- * PB13|SPI2    |        |MCO     |TSC     |LPUART1 |I2C2    |TIM21_C1|        |
- * PB14|SPI2    |        |RTC     |TSC     |LPUART1 |I2C2    |TIM21_C2|        |
- * PB15|SPI2    |        |RTC     |        |        |        |        |        |
- *______________________________________________________________________________
- * PC0 |LPTIM1_I|        |EVENTOUT|TSC     |        |        |LPUART1 |I2C3    |
- * PC1 |LPTIM1_O|        |EVENTOUT|TSC     |        |        |LPUART1 |I2C3    |
- * PC2 |LPTIM1_I|        |SPI2    |TSC     |        |        |        |        |
- * PC3 |LPTIM1_T|        |SPI2    |TSC     |        |        |        |        |
- * PC4 |EVENTOUT|        |LPUART1 |        |        |        |        |        |
- * PC5 |        |        |LPUART1 |TSC     |        |        |        |        |
- * PC6 |TIM22_C1|        |TIM3_C1 |TSC     |        |        |        |        |
- * PC7 |TIM22_C2|        |TIM3_C2 |TSC     |        |        |        |        |
- * PC8 |TIM22_TR|        |TIM3_C3 |TSC     |        |        |        |        |
- * PC9 |TIM21_TR|        |USB     |TSC     |        |        |        |I2C3    |
- *     |        |        |TIM3_C4 |        |        |        |        |        |
- * PC10|LPUART1 |        |        |        |        |        |USART4  |        |
- * PC11|LPUART1 |        |        |        |        |        |USART4  |        |
- * PC12|        |        |USART5  |        |        |        |USART4  |        |
- * PC13|        |        |        |        |        |        |        |        |
- * PC14|        |        |        |        |        |        |        |        |
- * PC15|        |        |        |        |        |        |        |        |
- *______________________________________________________________________________
- * PD0 |TIM21_C1|SPI2    |        |        |        |        |        |        |
- * PD1 |        |SPI2    |        |        |        |        |        |        |
- * PD2 |LPUART1 |        |TIM3_TR |        |        |        |USART5  |        |
- * PD3 |USART2  |        |SPI2    |        |        |        |        |        |
- * PD4 |USART2  |SPI2    |        |        |        |        |        |        |
- * PD5 |USART2  |        |        |        |        |        |        |        |
- * PD6 |USART2  |        |        |        |        |        |        |        |
- * PD7 |USART2  |TIM21_C2|        |        |        |        |        |        |
- * PD8 |LPUART1 |        |        |        |        |        |        |        |
- * PD9 |LPUART1 |        |        |        |        |        |        |        |
- * PD10|        |        |        |        |        |        |        |        |
- * PD11|LPUART1 |        |        |        |        |        |        |        |
- * PD12|LPUART1 |        |        |        |        |        |        |        |
- * PD13|        |        |        |        |        |        |        |        |
- * PD14|        |        |        |        |        |        |        |        |
- * PD15|USB     |        |        |        |        |        |        |        |
- *______________________________________________________________________________
- * PE0 |        |        |EVENTOUT|        |        |        |        |        |
- * PE1 |        |        |EVENTOUT|        |        |        |        |        |
- * PE2 |        |        |TIM3_TR |        |        |        |        |        |
- * PE3 |TIM22_C1|        |TIM3_C1 |        |        |        |        |        |
- * PE4 |TIM22_C2|        |TIM3_C2 |        |        |        |        |        |
- * PE5 |TIM21_C1|        |TIM3_C3 |        |        |        |        |        |
- * PE6 |TIM21_C2|        |TIM3_C4 |        |        |        |        |        |
- * PE7 |        |        |        |        |        |        |USART5  |        |
- * PE8 |        |        |        |        |        |        |USART4  |        |
- * PE9 |TIM2_C1 |        |TIM2_TR |        |        |        |USART4  |        |
- * PE10|TIM2_C2 |        |        |        |        |        |USART5  |        |
- * PE11|TIM2_C3 |        |        |        |        |        |USART5  |        |
- * PE12|TIM2_C4 |        |SPI1    |        |        |        |        |        |
- * PE13|        |        |SPI1    |        |        |        |        |        |
- * PE14|        |        |SPI1    |        |        |        |        |        |
- * PE15|        |        |SPI1    |        |        |        |        |        |
- *______________________________________________________________________________
- * PH0 |USB     |        |        |        |        |        |        |        |
- * PH1 |        |        |        |        |        |        |        |        |
- * PH9 |        |        |        |        |        |        |        |        |
- * PH10|        |        |        |        |        |        |        |        |
- *
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
-  * @{
-  */
-
-/*
- * Alternate function AF0
- */
-#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF0_TIM21         ((uint8_t)0x00U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF0_SPI1          ((uint8_t)0x00U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF0_SWDIO         ((uint8_t)0x00U)  /* SWDIO Alternate Function mapping    */
-#define GPIO_AF0_SWCLK         ((uint8_t)0x00U)  /* SWCLK Alternate Function mapping    */
-#define GPIO_AF0_USART1        ((uint8_t)0x00U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF0_SPI2          ((uint8_t)0x00U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF0_LPTIM1        ((uint8_t)0x00U)  /* LPTIM1 Alternate Function mapping   */
-#define GPIO_AF0_TIM22         ((uint8_t)0x00U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF0_LPUART1       ((uint8_t)0x00U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF0_USART2        ((uint8_t)0x00U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF0_TIM2          ((uint8_t)0x00U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF0_USB           ((uint8_t)0x00U)  /* USB Alternate Function mapping      */
-/**
-  *
-  */
-
-/*
- * Alternate function AF1
- */
-#define GPIO_AF1_I2C1          ((uint8_t)0x01U)  /* I2C1 Alternate Function mapping  */
-#define GPIO_AF1_SPI2          ((uint8_t)0x01U)  /* SPI2 Alternate Function mapping  */
-#define GPIO_AF1_TIM21         ((uint8_t)0x01U)  /* TIM21 Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF2
- */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping       */
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping       */
-#define GPIO_AF2_EVENTOUT      ((uint8_t)0x02U)  /* EVENTOUT Alternate Function mapping   */
-#define GPIO_AF2_LPTIM1        ((uint8_t)0x02U)  /* LPTIM1 Alternate Function mapping     */
-#define GPIO_AF2_LPUART1       ((uint8_t)0x02U)  /* LPUART1 Alternate Function mapping    */
-#define GPIO_AF2_MCO           ((uint8_t)0x02U)  /* MCO Alternate Function mapping        */
-#define GPIO_AF2_RTC           ((uint8_t)0x02U)  /* RTC Alternate Function mapping        */
-#define GPIO_AF2_SPI2          ((uint8_t)0x02U)  /* SPI2 Alternate Function mapping       */
-#define GPIO_AF2_USART5        ((uint8_t)0x02U)  /* USART5 Alternate Function mapping     */
-#define GPIO_AF2_SPI1          ((uint8_t)0x02U)  /* SPI1 Alternate Function mapping       */
-#define GPIO_AF2_USB           ((uint8_t)0x00U)  /* USB Alternate Function mapping        */
-/**
-  *
-  */
-
-/*
- * Alternate function AF3
- */
-#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03U)  /* EVENTOUT Alternate Function mapping   */
-#define GPIO_AF3_I2C1          ((uint8_t)0x03U)  /* I2C1 Alternate Function mapping       */
-#define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC  Alternate Function mapping       */
-/**
-  *
-  */
-
-/*
- * Alternate function AF4
- */
-#define GPIO_AF4_USART2          ((uint8_t)0x04U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF4_LPUART1         ((uint8_t)0x04U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF4_USART1          ((uint8_t)0x04U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF4_EVENTOUT        ((uint8_t)0x04U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF4_TIM22           ((uint8_t)0x04U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF4_TIM3            ((uint8_t)0x04U)  /* TIM3 Alternate Function mapping     */
-#define GPIO_AF4_I2C1            ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping     */
-/**
-  *
-  */
-
-/*
- * Alternate function AF5
- */
-#define GPIO_AF5_TIM2          ((uint8_t)0x05U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF5_TIM21         ((uint8_t)0x05U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF5_TIM22         ((uint8_t)0x05U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF5_USART1        ((uint8_t)0x05U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2 Alternate Function mapping      */
-#define GPIO_AF5_I2C2          ((uint8_t)0x05U)  /* I2C2 Alternate Function mapping      */
-/**
-  *
-  */
-
-/*
- * Alternate function AF6
- */
-#define GPIO_AF6_USART4        ((uint8_t)0x06U)  /* USART4 Alternate Function mapping    */
-#define GPIO_AF6_LPUART1       ((uint8_t)0x06U)  /* LPUART1 Alternate Function mapping   */
-#define GPIO_AF6_EVENTOUT      ((uint8_t)0x06U)  /* EVENTOUT Alternate Function mapping  */
-#define GPIO_AF6_I2C1          ((uint8_t)0x06U)  /* I2C1 Alternate Function mapping      */
-#define GPIO_AF6_I2C2          ((uint8_t)0x06U)  /* I2C2 Alternate Function mapping      */
-#define GPIO_AF6_USART5        ((uint8_t)0x06U)  /* USART5 Alternate Function mapping    */
-#define GPIO_AF6_TIM21         ((uint8_t)0x06U)  /* TIM21 Alternate Function mapping     */
-/**
-  *
-  */
-
-/*
- * Alternate function AF7
- */
-#define GPIO_AF7_COMP1        ((uint8_t)0x07U)  /* COMP1 Alternate Function mapping     */
-#define GPIO_AF7_COMP2        ((uint8_t)0x07U)  /* COMP2 Alternate Function mapping     */
-#define GPIO_AF7_I2C3         ((uint8_t)0x07U)  /* I2C3 Alternate Function mapping      */
-#define GPIO_AF7_LPUART1      ((uint8_t)0x07U)  /* LPUART1 Alternate Function mapping   */
-/**
-  *
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private  GPIOEx Private
-  * @{
-  */
-/**
-  * @brief IS_GPIO_AF macro definition
-  */
-#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
-
-/**
-  * @}
-  */
-#endif /* (STM32L082xx) || (STM32L072xx) */
-
-
-/*----------------------------------------------------------------------------*/
-/*------------------------- STM32L081xx and STM32L071xx-----------------------*/
-/*----------------------------------------------------------------------------*/
-#if defined (STM32L081xx) || defined (STM32L071xx)
-
-/* The table below gives an overview of the different alternate functions per port.
- * For more details refer yourself to the product data sheet.
- *
- */
-
-
-/*     |   AF0  |   AF1  |   AF2  |   AF3  |   AF4  |   AF5  |   AF6  |   AF7  |
- *______________________________________________________________________________
- * PA0 |        |        |TIM2_C1 |        |USART2  |TIM2_TR |USART4  |COMP1   |
- * PA1 |EVENTOUT|        |TIM2_C2 |        |USART2  |TIM21_TR|USART4  |        |
- * PA2 |TIM21_C1|        |TIM2_C3 |        |USART2  |        |LPUART1 |COMP2   |
- * PA3 |TIM21_C2|        |TIM2_C4 |        |USART2  |        |LPUART1 |        |
- * PA4 |SPI1    |        |        |        |USART2  |TIM22_TR|        |        |
- * PA5 |SPI1    |        |TIM2_TR |        |        |TIM2_C1 |        |        |
- * PA6 |SPI1    |        |TIM3_C1 |        |LPUART1 |TIM22_C1|EVENTOUT|COMP1   |
- * PA7 |SPI1    |        |TIM3_C2 |        |        |TIM22_C2|EVENTOUT|COMP2   |
- * PA8 |MCO     |        |        |EVENTOUT|USART1  |        |        |I2C3    |
- * PA9 |MCO     |        |        |        |USART1  |        |I2C1    |I2C3    |
- * PA10|        |        |        |        |USART1  |        |I2C1    |        |
- * PA11|SPI1    |        |EVENTOUT|        |USART1  |        |I2C2    |COMP1   |
- * PA12|SPI1    |        |EVENTOUT|        |USART1  |        |I2C2    |COMP2   |
- * PA13|SWDIO   |        |        |        |        |        |LPUART1 |        |
- * PA14|SWCLK   |        |        |        |USART2  |        |LPUART1 |        |
- * PA15|SPI1    |        |TIM2_TR |EVENTOUT|USART2  |TIM2_C1 |USART4  |        |
- *______________________________________________________________________________
- * PB0 |EVENTOUT|        |TIM3_C3 |        |        |        |        |        |
- * PB1 |        |        |TIM3_C4 |        |LPUART1 |        |        |        |
- * PB2 |        |        |LPTIM1_O|        |        |        |        |I2C3    |
- * PB3 |SPI1    |        |TIM2_C2 |        |EVENTOUT|USART1  |USART5  |        |
- * PB4 |SPI1    |        |TIM3_C1 |        |TIM22_C1|USART1  |USART5  |I2C3    |
- * PB5 |SPI1    |        |LPTIM1_I|I2C1    |TIM3_C2 |USART1  |USART5  |        |
- *     |        |        |        |        |TIM22_C2|        |        |        |
- * PB6 |USART1  |I2C1    |LPTIM1_T|        |        |        |        |        |
- * PB7 |USART1  |I2C1    |LPTIM1_I|        |        |        |USART4  |        |
- * PB8 |        |        |        |        |I2C1    |        |        |        |
- * PB9 |        |        |EVENTOUT|        |I2C1    |SPI2    |        |        |
- * PB10|        |        |TIM2_C3 |        |LPUART1 |SPI2    |I2C2    |LPUART1 |
- * PB11|EVENTOUT|        |TIM2_C4 |        |LPUART1 |        |I2C2    |LPUART1 |
- * PB12|SPI2    |        |LPUART1 |        |        |I2C2    |EVENTOUT|        |
- * PB13|SPI2    |        |MCO     |        |LPUART1 |I2C2    |TIM21_C1|        |
- * PB14|SPI2    |        |RTC     |        |LPUART1 |I2C2    |TIM21_C2|        |
- * PB15|SPI2    |        |RTC     |        |        |        |        |        |
- *______________________________________________________________________________
- * PC0 |LPTIM1_I|        |EVENTOUT|        |        |        |LPUART1 |I2C3    |
- * PC1 |LPTIM1_O|        |EVENTOUT|        |        |        |LPUART1 |I2C3    |
- * PC2 |LPTIM1_I|        |SPI2    |        |        |        |        |        |
- * PC3 |LPTIM1_T|        |SPI2    |        |        |        |        |        |
- * PC4 |EVENTOUT|        |LPUART1 |        |        |        |        |        |
- * PC5 |        |        |LPUART1 |        |        |        |        |        |
- * PC6 |TIM22_C1|        |TIM3_C1 |        |        |        |        |        |
- * PC7 |TIM22_C2|        |TIM3_C2 |        |        |        |        |        |
- * PC8 |TIM22_TR|        |TIM3_C3 |        |        |        |        |        |
- * PC9 |TIM21_TR|        |        |        |        |        |        |I2C3    |
- *     |        |        |TIM3_C4 |        |        |        |        |        |
- * PC10|LPUART1 |        |        |        |        |        |USART4  |        |
- * PC11|LPUART1 |        |        |        |        |        |USART4  |        |
- * PC12|        |        |USART5  |        |        |        |USART4  |        |
- * PC13|        |        |        |        |        |        |        |        |
- * PC14|        |        |        |        |        |        |        |        |
- * PC15|        |        |        |        |        |        |        |        |
- *______________________________________________________________________________
- * PD0 |TIM21_C1|SPI2    |        |        |        |        |        |        |
- * PD1 |        |SPI2    |        |        |        |        |        |        |
- * PD2 |LPUART1 |        |TIM3_TR |        |        |        |USART5  |        |
- * PD3 |USART2  |        |SPI2    |        |        |        |        |        |
- * PD4 |USART2  |SPI2    |        |        |        |        |        |        |
- * PD5 |USART2  |        |        |        |        |        |        |        |
- * PD6 |USART2  |        |        |        |        |        |        |        |
- * PD7 |USART2  |TIM21_C2|        |        |        |        |        |        |
- * PD8 |LPUART1 |        |        |        |        |        |        |        |
- * PD9 |LPUART1 |        |        |        |        |        |        |        |
- * PD10|        |        |        |        |        |        |        |        |
- * PD11|LPUART1 |        |        |        |        |        |        |        |
- * PD12|LPUART1 |        |        |        |        |        |        |        |
- * PD13|        |        |        |        |        |        |        |        |
- * PD14|        |        |        |        |        |        |        |        |
- * PD15|        |        |        |        |        |        |        |        |
- *______________________________________________________________________________
- * PE0 |        |        |EVENTOUT|        |        |        |        |        |
- * PE1 |        |        |EVENTOUT|        |        |        |        |        |
- * PE2 |        |        |TIM3_TR |        |        |        |        |        |
- * PE3 |TIM22_C1|        |TIM3_C1 |        |        |        |        |        |
- * PE4 |TIM22_C2|        |TIM3_C2 |        |        |        |        |        |
- * PE5 |TIM21_C1|        |TIM3_C3 |        |        |        |        |        |
- * PE6 |TIM21_C2|        |TIM3_C4 |        |        |        |        |        |
- * PE7 |        |        |        |        |        |        |USART5  |        |
- * PE8 |        |        |        |        |        |        |USART4  |        |
- * PE9 |TIM2_C1 |        |TIM2_TR |        |        |        |USART4  |        |
- * PE10|TIM2_C2 |        |        |        |        |        |USART5  |        |
- * PE11|TIM2_C3 |        |        |        |        |        |USART5  |        |
- * PE12|TIM2_C4 |        |SPI1    |        |        |        |        |        |
- * PE13|        |        |SPI1    |        |        |        |        |        |
- * PE14|        |        |SPI1    |        |        |        |        |        |
- * PE15|        |        |SPI1    |        |        |        |        |        |
- *______________________________________________________________________________
- * PH0 |        |        |        |        |        |        |        |        |
- * PH1 |        |        |        |        |        |        |        |        |
- * PH9 |        |        |        |        |        |        |        |        |
- * PH10|        |        |        |        |        |        |        |        |
- *
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
-  * @{
-  */
-
-/*
- * Alternate function AF0
- *
- */
-#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF0_TIM21         ((uint8_t)0x00U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF0_SPI1          ((uint8_t)0x00U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF0_SWDIO         ((uint8_t)0x00U)  /* SWDIO Alternate Function mapping    */
-#define GPIO_AF0_SWCLK         ((uint8_t)0x00U)  /* SWCLK Alternate Function mapping    */
-#define GPIO_AF0_USART1        ((uint8_t)0x00U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF0_SPI2          ((uint8_t)0x00U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF0_LPTIM1        ((uint8_t)0x00U)  /* LPTIM1 Alternate Function mapping   */
-#define GPIO_AF0_TIM22         ((uint8_t)0x00U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF0_LPUART1       ((uint8_t)0x00U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF0_USART2        ((uint8_t)0x00U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF0_TIM2          ((uint8_t)0x00U)  /* TIM2 Alternate Function mapping     */
-/**
-  *
-  */
-
-/*
- * Alternate function AF1
- *
- */
-#define GPIO_AF1_I2C1          ((uint8_t)0x01U)  /* I2C1 Alternate Function mapping  */
-#define GPIO_AF1_SPI2          ((uint8_t)0x01U)  /* SPI2 Alternate Function mapping  */
-#define GPIO_AF1_TIM21         ((uint8_t)0x01U)  /* TIM21 Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF2
- *
- */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping     */
-#define GPIO_AF2_EVENTOUT      ((uint8_t)0x02U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF2_LPTIM1        ((uint8_t)0x02U)  /* LPTIM1 Alternate Function mapping   */
-#define GPIO_AF2_LPUART1       ((uint8_t)0x02U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF2_MCO           ((uint8_t)0x02U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF2_RTC           ((uint8_t)0x02U)  /* RTC Alternate Function mapping      */
-#define GPIO_AF2_SPI2          ((uint8_t)0x02U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF2_USART5        ((uint8_t)0x02U)  /* USART5 Alternate Function mapping   */
-#define GPIO_AF2_SPI1          ((uint8_t)0x02U)  /* SPI1 Alternate Function mapping     */
-/**
-  *
-  */
-
-/*
- * Alternate function AF3
- * @{
- */
-#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF3_I2C1          ((uint8_t)0x03U)  /* I2C1 Alternate Function mapping     */
-/**
-  *
-  */
-
-/*
- * Alternate function AF4
- *
- */
-#define GPIO_AF4_USART2          ((uint8_t)0x04U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF4_LPUART1         ((uint8_t)0x04U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF4_USART1          ((uint8_t)0x04U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF4_EVENTOUT        ((uint8_t)0x04U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF4_TIM22           ((uint8_t)0x04U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF4_TIM3            ((uint8_t)0x04U)  /* TIM3 Alternate Function mapping    */
-#define GPIO_AF4_I2C1            ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF5
- *
- */
-#define GPIO_AF5_TIM2          ((uint8_t)0x05U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF5_TIM21         ((uint8_t)0x05U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF5_TIM22         ((uint8_t)0x05U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF5_USART1        ((uint8_t)0x05U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2 Alternate Function mapping       */
-#define GPIO_AF5_I2C2          ((uint8_t)0x05U)  /* I2C2 Alternate Function mapping       */
-/**
-  *
-  */
-
-/*
- * Alternate function AF6
- *
- */
-#define GPIO_AF6_USART4        ((uint8_t)0x06U)  /* USART4 Alternate Function mapping   */
-#define GPIO_AF6_LPUART1       ((uint8_t)0x06U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF6_EVENTOUT      ((uint8_t)0x06U)  /* EVENTOUT Alternate Function mapping  */
-#define GPIO_AF6_I2C1          ((uint8_t)0x06U)  /* I2C1 Alternate Function mapping  */
-#define GPIO_AF6_I2C2          ((uint8_t)0x06U)  /* I2C2 Alternate Function mapping  */
-#define GPIO_AF6_USART5        ((uint8_t)0x06U)  /* USART5 Alternate Function mapping   */
-#define GPIO_AF6_TIM21         ((uint8_t)0x06U)  /* TIM21 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF7
- *
- */
-#define GPIO_AF7_COMP1        ((uint8_t)0x07U)  /* COMP1 Alternate Function mapping     */
-#define GPIO_AF7_COMP2        ((uint8_t)0x07U)  /* COMP2 Alternate Function mapping     */
-#define GPIO_AF7_I2C3         ((uint8_t)0x07U)  /* I2C3 Alternate Function mapping     */
-#define GPIO_AF7_LPUART1      ((uint8_t)0x07U)  /* LPUART1 Alternate Function mapping     */
-/**
-  *
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private  GPIOEx Private
-  * @{
-  */
-
-/**
-  * IS_GPIO_AF macro definition
-  */
-#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
-
-/**
-  * @}
-  */
-#endif /* (STM32L081xx) || (STM32L071xx) */
-
-/*----------------------------------------------------------------------------*/
-/*------------------------- STM32L053xx/STM32L063xx---------------------------*/
-/*----------------------------------------------------------------------------*/
-#if defined (STM32L053xx) || defined (STM32L063xx)
-
-/* The table below gives an overview of the different alternate functions per port.
- * For more details refer yourself to the product data sheet.
- *
- */
-/*     |   AF0  |   AF1  |   AF2  |   AF3  |   AF4  |   AF5  |   AF6  |   AF7  |
- *______________________________________________________________________________
- * PA0 |        |        |TIM2_C1 |TSC     |USART2  |TIM2_TR |        |COMP1   |
- * PA1 |EVENTOUT|LCD     |TIM2_C2 |TSC     |USART2  |TIM21_TR|        |        |
- * PA2 |TIM21_C1|LCD     |TIM2_C3 |TSC     |USART2  |        |        |COMP2   |
- * PA3 |TIM21_C2|LCD     |TIM2_C4 |TSC     |USART2  |        |        |        |
- * PA4 |SPI1    |        |        |TSC     |USART2  |TIM22_TR|        |        |
- * PA5 |SPI1    |        |TIM2_TR |TSC     |        |TIM2_C1 |        |        |
- * PA6 |SPI1    |LCD     |        |TSC     |LPUART  |TIM22_C1|EVENTOUT|COMP1   |
- * PA7 |SPI1    |LCD     |        |TSC     |        |TIM22_C2|EVENTOUT|COMP2   |
- * PA8 |MCO     |LCD     |USB     |EVENTOUT|USART1  |        |        |        |
- * PA9 |MCO     |LCD     |        |TSC     |USART1  |        |        |        |
- * PA10|        |LCD     |        |TSC     |USART1  |        |        |        |
- * PA11|SPI1    |        |EVENTOUT|TSC     |USART1  |        |        |COMP1   |
- * PA12|SPI1    |        |EVENTOUT|TSC     |USART1  |        |        |COMP2   |
- * PA13|SWDIO   |        |USB     |        |        |        |        |        |
- * PA14|SWCLK   |        |        |        |USART2  |        |        |        |
- * PA15|SPI1    |LCD     |TIM2_TR |EVENTOUT|USART2  |TIM2_C1 |        |        |
- *______________________________________________________________________________
- * PB0 |EVENTOUT|LCD     |        |TSC     |        |        |        |        |
- * PB1 |        |LCD     |        |TSC     |LPUART1 |        |        |        |
- * PB2 |        |        |LPTIM1_O|TSC     |        |        |        |        |
- * PB3 |SPI1    |LCD     |TIM2_C2 |TSC     |EVENTOUT|        |        |        |
- * PB4 |SPI1    |LCD     |EVENTOUT|TSC     |TIM22_C1|        |        |        |
- * PB5 |SPI1    |LCD     |LPTIM1_I|I2C1    |TIM22_C2|        |        |        |
- * PB6 |USART1  |I2C1    |LPTIM1_T|TSC     |        |        |        |        |
- * PB7 |USART1  |I2C1    |LPTIM1_I|TSC     |        |        |        |        |
- * PB8 |        |LCD     |        |TSC     |I2C1    |        |        |        |
- * PB9 |        |LCD     |EVENTOUT|        |I2C1    |SPI2    |        |        |
- * PB10|        |LCD     |TIM2_C3 |TSC     |LPUART1 |SPI2    |I2C2    |        |
- * PB11|EVENTOUT|LCD     |TIM2_C4 |TSC     |LPUART1 |        |I2C2    |        |
- * PB12|SPI2    |LCD     |LPUART1 |TSC     |        |I2C2    |EVENTOUT|        |
- * PB13|SPI2    |LCD     |        |TSC     |LPUART1 |I2C2    |TIM21_C1|        |
- * PB14|SPI2    |LCD     |RTC     |TSC     |LPUART1 |I2C2    |TIM21_C2|        |
- * PB15|SPI2    |LCD     |RTC     |        |        |        |        |        |
- *______________________________________________________________________________
- * PC0 |LPTIM1_I|LCD     |EVENTOUT|TSC     |        |        |        |        |
- * PC1 |LPTIM1_O|LCD     |EVENTOUT|TSC     |        |        |        |        |
- * PC2 |LPTIM1_I|LCD     |SPI2    |TSC     |        |        |        |        |
- * PC3 |LPTIM1_T|LCD     |SPI2    |TSC     |        |        |        |        |
- * PC4 |EVENTOUT|LCD     |LPUART  |        |        |        |        |        |
- * PC5 |        |LCD     |LPUART  |TSC     |        |        |        |        |
- * PC6 |TIM22_C1|LCD     |        |TSC     |        |        |        |        |
- * PC7 |TIM22_C2|LCD     |        |TSC     |        |        |        |        |
- * PC8 |TIM22_TR|LCD     |        |TSC     |        |        |        |        |
- * PC9 |TIM21_TR|LCD     |USB     |TSC     |        |        |        |        |
- * PC10|LPUART  |LCD     |        |        |        |        |        |        |
- * PC11|LPUART  |LCD     |        |        |        |        |        |        |
- * PC12|        |LCD     |        |        |        |        |        |        |
- * PC13|        |        |        |        |        |        |        |        |
- * PC14|        |        |        |        |        |        |        |        |
- * PC15|        |        |        |        |        |        |        |        |
- *______________________________________________________________________________
- * PD2 |LPUART  |LCD     |        |        |        |        |        |        |
- *______________________________________________________________________________
- * PH0 |USB     |        |        |        |        |        |        |        |
- * PH1 |        |        |        |        |        |        |        |        |
- *  *
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
-  * @{
-  */
-
-/*
- * Alternate function AF0
- */
-#define GPIO_AF0_SPI1          ((uint8_t)0x00U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF0_SPI2          ((uint8_t)0x00U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF0_USART1        ((uint8_t)0x00U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF0_USART2        ((uint8_t)0x00U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF0_LPUART1       ((uint8_t)0x00U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF0_USB           ((uint8_t)0x00U)  /* USB Alternate Function mapping      */
-#define GPIO_AF0_LPTIM1        ((uint8_t)0x00U)  /* LPTIM1 Alternate Function mapping   */
-#define GPIO_AF0_TSC           ((uint8_t)0x00U)  /* TSC Alternate Function mapping      */
-#define GPIO_AF0_TIM2          ((uint8_t)0x00U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF0_TIM21         ((uint8_t)0x00U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF0_TIM22         ((uint8_t)0x00U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF0_SWDIO         ((uint8_t)0x00U)  /* SWDIO Alternate Function mapping    */
-#define GPIO_AF0_SWCLK         ((uint8_t)0x00U)  /* SWCLK Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF1
- */
-#define GPIO_AF1_SPI1          ((uint8_t)0x01U)  /* SPI1 Alternate Function mapping  */
-#define GPIO_AF1_SPI2          ((uint8_t)0x01U)  /* SPI2 Alternate Function mapping  */
-#define GPIO_AF1_I2C1          ((uint8_t)0x01U)  /* I2C1 Alternate Function mapping  */
-#define GPIO_AF1_LCD           ((uint8_t)0x01U)  /* LCD Alternate Function mapping   */
-/**
-  *
-  */
-
-/*
- * Alternate function AF2
- */
-#define GPIO_AF2_SPI2          ((uint8_t)0x02U)  /* SPI2 Alternate Function mapping       */
-#define GPIO_AF2_LPUART1       ((uint8_t)0x02U)  /* LPUART1 Alternate Function mapping    */
-#define GPIO_AF2_USB           ((uint8_t)0x02U)  /* USB Alternate Function mapping        */
-#define GPIO_AF2_LPTIM1        ((uint8_t)0x02U)  /* LPTIM1 Alternate Function mapping     */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping       */
-#define GPIO_AF2_EVENTOUT      ((uint8_t)0x02U)  /* EVENTOUT Alternate Function mapping   */
-#define GPIO_AF2_RTC           ((uint8_t)0x02U)  /* RTC Alternate Function mapping        */
-/**
-  *
-  */
-
-/*
- * Alternate function AF3
- */
-#define GPIO_AF3_I2C1          ((uint8_t)0x03U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC  Alternate Function mapping     */
-#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03U)  /* EVENTOUT Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF4
- */
-#define GPIO_AF4_I2C1            ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF4_USART1          ((uint8_t)0x04U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF4_USART2          ((uint8_t)0x04U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF4_LPUART1         ((uint8_t)0x04U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF4_TIM22           ((uint8_t)0x04U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF4_EVENTOUT        ((uint8_t)0x04U)  /* EVENTOUT Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF5
- */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF5_I2C2          ((uint8_t)0x05U)  /* I2C2 Alternate Function mapping     */
-#define GPIO_AF5_TIM2          ((uint8_t)0x05U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF5_TIM21         ((uint8_t)0x05U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF5_TIM22         ((uint8_t)0x05U)  /* TIM22 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF6
- */
-#define GPIO_AF6_I2C2          ((uint8_t)0x06U)  /* I2C2 Alternate Function mapping      */
-#define GPIO_AF6_TIM21         ((uint8_t)0x06U)  /* TIM21 Alternate Function mapping     */
-#define GPIO_AF6_EVENTOUT      ((uint8_t)0x06U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF7
- */
-#define GPIO_AF7_COMP1        ((uint8_t)0x07U)  /* COMP1 Alternate Function mapping     */
-#define GPIO_AF7_COMP2        ((uint8_t)0x07U)  /* COMP2 Alternate Function mapping     */
-/**
-  *
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private  GPIOEx Private
-  * @{
-  */
-/**
-  * @brief  IS_GPIO_AF macro definition
-  */
-
-#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
-
-/**
-  * @}
-  */
-
-#endif /* STM32L053xx || STM32L063xx */
-/*------------------------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------*/
-/*------------------------- STM32L052xx/STM32L062xx---------------------------*/
-/*----------------------------------------------------------------------------*/
-#if defined (STM32L052xx) || defined (STM32L062xx)
-
-/* The table below gives an overview of the different alternate functions per port.
- * For more details refer yourself to the product data sheet.
- *
- */
-/*     |   AF0  |   AF1  |   AF2  |   AF3  |   AF4  |   AF5  |   AF6  |   AF7  |
- *______________________________________________________________________________
- * PA0 |        |        |TIM2_C1 |TSC     |USART2  |TIM2_TR |        |COMP1   |
- * PA1 |EVENTOUT|        |TIM2_C2 |TSC     |USART2  |TIM21_TR|        |        |
- * PA2 |TIM21_C1|        |TIM2_C3 |TSC     |USART2  |        |        |COMP2   |
- * PA3 |TIM21_C2|        |TIM2_C4 |TSC     |USART2  |        |        |        |
- * PA4 |SPI1    |        |        |TSC     |USART2  |TIM22_TR|        |        |
- * PA5 |SPI1    |        |TIM2_TR |TSC     |        |TIM2_C1 |        |        |
- * PA6 |SPI1    |        |        |TSC     |LPUART  |TIM22_C1|EVENTOUT|COMP1   |
- * PA7 |SPI1    |        |        |TSC     |        |TIM22_C2|EVENTOUT|COMP2   |
- * PA8 |MCO     |        |USB     |EVENTOUT|USART1  |        |        |        |
- * PA9 |MCO     |        |        |TSC     |USART1  |        |        |        |
- * PA10|        |        |        |TSC     |USART1  |        |        |        |
- * PA11|SPI1    |        |EVENTOUT|TSC     |USART1  |        |        |COMP1   |
- * PA12|SPI1    |        |EVENTOUT|TSC     |USART1  |        |        |COMP2   |
- * PA13|SWDIO   |        |USB     |        |        |        |        |        |
- * PA14|SWCLK   |        |        |        |USART2  |        |        |        |
- * PA15|SPI1    |        |TIM2_TR |EVENTOUT|USART2  |TIM2_C1 |        |        |
- *______________________________________________________________________________
- * PB0 |EVENTOUT|        |        |TSC     |        |        |        |        |
- * PB1 |        |        |        |TSC     |LPUART1 |        |        |        |
- * PB2 |        |        |LPTIM1_O|TSC     |        |        |        |        |
- * PB3 |SPI1    |        |TIM2_C2 |TSC     |EVENTOUT|        |        |        |
- * PB4 |SPI1    |        |EVENTOUT|TSC     |TIM22_C1|        |        |        |
- * PB5 |SPI1    |        |LPTIM1_I|I2C1    |TIM22_C2|        |        |        |
- * PB6 |USART1  |I2C1    |LPTIM1_T|TSC     |        |        |        |        |
- * PB7 |USART1  |I2C1    |LPTIM1_I|TSC     |        |        |        |        |
- * PB8 |        |        |        |TSC     |I2C1    |        |        |        |
- * PB9 |        |        |EVENTOUT|        |I2C1    |SPI2    |        |        |
- * PB10|        |        |TIM2_C3 |TSC     |LPUART1 |SPI2    |I2C2    |        |
- * PB11|EVENTOUT|        |TIM2_C4 |TSC     |LPUART1 |        |I2C2    |        |
- * PB12|SPI2    |        |LPUART1 |TSC     |        |I2C2    |EVENTOUT|        |
- * PB13|SPI2    |        |        |TSC     |LPUART1 |I2C2    |TIM21_C1|        |
- * PB14|SPI2    |        |RTC     |TSC     |LPUART1 |I2C2    |TIM21_C2|        |
- * PB15|SPI2    |        |RTC     |        |        |        |        |        |
- *______________________________________________________________________________
- * PC0 |LPTIM1_I|        |EVENTOUT|TSC     |        |        |        |        |
- * PC1 |LPTIM1_O|        |EVENTOUT|TSC     |        |        |        |        |
- * PC2 |LPTIM1_I|        |SPI2    |TSC     |        |        |        |        |
- * PC3 |LPTIM1_T|        |SPI2    |TSC     |        |        |        |        |
- * PC4 |EVENTOUT|        |LPUART  |        |        |        |        |        |
- * PC5 |        |        |LPUART  |TSC     |        |        |        |        |
- * PC6 |TIM22_C1|        |        |TSC     |        |        |        |        |
- * PC7 |TIM22_C2|        |        |TSC     |        |        |        |        |
- * PC8 |TIM22_TR|        |        |TSC     |        |        |        |        |
- * PC9 |TIM21_TR|        |USB     |TSC     |        |        |        |        |
- * PC10|LPUART  |        |        |        |        |        |        |        |
- * PC11|LPUART  |        |        |        |        |        |        |        |
- * PC12|        |        |        |        |        |        |        |        |
- * PC13|        |        |        |        |        |        |        |        |
- * PC14|        |        |        |        |        |        |        |        |
- * PC15|        |        |        |        |        |        |        |        |
- *______________________________________________________________________________
- * PD2 |LPUART  |        |        |        |        |        |        |        |
- *______________________________________________________________________________
- * PH0 |USB     |        |        |        |        |        |        |        |
- * PH1 |        |        |        |        |        |        |        |        |
- *  *
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
-  * @{
-  */
-
-/*
- * Alternate function AF0
- */
-#define GPIO_AF0_SPI1          ((uint8_t)0x00U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF0_SPI2          ((uint8_t)0x00U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF0_USART1        ((uint8_t)0x00U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF0_USART2        ((uint8_t)0x00U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF0_LPUART1       ((uint8_t)0x00U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF0_USB           ((uint8_t)0x00U)  /* USB Alternate Function mapping      */
-#define GPIO_AF0_LPTIM1        ((uint8_t)0x00U)  /* LPTIM1 Alternate Function mapping   */
-#define GPIO_AF0_TSC           ((uint8_t)0x00U)  /* TSC Alternate Function mapping      */
-#define GPIO_AF0_TIM2          ((uint8_t)0x00U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF0_TIM21         ((uint8_t)0x00U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF0_TIM22         ((uint8_t)0x00U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF0_SWDIO         ((uint8_t)0x00U)  /* SWDIO Alternate Function mapping    */
-#define GPIO_AF0_SWCLK         ((uint8_t)0x00U)  /* SWCLK Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF1
- */
-#define GPIO_AF1_SPI1          ((uint8_t)0x01U)  /* SPI1 Alternate Function mapping  */
-#define GPIO_AF1_SPI2          ((uint8_t)0x01U)  /* SPI2 Alternate Function mapping  */
-#define GPIO_AF1_I2C1          ((uint8_t)0x01U)  /* I2C1 Alternate Function mapping  */
-/**
-  *
-  */
-
-/**
-  * Alternate function AF2
-  */
-#define GPIO_AF2_SPI2          ((uint8_t)0x02U)  /* SPI2 Alternate Function mapping       */
-#define GPIO_AF2_LPUART1       ((uint8_t)0x02U)  /* LPUART1 Alternate Function mapping    */
-#define GPIO_AF2_USB           ((uint8_t)0x02U)  /* USB Alternate Function mapping        */
-#define GPIO_AF2_LPTIM1        ((uint8_t)0x02U)  /* LPTIM1 Alternate Function mapping     */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping       */
-#define GPIO_AF2_EVENTOUT      ((uint8_t)0x02U)  /* EVENTOUT Alternate Function mapping   */
-#define GPIO_AF2_RTC           ((uint8_t)0x02U)  /* RTC Alternate Function mapping        */
-/**
-  *
-  */
-
-/*
- * Alternate function AF3
- */
-#define GPIO_AF3_I2C1          ((uint8_t)0x03U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF3_TSC           ((uint8_t)0x03U)  /* TSC  Alternate Function mapping     */
-#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03U)  /* EVENTOUT Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF4
- */
-#define GPIO_AF4_I2C1            ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF4_USART1          ((uint8_t)0x04U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF4_USART2          ((uint8_t)0x04U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF4_LPUART1         ((uint8_t)0x04U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF4_TIM22           ((uint8_t)0x04U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF4_EVENTOUT        ((uint8_t)0x04U)  /* EVENTOUT Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF5
- */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF5_I2C2          ((uint8_t)0x05U)  /* I2C2 Alternate Function mapping     */
-#define GPIO_AF5_TIM2          ((uint8_t)0x05U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF5_TIM21         ((uint8_t)0x05U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF5_TIM22         ((uint8_t)0x05U)  /* TIM22 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF6
- */
-#define GPIO_AF6_I2C2          ((uint8_t)0x06U)  /* I2C2 Alternate Function mapping      */
-#define GPIO_AF6_TIM21         ((uint8_t)0x06U)  /* TIM21 Alternate Function mapping     */
-#define GPIO_AF6_EVENTOUT      ((uint8_t)0x06U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF7
- */
-#define GPIO_AF7_COMP1        ((uint8_t)0x07U)  /* COMP1 Alternate Function mapping     */
-#define GPIO_AF7_COMP2        ((uint8_t)0x07U)  /* COMP2 Alternate Function mapping     */
-/**
-  *
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private  GPIOEx Private
-  * @{
-  */
-/**
-  * @brief  IS_GPIO_AF macro definition
-  */
-
-#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
-
-/**
-  * @}
-  */
-#endif /* STM32L052xx || STM32L062xx */
-/*------------------------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------*/
-/*------------------------------- STM32L051xx---------------------------------*/
-/*----------------------------------------------------------------------------*/
-#if defined (STM32L051xx)
-/* The table below gives an overview of the different alternate functions per port.
- * For more details refer yourself to the product data sheet.
- *
- */
-/*     |   AF0  |   AF1  |   AF2  |   AF3  |   AF4  |   AF5  |   AF6  |   AF7  |
- *______________________________________________________________________________
- * PA0 |        |        |TIM2_C1 |        |USART2  |TIM2_TR |        |COMP1   |
- * PA1 |EVENTOUT|        |TIM2_C2 |        |USART2  |TIM21_TR|        |        |
- * PA2 |TIM21_C1|        |TIM2_C3 |        |USART2  |        |        |COMP2   |
- * PA3 |TIM21_C2|        |TIM2_C4 |        |USART2  |        |        |        |
- * PA4 |SPI1    |        |        |        |USART2  |TIM22_TR|        |        |
- * PA5 |SPI1    |        |TIM2_TR |        |        |TIM2_C1 |        |        |
- * PA6 |SPI1    |        |        |        |LPUART  |TIM22_C1|EVENTOUT|COMP1   |
- * PA7 |SPI1    |        |        |        |        |TIM22_C2|EVENTOUT|COMP2   |
- * PA8 |MCO     |        |        |EVENTOUT|USART1  |        |        |        |
- * PA9 |MCO     |        |        |        |USART1  |        |        |        |
- * PA10|        |        |        |        |USART1  |        |        |        |
- * PA11|SPI1    |        |EVENTOUT|        |USART1  |        |        |COMP1   |
- * PA12|SPI1    |        |EVENTOUT|        |USART1  |        |        |COMP2   |
- * PA13|SWDIO   |        |        |        |        |        |        |        |
- * PA14|SWCLK   |        |        |        |USART2  |        |        |        |
- * PA15|SPI1    |        |TIM2_TR |EVENTOUT|USART2  |TIM2_C1 |        |        |
- *______________________________________________________________________________
- * PB0 |EVENTOUT|        |        |        |        |        |        |        |
- * PB1 |        |        |        |        |LPUART1 |        |        |        |
- * PB2 |        |        |LPTIM1_O|        |        |        |        |        |
- * PB3 |SPI1    |        |TIM2_C2 |        |EVENTOUT|        |        |        |
- * PB4 |SPI1    |        |EVENTOUT|        |TIM22_C1|        |        |        |
- * PB5 |SPI1    |        |LPTIM1_I|I2C1    |TIM22_C2|        |        |        |
- * PB6 |USART1  |I2C1    |LPTIM1_T|        |        |        |        |        |
- * PB7 |USART1  |I2C1    |LPTIM1_I|        |        |        |        |        |
- * PB8 |        |        |        |        |I2C1    |        |        |        |
- * PB9 |        |        |EVENTOUT|        |I2C1    |SPI2    |        |        |
- * PB10|        |        |TIM2_C3 |        |LPUART1 |SPI2    |I2C2    |        |
- * PB11|EVENTOUT|        |TIM2_C4 |        |LPUART1 |        |I2C2    |        |
- * PB12|SPI2    |        |LPUART1 |        |        |I2C2    |EVENTOUT|        |
- * PB13|SPI2    |        |        |        |LPUART1 |I2C2    |TIM21_C1|        |
- * PB14|SPI2    |        |RTC     |        |LPUART1 |I2C2    |TIM21_C2|        |
- * PB15|SPI2    |        |RTC     |        |        |        |        |        |
- *______________________________________________________________________________
- * PC0 |LPTIM1_I|        |EVENTOUT|        |        |        |        |        |
- * PC1 |LPTIM1_O|        |EVENTOUT|        |        |        |        |        |
- * PC2 |LPTIM1_I|        |SPI2    |        |        |        |        |        |
- * PC3 |LPTIM1_T|        |SPI2    |        |        |        |        |        |
- * PC4 |EVENTOUT|        |LPUART  |        |        |        |        |        |
- * PC5 |        |        |LPUART  |        |        |        |        |        |
- * PC6 |TIM22_C1|        |        |        |        |        |        |        |
- * PC7 |TIM22_C2|        |        |        |        |        |        |        |
- * PC8 |TIM22_TR|        |        |        |        |        |        |        |
- * PC9 |TIM21_TR|        |        |        |        |        |        |        |
- * PC10|LPUART  |        |        |        |        |        |        |        |
- * PC11|LPUART  |        |        |        |        |        |        |        |
- * PC12|        |        |        |        |        |        |        |        |
- * PC13|        |        |        |        |        |        |        |        |
- * PC14|        |        |        |        |        |        |        |        |
- * PC15|        |        |        |        |        |        |        |        |
- *______________________________________________________________________________
- * PD2 |LPUART  |        |        |        |        |        |        |        |
- *______________________________________________________________________________
- * PH0 |        |        |        |        |        |        |        |        |
- * PH1 |        |        |        |        |        |        |        |        |
- *  *
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
-  * @{
-  */
-
-/*
- * Alternate function AF0
- */
-#define GPIO_AF0_SPI1          ((uint8_t)0x00U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF0_SPI2          ((uint8_t)0x00U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF0_USART1        ((uint8_t)0x00U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF0_USART2        ((uint8_t)0x00U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF0_LPUART1       ((uint8_t)0x00U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF0_LPTIM1        ((uint8_t)0x00U)  /* LPTIM1 Alternate Function mapping   */
-#define GPIO_AF0_TIM2          ((uint8_t)0x00U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF0_TIM21         ((uint8_t)0x00U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF0_TIM22         ((uint8_t)0x00U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF0_SWDIO         ((uint8_t)0x00U)  /* SWDIO Alternate Function mapping    */
-#define GPIO_AF0_SWCLK         ((uint8_t)0x00U)  /* SWCLK Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF1
- */
-#define GPIO_AF1_SPI1          ((uint8_t)0x01U)  /* SPI1 Alternate Function mapping  */
-#define GPIO_AF1_SPI2          ((uint8_t)0x01U)  /* SPI2 Alternate Function mapping  */
-#define GPIO_AF1_I2C1          ((uint8_t)0x01U)  /* I2C1 Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF2
- */
-#define GPIO_AF2_SPI2          ((uint8_t)0x02U)  /* SPI2 Alternate Function mapping       */
-#define GPIO_AF2_LPUART1       ((uint8_t)0x02U)  /* LPUART1 Alternate Function mapping    */
-#define GPIO_AF2_USB           ((uint8_t)0x02U)  /* USB Alternate Function mapping        */
-#define GPIO_AF2_LPTIM1        ((uint8_t)0x02U)  /* LPTIM1 Alternate Function mapping     */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping       */
-#define GPIO_AF2_EVENTOUT      ((uint8_t)0x02U)  /* EVENTOUT Alternate Function mapping   */
-#define GPIO_AF2_RTC           ((uint8_t)0x02U)  /* RTC Alternate Function mapping        */
-/**
-  *
-  */
-
-/*
- * Alternate function AF3
- */
-#define GPIO_AF3_I2C1          ((uint8_t)0x03U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03U)  /* EVENTOUT Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF4
- */
-#define GPIO_AF4_I2C1            ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF4_USART1          ((uint8_t)0x04U)  /* USART1 Alternate Function mapping   */
-#define GPIO_AF4_USART2          ((uint8_t)0x04U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF4_LPUART1         ((uint8_t)0x04U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF4_TIM22           ((uint8_t)0x04U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF4_EVENTOUT        ((uint8_t)0x04U)  /* EVENTOUT Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF5
- */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2 Alternate Function mapping     */
-#define GPIO_AF5_I2C2          ((uint8_t)0x05U)  /* I2C2 Alternate Function mapping     */
-#define GPIO_AF5_TIM2          ((uint8_t)0x05U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF5_TIM21         ((uint8_t)0x05U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF5_TIM22         ((uint8_t)0x05U)  /* TIM22 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF6
- */
-#define GPIO_AF6_I2C2          ((uint8_t)0x06U)  /* I2C2 Alternate Function mapping      */
-#define GPIO_AF6_TIM21         ((uint8_t)0x06U)  /* TIM21 Alternate Function mapping     */
-#define GPIO_AF6_EVENTOUT      ((uint8_t)0x06U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF7
- */
-#define GPIO_AF7_COMP1        ((uint8_t)0x07U)  /* COMP1 Alternate Function mapping     */
-#define GPIO_AF7_COMP2        ((uint8_t)0x07U)  /* COMP2 Alternate Function mapping     */
-/**
-  *
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private  GPIOEx Private
-  * @{
-  */
-
-/**
-  * @brief  IS_GPIO_AF macro definition
-  */
-#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
-
-/**
-  * @}
-  */
-#endif /* STM32L051xx */
-/*------------------------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------*/
-/*------------------------- STM32L031xx/STM32L041xx---------------------------*/
-/*----------------------------------------------------------------------------*/
-#if defined (STM32L031xx)|| defined (STM32L041xx)
-/* The table below gives an overview of the different alternate functions per port.
- * For more details refer yourself to the product data sheet.
- *
- */
-/*     |   AF0  |   AF1  |   AF2  |   AF3  |   AF4  |   AF5  |   AF6  |   AF7  |
- *______________________________________________________________________________
- * PA0 |        |LPTIM1  |TIM2_C1 |        |USART2  |TIM2_TR |        |COMP1   |
- * PA1 |EVENTOUT|LPTIM1  |TIM2_C2 |I2C1    |USART2  |TIM21_TR|        |        |
- * PA2 |TIM21_C1|        |TIM2_C3 |        |USART2  |        |LPUART1 |COMP2   |
- * PA3 |TIM21_C2|        |TIM2_C4 |        |USART2  |        |LPUART1 |        |
- * PA4 |SPI1    |LPTIM1  |        |        |USART2  |TIM22_TR|        |        |
- * PA5 |SPI1    |LPTIM1  |TIM2_TR |        |        |TIM2_C1 |        |        |
- * PA6 |SPI1    |LPTIM1  |        |        |LPUART  |TIM22_C1|EVENTOUT|COMP1   |
- * PA7 |SPI1    |LPTIM1  |        |        |USART2  |TIM22_C2|EVENTOUT|COMP2   |
- * PA8 |MCO     |        |LPTIM1  |EVENTOUT|USART2  |TIM2_C1 |        |        |
- * PA9 |MCO     |I2C1    |        |        |USART2  |TIM22_C1|        |        |
- * PA10|        |I2C1    |        |        |USART2  |TIM22_C2|        |        |
- * PA11|SPI1    |        |EVENTOUT|        |USART2  |TIM21_C2|        |COMP1   |
- * PA12|SPI1    |        |EVENTOUT|        |USART2  |        |        |COMP2   |
- * PA13|SWDIO   |LPTIM1  |        |        |        |        |LPUART1 |        |
- * PA14|SWCLK   |LPTIM1  |        |I2C1    |USART2  |        |LPUART1 |        |
- * PA15|SPI1    |        |TIM2_TR |EVENTOUT|USART2  |TIM2_C1 |        |        |
- *_____________________________________________________________________________|
- * PB0 |EVENTOUT|SPI1    |        |        |USART2  |TIM2_C3 |        |        |
- * PB1 |USART2  |SPI1    |        |        |LPUART1 |TIM2_C4 |        |        |
- * PB2 |        |        |LPTIM1_O|        |        |        |        |        |
- * PB3 |SPI1    |        |TIM2_C2 |        |EVENTOUT|        |        |        |
- * PB4 |SPI1    |        |EVENTOUT|        |TIM22_C1|        |        |        |
- * PB5 |SPI1    |        |LPTIM1_I|I2C1    |TIM22_C2|        |        |        |
- * PB6 |USART2  |I2C1    |LPTIM1_T|        |        |TIM21_C1|        |        |
- * PB7 |USART2  |I2C1    |LPTIM1_I|        |        |        |        |        |
- * PB8 |        |        |        |        |I2C1    |        |        |        |
- * PB9 |        |        |EVENTOUT|        |I2C1    |        |        |        |
- * PB10|        |        |TIM2_C3 |        |        |        |LPUART1 |        |
- * PB11|EVENTOUT|        |TIM2_C4 |        |        |        |LPUART1 |        |
- * PB12|SPI2    |        |        |        |        |        |EVENTOUT|        |
- * PB13|SPI2    |        |MCO     |        |        |TIM21_C1|LPUART1 |        |
- * PB14|SPI2    |        |RTC     |        |        |TIM21_C2|LPUART1 |        |
- * PB15|SPI2    |        |RTC     |        |        |        |        |        |
- *_____________________________________________________________________________|
- * PC0 |LPTIM1_I|        |EVENTOUT|        |        |        |LPUART1 |        |
- * PC13|        |        |        |        |        |        |        |        |
- * PC14|        |        |        |        |        |        |        |        |
- * PC15|        |        |        |        |        |        |        |        |
- *_____________________________________________________________________________|
- * PH0 |        |        |        |        |        |        |        |        |
- * PH1 |        |        |        |        |        |        |        |        |
- *_____________________________________________________________________________|
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
-  * @{
-  */
-
-/*
- * Alternate function AF0
- */
-#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF0_TIM21         ((uint8_t)0x00U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF0_SPI1          ((uint8_t)0x00U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF0_USART2        ((uint8_t)0x00U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF0_LPTIM1        ((uint8_t)0x00U)  /* LPTIM1 Alternate Function mapping   */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF0_SWDIO         ((uint8_t)0x00U)  /* SWDIO Alternate Function mapping    */
-#define GPIO_AF0_SWCLK         ((uint8_t)0x00U)  /* SWCLK Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF1
- */
-#define GPIO_AF1_SPI1          ((uint8_t)0x01U)  /* SPI1 Alternate Function mapping   */
-#define GPIO_AF1_I2C1          ((uint8_t)0x01U)  /* I2C1 Alternate Function mapping   */
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01U)  /* LPTIM1 Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF2
- */
-#define GPIO_AF2_LPTIM1        ((uint8_t)0x02U)  /* LPTIM1 Alternate Function mapping     */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping       */
-#define GPIO_AF2_MCO           ((uint8_t)0x02U)  /* MCO Alternate Function mapping        */
-#define GPIO_AF2_EVENTOUT      ((uint8_t)0x02U)  /* EVENTOUT Alternate Function mapping   */
-#define GPIO_AF2_RTC           ((uint8_t)0x02U)  /* RTC Alternate Function mapping        */
-/**
-  *
-  */
-
-/*
- * Alternate function AF3
- */
-#define GPIO_AF3_I2C1          ((uint8_t)0x03U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF4
- */
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF4_USART2        ((uint8_t)0x04U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF4_LPUART1       ((uint8_t)0x04U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF4_TIM22         ((uint8_t)0x04U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF4_EVENTOUT      ((uint8_t)0x04U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF5
- */
-#define GPIO_AF5_TIM2          ((uint8_t)0x05U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF5_TIM21         ((uint8_t)0x05U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF5_TIM22         ((uint8_t)0x05U)  /* TIM22 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF6
- */
-#define GPIO_AF6_LPUART1       ((uint8_t)0x06U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF6_EVENTOUT      ((uint8_t)0x06U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF7
- */
-#define GPIO_AF7_COMP1         ((uint8_t)0x07U)  /* COMP1 Alternate Function mapping     */
-#define GPIO_AF7_COMP2         ((uint8_t)0x07U)  /* COMP2 Alternate Function mapping     */
-/**
-  *
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private  GPIOEx Private
-  * @{
-  */
-/**
-  * @brief  IS_GPIO_AF macro definition
-  */
-
-#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
-
-/**
-  * @}
-  */
-
-#endif /* STM32L031xx/STM32L041xx*/
-/*------------------------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------*/
-/*------------------------- STM32L011xx/STM32L021xx---------------------------*/
-/*----------------------------------------------------------------------------*/
-#if defined (STM32L011xx)|| defined (STM32L021xx)
-/* The table below gives an overview of the different alternate functions per port.
- * For more details refer yourself to the product data sheet.
- *
- */
-/*     |   AF0   |   AF1    |   AF2  |   AF3   |   AF4    |   AF5  |   AF6     |   AF7   |
- *______________________________________________________________________________________
- * PA0 |USART2_RX|LPTIM1_IN1|TIM2_C1  |        |USART2_CTS|TIM2_ETR|LPUART1_RX |COMP1_OUT|
- * PA1 |EVENTOUT |LPTIM1_IN2|TIM2_C2  |I2C1    |USART2_RTS|TIM21_TR|LPUART1_TX |         |
- * PA2 |TIM21_C1 |          |TIM2_C3  |        |USART2_TX |        |LPUART1_TX |COMP2_OUT|
- * PA3 |TIM21_C2 |          |TIM2_C4  |        |USART2_RX |        |LPUART1_RX |         |
- * PA4 |SPI1     |LPTIM1_IN1|LPTIM1_TR|I2C1_SCL|USART2_CK |TIM2_TR |LPUART1_TX |COMP2_OUT|
- * PA5 |SPI1     |LPTIM1_IN2|TIM2_TR  |        |          |TIM2_C1 |           |         |
- * PA6 |SPI1     |LPTIM1_ETR|         |        |LPUART1_CT|        |EVENTOUT   |COMP1_OUT|
- * PA7 |SPI1     |LPTIM1_OUT|         |        |USART2_CTS|TIM21_T |EVENTOUT   |COMP2_OUT|
- * PA8 |MCO      |          |LPTIM1_I1|EVENTOUT|USART2_CK |TIM2_C1 |           |         |
- * PA9 |MCO      |I2C1_SCL  |LPTIM1_O |        |USART2_TX |TIM21_C2|           |COMP1_OUT|
- * PA10|TIM21_C1 |I2C1_SDA  |RTC_REFIN|        |USART2_RX |TIM2_C3 |           |COMP1_OUT|
- * PA11|SPI1     |LPTIM1_OUT|EVENTOUT |        |USART2_CTS|TIM21_C2|           |COMP1_OUT|
- * PA12|SPI1     |          |EVENTOUT |        |USART2_RTS|        |           |COMP2_OUT|
- * PA13|SWDIO    |LPTIM1_T  |         |I2C1_SDA|          |SPI1    |LPUART1_RX |COMP1_OUT|
- * PA14|SWCLK    |LPTIM1_O  |         |I2C1_SMB|USART2_TX |SPI1    |LPUART1_TX |COMP2_OUT|
- * PA15|SPI1     |          |TIM2_TR  |EVENTOUT|USART2_RX |TIM2_C1 |           |         |
- *______________________________________________________________________________________ |
- * PB0 |EVENTOUT |SPI1      |TIM2_C2  |        |USART2_RTS|TIM2_C3 |           |         |
- * PB1 |USART2_CK|SPI1      |LPTIM1_I1|        |LPUART1_RT|TIM2_C4 |           |         |
- * PB2 |         |          |LPTIM1_O |        |          |        |           |         |
- * PB3 |SPI1     |          |TIM2_C2  |        |EVENTOUT  |        |           |         |
- * PB4 |SPI1     |          |EVENTOUT |        |          |        |           |         |
- * PB5 |SPI1     |          |LPTIM1_I1|I2C1    |          |TIM21_C1|           |         |
- * PB6 |USART2_TX|I2C1_SCL  |LPTIM1_T |        |          |TIM2_C3 |LPUART1_TX |         |
- * PB7 |USART2_RX|I2C1      |LPTIM1_I2|        |          |TIM2_C4 |LPUART1_RX |         |
- * PB8 |USART2_TX|          |EVENTOUT |        |I2C1      |SPI1    |           |         |
- * PB9 |         |          |         |        |          |        |           |         |
- *______________________________________________________________________________________ |
- * PC14|         |          |         |        |          |        |           |         |
- * PC15|         |          |         |        |          |        |           |         |
- *______________________________________________________________________________________ |
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
-  * @{
-  */
-
-/*
- * Alternate function AF0
- */
-#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF0_TIM21         ((uint8_t)0x00U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF0_SPI1          ((uint8_t)0x00U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF0_USART2        ((uint8_t)0x00U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF0_SWDIO         ((uint8_t)0x00U)  /* SWDIO Alternate Function mapping    */
-#define GPIO_AF0_SWCLK         ((uint8_t)0x00U)  /* SWCLK Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- *  Alternate function AF1
- */
-#define GPIO_AF1_SPI1          ((uint8_t)0x01U)  /* SPI1 Alternate Function mapping   */
-#define GPIO_AF1_I2C1          ((uint8_t)0x01U)  /* I2C1 Alternate Function mapping   */
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01U)  /* LPTIM1 Alternate Function mapping */
-/**
-  *
-  */
-
-/*  Alternate function AF2
- *
- */
-#define GPIO_AF2_LPTIM1        ((uint8_t)0x02U)  /* LPTIM1 Alternate Function mapping     */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping       */
-#define GPIO_AF2_RTC           ((uint8_t)0x02U)  /* RTC Alternate Function mapping        */
-#define GPIO_AF2_EVENTOUT      ((uint8_t)0x02U)  /* EVENTOUT Alternate Function mapping   */
-/**
-  *
-  */
-
-/*
- * Alternate function AF3
- */
-#define GPIO_AF3_I2C1          ((uint8_t)0x03U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF4
- */
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF4_USART2        ((uint8_t)0x04U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF4_LPUART1       ((uint8_t)0x04U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF4_EVENTOUT      ((uint8_t)0x04U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF5
- */
-#define GPIO_AF5_TIM2          ((uint8_t)0x05U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF5_TIM21         ((uint8_t)0x05U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF6
- */
-#define GPIO_AF6_LPUART1       ((uint8_t)0x06U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF6_EVENTOUT      ((uint8_t)0x06U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF7
- */
-#define GPIO_AF7_COMP1         ((uint8_t)0x07U)  /* COMP1 Alternate Function mapping     */
-#define GPIO_AF7_COMP2         ((uint8_t)0x07U)  /* COMP2 Alternate Function mapping     */
-/**
-  *
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private  GPIOEx Private
-  * @{
-  */
-/**
-  *  IS_GPIO_AF macro definition
-  */
-
-#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
-
-/**
-  * @}
-  */
-
-#endif /* STM32L011xx/STM32L021xx*/
-
-/*----------------------------------------------------------------------------*/
-/*----------------------------- STM32L010xB ----------------------------------*/
-/*----------------------------------------------------------------------------*/
-#if defined (STM32L010xB)
-/* The table below gives an overview of the different alternate functions per port.
- * For more details refer yourself to the product data sheet.
- *
- */
-/*     |   AF0     |   AF1    |   AF2     |   AF3   |   AF4     |   AF5   |   AF6     |   AF7    |
- *_______________________________________________________________________________________________|
- * PA0 |           |          |TIM2_CH1   |         |USART2_CTS |TIM2_ETR |           |          |
- * PA1 |EVENTOUT   |          |TIM2_CH2   |         |USART2_RTS |TIM21_ETR|           |          |
- * PA2 |TIM21_CH1  |          |TIM2_CH3   |         |USART2_TX  |         |LPUART1_TX |          |
- * PA3 |TIM21_CH2  |          |TIM2_CH4   |         |USART2_RX  |         |LPUART1_RX |          |
- * PA4 |SPI1_NSS   |          |           |         |USART2_CK  |TIM22_ETR|           |          |
- * PA5 |SPI1_SCK   |          |TIM2_ETR   |         |           |TIM2_CH1 |           |          |
- * PA6 |SPI1_MISO  |          |           |         |LPUART1_CTS|TIM22_CH1|EVENTOUT   |          |
- * PA7 |SPI1_MOSI  |          |           |         |           |TIM22_CH2|EVENTOUT   |          |
- * PA8 |MCO        |          |           |EVENTOUT |           |         |           |          |
- * PA9 |MCO        |          |           |         |           |         |I2C1_SCL   |          |
- * PA10|           |          |           |         |           |         |I2C1_SDA   |          |
- * PA11|SPI1_MISO  |          |EVENTOUT   |         |           |         |           |          |
- * PA12|SPI1_MOSI  |          |EVENTOUT   |         |           |         |           |          |
- * PA13|SWDIO      |          |           |         |           |         |LPUART1_RX |          |
- * PA14|SWCLK      |          |           |         |USART2_TX  |         |LPUART1_TX |          |
- * PA15|SPI1_NSS   |          |TIM2_ETR   |EVENTOUT |USART2_RX  |TIM2_CH1 |           |          |
- *_______________________________________________________________________________________________|
- * PB0 |EVENTOUT   |          |           |         |           |         |           |          |
- * PB1 |           |          |           |         |LPUART1_RTS|         |           |          |
- * PB2 |           |          |LPTIM1_OUT |         |           |         |           |          |
- * PB3 |SPI1_SCK   |          |TIM2_CH2   |         |EVENTOUT   |         |           |          |
- * PB4 |SPI1_MISO  |          |           |         |TIM22_CH1  |         |           |          |
- * PB5 |SPI1_MOSI  |          |LPTIM1_IN1 |I2C1_SMBA|TIM22_CH2  |         |           |          |
- * PB6 |           |I2C1_SCL  |LPTIM1_ETR |         |           |         |           |          |
- * PB7 |           |I2C1_SDA  |LPTIM1_IN2 |         |           |         |           |          |
- * PB8 |           |          |           |         |I2C1_SCL   |         |           |          |
- * PB9 |           |          |EVENTOUT   |         |I2C1_SDA   |         |           |          |
- * PB10|           |          |TIM2_CH3   |         |LPUART1_TX |         |           |LPUART1_RX|
- * PB11|EVENTOUT   |          |TIM2_CH4   |         |LPUART1_RX |         |           |LPUART1_TX|
- * PB12|           |          |LPUART1_RTS|         |           |         |EVENTOUT   |          |
- * PB13|           |          |MCO        |         |LPUART1_CTS|         |TIM21_CH1  |          |
- * PB14|           |          |RTC_OUT    |         |LPUART1_RTS|         |TIM21_CH2  |          |
- * PB15|           |          |RTC_REFIN  |         |           |         |           |          |
- *_______________________________________________________________________________________________|
- * PC0 |LPTIM1_IN1 |          |EVENTOUT   |         |           |         |LPUART1_RX |          |
- * PC1 |LPTIM1_OUT |          |EVENTOUT   |         |           |         |LPUART1_TX |          |
- * PC2 |LPTIM1_IN2 |          |           |         |           |         |           |          |
- * PC3 |LPTIM1_ETR |          |           |         |           |         |           |          |
- * PC4 |EVENTOUT   |          |LPUART1_TX |         |           |         |           |          |
- * PC5 |           |          |LPUART1_RX |         |           |         |           |          |
- * PC6 |TIM22_CH1  |          |           |         |           |         |           |          |
- * PC7 |TIM22_CH2  |          |           |         |           |         |           |          |
- * PC8 |TIM22_ETR  |          |           |         |           |         |           |          |
- * PC9 |TIM21_ETR  |          |           |         |           |         |           |          |
- * PC10|LPUART1_TX |          |           |         |           |         |           |          |
- * PC11|LPUART1_RX |          |           |         |           |         |           |          |
- *_______________________________________________________________________________________________|
- * PD2 |LPUART1_RTS|          |           |         |           |         |           |          |
- *_______________________________________________________________________________________________|
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
-  * @{
-  */
-
-/*
- * Alternate function AF0
- *
- */
-#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF0_TIM21         ((uint8_t)0x00U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF0_SPI1          ((uint8_t)0x00U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF0_SWDIO         ((uint8_t)0x00U)  /* SWDIO Alternate Function mapping    */
-#define GPIO_AF0_SWCLK         ((uint8_t)0x00U)  /* SWCLK Alternate Function mapping    */
-#define GPIO_AF0_LPTIM1        ((uint8_t)0x00U)  /* LPTIM1 Alternate Function mapping   */
-#define GPIO_AF0_TIM22         ((uint8_t)0x00U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF0_LPUART1       ((uint8_t)0x00U)  /* LPUART1 Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF1
- *
- */
-#define GPIO_AF1_I2C1          ((uint8_t)0x01U)  /* I2C1 Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF2
- *
- */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF2_EVENTOUT      ((uint8_t)0x02U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF2_LPTIM1        ((uint8_t)0x02U)  /* LPTIM1 Alternate Function mapping   */
-#define GPIO_AF2_LPUART1       ((uint8_t)0x02U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF2_MCO           ((uint8_t)0x02U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF2_RTC           ((uint8_t)0x02U)  /* RTC Alternate Function mapping      */
-/**
-  *
-  */
-
-/*
- * Alternate function AF3
- * @{
- */
-#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF3_I2C1          ((uint8_t)0x03U)  /* I2C1 Alternate Function mapping     */
-/**
-  *
-  */
-
-/*
- * Alternate function AF4
- *
- */
-#define GPIO_AF4_USART2          ((uint8_t)0x04U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF4_LPUART1         ((uint8_t)0x04U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF4_EVENTOUT        ((uint8_t)0x04U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF4_TIM22           ((uint8_t)0x04U)  /* TIM22 Alternate Function mapping    */
-#define GPIO_AF4_I2C1            ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF5
- *
- */
-#define GPIO_AF5_TIM2          ((uint8_t)0x05U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF5_TIM21         ((uint8_t)0x05U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF5_TIM22         ((uint8_t)0x05U)  /* TIM22 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF6
- *
- */
-#define GPIO_AF6_LPUART1       ((uint8_t)0x06U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF6_EVENTOUT      ((uint8_t)0x06U)  /* EVENTOUT Alternate Function mapping  */
-#define GPIO_AF6_I2C1          ((uint8_t)0x06U)  /* I2C1 Alternate Function mapping  */
-#define GPIO_AF6_TIM21         ((uint8_t)0x06U)  /* TIM21 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF7
- *
- */
-#define GPIO_AF7_LPUART1      ((uint8_t)0x07U)  /* LPUART1 Alternate Function mapping     */
-/**
-  *
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private  GPIOEx Private
-  * @{
-  */
-
-/**
-  * IS_GPIO_AF macro definition
-  */
-#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
-
-/**
-  * @}
-  */
-
-#endif /* STM32L010xB */
-
-/*----------------------------------------------------------------------------*/
-/*------------------------- STM32L010x8 --------------------------------------*/
-/*----------------------------------------------------------------------------*/
-#if defined (STM32L010x8)
-/* The table below gives an overview of the different alternate functions per port.
- * For more details refer yourself to the product data sheet.
- *
- */
-/*      |   AF0       |   AF1      |   AF2       |   AF3    |   AF4      |   AF5      |   AF6     |
- *________________________________________________________________________________________________|
- * PA0  |             |            | TIM2_CH1    |          | USART2_CTS  | TIM2_ETR  |           |
- * PA1  | EVENTOUT    |            | TIM2_CH2    |          | USART2_RTS  | TIM21_ETR |           |
- * PA2  | TIM21_CH1   |            | TIM2_CH3    |          | USART2_TX   |           |           |
- * PA3  | TIM21_CH2   |            | TIM2_CH4    |          | USART2_RX   |           |           |
- * PA4  | SPI1_NSS    |            |             |          | USART2_CK   |           |           |
- * PA5  | SPI1_SCK    |            | TIM2_ETR    |          |             | TIM2_CH1  |           |
- * PA6  | SPI1_MISO   |            |             |          | LPUART1_CTS |           | EVENTOUT  |
- * PA7  | SPI1_MOSI   |            |             |          |             |           | EVENTOUT  |
- * PA8  | MCO         |            |             | EVENTOUT |             |           |           |
- * PA9  | MCO         |            |             |          |             |           |           |
- * PA10 |             |            |             |          |             |           |           |
- * PA11 | SPI1_MISO   |            | EVENTOUT    |          |             |           |           |
- * PA12 | SPI1_MOSI   |            | EVENTOUT    |          |             |           |           |
- * PA13 | SWDIO       |            |             |          |             |           |           |
- * PA14 | SWCLK       |            |             |          | USART2_TX   |           |           |
- * PA15 | SPI1_NSS    |            | TIM2_ETR    | EVENTOUT | USART2_RX   | TIM2_CH1  |           |
- *________________________________________________________________________________________________|
- * PB0  | EVENTOUT    |            |             |          |             |           |           |
- * PB1  |             |            |             |          | LPUART1_RTS |           |           |
- * PB2  |             |            | LPTIM1_OUT  |          |             |           |           |
- * PB3  | SPI1_SCK    |            | TIM2_CH2    |          | EVENTOUT    |           |           |
- * PB4  | SPI1_MISO   | EVENTOUT   |             |          |             |           |           |
- * PB5  | SPI1_MOSI   | LPTIM1_IN1 | I2C1_SMBA   |          |             |           |           |
- * PB6  |             | I2C1_SCL   | LPTIM1_ETR  |          |             |           |           |
- * PB7  |             | I2C1_SDA   | LPTIM1_IN2  |          |             |           |           |
- * PB8  |             |            |             |          | I2C1_SCL    |           |           |
- * PB9  |             |            | EVENTOUT    |          | I2C1_SDA    |           |           |
- * PB10 |             |            | TIM2_CH3    |          | LPUART1_TX  |           |           |
- * PB11 | EVENTOUT    |            | TIM2_CH4    |          | LPUART1_RX  |           |           |
- * PB12 |             |            | LPUART1_RTS |          |             | EVENTOUT  |           |
- * PB13 |             |            |             |          | LPUART1_CTS |           | TIM21_CH1 |
- * PB14 |             |            | RTC_OUT     |          | LPUART1_RTS |           | TIM21_CH2 |
- * PB15 |             |            | RTC_REFIN   |          |             |           |           |
- *________________________________________________________________________________________________|
- * PC0  | LPTIM1_IN1  |            | EVENTOUT    |          |             |           |           |
- * PC1  | LPTIM1_OUT  |            | EVENTOUT    |          |             |           |           |
- * PC2  | LPTIM1_IN2  |            |             |          |             |           |           |
- * PC3  | LPTIM1_ETR  |            |             |          |             |           |           |
- * PC4  | EVENTOUT    |            | LPUART1_TX  |          |             |           |           |
- * PC5  |             |            | LPUART1_RX  |          |             |           |           |
- * PC9  | TIM21_ETR   |            |             |          |             |           |           |
- * PC10 | LPUART1_TX  |            |             |          |             |           |           |
- * PC11 | LPUART1_RX  |            |             |          |             |           |           |
- * PD2  | LPUART1_RTS |            |             |          |             |           |           |
- *________________________________________________________________________________________________|
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
-  * @{
-  */
-
-/*
- * Alternate function AF0
- */
-#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF0_TIM21         ((uint8_t)0x00U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF0_SPI1          ((uint8_t)0x00U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF0_SWDIO         ((uint8_t)0x00U)  /* SWDIO Alternate Function mapping    */
-#define GPIO_AF0_SWCLK         ((uint8_t)0x00U)  /* SWCLK Alternate Function mapping    */
-#define GPIO_AF0_LPTIM1        ((uint8_t)0x00U)  /* LPTIM1 Alternate Function mapping   */
-#define GPIO_AF0_LPUART1       ((uint8_t)0x00U)  /* LPUART1 Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF1
- */
-#define GPIO_AF1_I2C1          ((uint8_t)0x01U)  /* I2C1 Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF2
- */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping       */
-#define GPIO_AF2_EVENTOUT      ((uint8_t)0x02U)  /* EVENTOUT Alternate Function mapping   */
-#define GPIO_AF2_LPTIM1        ((uint8_t)0x02U)  /* LPTIM1 Alternate Function mapping     */
-#define GPIO_AF2_LPUART1       ((uint8_t)0x02U)  /* LPUART1 Alternate Function mapping    */
-#define GPIO_AF2_RTC           ((uint8_t)0x02U)  /* RTC Alternate Function mapping        */
-/**
-  *
-  */
-
-/*
- * Alternate function AF3
- */
-#define GPIO_AF3_I2C1          ((uint8_t)0x03U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03U)  /* EVENTOUT Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF4
- */
-#define GPIO_AF4_USART2          ((uint8_t)0x04U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF4_LPUART1         ((uint8_t)0x04U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF4_I2C1            ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF4_EVENTOUT        ((uint8_t)0x04U)  /* EVENTOUT Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF5
- */
-#define GPIO_AF5_TIM2          ((uint8_t)0x05U)  /* TIM2 Alternate Function mapping     */
-/**
-  *
-  */
-
-/*
- * Alternate function AF6
- */
-#define GPIO_AF6_TIM21         ((uint8_t)0x06U)  /* TIM21 Alternate Function mapping     */
-#define GPIO_AF6_EVENTOUT      ((uint8_t)0x06U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private  GPIOEx Private
-  * @{
-  */
-
-/**
-  * @brief  IS_GPIO_AF macro definition
-  */
-#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x06)
-
-/**
-  * @}
-  */
-#endif /* STM32L010x8 */
-
-
-/*----------------------------------------------------------------------------*/
-/*------------------------- STM32L010x6 --------------------------------------*/
-/*----------------------------------------------------------------------------*/
-#if defined (STM32L010x6)
-/* The table below gives an overview of the different alternate functions per port.
- * For more details refer yourself to the product data sheet.
- *
- */
-/*      |   AF0      |   AF1      |   AF2      |     AF3     |   AF4       |   AF5     |   AF6      |
- *__________________________________________________________________________________________________|
- * PA1  | EVENTOUT   | LPTIM1_IN2 | TIM2_CH2   | I2C1_SMBA   | USART2_RTS  | TIM21_ETR |            |
- * PA2  | TIM21_CH1  |            | TIM2_CH3   |             | USART2_TX   |           | LPUART1_TX |
- * PA3  | TIM21_CH2  |            | TIM2_CH4   |             | USART2_RX   |           | LPUART1_RX |
- * PA4  | SPI1_NSS   | LPTIM1_IN1 |            |             | USART2_CK   |           |            |
- * PA5  | SPI1_SCK   | LPTIM1_IN2 | TIM2_ETR   |             |             | TIM2_CH1  |            |
- * PA6  | SPI1_MISO  | LPTIM1_ETR |            |             | LPUART1_CTS |           | EVENTOUT   |
- * PA7  | SPI1_MOSI  | LPTIM1_OUT |            |             | USART2_CTS  |           | EVENTOUT   |
- * PA8  | MCO        |            | LPTIM1_IN1 | EVENTOUT    | USART2_CK   | TIM2_CH1  |            |
- * PA9  | MCO        | I2C1_SCL   |            |             | USART2_TX   |           |            |
- * PA10 |            | I2C1_SDA   |            |             | USART2_RX   |           |            |
- * PA11 | SPI1_MISO  |            | EVENTOUT   |             | USART2_CTS  | TIM21_CH2 |            |
- * PA12 | SPI1_MOSI  |            | EVENTOUT   |             | USART2_RTS  |           |            |
- * PA13 | SWDIO      | LPTIM1_ETR |            |             |             |           | LPUART1_RX |
- * PA14 | SWCLK      | LPTIM1_OUT |            | I2C1_SMBA   | USART2_TX   |           | LPUART1_TX |
- * PA15 | SPI1_NSS   |            | TIM2_ETR   | EVENTOUT    | USART2_RX   | TIM2_CH1  |            |
- *__________________________________________________________________________________________________|
- * PB0  | EVENTOUT   | SPI1_MISO  |            |             | USART2_RTS  | TIM2_CH3  |            |
- * PB1  | USART2_CK  | SPI1_MOSI  |            |             | LPUART1_RTS | TIM2_CH4  |            |
- * PB2  |            |            | LPTIM1_OUT |             |             |           |            |
- * PB3  | SPI1_SCK   |            | TIM2_CH2   |             | EVENTOUT    |           |            |
- * PB4  | SPI1_MISO  |            | EVENTOUT   |             |             |           |            |
- * PB5  | SPI1_MOSI  | LPTIM1_IN1 | I2C1_SMBA  |             |             |           |            |
- * PB6  | USART2_TX  | I2C1_SCL   | LPTIM1_ETR |             |             | TIM21_CH1 |            |
- * PB7  | USART2_RX  | I2C1_SDA   | LPTIM1_IN2 |             |             |           |            |
- * PB8  |            |            |            |             | I2C1_SCL    |           |            |
- * PB9  |            |            | EVENTOUT   |             | I2C1_SDA    |           |            |
- * PB10 |            |            | TIM2_CH3   |             |             |           | LPUART1_TX |
- * PB11 | EVENTOUT   |            | TIM2_CH4   |             |             |           | LPUART1_RX |
- * PB12 | SPI1_NSS   |            |            |             |             |           | EVENTOUT   |
- * PB13 | SPI1_SCK   |            | MCO        |             |             | TIM21_CH1 | LPUART1_CTS|
- * PB14 | SPI1_MISO  |            | RTC_OUT    |             |             | TIM21_CH2 | LPUART1_RTS|
- * PB15 | SPI1_MOSI  |            | RTC_REFIN  |             |             |           |            |
- *__________________________________________________________________________________________________|
- * PC0  | LPTIM1_IN1 |            | EVENTOUT   |             |             |           | LPUART1_RX |
- *__________________________________________________________________________________________________|
-*/
-/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
-  * @{
-  */
-
-/*
- * Alternate function AF0
- */
-#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF0_TIM21         ((uint8_t)0x00U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF0_SPI1          ((uint8_t)0x00U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF0_SWDIO         ((uint8_t)0x00U)  /* SWDIO Alternate Function mapping    */
-#define GPIO_AF0_SWCLK         ((uint8_t)0x00U)  /* SWCLK Alternate Function mapping    */
-#define GPIO_AF0_USART2        ((uint8_t)0x00U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF0_LPTIM1        ((uint8_t)0x00U)  /* LPTIM1 Alternate Function mapping   */
-/**
-  *
-  */
-
-/*
- * Alternate function AF1
- */
-#define GPIO_AF1_I2C1          ((uint8_t)0x01U)  /* I2C1 Alternate Function mapping   */
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01U)  /* LPTIM1 Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF2
- */
-#define GPIO_AF2_LPTIM1        ((uint8_t)0x02U)  /* LPTIM1 Alternate Function mapping     */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping       */
-#define GPIO_AF2_MCO           ((uint8_t)0x02U)  /* MCO Alternate Function mapping        */
-#define GPIO_AF2_I2C1          ((uint8_t)0x02U)  /* I2C1 Alternate Function mapping       */
-#define GPIO_AF2_EVENTOUT      ((uint8_t)0x02U)  /* EVENTOUT Alternate Function mapping   */
-#define GPIO_AF2_RTC           ((uint8_t)0x02U)  /* RTC Alternate Function mapping        */
-/**
-  *
-  */
-
-/*
- * Alternate function AF3
- */
-#define GPIO_AF3_I2C1          ((uint8_t)0x03U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF4
- */
-#define GPIO_AF4_USART2        ((uint8_t)0x04U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF4_LPUART1       ((uint8_t)0x04U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF4_EVENTOUT      ((uint8_t)0x04U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF5
- */
-#define GPIO_AF5_TIM2          ((uint8_t)0x05U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF5_TIM21         ((uint8_t)0x05U)  /* TIM21 Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- * Alternate function AF6
- */
-#define GPIO_AF6_LPUART1       ((uint8_t)0x06U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF6_EVENTOUT      ((uint8_t)0x06U)  /* EVENTOUT Alternate Function mapping  */
-/**
-  *
-  */
-
-/*
- * Alternate function AF7
- */
-#define GPIO_AF7_COMP1         ((uint8_t)0x07U)  /* COMP1 Alternate Function mapping     */
-#define GPIO_AF7_COMP2         ((uint8_t)0x07U)  /* COMP2 Alternate Function mapping     */
-/**
-  *
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private  GPIOEx Private
-  * @{
-  */
-/**
-  * @brief  IS_GPIO_AF macro definition
-  */
-
-#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x06)
-
-/**
-  * @}
-  */
-
-#endif /* STM32L010x6 */
-
-/*----------------------------------------------------------------------------*/
-/*------------------------- STM32L010x4 --------------------------------------*/
-/*----------------------------------------------------------------------------*/
-#if defined (STM32L010x4)
-/* The table below gives an overview of the different alternate functions per port.
- * For more details refer yourself to the product data sheet.
- *
- */
-/*      |   AF0     |   AF1      |   AF2      |     AF3     |   AF4       |   AF5     |   AF6      |
- *_______________________________________________________________________ _________________________|
- * PA0  | USART2_RX | LPTIM1_IN1 | TIM2_CH1   |             | USART2_CTS  | TIM2_ETR  | LPUART1_RX |
- * PA1  | EVENTOUT  | LPTIM1_IN2 | TIM2_CH2   | I2C1_SMBA   | USART2_RTS  | TIM21_ETR | LPUART1_TX |
- * PA2  | TIM21_CH1 |            | TIM2_CH3   |             | USART2_TX   |           | LPUART1_TX |
- * PA3  | TIM21_CH2 |            | TIM2_CH4   |             | USART2_RX   |           | LPUART1_RX |
- * PA4  | SPI1_NSS  | LPTIM1_IN1 | LPTIM1_ETR | I2C1_SCL    | USART2_CK   | TIM2_ETR  | LPUART1_TX |
- * PA5  | SPI1_SCK  | LPTIM1_IN2 | TIM2_ETR   |             |             | TIM2_CH1  |            |
- * PA6  | SPI1_MISO | LPTIM1_ETR |            | LPUART1_CTS |             | EVENTOUT  |            |
- * PA7  | SPI1_MOSI | LPTIM1_OUT |            | USART2_CTS  | TIM21_ETR   | EVENTOUT  |            |
- * PA8  | MCO       |            | LPTIM1_IN1 | EVENTOUT    | USART2_CK   | TIM2_CH1  |            |
- * PA9  | MCO       | I2C1_SCL   | LPTIM1_OUT |             | USART2_TX   | TIM21_CH2 |            |
- * PA10 | TIM21_CH1 | I2C1_SDA   | RTC_REFIN  |             | USART2_RX   | TIM2_CH3  |            |
- * PA11 | SPI1_MISO | LPTIM1_OUT | EVENTOUT   |             | USART2_CTS  | TIM21_CH2 |            |
- * PA12 | SPI1_MOSI |            | EVENTOUT   |             | USART2_RTS  |           |            |
- * PA13 | SWDIO     | LPTIM1_ETR |            | I2C1_SDA    |             | SPI1_SCK  | LPUART1_RX |
- * PA14 | SWCLK     | LPTIM1_OUT |            | I2C1_SMBA   | USART2_TX   | SPI1_MISO | LPUART1_TX |
- * PA15 | SPI1_NSS  |            | TIM2_ETR   | EVENTOUT    | USART2_RX   | TIM2_CH1  |            |
- *_________________________________________________________________________________________________|
- * PB0  | EVENTOUT  | SPI1_MISO  | TIM2_CH2   |             | USART2_RTS  | TIM2_CH3  |            |
- * PB1  | USART2_CK | SPI1_MOSI  | LPTIM1_IN1 |             | LPUART1_RTS | TIM2_CH4  |            |
- * PB3  | SPI1_SCK  |            | TIM2_CH2   |             | EVENTOUT    |           |            |
- * PB4  | SPI1_MISO |            | EVENTOUT   |             |             |           |            |
- * PB5  | SPI1_MOSI |            | LPTIM1_IN1 | I2C1_SMBA   |             | TIM21_CH1 |            |
- * PB6  | USART2_TX | I2C1_SCL   | LPTIM1_ETR |             |             | TIM2_CH3  | LPUART1_TX |
- * PB7  | USART2_RX | I2C1_SDA   | LPTIM1_IN2 |             |             | TIM2_CH4  | LPUART1_RX |
- *_________________________________________________________________________________________________|
-*/
-
-/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
-  * @{
-  */
-
-/*
- * Alternate function AF0
- */
-#define GPIO_AF0_USART2        ((uint8_t)0x00U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF0_TIM21         ((uint8_t)0x00U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF0_SPI1          ((uint8_t)0x00U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO Alternate Function mapping      */
-#define GPIO_AF0_SWDIO         ((uint8_t)0x00U)  /* SWDIO Alternate Function mapping    */
-#define GPIO_AF0_SWCLK         ((uint8_t)0x00U)  /* SWCLK Alternate Function mapping    */
-/**
-  *
-  */
-
-/*
- *  Alternate function AF1
- */
-#define GPIO_AF1_SPI1          ((uint8_t)0x01U)  /* SPI1 Alternate Function mapping   */
-#define GPIO_AF1_I2C1          ((uint8_t)0x01U)  /* I2C1 Alternate Function mapping   */
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01U)  /* LPTIM1 Alternate Function mapping */
-/**
-  *
-  */
-
-/*  Alternate function AF2
- *
- */
-#define GPIO_AF2_LPTIM1        ((uint8_t)0x02U)  /* LPTIM1 Alternate Function mapping     */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02U)  /* TIM2 Alternate Function mapping       */
-#define GPIO_AF2_RTC           ((uint8_t)0x02U)  /* RTC Alternate Function mapping        */
-#define GPIO_AF2_EVENTOUT      ((uint8_t)0x02U)  /* EVENTOUT Alternate Function mapping   */
-/**
-  *
-  */
-
-/*
- * Alternate function AF3
- */
-#define GPIO_AF3_I2C1          ((uint8_t)0x03U)  /* I2C1 Alternate Function mapping     */
-#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03U)  /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF3_LPUART1       ((uint8_t)0x03U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF3_USART2        ((uint8_t)0x03U)  /* USART2 Alternate Function mapping   */
-/**
-  *
-  */
-
-/*
- * Alternate function AF4
- */
-#define GPIO_AF4_USART2        ((uint8_t)0x04U)  /* USART2 Alternate Function mapping   */
-#define GPIO_AF4_TIM21         ((uint8_t)0x04U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF4_LPUART1       ((uint8_t)0x04U)  /* LPUART1 Alternate Function mapping  */
-#define GPIO_AF4_EVENTOUT      ((uint8_t)0x04U)  /* EVENTOUT Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF5
- */
-#define GPIO_AF5_TIM2          ((uint8_t)0x05U)  /* TIM2 Alternate Function mapping     */
-#define GPIO_AF5_TIM21         ((uint8_t)0x05U)  /* TIM21 Alternate Function mapping    */
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping     */
-#define GPIO_AF5_EVENTOUT      ((uint8_t)0x05U)  /* EVENTOUT Alternate Function mapping */
-/**
-  *
-  */
-
-/*
- * Alternate function AF6
- */
-#define GPIO_AF6_LPUART1       ((uint8_t)0x06U)  /* LPUART1 Alternate Function mapping  */
-/**
-  *
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private  GPIOEx Private
-  * @{
-  */
-/**
-  *  IS_GPIO_AF macro definition
-  */
-
-#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x06)
-
-/**
-  * @}
-  */
-
-#endif /* STM32L010x4*/
-
-#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
-    defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
-    defined (STM32L010xB)
-
-/** @addtogroup GPIOEx_Exported_Constants
-  * @{
-  */
-/** @defgroup GPIOEx_Pin_Available Pin available
-  * @{
-  */
-#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOC_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOD_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOE_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOH_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_9 | GPIO_PIN_10)
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/** @addtogroup GPIOEx_Private
-  * @{
-  */
-#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
-                                      ((__GPIOx__) == (GPIOB))? 1U :\
-                                      ((__GPIOx__) == (GPIOC))? 2U :\
-                                      ((__GPIOx__) == (GPIOD))? 3U :\
-                                      ((__GPIOx__) == (GPIOE))? 4U :\
-                                      ((__GPIOx__) == (GPIOH))? 5U : 6U)
-
-#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__)  \
-           ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
-/**
-  * @}
-  */
-#elif defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L010x6)
-
-/** @addtogroup GPIOEx_Exported_Constants
-  * @{
-  */
-/** @defgroup GPIOEx_Pin_Available Pin available
-  * @{
-  */
-
-#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOC_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)
-#define GPIOH_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1)
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/** @addtogroup GPIOEx_Private
-  * @{
-  */
-#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
-                                      ((__GPIOx__) == (GPIOB))? 1U :\
-                                      ((__GPIOx__) == (GPIOC))? 2U :\
-                                      ((__GPIOx__) == (GPIOH))? 5U : 6U)
-
-
-#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__)  \
-           ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
-
-/**
-  * @}
-  */
-
-#elif defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L010x4)
-
-/** @addtogroup GPIOEx_Exported_Constants
-  * @{
-  */
-/** @defgroup GPIOEx_Pin_Available Pin available
-  * @{
-  */
-
-#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOB_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
-                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 )
-#define GPIOC_PIN_AVAILABLE  (GPIO_PIN_14 | GPIO_PIN_15)
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/** @addtogroup GPIOEx_Private
-  * @{
-  */
-#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
-                                      ((__GPIOx__) == (GPIOB))? 1U :\
-                                      ((__GPIOx__) == (GPIOC))? 2U : 6U)
-
-
-#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__)  \
-           ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))))
-/**
-  * @}
-  */
-
-#elif defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L053xx) || \
-      defined (STM32L052xx) || defined (STM32L051xx) || defined (STM32L010x8)
-
-/** @addtogroup GPIOEx_Exported_Constants
-  * @{
-  */
-/** @defgroup GPIOEx_Pin_Available Pin available
-  * @{
-  */
-#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOC_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOD_PIN_AVAILABLE  GPIO_PIN_2
-#define GPIOH_PIN_AVAILABLE  GPIO_PIN_0 | GPIO_PIN_1
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/** @addtogroup GPIOEx_Private
-  * @{
-  */
-#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
-                                      ((__GPIOx__) == (GPIOB))? 1U :\
-                                      ((__GPIOx__) == (GPIOC))? 2U :\
-                                      ((__GPIOx__) == (GPIOD))? 3U :\
-                                      ((__GPIOx__) == (GPIOH))? 5U : 6U)
-
-#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__)  \
-                ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
-                 (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
-                 (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
-                 (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
-                 (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
-/**
-  * @}
-  */
-
-#endif /* STM32L083xx || STM32L082xx || STM32L081xx || STM32L073xx || STM32L072xx || STM32L071xx*/
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h
deleted file mode 100644
index 13b8f4dcc0..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h
+++ /dev/null
@@ -1,838 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_i2c.h
-  * @author  MCD Application Team
-  * @brief   Header file of I2C HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_I2C_H
-#define STM32L0xx_HAL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Types I2C Exported Types
-  * @{
-  */
-
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
-  * @brief  I2C Configuration Structure definition
-  * @{
-  */
-typedef struct
-{
-  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
-                                     This parameter calculated by referring to I2C initialization section
-                                     in Reference manual */
-
-  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
-                                     This parameter can be a 7-bit or 10-bit address. */
-
-  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
-                                     This parameter can be a value of @ref I2C_ADDRESSING_MODE */
-
-  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
-                                     This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
-
-  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
-                                     This parameter can be a 7-bit address. */
-
-  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing
-                                     mode is selected.
-                                     This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
-
-  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
-                                     This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
-
-  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
-                                     This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
-
-} I2C_InitTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
-  * @brief  HAL State structure definition
-  * @note  HAL I2C State value coding follow below described bitmap :\n
-  *          b7-b6  Error information\n
-  *             00 : No Error\n
-  *             01 : Abort (Abort user request on going)\n
-  *             10 : Timeout\n
-  *             11 : Error\n
-  *          b5     Peripheral initialization status\n
-  *             0  : Reset (peripheral not initialized)\n
-  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
-  *          b4     (not used)\n
-  *             x  : Should be set to 0\n
-  *          b3\n
-  *             0  : Ready or Busy (No Listen mode ongoing)\n
-  *             1  : Listen (peripheral in Address Listen Mode)\n
-  *          b2     Intrinsic process state\n
-  *             0  : Ready\n
-  *             1  : Busy (peripheral busy with some configuration or internal operations)\n
-  *          b1     Rx state\n
-  *             0  : Ready (no Rx operation ongoing)\n
-  *             1  : Busy (Rx operation ongoing)\n
-  *          b0     Tx state\n
-  *             0  : Ready (no Tx operation ongoing)\n
-  *             1  : Busy (Tx operation ongoing)
-  * @{
-  */
-typedef enum
-{
-  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
-  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
-  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
-  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
-  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
-  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
-  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
-                                                 process is ongoing                         */
-  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
-                                                 process is ongoing                         */
-  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
-  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
-  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
-
-} HAL_I2C_StateTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition
-  * @brief  HAL Mode structure definition
-  * @note  HAL I2C Mode value coding follow below described bitmap :\n
-  *          b7     (not used)\n
-  *             x  : Should be set to 0\n
-  *          b6\n
-  *             0  : None\n
-  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
-  *          b5\n
-  *             0  : None\n
-  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
-  *          b4\n
-  *             0  : None\n
-  *             1  : Master (HAL I2C communication is in Master Mode)\n
-  *          b3-b2-b1-b0  (not used)\n
-  *             xxxx : Should be set to 0000
-  * @{
-  */
-typedef enum
-{
-  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
-  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
-  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
-  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
-
-} HAL_I2C_ModeTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Error_Code_definition I2C Error Code definition
-  * @brief  I2C Error Code definition
-  * @{
-  */
-#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
-#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
-#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
-#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
-#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
-#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
-#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
-#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
-#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
-  * @brief  I2C handle Structure definition
-  * @{
-  */
-typedef struct __I2C_HandleTypeDef
-{
-  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
-
-  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
-
-  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
-
-  uint16_t                   XferSize;       /*!< I2C transfer size                         */
-
-  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
-
-  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
-                                                  be a value of @ref I2C_XFEROPTIONS */
-
-  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
-
-  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-  /*!< I2C transfer IRQ handler function pointer */
-
-  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
-
-  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
-
-  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
-
-  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
-
-  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
-
-  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
-
-  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Master Tx Transfer completed callback */
-  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Master Rx Transfer completed callback */
-  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Slave Tx Transfer completed callback  */
-  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Slave Rx Transfer completed callback  */
-  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Listen Complete callback              */
-  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Memory Tx Transfer completed callback */
-  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Memory Rx Transfer completed callback */
-  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Error callback                        */
-  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Abort callback                        */
-
-  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-  /*!< I2C Slave Address Match callback */
-
-  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Msp Init callback                     */
-  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Msp DeInit callback                   */
-
-#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
-} I2C_HandleTypeDef;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL I2C Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
-  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
-  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
-  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
-  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
-  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
-  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
-  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
-  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
-
-  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
-  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
-
-} HAL_I2C_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL I2C Callback pointer definition
-  */
-typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
-/*!< pointer to an I2C callback function */
-typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
-                                          uint16_t AddrMatchCode);
-/*!< pointer to an I2C Address Match callback function */
-
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
-  * @{
-  */
-#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
-#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
-#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
-#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
-
-/* List of XferOptions in usage of :
- * 1- Restart condition in all use cases (direction change or not)
- */
-#define  I2C_OTHER_FRAME                (0x000000AAU)
-#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
-  * @{
-  */
-#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
-#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
-#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
-/**
-  * @}
-  */
-
-/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
-  * @{
-  */
-#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
-#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
-#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
-#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
-#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
-#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
-#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
-#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
-  * @{
-  */
-#define I2C_GENERALCALL_DISABLE         (0x00000000U)
-#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
-/**
-  * @}
-  */
-
-/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
-  * @{
-  */
-#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
-#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
-/**
-  * @}
-  */
-
-/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
-  * @{
-  */
-#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
-#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
-  * @{
-  */
-#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
-#define I2C_DIRECTION_RECEIVE           (0x00000001U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
-  * @{
-  */
-#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
-#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
-#define  I2C_SOFTEND_MODE               (0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
-  * @{
-  */
-#define  I2C_NO_STARTSTOP               (0x00000000U)
-#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
-#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
-  * @brief I2C Interrupt definition
-  *        Elements values convention: 0xXXXXXXXX
-  *           - XXXXXXXX  : Interrupt control mask
-  * @{
-  */
-#define I2C_IT_ERRI                     I2C_CR1_ERRIE
-#define I2C_IT_TCI                      I2C_CR1_TCIE
-#define I2C_IT_STOPI                    I2C_CR1_STOPIE
-#define I2C_IT_NACKI                    I2C_CR1_NACKIE
-#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
-#define I2C_IT_RXI                      I2C_CR1_RXIE
-#define I2C_IT_TXI                      I2C_CR1_TXIE
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Flag_definition I2C Flag definition
-  * @{
-  */
-#define I2C_FLAG_TXE                    I2C_ISR_TXE
-#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
-#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
-#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
-#define I2C_FLAG_AF                     I2C_ISR_NACKF
-#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
-#define I2C_FLAG_TC                     I2C_ISR_TC
-#define I2C_FLAG_TCR                    I2C_ISR_TCR
-#define I2C_FLAG_BERR                   I2C_ISR_BERR
-#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
-#define I2C_FLAG_OVR                    I2C_ISR_OVR
-#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
-#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
-#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
-#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
-#define I2C_FLAG_DIR                    I2C_ISR_DIR
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
-  * @{
-  */
-
-/** @brief Reset I2C handle state.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                             \
-                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;  \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;       \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;     \
-                                                                  } while(0)
-#else
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-
-/** @brief  Enable the specified I2C interrupt.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
-
-/** @brief  Disable the specified I2C interrupt.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
-/** @brief  Check whether the specified I2C interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & \
-                                                                   (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified I2C flag is set or not.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
-  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
-  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
-  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
-  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
-  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
-  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
-  *            @arg @ref I2C_FLAG_BERR    Bus error
-  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
-  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
-  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
-  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
-  *            @arg @ref I2C_FLAG_BUSY    Bus busy
-  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
-  *
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define I2C_FLAG_MASK  (0x0001FFFFU)
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
-                                                    (__FLAG__)) == (__FLAG__)) ? SET : RESET)
-
-/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
-  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
-  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
-  *            @arg @ref I2C_FLAG_BERR    Bus error
-  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
-  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
-  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
-  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
-  *
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
-                                                    ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
-                                                    ((__HANDLE__)->Instance->ICR = (__FLAG__)))
-
-/** @brief  Enable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE(__HANDLE__)                         (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief  Disable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE(__HANDLE__)                        (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
-/**
-  * @}
-  */
-
-/* Include I2C HAL Extended module */
-#include "stm32l0xx_hal_i2c_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-/* Initialization and de-initialization functions******************************/
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
-                                           pI2C_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-/* IO operation functions  ****************************************************/
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                          uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                         uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                         uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                        uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                   uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
-                                        uint32_t Timeout);
-
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                             uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                            uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                      uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                                 uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                                uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                                uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                               uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
-
-/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                              uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                             uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                                  uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                                 uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                                 uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                                uint32_t XferOptions);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
-  * @{
-  */
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
-  * @{
-  */
-/* Peripheral State, Mode and Error functions  *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
-  * @{
-  */
-
-#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
-                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
-                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
-                                         ((MASK) == I2C_OA2_MASK01) || \
-                                         ((MASK) == I2C_OA2_MASK02) || \
-                                         ((MASK) == I2C_OA2_MASK03) || \
-                                         ((MASK) == I2C_OA2_MASK04) || \
-                                         ((MASK) == I2C_OA2_MASK05) || \
-                                         ((MASK) == I2C_OA2_MASK06) || \
-                                         ((MASK) == I2C_OA2_MASK07))
-
-#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
-                                         ((CALL) == I2C_GENERALCALL_ENABLE))
-
-#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
-                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-
-#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
-                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-
-#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
-                                         ((MODE) == I2C_AUTOEND_MODE) || \
-                                         ((MODE) == I2C_SOFTEND_MODE))
-
-#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
-                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
-                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
-                                         ((REQUEST) == I2C_NO_STARTSTOP))
-
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
-                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
-                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
-                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
-                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
-                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
-                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
-
-#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
-                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
-
-#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= \
-                                                   (uint32_t)~((uint32_t)(I2C_CR2_SADD   | I2C_CR2_HEAD10R | \
-                                                                          I2C_CR2_NBYTES | I2C_CR2_RELOAD  | \
-                                                                          I2C_CR2_RD_WRN)))
-
-#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
-                                                              >> 16U))
-#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
-                                                             >> 16U))
-#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
-#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
-                                                                         (uint16_t)(0xFF00U))) >> 8U)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
-
-#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
-                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
-                                                                 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
-                                                                (~I2C_CR2_RD_WRN)) : \
-                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
-                                                                 (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
-                                                                (~I2C_CR2_RD_WRN)))
-
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
-                                                    ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
-#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
-/**
-  * @}
-  */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32l0xx_hal_i2c.c file */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L0xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h
deleted file mode 100644
index 9874792599..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_i2c_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of I2C HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_I2C_EX_H
-#define STM32L0xx_HAL_I2C_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2CEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
-  * @{
-  */
-#define I2C_ANALOGFILTER_ENABLE         0x00000000U
-#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
-/**
-  * @}
-  */
-
-/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
-  * @{
-  */
-#define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
-#if defined(SYSCFG_CFGR2_I2C_PB6_FMP)
-#define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR2_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
-#define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR2_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
-#else
-#define I2C_FASTMODEPLUS_PB6            (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported   */
-#define I2C_FASTMODEPLUS_PB7            (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported   */
-#endif /* SYSCFG_CFGR2_I2C_PB6_FMP */
-#if defined(SYSCFG_CFGR2_I2C_PB8_FMP)
-#define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR2_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
-#define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR2_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
-#else
-#define I2C_FASTMODEPLUS_PB8            (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported   */
-#define I2C_FASTMODEPLUS_PB9            (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported   */
-#endif /* SYSCFG_CFGR2_I2C_PB8_FMP */
-#if defined(SYSCFG_CFGR2_I2C1_FMP)
-#define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR2_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
-#else
-#define I2C_FASTMODEPLUS_I2C1           (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported  */
-#endif /* SYSCFG_CFGR2_I2C1_FMP */
-#if defined(SYSCFG_CFGR2_I2C2_FMP)
-#define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR2_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
-#else
-#define I2C_FASTMODEPLUS_I2C2           (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported  */
-#endif /* SYSCFG_CFGR2_I2C2_FMP */
-#if defined(SYSCFG_CFGR2_I2C3_FMP)
-#define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR2_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
-#else
-#define I2C_FASTMODEPLUS_I2C3           (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported  */
-#endif /* SYSCFG_CFGR2_I2C3_FMP */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
-  * @{
-  */
-
-/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
-/**
-  * @}
-  */
-
-/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-#if  (defined(SYSCFG_CFGR2_I2C_PB6_FMP) || defined(SYSCFG_CFGR2_I2C_PB7_FMP)) || (defined(SYSCFG_CFGR2_I2C_PB8_FMP) || defined(SYSCFG_CFGR2_I2C_PB9_FMP)) || (defined(SYSCFG_CFGR2_I2C1_FMP)) || defined(SYSCFG_CFGR2_I2C2_FMP) || defined(SYSCFG_CFGR2_I2C3_FMP)
-
-/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
-  * @{
-  */
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
-/**
-  * @}
-  */
-#endif /* Fast Mode Plus Availability */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
-  * @{
-  */
-#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
-                                         ((FILTER) == I2C_ANALOGFILTER_DISABLE))
-
-#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
-
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
-                                         ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))
-/**
-  * @}
-  */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32l0xx_hal_i2c_ex.c file */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_I2C_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2s.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2s.h
deleted file mode 100644
index fd15a3d9ab..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2s.h
+++ /dev/null
@@ -1,556 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_i2s.h
-  * @author  MCD Application Team
-  * @brief   Header file of I2S HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_I2S_H
-#define STM32L0xx_HAL_I2S_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-#if defined(SPI_I2S_SUPPORT)
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2S
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Types I2S Exported Types
-  * @{
-  */
-
-/**
-  * @brief I2S Init structure definition
-  */
-typedef struct
-{
-  uint32_t Mode;                /*!< Specifies the I2S operating mode.
-                                     This parameter can be a value of @ref I2S_Mode */
-
-  uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Standard */
-
-  uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Data_Format */
-
-  uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.
-                                     This parameter can be a value of @ref I2S_MCLK_Output */
-
-  uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Audio_Frequency */
-
-  uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.
-                                     This parameter can be a value of @ref I2S_Clock_Polarity */
-} I2S_InitTypeDef;
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
-  HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
-  HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */
-  HAL_I2S_STATE_BUSY_TX    = 0x03U,  /*!< Data Transmission process is ongoing               */
-  HAL_I2S_STATE_BUSY_RX    = 0x04U,  /*!< Data Reception process is ongoing                  */
-  HAL_I2S_STATE_TIMEOUT    = 0x06U,  /*!< I2S timeout state                                  */
-  HAL_I2S_STATE_ERROR      = 0x07U   /*!< I2S error state                                    */
-} HAL_I2S_StateTypeDef;
-
-/**
-  * @brief I2S handle Structure definition
-  */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
-typedef struct __I2S_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-{
-  SPI_TypeDef                *Instance;    /*!< I2S registers base address */
-
-  I2S_InitTypeDef            Init;         /*!< I2S communication parameters */
-
-  uint16_t                   *pTxBuffPtr;  /*!< Pointer to I2S Tx transfer buffer */
-
-  __IO uint16_t              TxXferSize;   /*!< I2S Tx transfer size */
-
-  __IO uint16_t              TxXferCount;  /*!< I2S Tx transfer Counter */
-
-  uint16_t                   *pRxBuffPtr;  /*!< Pointer to I2S Rx transfer buffer */
-
-  __IO uint16_t              RxXferSize;   /*!< I2S Rx transfer size */
-
-  __IO uint16_t              RxXferCount;  /*!< I2S Rx transfer counter
-                                              (This field is initialized at the
-                                               same value as transfer size at the
-                                               beginning of the transfer and
-                                               decremented when a sample is received
-                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */
-  DMA_HandleTypeDef          *hdmatx;      /*!< I2S Tx DMA handle parameters */
-
-  DMA_HandleTypeDef          *hdmarx;      /*!< I2S Rx DMA handle parameters */
-
-  __IO HAL_LockTypeDef       Lock;         /*!< I2S locking object */
-
-  __IO HAL_I2S_StateTypeDef  State;        /*!< I2S communication state */
-
-  __IO uint32_t              ErrorCode;    /*!< I2S Error code
-                                                This parameter can be a value of @ref I2S_Error */
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Tx Completed callback          */
-  void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Rx Completed callback          */
-  void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Tx Half Completed callback     */
-  void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Rx Half Completed callback     */
-  void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s);              /*!< I2S Error callback                 */
-  void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s);            /*!< I2S Msp Init callback              */
-  void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s);          /*!< I2S Msp DeInit callback            */
-
-#endif  /* USE_HAL_I2S_REGISTER_CALLBACKS */
-} I2S_HandleTypeDef;
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  HAL I2S Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_I2S_TX_COMPLETE_CB_ID             = 0x00U,    /*!< I2S Tx Completed callback ID         */
-  HAL_I2S_RX_COMPLETE_CB_ID             = 0x01U,    /*!< I2S Rx Completed callback ID         */
-  HAL_I2S_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< I2S Tx Half Completed callback ID    */
-  HAL_I2S_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< I2S Rx Half Completed callback ID    */
-  HAL_I2S_ERROR_CB_ID                   = 0x06U,    /*!< I2S Error callback ID                */
-  HAL_I2S_MSPINIT_CB_ID                 = 0x07U,    /*!< I2S Msp Init callback ID             */
-  HAL_I2S_MSPDEINIT_CB_ID               = 0x08U     /*!< I2S Msp DeInit callback ID           */
-
-} HAL_I2S_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL I2S Callback pointer definition
-  */
-typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
-
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
-  * @{
-  */
-/** @defgroup I2S_Error I2S Error
-  * @{
-  */
-#define HAL_I2S_ERROR_NONE               (0x00000000U)  /*!< No error                    */
-#define HAL_I2S_ERROR_TIMEOUT            (0x00000001U)  /*!< Timeout error               */
-#define HAL_I2S_ERROR_OVR                (0x00000002U)  /*!< OVR error                   */
-#define HAL_I2S_ERROR_UDR                (0x00000004U)  /*!< UDR error                   */
-#define HAL_I2S_ERROR_DMA                (0x00000008U)  /*!< DMA transfer error          */
-#define HAL_I2S_ERROR_PRESCALER          (0x00000010U)  /*!< Prescaler Calculation error */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-#define HAL_I2S_ERROR_INVALID_CALLBACK   (0x00000020U)  /*!< Invalid Callback error      */
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-#define HAL_I2S_ERROR_BUSY_LINE_RX       (0x00000040U)  /*!< Busy Rx Line error          */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Mode I2S Mode
-  * @{
-  */
-#define I2S_MODE_SLAVE_TX                (0x00000000U)
-#define I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)
-#define I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)
-#define I2S_MODE_MASTER_RX               ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Standard I2S Standard
-  * @{
-  */
-#define I2S_STANDARD_PHILIPS             (0x00000000U)
-#define I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)
-#define I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)
-#define I2S_STANDARD_PCM_SHORT           ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
-#define I2S_STANDARD_PCM_LONG            ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Data_Format I2S Data Format
-  * @{
-  */
-#define I2S_DATAFORMAT_16B               (0x00000000U)
-#define I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)
-#define I2S_DATAFORMAT_24B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
-#define I2S_DATAFORMAT_32B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_MCLK_Output I2S MCLK Output
-  * @{
-  */
-#define I2S_MCLKOUTPUT_ENABLE            (SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE           (0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
-  * @{
-  */
-#define I2S_AUDIOFREQ_192K               (192000U)
-#define I2S_AUDIOFREQ_96K                (96000U)
-#define I2S_AUDIOFREQ_48K                (48000U)
-#define I2S_AUDIOFREQ_44K                (44100U)
-#define I2S_AUDIOFREQ_32K                (32000U)
-#define I2S_AUDIOFREQ_22K                (22050U)
-#define I2S_AUDIOFREQ_16K                (16000U)
-#define I2S_AUDIOFREQ_11K                (11025U)
-#define I2S_AUDIOFREQ_8K                 (8000U)
-#define I2S_AUDIOFREQ_DEFAULT            (2U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
-  * @{
-  */
-#define I2S_CPOL_LOW                     (0x00000000U)
-#define I2S_CPOL_HIGH                    (SPI_I2SCFGR_CKPOL)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
-  * @{
-  */
-#define I2S_IT_TXE                       SPI_CR2_TXEIE
-#define I2S_IT_RXNE                      SPI_CR2_RXNEIE
-#define I2S_IT_ERR                       SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Flags_Definition I2S Flags Definition
-  * @{
-  */
-#define I2S_FLAG_TXE                     SPI_SR_TXE
-#define I2S_FLAG_RXNE                    SPI_SR_RXNE
-
-#define I2S_FLAG_UDR                     SPI_SR_UDR
-#define I2S_FLAG_OVR                     SPI_SR_OVR
-#define I2S_FLAG_FRE                     SPI_SR_FRE
-
-#define I2S_FLAG_CHSIDE                  SPI_SR_CHSIDE
-#define I2S_FLAG_BSY                     SPI_SR_BSY
-
-#define I2S_FLAG_MASK                   (SPI_SR_RXNE\
-                                         | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup I2S_Exported_macros I2S Exported Macros
-  * @{
-  */
-
-/** @brief  Reset I2S handle state
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
-                                                                    (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                  } while(0)
-#else
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-
-/** @brief  Enable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief  Disable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief  Enable the specified I2S interrupts.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-
-/** @brief  Disable the specified I2S interrupts.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-
-/** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
-                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks whether the specified I2S flag is set or not.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
-  *            @arg I2S_FLAG_UDR: Underrun flag
-  *            @arg I2S_FLAG_OVR: Overrun flag
-  *            @arg I2S_FLAG_FRE: Frame error flag
-  *            @arg I2S_FLAG_CHSIDE: Channel Side flag
-  *            @arg I2S_FLAG_BSY: Busy flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2S OVR pending flag.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
-                                                __IO uint32_t tmpreg_ovr = 0x00U; \
-                                                tmpreg_ovr = (__HANDLE__)->Instance->DR; \
-                                                tmpreg_ovr = (__HANDLE__)->Instance->SR; \
-                                                UNUSED(tmpreg_ovr); \
-                                              }while(0U)
-/** @brief Clears the I2S UDR pending flag.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
-                                                __IO uint32_t tmpreg_udr = 0x00U;\
-                                                tmpreg_udr = ((__HANDLE__)->Instance->SR);\
-                                                UNUSED(tmpreg_udr); \
-                                              }while(0U)
-/** @brief Flush the I2S DR Register.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__)  do{\
-                                                __IO uint32_t tmpreg_dr = 0x00U;\
-                                                tmpreg_dr = ((__HANDLE__)->Instance->DR);\
-                                                UNUSED(tmpreg_dr); \
-                                              }while(0U)
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
-                                           pI2S_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  ***************************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
-void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control and State functions  ************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_Private_Macros I2S Private Macros
-  * @{
-  */
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __SR__  copy of I2S SR register.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
-  *            @arg I2S_FLAG_UDR: Underrun error flag
-  *            @arg I2S_FLAG_OVR: Overrun flag
-  *            @arg I2S_FLAG_CHSIDE: Channel side flag
-  *            @arg I2S_FLAG_BSY: Busy flag
-  * @retval SET or RESET.
-  */
-#define I2S_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__)\
-                                                    & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI Interrupt is set or not.
-  * @param  __CR2__  copy of I2S CR2 register.
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval SET or RESET.
-  */
-#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)      ((((__CR2__)\
-                                                            & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks if I2S Mode parameter is in allowed range.
-  * @param  __MODE__ specifies the I2S Mode.
-  *         This parameter can be a value of @ref I2S_Mode
-  * @retval None
-  */
-#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX)  || \
-                               ((__MODE__) == I2S_MODE_SLAVE_RX)  || \
-                               ((__MODE__) == I2S_MODE_MASTER_TX) || \
-                               ((__MODE__) == I2S_MODE_MASTER_RX))
-
-#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS)   || \
-                                       ((__STANDARD__) == I2S_STANDARD_MSB)       || \
-                                       ((__STANDARD__) == I2S_STANDARD_LSB)       || \
-                                       ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
-                                       ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
-
-#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B)          || \
-                                        ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
-                                        ((__FORMAT__) == I2S_DATAFORMAT_24B)          || \
-                                        ((__FORMAT__) == I2S_DATAFORMAT_32B))
-
-#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
-                                        ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
-
-#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K)    && \
-                                      ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
-                                     ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
-
-/** @brief  Checks if I2S Serial clock steady state parameter is in allowed range.
-  * @param  __CPOL__ specifies the I2S serial clock steady state.
-  *         This parameter can be a value of @ref I2S_Clock_Polarity
-  * @retval None
-  */
-#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
-                               ((__CPOL__) == I2S_CPOL_HIGH))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* SPI_I2S_SUPPORT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_I2S_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda.h
deleted file mode 100644
index 352bf85ee3..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda.h
+++ /dev/null
@@ -1,857 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_irda.h
-  * @author  MCD Application Team
-  * @brief   Header file of IRDA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_IRDA_H
-#define STM32L0xx_HAL_IRDA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup IRDA
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Types IRDA Exported Types
-  * @{
-  */
-
-/**
-  * @brief IRDA Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
-                                           The baud rate register is computed using the following formula:
-                                              Baud Rate Register = ((usart_ker_clk) / ((hirda->Init.BaudRate)))
-                                           where usart_ker_clk is the IRDA input clock */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref IRDAEx_Word_Length */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref IRDA_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
-
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref IRDA_Transfer_Mode */
-
-  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
-                                           to achieve low-power frequency.
-                                           @note Prescaler value 0 is forbidden */
-
-  uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
-                                           This parameter can be a value of @ref IRDA_Low_Power */
-
-} IRDA_InitTypeDef;
-
-/**
-  * @brief HAL IRDA State definition
-  * @note  HAL IRDA State value is a combination of 2 different substates:
-  *        gState and RxState (see @ref IRDA_State_Definition).
-  *        - gState contains IRDA state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized. HAL IRDA Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (Peripheral busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */
-typedef uint32_t HAL_IRDA_StateTypeDef;
-
-/**
-  * @brief IRDA clock sources definition
-  */
-typedef enum
-{
-  IRDA_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source         */
-  IRDA_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source         */
-  IRDA_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source           */
-  IRDA_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source        */
-  IRDA_CLOCKSOURCE_LSE        = 0x10U,    /*!< LSE clock source           */
-  IRDA_CLOCKSOURCE_UNDEFINED  = 0x20U     /*!< Undefined clock source     */
-} IRDA_ClockSourceTypeDef;
-
-/**
-  * @brief  IRDA handle Structure definition
-  */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-typedef struct __IRDA_HandleTypeDef
-#else
-typedef struct
-#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-{
-  USART_TypeDef            *Instance;        /*!< USART registers base address       */
-
-  IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
-
-  uint8_t                  *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
-
-  uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
-
-  __IO uint16_t            TxXferCount;      /*!< IRDA Tx Transfer Counter           */
-
-  uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
-
-  uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
-
-  __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */
-
-  uint16_t                 Mask;             /*!< USART RX RDR register mask         */
-
-  DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef          Lock;             /*!< Locking object                     */
-
-  __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management
-                                                  and also related to Tx operations.
-                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
-  __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
-                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
-  __IO uint32_t            ErrorCode;        /*!< IRDA Error code                    */
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Tx Half Complete Callback        */
-
-  void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Tx Complete Callback             */
-
-  void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Rx Half Complete Callback        */
-
-  void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Rx Complete Callback             */
-
-  void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda);             /*!< IRDA Error Callback                   */
-
-  void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Abort Complete Callback          */
-
-  void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
-
-  void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda);  /*!< IRDA Abort Receive Complete Callback  */
-
-
-  void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda);           /*!< IRDA Msp Init callback                */
-
-  void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Msp DeInit callback              */
-#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-} IRDA_HandleTypeDef;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL IRDA Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_IRDA_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< IRDA Tx Half Complete Callback ID        */
-  HAL_IRDA_TX_COMPLETE_CB_ID             = 0x01U,    /*!< IRDA Tx Complete Callback ID             */
-  HAL_IRDA_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< IRDA Rx Half Complete Callback ID        */
-  HAL_IRDA_RX_COMPLETE_CB_ID             = 0x03U,    /*!< IRDA Rx Complete Callback ID             */
-  HAL_IRDA_ERROR_CB_ID                   = 0x04U,    /*!< IRDA Error Callback ID                   */
-  HAL_IRDA_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< IRDA Abort Complete Callback ID          */
-  HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< IRDA Abort Transmit Complete Callback ID */
-  HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< IRDA Abort Receive Complete Callback ID  */
-
-  HAL_IRDA_MSPINIT_CB_ID                 = 0x08U,    /*!< IRDA MspInit callback ID                 */
-  HAL_IRDA_MSPDEINIT_CB_ID               = 0x09U     /*!< IRDA MspDeInit callback ID               */
-
-} HAL_IRDA_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL IRDA Callback pointer definition
-  */
-typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer to an IRDA callback function */
-
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
-  * @{
-  */
-
-/** @defgroup IRDA_State_Definition IRDA State Code Definition
-  * @{
-  */
-#define HAL_IRDA_STATE_RESET                0x00000000U   /*!< Peripheral is not initialized
-                                                               Value is allowed for gState and RxState */
-#define HAL_IRDA_STATE_READY                0x00000020U   /*!< Peripheral Initialized and ready for use
-                                                               Value is allowed for gState and RxState */
-#define HAL_IRDA_STATE_BUSY                 0x00000024U   /*!< An internal process is ongoing
-                                                               Value is allowed for gState only */
-#define HAL_IRDA_STATE_BUSY_TX              0x00000021U   /*!< Data Transmission process is ongoing
-                                                               Value is allowed for gState only */
-#define HAL_IRDA_STATE_BUSY_RX              0x00000022U   /*!< Data Reception process is ongoing
-                                                               Value is allowed for RxState only */
-#define HAL_IRDA_STATE_BUSY_TX_RX           0x00000023U   /*!< Data Transmission and Reception process is ongoing
-                                                               Not to be used for neither gState nor RxState.
-                                                               Value is result of combination (Or) between
-                                                               gState and RxState values */
-#define HAL_IRDA_STATE_TIMEOUT              0x000000A0U   /*!< Timeout state
-                                                               Value is allowed for gState only */
-#define HAL_IRDA_STATE_ERROR                0x000000E0U   /*!< Error
-                                                               Value is allowed for gState only */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
-  * @{
-  */
-#define HAL_IRDA_ERROR_NONE                 (0x00000000U)          /*!< No error                */
-#define HAL_IRDA_ERROR_PE                   (0x00000001U)          /*!< Parity error            */
-#define HAL_IRDA_ERROR_NE                   (0x00000002U)          /*!< Noise error             */
-#define HAL_IRDA_ERROR_FE                   (0x00000004U)          /*!< frame error             */
-#define HAL_IRDA_ERROR_ORE                  (0x00000008U)          /*!< Overrun error           */
-#define HAL_IRDA_ERROR_DMA                  (0x00000010U)          /*!< DMA transfer error      */
-#define HAL_IRDA_ERROR_BUSY                 (0x00000020U)          /*!< Busy Error              */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-#define HAL_IRDA_ERROR_INVALID_CALLBACK     (0x00000040U)          /*!< Invalid Callback error  */
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Parity IRDA Parity
-  * @{
-  */
-#define IRDA_PARITY_NONE                    0x00000000U                      /*!< No parity   */
-#define IRDA_PARITY_EVEN                    USART_CR1_PCE                    /*!< Even parity */
-#define IRDA_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
-  * @{
-  */
-#define IRDA_MODE_RX                        USART_CR1_RE                   /*!< RX mode        */
-#define IRDA_MODE_TX                        USART_CR1_TE                   /*!< TX mode        */
-#define IRDA_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)   /*!< RX and TX mode */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Low_Power IRDA Low Power
-  * @{
-  */
-#define IRDA_POWERMODE_NORMAL               0x00000000U       /*!< IRDA normal power mode */
-#define IRDA_POWERMODE_LOWPOWER             USART_CR3_IRLP    /*!< IRDA low power mode    */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_State IRDA State
-  * @{
-  */
-#define IRDA_STATE_DISABLE                  0x00000000U     /*!< IRDA disabled  */
-#define IRDA_STATE_ENABLE                   USART_CR1_UE    /*!< IRDA enabled   */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Mode IRDA Mode
-  * @{
-  */
-#define IRDA_MODE_DISABLE                   0x00000000U      /*!< Associated UART disabled in IRDA mode */
-#define IRDA_MODE_ENABLE                    USART_CR3_IREN   /*!< Associated UART enabled in IRDA mode  */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
-  * @{
-  */
-#define IRDA_ONE_BIT_SAMPLE_DISABLE         0x00000000U       /*!< One-bit sampling disabled */
-#define IRDA_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT  /*!< One-bit sampling enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
-  * @{
-  */
-#define IRDA_DMA_TX_DISABLE                 0x00000000U       /*!< IRDA DMA TX disabled */
-#define IRDA_DMA_TX_ENABLE                  USART_CR3_DMAT    /*!< IRDA DMA TX enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
-  * @{
-  */
-#define IRDA_DMA_RX_DISABLE                 0x00000000U       /*!< IRDA DMA RX disabled */
-#define IRDA_DMA_RX_ENABLE                  USART_CR3_DMAR    /*!< IRDA DMA RX enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
-  * @{
-  */
-#define IRDA_AUTOBAUD_REQUEST            USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
-#define IRDA_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
-#define IRDA_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Flags IRDA Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the ISR register
-  * @{
-  */
-#define IRDA_FLAG_REACK                     USART_ISR_REACK         /*!< IRDA receive enable acknowledge flag      */
-#define IRDA_FLAG_TEACK                     USART_ISR_TEACK         /*!< IRDA transmit enable acknowledge flag     */
-#define IRDA_FLAG_BUSY                      USART_ISR_BUSY          /*!< IRDA busy flag                            */
-#define IRDA_FLAG_ABRF                      USART_ISR_ABRF          /*!< IRDA auto Baud rate flag                  */
-#define IRDA_FLAG_ABRE                      USART_ISR_ABRE          /*!< IRDA auto Baud rate error                 */
-#define IRDA_FLAG_TXE                       USART_ISR_TXE           /*!< IRDA transmit data register empty         */
-#define IRDA_FLAG_TC                        USART_ISR_TC            /*!< IRDA transmission complete                */
-#define IRDA_FLAG_RXNE                      USART_ISR_RXNE          /*!< IRDA read data register not empty         */
-#define IRDA_FLAG_ORE                       USART_ISR_ORE           /*!< IRDA overrun error                        */
-#define IRDA_FLAG_NE                        USART_ISR_NE            /*!< IRDA noise error                          */
-#define IRDA_FLAG_FE                        USART_ISR_FE            /*!< IRDA frame error                          */
-#define IRDA_FLAG_PE                        USART_ISR_PE            /*!< IRDA parity error                         */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
-  *        Elements values convention: 0000ZZZZ0XXYYYYYb
-  *           - YYYYY  : Interrupt source position in the XX register (5bits)
-  *           - XX  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  *           - ZZZZ  : Flag position in the ISR register(4bits)
-  * @{
-  */
-#define IRDA_IT_PE                          0x0028U     /*!< IRDA Parity error interruption                 */
-#define IRDA_IT_TXE                         0x0727U     /*!< IRDA Transmit data register empty interruption */
-#define IRDA_IT_TC                          0x0626U     /*!< IRDA Transmission complete interruption        */
-#define IRDA_IT_RXNE                        0x0525U     /*!< IRDA Read data register not empty interruption */
-#define IRDA_IT_IDLE                        0x0424U     /*!< IRDA Idle interruption                         */
-
-/*       Elements values convention: 000000000XXYYYYYb
-             - YYYYY  : Interrupt source position in the XX register (5bits)
-             - XX  : Interrupt source register (2bits)
-                   - 01: CR1 register
-                   - 10: CR2 register
-                   - 11: CR3 register */
-#define IRDA_IT_ERR                         0x0060U       /*!< IRDA Error interruption        */
-
-/*       Elements values convention: 0000ZZZZ00000000b
-             - ZZZZ  : Flag position in the ISR register(4bits) */
-#define IRDA_IT_ORE                         0x0300U      /*!< IRDA Overrun error interruption */
-#define IRDA_IT_NE                          0x0200U      /*!< IRDA Noise error interruption   */
-#define IRDA_IT_FE                          0x0100U      /*!< IRDA Frame error interruption   */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
-  * @{
-  */
-#define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
-#define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
-#define IRDA_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise Error detected Clear Flag  */
-#define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
-#define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
-#define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
-  * @{
-  */
-#define IRDA_IT_MASK  0x001FU  /*!< IRDA Interruptions flags mask  */
-#define IRDA_CR_MASK  0x00E0U  /*!< IRDA control register mask     */
-#define IRDA_CR_POS   5U       /*!< IRDA control register position */
-#define IRDA_ISR_MASK 0x1F00U  /*!< IRDA ISR register mask         */
-#define IRDA_ISR_POS  8U       /*!< IRDA ISR register position     */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
-  * @{
-  */
-
-/** @brief  Reset IRDA handle state.
-  * @param  __HANDLE__ IRDA handle.
-  * @retval None
-  */
-#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
-                                                       (__HANDLE__)->MspInitCallback = NULL;             \
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
-                                                     } while(0U)
-#else
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
-                                                     } while(0U)
-#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS  */
-
-/** @brief  Flush the IRDA DR register.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
-  do{                                                                    \
-    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
-    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
-  } while(0U)
-
-/** @brief  Clear the specified IRDA pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref IRDA_CLEAR_PEF
-  *            @arg @ref IRDA_CLEAR_FEF
-  *            @arg @ref IRDA_CLEAR_NEF
-  *            @arg @ref IRDA_CLEAR_OREF
-  *            @arg @ref IRDA_CLEAR_TCF
-  *            @arg @ref IRDA_CLEAR_IDLEF
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief  Clear the IRDA PE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
-
-
-/** @brief  Clear the IRDA FE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
-
-/** @brief  Clear the IRDA NE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
-
-/** @brief  Clear the IRDA ORE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
-
-/** @brief  Clear the IRDA IDLE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
-
-/** @brief  Check whether the specified IRDA flag is set or not.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
-  *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
-  *            @arg @ref IRDA_FLAG_BUSY  Busy flag
-  *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
-  *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
-  *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
-  *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
-  *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
-  *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
-  *            @arg @ref IRDA_FLAG_NE    Noise Error flag
-  *            @arg @ref IRDA_FLAG_FE    Framing Error flag
-  *            @arg @ref IRDA_FLAG_PE    Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-
-/** @brief  Enable the specified IRDA interrupt.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
-  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
-  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
-  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
-  *            @arg @ref IRDA_IT_PE   Parity Error interrupt
-  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
-                                                           ((__HANDLE__)->Instance->CR1 |= (1U << \
-                                                               ((__INTERRUPT__) & IRDA_IT_MASK))):\
-                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
-                                                           ((__HANDLE__)->Instance->CR2 |= (1U << \
-                                                               ((__INTERRUPT__) & IRDA_IT_MASK))):\
-                                                           ((__HANDLE__)->Instance->CR3 |= (1U << \
-                                                               ((__INTERRUPT__) & IRDA_IT_MASK))))
-
-/** @brief  Disable the specified IRDA interrupt.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
-  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
-  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
-  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
-  *            @arg @ref IRDA_IT_PE   Parity Error interrupt
-  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
-                                                           ((__HANDLE__)->Instance->CR1 &= ~ (1U << \
-                                                               ((__INTERRUPT__) & IRDA_IT_MASK))): \
-                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
-                                                           ((__HANDLE__)->Instance->CR2 &= ~ (1U << \
-                                                               ((__INTERRUPT__) & IRDA_IT_MASK))): \
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << \
-                                                               ((__INTERRUPT__) & IRDA_IT_MASK))))
-
-/** @brief  Check whether the specified IRDA interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
-  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
-  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
-  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
-  *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
-  *            @arg @ref IRDA_IT_NE Noise Error interrupt
-  *            @arg @ref IRDA_IT_FE Framing Error interrupt
-  *            @arg @ref IRDA_IT_PE Parity Error interrupt
-  * @retval The new state of __IT__ (SET or RESET).
-  */
-#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
-  ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
-
-/** @brief  Check whether the specified IRDA interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
-  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
-  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
-  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
-  *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
-  *            @arg @ref IRDA_IT_PE Parity Error interrupt
-  * @retval The new state of __IT__ (SET or RESET).
-  */
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                                                          \
-  ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__)  \
-      & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3))           \
-     & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
-
-/** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
-  *                       to clear the corresponding interrupt
-  *          This parameter can be one of the following values:
-  *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
-  *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
-  *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
-  *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
-  *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-
-/** @brief  Set a specific IRDA request flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __REQ__ specifies the request flag to set
-  *          This parameter can be one of the following values:
-  *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
-  *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
-  *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
-  * @retval None
-  */
-#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-
-/** @brief  Enable the IRDA one bit sample method.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief  Disable the IRDA one bit sample method.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
-                                                       &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable UART/USART associated to IRDA Handle.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
-
-/** @brief  Disable UART/USART associated to IRDA Handle.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup IRDA_Private_Macros
-  * @{
-  */
-
-/** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
-  * @param  __BAUDRATE__ specifies the IRDA Baudrate set by the user.
-  * @retval True or False
-  */
-#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
-
-/** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
-  * @param  __PRESCALER__ specifies the IRDA prescaler value set by the user.
-  * @retval True or False
-  */
-#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
-
-/** @brief Ensure that IRDA frame parity is valid.
-  * @param __PARITY__ IRDA frame parity.
-  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
-  */
-#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
-                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
-                                    ((__PARITY__) == IRDA_PARITY_ODD))
-
-/** @brief Ensure that IRDA communication mode is valid.
-  * @param __MODE__ IRDA communication mode.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
-                                        & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
-
-/** @brief Ensure that IRDA power mode is valid.
-  * @param __MODE__ IRDA power mode.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
-                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))
-
-/** @brief Ensure that IRDA state is valid.
-  * @param __STATE__ IRDA state mode.
-  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
-  */
-#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
-                                  ((__STATE__) == IRDA_STATE_ENABLE))
-
-/** @brief Ensure that IRDA associated UART/USART mode is valid.
-  * @param __MODE__ IRDA associated UART/USART mode.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
-                                 ((__MODE__) == IRDA_MODE_ENABLE))
-
-/** @brief Ensure that IRDA sampling rate is valid.
-  * @param __ONEBIT__ IRDA sampling rate.
-  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
-  */
-#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
-                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
-
-/** @brief Ensure that IRDA DMA TX mode is valid.
-  * @param __DMATX__ IRDA DMA TX mode.
-  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
-  */
-#define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
-                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))
-
-/** @brief Ensure that IRDA DMA RX mode is valid.
-  * @param __DMARX__ IRDA DMA RX mode.
-  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
-  */
-#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
-                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))
-
-/** @brief Ensure that IRDA request is valid.
-  * @param __PARAM__ IRDA request.
-  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
-  */
-#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
-                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
-                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
-/**
-  * @}
-  */
-
-/* Include IRDA HAL Extended module */
-#include "stm32l0xx_hal_irda_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
-  * @{
-  */
-
-/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
-                                            pIRDA_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
-
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
-
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  ************************************************/
-
-/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
-  * @{
-  */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_IRDA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda_ex.h
deleted file mode 100644
index 5769d27940..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda_ex.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_irda_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of IRDA HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_IRDA_EX_H
-#define STM32L0xx_HAL_IRDA_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup IRDAEx IRDAEx
-  * @brief IRDA Extended HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
-  * @{
-  */
-#define IRDA_WORDLENGTH_7B                  USART_CR1_M1   /*!< 7-bit long frame */
-#define IRDA_WORDLENGTH_8B                  0x00000000U    /*!< 8-bit long frame */
-#define IRDA_WORDLENGTH_9B                  USART_CR1_M0   /*!< 9-bit long frame */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
-  * @{
-  */
-
-/** @brief  Report the IRDA clock source.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __CLOCKSOURCE__ output variable.
-  * @retval IRDA clocking source, written in __CLOCKSOURCE__.
-  */
-#if defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L010xB) || defined (STM32L010x8)
-#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
-  do {                                                        \
-    if((__HANDLE__)->Instance == USART2)                      \
-    {                                                         \
-      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
-      {                                                       \
-        case RCC_USART2CLKSOURCE_PCLK1:                       \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else if((__HANDLE__)->Instance == LPUART1)                \
-    {                                                         \
-      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
-      {                                                       \
-        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_HSI:                        \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_LSE:                        \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else                                                      \
-    {                                                         \
-      (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
-    }                                                         \
-  } while(0U)
-
-#else /* (STM32L031xx) || defined (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) || defined (STM32L010xB) || defined (STM32L010x8)*/
-
-#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
-  do {                                                        \
-    if((__HANDLE__)->Instance == USART1)                      \
-    {                                                         \
-      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
-      {                                                       \
-        case RCC_USART1CLKSOURCE_PCLK2:                       \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else if((__HANDLE__)->Instance == USART2)                 \
-    {                                                         \
-      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
-      {                                                       \
-        case RCC_USART2CLKSOURCE_PCLK1:                       \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else if((__HANDLE__)->Instance == LPUART1)                \
-    {                                                         \
-      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
-      {                                                       \
-        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_HSI:                        \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_LSE:                        \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else                                                      \
-    {                                                         \
-      (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
-    }                                                         \
-  } while(0U)
-#endif /* (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx) || (STM32L010xB) || (STM32L010x8)*/
-
-
-/** @brief  Compute the mask to apply to retrieve the received data
-  *         according to the word length and to the parity bits activation.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
-  */
-#define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
-  do {                                                                \
-    if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)          \
-    {                                                                 \
-      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x01FFU ;                                \
-      }                                                               \
-      else                                                            \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x00FFU ;                                \
-      }                                                               \
-    }                                                                 \
-    else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)     \
-    {                                                                 \
-      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x00FFU ;                                \
-      }                                                               \
-      else                                                            \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x007FU ;                                \
-      }                                                               \
-    }                                                                 \
-    else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)     \
-    {                                                                 \
-      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x007FU ;                                \
-      }                                                               \
-      else                                                            \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x003FU ;                                \
-      }                                                               \
-    }                                                                 \
-    else                                                              \
-    {                                                                 \
-      (__HANDLE__)->Mask = 0x0000U;                                   \
-    }                                                                 \
-  } while(0U)
-
-/** @brief Ensure that IRDA frame length is valid.
-  * @param __LENGTH__ IRDA frame length.
-  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
-  */
-#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
-                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
-                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_IRDA_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h
deleted file mode 100644
index 87730cb5d5..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_iwdg.h
-  * @author  MCD Application Team
-  * @brief   Header file of IWDG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_IWDG_H
-#define STM32L0xx_HAL_IWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup IWDG IWDG
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Types IWDG Exported Types
-  * @{
-  */
-
-/**
-  * @brief  IWDG Init structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
-                            This parameter can be a value of @ref IWDG_Prescaler */
-
-  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
-  uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
-} IWDG_InitTypeDef;
-
-/**
-  * @brief  IWDG Handle Structure definition
-  */
-typedef struct
-{
-  IWDG_TypeDef                 *Instance;  /*!< Register base address    */
-
-  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
-} IWDG_HandleTypeDef;
-
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup IWDG_Prescaler IWDG Prescaler
-  * @{
-  */
-#define IWDG_PRESCALER_4                0x00000000u                                     /*!< IWDG prescaler set to 4   */
-#define IWDG_PRESCALER_8                IWDG_PR_PR_0                                    /*!< IWDG prescaler set to 8   */
-#define IWDG_PRESCALER_16               IWDG_PR_PR_1                                    /*!< IWDG prescaler set to 16  */
-#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 32  */
-#define IWDG_PRESCALER_64               IWDG_PR_PR_2                                    /*!< IWDG prescaler set to 64  */
-#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)                   /*!< IWDG prescaler set to 256 */
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Window_option IWDG Window option
-  * @{
-  */
-#define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Enable the IWDG peripheral.
-  * @param  __HANDLE__  IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
-
-/**
-  * @brief  Reload IWDG counter with value defined in the reload register
-  *         (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
-  * @param  __HANDLE__  IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
-  * @{
-  */
-
-/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
-  * @{
-  */
-/* Initialization/Start functions  ********************************************/
-HAL_StatusTypeDef     HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef     HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_Private_Constants IWDG Private Constants
-  * @{
-  */
-
-/**
-  * @brief  IWDG Key Register BitMask
-  */
-#define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
-#define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup IWDG_Private_Macros IWDG Private Macros
-  * @{
-  */
-
-/**
-  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
-  * @param  __HANDLE__  IWDG handle
-  * @retval None
-  */
-#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
-
-/**
-  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
-  * @param  __HANDLE__  IWDG handle
-  * @retval None
-  */
-#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
-
-/**
-  * @brief  Check IWDG prescaler value.
-  * @param  __PRESCALER__  IWDG prescaler value
-  * @retval None
-  */
-#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_256))
-
-/**
-  * @brief  Check IWDG reload value.
-  * @param  __RELOAD__  IWDG reload value
-  * @retval None
-  */
-#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
-
-/**
-  * @brief  Check IWDG window value.
-  * @param  __WINDOW__  IWDG window value
-  * @retval None
-  */
-#define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lcd.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lcd.h
deleted file mode 100644
index ea6acfa5ec..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lcd.h
+++ /dev/null
@@ -1,788 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_lcd.h
-  * @author  MCD Application Team
-  * @brief   Header file of LCD Controller HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_LCD_H
-#define __STM32L0xx_HAL_LCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
-   
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup LCD LCD
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup LCD_Exported_Types LCD Exported Types
-  * @{
-  */
-
-/** 
-  * @brief LCD Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t Prescaler;       /*!< Configures the LCD Prescaler. 
-                                 This parameter can be one value of @ref LCD_Prescaler */
-  uint32_t Divider;         /*!< Configures the LCD Divider.
-                                 This parameter can be one value of @ref LCD_Divider */
-  uint32_t Duty;            /*!< Configures the LCD Duty.
-                                 This parameter can be one value of @ref LCD_Duty */
-  uint32_t Bias;            /*!< Configures the LCD Bias.
-                                 This parameter can be one value of @ref LCD_Bias */ 
-  uint32_t VoltageSource;   /*!< Selects the LCD Voltage source.
-                                 This parameter can be one value of @ref LCD_Voltage_Source */  
-  uint32_t Contrast;        /*!< Configures the LCD Contrast.
-                                 This parameter can be one value of @ref LCD_Contrast */
-  uint32_t DeadTime;        /*!< Configures the LCD Dead Time.
-                                 This parameter can be one value of @ref LCD_DeadTime */
-  uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
-                                 This parameter can be one value of @ref LCD_PulseOnDuration */
-  uint32_t HighDrive;      /*!< Configures the LCD High Drive.
-                                 This parameter can be one value of @ref LCD_HighDrive */
-  uint32_t BlinkMode;       /*!< Configures the LCD Blink Mode.
-                                 This parameter can be one value of @ref LCD_BlinkMode */
-  uint32_t BlinkFrequency;  /*!< Configures the LCD Blink frequency.
-                                 This parameter can be one value of @ref LCD_BlinkFrequency */
-  uint32_t MuxSegment;      /*!< Enable or disable mux segment.
-                                 This parameter can be one value of @ref LCD_MuxSegment */
-}LCD_InitTypeDef;
-
-/** 
-  * @brief HAL LCD State structures definition
-  */ 
-typedef enum
-{
-  HAL_LCD_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized */
-  HAL_LCD_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */
-  HAL_LCD_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing */
-  HAL_LCD_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state */
-  HAL_LCD_STATE_ERROR             = 0x04U     /*!< Error */
-}HAL_LCD_StateTypeDef;
-
-/** 
-  * @brief  UART handle Structure definition
-  */  
-typedef struct
-{
-  LCD_TypeDef                   *Instance;  /* LCD registers base address */
-  
-  LCD_InitTypeDef               Init;       /* LCD communication parameters */
-
-  HAL_LockTypeDef               Lock;       /* Locking object */
-
-  __IO HAL_LCD_StateTypeDef     State;      /* LCD communication state */
-  
-  __IO uint32_t                 ErrorCode;  /* LCD Error code */
-  
-}LCD_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup LCD_Exported_Constants LCD Exported Constants
-  * @{
-  */
-
-/** @defgroup  LCD_ErrorCode LCD Error Code
-  * @{
-  */ 
-#define HAL_LCD_ERROR_NONE       (0x00U)    /*!< No error */
-#define HAL_LCD_ERROR_FCRSF      (0x01U)    /*!< Synchro flag timeout error */
-#define HAL_LCD_ERROR_UDR        (0x02U)    /*!< Update display request flag timeout error */
-#define HAL_LCD_ERROR_UDD        (0x04U)    /*!< Update display done flag timeout error */
-#define HAL_LCD_ERROR_ENS        (0x08U)    /*!< LCD enabled status flag timeout error */
-#define HAL_LCD_ERROR_RDY        (0x10U)    /*!< LCD Booster ready timeout error */
-/**
-  * @}
-  */
-  
-/** @defgroup LCD_Prescaler LCD Prescaler
-  * @{
-  */
-
-#define LCD_PRESCALER_1        (0x00000000U)  /*!< CLKPS = LCDCLK        */
-#define LCD_PRESCALER_2        (0x00400000U)  /*!< CLKPS = LCDCLK/2      */
-#define LCD_PRESCALER_4        (0x00800000U)  /*!< CLKPS = LCDCLK/4      */
-#define LCD_PRESCALER_8        (0x00C00000U)  /*!< CLKPS = LCDCLK/8      */
-#define LCD_PRESCALER_16       (0x01000000U)  /*!< CLKPS = LCDCLK/16     */
-#define LCD_PRESCALER_32       (0x01400000U)  /*!< CLKPS = LCDCLK/32     */
-#define LCD_PRESCALER_64       (0x01800000U)  /*!< CLKPS = LCDCLK/64     */
-#define LCD_PRESCALER_128      (0x01C00000U)  /*!< CLKPS = LCDCLK/128    */
-#define LCD_PRESCALER_256      (0x02000000U)  /*!< CLKPS = LCDCLK/256    */
-#define LCD_PRESCALER_512      (0x02400000U)  /*!< CLKPS = LCDCLK/512    */
-#define LCD_PRESCALER_1024     (0x02800000U)  /*!< CLKPS = LCDCLK/1024   */
-#define LCD_PRESCALER_2048     (0x02C00000U)  /*!< CLKPS = LCDCLK/2048   */
-#define LCD_PRESCALER_4096     (0x03000000U)  /*!< CLKPS = LCDCLK/4096   */
-#define LCD_PRESCALER_8192     (0x03400000U)  /*!< CLKPS = LCDCLK/8192   */
-#define LCD_PRESCALER_16384    (0x03800000U)  /*!< CLKPS = LCDCLK/16384  */
-#define LCD_PRESCALER_32768    (LCD_FCR_PS)  /*!< CLKPS = LCDCLK/32768  */
-
-#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1)     || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_2)     || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_4)     || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_8)     || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_16)    || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_32)    || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_64)    || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_128)   || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_256)   || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_512)   || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_1024)  || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_2048)  || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_4096)  || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_8192)  || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_16384) || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_32768))
-
-/**
-  * @}
-  */
-  
-/** @defgroup LCD_Divider LCD Divider
-  * @{
-  */
-
-#define LCD_DIVIDER_16    (0x00000000U)  /*!< LCD frequency = CLKPS/16 */
-#define LCD_DIVIDER_17    (0x00040000U)  /*!< LCD frequency = CLKPS/17 */
-#define LCD_DIVIDER_18    (0x00080000U)  /*!< LCD frequency = CLKPS/18 */
-#define LCD_DIVIDER_19    (0x000C0000U)  /*!< LCD frequency = CLKPS/19 */
-#define LCD_DIVIDER_20    (0x00100000U)  /*!< LCD frequency = CLKPS/20 */
-#define LCD_DIVIDER_21    (0x00140000U)  /*!< LCD frequency = CLKPS/21 */
-#define LCD_DIVIDER_22    (0x00180000U)  /*!< LCD frequency = CLKPS/22 */
-#define LCD_DIVIDER_23    (0x001C0000U)  /*!< LCD frequency = CLKPS/23 */
-#define LCD_DIVIDER_24    (0x00200000U)  /*!< LCD frequency = CLKPS/24 */
-#define LCD_DIVIDER_25    (0x00240000U)  /*!< LCD frequency = CLKPS/25 */
-#define LCD_DIVIDER_26    (0x00280000U)  /*!< LCD frequency = CLKPS/26 */
-#define LCD_DIVIDER_27    (0x002C0000U)  /*!< LCD frequency = CLKPS/27 */
-#define LCD_DIVIDER_28    (0x00300000U)  /*!< LCD frequency = CLKPS/28 */
-#define LCD_DIVIDER_29    (0x00340000U)  /*!< LCD frequency = CLKPS/29 */
-#define LCD_DIVIDER_30    (0x00380000U)  /*!< LCD frequency = CLKPS/30 */
-#define LCD_DIVIDER_31    (LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */
-
-#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_17) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_18) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_19) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_20) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_21) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_22) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_23) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_24) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_25) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_26) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_27) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_28) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_29) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_30) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_31))
-
-/**
-  * @}
-  */
-
-
-/** @defgroup LCD_Duty LCD Duty
-  * @{
-  */
-  
-#define LCD_DUTY_STATIC                 (0x00000000U)           /*!< Static duty */
-#define LCD_DUTY_1_2                    (LCD_CR_DUTY_0)                   /*!< 1/2 duty    */
-#define LCD_DUTY_1_3                    (LCD_CR_DUTY_1)                   /*!< 1/3 duty    */
-#define LCD_DUTY_1_4                    ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty    */
-#define LCD_DUTY_1_8                    (LCD_CR_DUTY_2)                   /*!< 1/8 duty    */
-
-#define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC)  || \
-                               ((__DUTY__) == LCD_DUTY_1_2)     || \
-                               ((__DUTY__) == LCD_DUTY_1_3)     || \
-                               ((__DUTY__) == LCD_DUTY_1_4)     || \
-                               ((__DUTY__) == LCD_DUTY_1_8))
-
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup LCD_Bias LCD Bias
-  * @{
-  */
-  
-#define LCD_BIAS_1_4                    (0x00000000U) /*!< 1/4 Bias */
-#define LCD_BIAS_1_2                    LCD_CR_BIAS_0           /*!< 1/2 Bias */
-#define LCD_BIAS_1_3                    LCD_CR_BIAS_1           /*!< 1/3 Bias */
-
-#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
-                               ((__BIAS__) == LCD_BIAS_1_2) || \
-                               ((__BIAS__) == LCD_BIAS_1_3))
-/**
-  * @}
-  */ 
-    
-/** @defgroup LCD_Voltage_Source LCD Voltage Source
-  * @{
-  */
-  
-#define LCD_VOLTAGESOURCE_INTERNAL      (0x00000000U) /*!< Internal voltage source for the LCD */
-#define LCD_VOLTAGESOURCE_EXTERNAL      LCD_CR_VSEL             /*!< External voltage source for the LCD */
-
-#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
-                                       ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))
-
-/**
-  * @}
-  */  
-
-/** @defgroup LCD_Interrupts LCD Interrupts
-  * @{
-  */
-#define LCD_IT_SOF                      LCD_FCR_SOFIE
-#define LCD_IT_UDD                      LCD_FCR_UDDIE
-
-/**
-  * @}
-  */
-
-/** @defgroup LCD_PulseOnDuration LCD Pulse On Duration
-  * @{
-  */
-
-#define LCD_PULSEONDURATION_0           (0x00000000U)         /*!< Pulse ON duration = 0 pulse   */
-#define LCD_PULSEONDURATION_1           (LCD_FCR_PON_0)                 /*!< Pulse ON duration = 1/CK_PS  */
-#define LCD_PULSEONDURATION_2           (LCD_FCR_PON_1)                 /*!< Pulse ON duration = 2/CK_PS  */
-#define LCD_PULSEONDURATION_3           (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS  */
-#define LCD_PULSEONDURATION_4           (LCD_FCR_PON_2)                 /*!< Pulse ON duration = 4/CK_PS  */
-#define LCD_PULSEONDURATION_5           (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS  */
-#define LCD_PULSEONDURATION_6           (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS  */
-#define LCD_PULSEONDURATION_7           (LCD_FCR_PON)                   /*!< Pulse ON duration = 7/CK_PS  */
-
-#define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_1) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_2) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_3) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_4) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_5) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_6) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_7))
-/**
-  * @}
-  */
-
-/** @defgroup LCD_HighDrive LCD HighDrive
-  * @{
-  */
-
-#define LCD_HIGHDRIVE_0           (0x00000000U)         /*!< Low resistance Drive   */
-#define LCD_HIGHDRIVE_1           (LCD_FCR_HD)                    /*!< High resistance Drive  */
-
-#define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) (((__HIGHDRIVE__) == LCD_HIGHDRIVE_0) || \
-                                         ((__HIGHDRIVE__) == LCD_HIGHDRIVE_1))
-/**
-  * @}
-  */
-
-/** @defgroup LCD_DeadTime LCD Dead Time
-  * @{
-  */
-
-#define LCD_DEADTIME_0                  (0x00000000U)           /*!< No dead Time  */
-#define LCD_DEADTIME_1                  (LCD_FCR_DEAD_0)                  /*!< One Phase between different couple of Frame   */
-#define LCD_DEADTIME_2                  (LCD_FCR_DEAD_1)                  /*!< Two Phase between different couple of Frame   */
-#define LCD_DEADTIME_3                  (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
-#define LCD_DEADTIME_4                  (LCD_FCR_DEAD_2)                  /*!< Four Phase between different couple of Frame  */
-#define LCD_DEADTIME_5                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame  */
-#define LCD_DEADTIME_6                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame   */
-#define LCD_DEADTIME_7                  (LCD_FCR_DEAD)                    /*!< Seven Phase between different couple of Frame */
-
-#define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \
-                                    ((__TIME__) == LCD_DEADTIME_1) || \
-                                    ((__TIME__) == LCD_DEADTIME_2) || \
-                                    ((__TIME__) == LCD_DEADTIME_3) || \
-                                    ((__TIME__) == LCD_DEADTIME_4) || \
-                                    ((__TIME__) == LCD_DEADTIME_5) || \
-                                    ((__TIME__) == LCD_DEADTIME_6) || \
-                                    ((__TIME__) == LCD_DEADTIME_7))
-/**
-  * @}
-  */
-
-/** @defgroup LCD_BlinkMode LCD Blink Mode
-  * @{
-  */
-
-#define LCD_BLINKMODE_OFF               (0x00000000U) /*!< Blink disabled            */
-#define LCD_BLINKMODE_SEG0_COM0         (LCD_FCR_BLINK_0)       /*!< Blink enabled on SEG[0], COM[0] (1 pixel)   */
-#define LCD_BLINKMODE_SEG0_ALLCOM       (LCD_FCR_BLINK_1)       /*!< Blink enabled on SEG[0], all COM (up to 
-                                                                    8 pixels according to the programmed duty)  */
-#define LCD_BLINKMODE_ALLSEG_ALLCOM     (LCD_FCR_BLINK)         /*!< Blink enabled on all SEG and all COM (all pixels)  */
-
-#define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF)            || \
-                                     ((__MODE__) == LCD_BLINKMODE_SEG0_COM0)      || \
-                                     ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM)    || \
-                                     ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))
-/**
-  * @}
-  */    
-
-/** @defgroup LCD_BlinkFrequency LCD Blink Frequency
-  * @{
-  */
-
-#define LCD_BLINKFREQUENCY_DIV8         (0x00000000U)               /*!< The Blink frequency = fLCD/8    */
-#define LCD_BLINKFREQUENCY_DIV16        (LCD_FCR_BLINKF_0)                    /*!< The Blink frequency = fLCD/16   */
-#define LCD_BLINKFREQUENCY_DIV32        (LCD_FCR_BLINKF_1)                    /*!< The Blink frequency = fLCD/32   */
-#define LCD_BLINKFREQUENCY_DIV64        (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64   */
-#define LCD_BLINKFREQUENCY_DIV128       (LCD_FCR_BLINKF_2)                    /*!< The Blink frequency = fLCD/128  */
-#define LCD_BLINKFREQUENCY_DIV256       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)  /*!< The Blink frequency = fLCD/256  */
-#define LCD_BLINKFREQUENCY_DIV512       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)  /*!< The Blink frequency = fLCD/512  */
-#define LCD_BLINKFREQUENCY_DIV1024      (LCD_FCR_BLINKF)                      /*!< The Blink frequency = fLCD/1024 */
-
-#define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8)   || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16)  || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32)  || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64)  || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Contrast LCD Contrast
-  * @{
-  */
-
-#define LCD_CONTRASTLEVEL_0               (0x00000000U)       /*!< Maximum Voltage = 2.60V    */
-#define LCD_CONTRASTLEVEL_1               (LCD_FCR_CC_0)                /*!< Maximum Voltage = 2.73V    */
-#define LCD_CONTRASTLEVEL_2               (LCD_FCR_CC_1)                /*!< Maximum Voltage = 2.86V    */
-#define LCD_CONTRASTLEVEL_3               (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V    */
-#define LCD_CONTRASTLEVEL_4               (LCD_FCR_CC_2)                /*!< Maximum Voltage = 3.12V    */
-#define LCD_CONTRASTLEVEL_5               (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.25V    */
-#define LCD_CONTRASTLEVEL_6               (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.38V    */
-#define LCD_CONTRASTLEVEL_7               (LCD_FCR_CC)                  /*!< Maximum Voltage = 3.51V    */
-
-#define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_7))
-/**
-  * @}
-  */
-      
-/** @defgroup LCD_MuxSegment LCD Mux Segment
-  * @{
-  */
-
-#define LCD_MUXSEGMENT_DISABLE            (0x00000000U)       /*!< SEG pin multiplexing disabled */
-#define LCD_MUXSEGMENT_ENABLE             (LCD_CR_MUX_SEG)              /*!< SEG[31:28] are multiplexed with SEG[43:40]    */
-
-#define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
-                                      ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup LCD_BUFEN LCD Voltage output buffer enable
-  * @{
-  */
-
-#define LCD_VOLTBUFOUT_DISABLE            (0x00000000U)       /*!< Voltage output buffer disabled */
-#define LCD_VOLTBUFOUT_ENABLE             (LCD_CR_BUFEN)                /*!< BUFEN[1] Voltage output buffer enabled    */
-
-#define IS_LCD_VOLTBUFOUT(__VALUE__) (((__VALUE__) == LCD_VOLTBUFOUT_ENABLE) || \
-                                      ((__VALUE__) == LCD_VOLTBUFOUT_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Flag LCD Flag
-  * @{
-  */
-
-#define LCD_FLAG_ENS                    LCD_SR_ENS
-#define LCD_FLAG_SOF                    LCD_SR_SOF
-#define LCD_FLAG_UDR                    LCD_SR_UDR
-#define LCD_FLAG_UDD                    LCD_SR_UDD
-#define LCD_FLAG_RDY                    LCD_SR_RDY
-#define LCD_FLAG_FCRSF                  LCD_SR_FCRSR
-
-/**
-  * @}
-  */   
-
-/** @defgroup LCD_RAMRegister LCD RAMRegister
-  * @{
-  */
-
-#define LCD_RAM_REGISTER0               (0x00000000U) /*!< LCD RAM Register 0  */
-#define LCD_RAM_REGISTER1               (0x00000001U) /*!< LCD RAM Register 1  */
-#define LCD_RAM_REGISTER2               (0x00000002U) /*!< LCD RAM Register 2  */
-#define LCD_RAM_REGISTER3               (0x00000003U) /*!< LCD RAM Register 3  */
-#define LCD_RAM_REGISTER4               (0x00000004U) /*!< LCD RAM Register 4  */
-#define LCD_RAM_REGISTER5               (0x00000005U) /*!< LCD RAM Register 5  */
-#define LCD_RAM_REGISTER6               (0x00000006U) /*!< LCD RAM Register 6  */
-#define LCD_RAM_REGISTER7               (0x00000007U) /*!< LCD RAM Register 7  */
-#define LCD_RAM_REGISTER8               (0x00000008U) /*!< LCD RAM Register 8  */
-#define LCD_RAM_REGISTER9               (0x00000009U) /*!< LCD RAM Register 9  */
-#define LCD_RAM_REGISTER10              (0x0000000AU) /*!< LCD RAM Register 10 */
-#define LCD_RAM_REGISTER11              (0x0000000BU) /*!< LCD RAM Register 11 */
-#define LCD_RAM_REGISTER12              (0x0000000CU) /*!< LCD RAM Register 12 */
-#define LCD_RAM_REGISTER13              (0x0000000DU) /*!< LCD RAM Register 13 */
-#define LCD_RAM_REGISTER14              (0x0000000EU) /*!< LCD RAM Register 14 */
-#define LCD_RAM_REGISTER15              (0x0000000FU) /*!< LCD RAM Register 15 */
-
-#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER1)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER2)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER3)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER4)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER5)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER6)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER7)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER8)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER9)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER10) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER11) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER12) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER13) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER14) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER15))
-
-/**
-  * @}
-  */  
-   
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup LCD_Exported_Macros LCD Exported Macros
-  * @{
-  */
-
-/** @brief Reset LCD handle state
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @retval None
-  */
-#define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
-
-/** @brief  macros to enables or disables the LCD
-  * @param  __HANDLE__ specifies the LCD Handle.  
-  * @retval None
-  */     
-#define __HAL_LCD_ENABLE(__HANDLE__)              (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
-#define __HAL_LCD_DISABLE(__HANDLE__)             (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
-
-/** @brief  macros to enables or disables the Voltage output buffer
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @retval None
-  */
-#define __HAL_LCD_VOLTOUTBUFFER_ENABLE(__HANDLE__)              (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN))
-#define __HAL_LCD_VOLTOUTBUFFER_DISABLE(__HANDLE__)             (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN))
-
-/** @brief  Macros to enable or disable the low resistance divider. Displays with high 
-  *         internal resistance may need a longer drive time to achieve 
-  *         satisfactory contrast. This function is useful in this case if some 
-  *         additional power consumption can be tolerated.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @note   When this mode is enabled, the PulseOn Duration (PON) have to be 
-  *         programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
-  * @retval None
-  */
-#define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__)                                \
-                              do{                                              \
-                                  SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
-                                  LCD_WaitForSynchro(__HANDLE__);              \
-                                 }while(0)
-
-#define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__)                               \
-                              do{                                              \
-                                  CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
-                                  LCD_WaitForSynchro(__HANDLE__);              \
-                                 }while(0)
-
-/**
-  * @brief  Macro to configure the LCD pulses on duration.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __DURATION__ specifies the LCD pulse on duration in terms of 
-  *         CK_PS (prescaled LCD clock period) pulses.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_PULSEONDURATION_0: 0 pulse
-  *     @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
-  *     @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
-  *     @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
-  *     @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
-  *     @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
-  *     @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
-  *     @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
-  * @retval None
-  */
-#define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__)                \
-        do{                                                                       \
-            MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
-            LCD_WaitForSynchro(__HANDLE__);                                       \
-           }while(0)
-
-/**
-  * @brief  Macro to configure the LCD dead time.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __DEADTIME__ specifies the LCD dead time.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_DEADTIME_0: No dead Time
-  *     @arg LCD_DEADTIME_1: One Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_6: Six Phase between different couple of Frame 
-  *     @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
-  * @retval None
-  */
-#define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__)                        \
-        do{                                                                        \
-            MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
-            LCD_WaitForSynchro(__HANDLE__);                                        \
-           }while(0)
-
-/**
-  * @brief  Macro to configure the LCD Contrast.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __CONTRAST__ specifies the LCD Contrast.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
-  *     @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
-  *     @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
-  *     @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
-  *     @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
-  *     @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
-  *     @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
-  *     @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
-  * @retval None
-  */
-#define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__)                       \
-        do{                                                                       \
-            MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__));  \
-            LCD_WaitForSynchro(__HANDLE__);                                       \
-           } while(0) 
-
-/**
-  * @brief  Macro to configure the LCD Blink mode and Blink frequency.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __BLINKMODE__ specifies the LCD blink mode.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_BLINKMODE_OFF:           Blink disabled
-  *     @arg LCD_BLINKMODE_SEG0_COM0:     Blink enabled on SEG[0], COM[0] (1 pixel)
-  *     @arg LCD_BLINKMODE_SEG0_ALLCOM:   Blink enabled on SEG[0], all COM (up to 8 
-  *                                       pixels according to the programmed duty)
-  *     @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM 
-  *                                       (all pixels)
-  * @param  __BLINKFREQUENCY__ specifies the LCD blink frequency.
-  *     @arg LCD_BLINKFREQUENCY_DIV8:    The Blink frequency = fLcd/8
-  *     @arg LCD_BLINKFREQUENCY_DIV16:   The Blink frequency = fLcd/16
-  *     @arg LCD_BLINKFREQUENCY_DIV32:   The Blink frequency = fLcd/32
-  *     @arg LCD_BLINKFREQUENCY_DIV64:   The Blink frequency = fLcd/64 
-  *     @arg LCD_BLINKFREQUENCY_DIV128:  The Blink frequency = fLcd/128
-  *     @arg LCD_BLINKFREQUENCY_DIV256:  The Blink frequency = fLcd/256
-  *     @arg LCD_BLINKFREQUENCY_DIV512:  The Blink frequency = fLcd/512
-  *     @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
-  * @retval None
-  */
-#define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__)  \
-        do{                                                                    \
-            MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
-            LCD_WaitForSynchro(__HANDLE__);                                    \
-          }while(0)
-
-/** @brief  Enables or disables the specified LCD interrupt.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __INTERRUPT__ specifies the LCD interrupt source to be enabled or disabled.
-  *          This parameter can be one of the following values:
-  *     @arg LCD_IT_SOF: Start of Frame Interrupt
-  *     @arg LCD_IT_UDD: Update Display Done Interrupt
-  * @retval None
-  */
-#define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__)                                \
-                         do{                                                          \
-                             SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__));   \
-                             LCD_WaitForSynchro(__HANDLE__);                          \
-                            }while(0)         
-#define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__)                               \
-                         do{                                                          \
-                             CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
-                             LCD_WaitForSynchro(__HANDLE__);                          \
-                            }while(0)
-
-/** @brief  Checks whether the specified LCD interrupt is enabled or not.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __IT__ specifies the LCD interrupt source to check.
-  *        This parameter can be one of the following values:
-  *        @arg LCD_IT_SOF: Start of Frame Interrupt
-  *        @arg LCD_IT_UDD: Update Display Done Interrupt.
-  * @note If the device is in STOP mode (PCLK not provided) UDD will not 
-  *          generate an interrupt even if UDDIE = 1. 
-  *          If the display is not enabled the UDD interrupt will never occur.
-  * @retval The state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
-
-/** @brief  Checks whether the specified LCD flag is set or not.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *        @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
-  * @note  The ENS bit is set immediately when the LCDEN bit in the LCD_CR 
-  *             goes from 0 to 1. On deactivation it reflects the real status of 
-  *             LCD so it becomes 0 at the end of the last displayed frame.  
-  *        @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at 
-  *             the beginning of a new frame, at the same time as the display data is 
-  *             updated.
-  *        @arg LCD_FLAG_UDR: Update Display Request flag.
-  *        @arg LCD_FLAG_UDD: Update Display Done flag. 
-  *        @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status 
-  *             of the step-up converter.
-  *        @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. 
-  *             This flag is set by hardware each time the LCD_FCR register is updated 
-  *             in the LCDCLK domain. 
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__)    (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))   
-
-/** @brief  Clears the specified LCD pending flag.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *        This parameter can be any combination of the following values:
-  *        @arg LCD_FLAG_SOF: Start of Frame Interrupt
-  *        @arg LCD_FLAG_UDD: Update Display Done Interrupt
-  * @retval None
-  */
-#define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CLR = (__FLAG__))
-
-/**
-  * @}
-  */
-  
-/* Exported functions ------------------------------------------------------- */
-
-/** @defgroup LCD_Exported_Functions LCD Exported Functions
-  * @{
-  */
-
-/** @defgroup LCD_Exported_Functions_Group1 Initialization and de-initialization methods
-  * @{
-  */
-
-/* Initialization/de-initialization methods  **********************************/
-HAL_StatusTypeDef     HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
-HAL_StatusTypeDef     HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
-void                  HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
-void                  HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
-
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Exported_Functions_Group2 IO operation methods
-  * @{
-  */
-
-/* IO operation methods *******************************************************/
-HAL_StatusTypeDef     HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data);
-HAL_StatusTypeDef     HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
-HAL_StatusTypeDef     HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd);
-
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods
-  * @{
-  */
-
-/* Peripheral State methods  **************************************************/
-HAL_LCD_StateTypeDef  HAL_LCD_GetState(LCD_HandleTypeDef *hlcd);
-uint32_t              HAL_LCD_GetError(LCD_HandleTypeDef *hlcd);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup LCD_Private
-  * @{
-  */
-
-/* Private functions ---------------------------------------------------------*/
-HAL_StatusTypeDef     LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
-
-/**
-  * @}
-  */
-
-/* Define the private group ***********************************/
-/**************************************************************/
-/** @defgroup LCD_Private LCD Private
-  * @{
-  */
-/**
-  * @}
-  */
-/**************************************************************/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_LCD_H */
-
-/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h
deleted file mode 100644
index 1bf4bb4549..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h
+++ /dev/null
@@ -1,772 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_lptim.h
-  * @author  MCD Application Team
-  * @brief   Header file of LPTIM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_LPTIM_H
-#define STM32L0xx_HAL_LPTIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#if defined (LPTIM1)
-
-/** @addtogroup LPTIM
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
-  * @{
-  */
-#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT  EXTI_IMR_IM29  /*!< External interrupt line 29 Connected to the LPTIM EXTI Line */
-
-/**
-  * @brief  LPTIM Clock configuration definition
-  */
-typedef struct
-{
-  uint32_t Source;         /*!< Selects the clock source.
-                           This parameter can be a value of @ref LPTIM_Clock_Source   */
-
-  uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
-                           This parameter can be a value of @ref LPTIM_Clock_Prescaler */
-
-} LPTIM_ClockConfigTypeDef;
-
-/**
-  * @brief  LPTIM Clock configuration definition
-  */
-typedef struct
-{
-  uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
-                           if the ULPTIM input is selected.
-                           Note: This parameter is used only when Ultra low power clock source is used.
-                           Note: If the polarity is configured on 'both edges', an auxiliary clock
-                           (one of the Low power oscillator) must be active.
-                           This parameter can be a value of @ref LPTIM_Clock_Polarity */
-
-  uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
-                           Note: This parameter is used only when Ultra low power clock source is used.
-                           This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
-
-} LPTIM_ULPClockConfigTypeDef;
-
-/**
-  * @brief  LPTIM Trigger configuration definition
-  */
-typedef struct
-{
-  uint32_t Source;        /*!< Selects the Trigger source.
-                          This parameter can be a value of @ref LPTIM_Trigger_Source */
-
-  uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
-                          Note: This parameter is used only when an external trigger is used.
-                          This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
-
-  uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
-                          Note: This parameter is used only when an external trigger is used.
-                          This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */
-} LPTIM_TriggerConfigTypeDef;
-
-/**
-  * @brief  LPTIM Initialization Structure definition
-  */
-typedef struct
-{
-  LPTIM_ClockConfigTypeDef     Clock;             /*!< Specifies the clock parameters */
-
-  LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
-
-  LPTIM_TriggerConfigTypeDef   Trigger;           /*!< Specifies the Trigger parameters */
-
-  uint32_t                     OutputPolarity;    /*!< Specifies the Output polarity.
-                                                  This parameter can be a value of @ref LPTIM_Output_Polarity */
-
-  uint32_t                     UpdateMode;        /*!< Specifies whether the update of the autoreload and the compare
-                                                  values is done immediately or after the end of current period.
-                                                  This parameter can be a value of @ref LPTIM_Updating_Mode */
-
-  uint32_t                     CounterSource;     /*!< Specifies whether the counter is incremented each internal event
-                                                  or each external event.
-                                                  This parameter can be a value of @ref LPTIM_Counter_Source */
-} LPTIM_InitTypeDef;
-
-/**
-  * @brief  HAL LPTIM State structure definition
-  */
-typedef enum
-{
-  HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
-  HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */
-  HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */
-  HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */
-  HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                 */
-} HAL_LPTIM_StateTypeDef;
-
-/**
-  * @brief  LPTIM handle Structure definition
-  */
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-typedef struct __LPTIM_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-{
-  LPTIM_TypeDef                 *Instance;         /*!< Register base address     */
-
-  LPTIM_InitTypeDef              Init;             /*!< LPTIM required parameters */
-
-  HAL_StatusTypeDef              Status;           /*!< LPTIM peripheral status   */
-
-  HAL_LockTypeDef                Lock;             /*!< LPTIM locking object      */
-
-  __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
-
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-  void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< LPTIM Base Msp Init Callback                 */
-  void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);          /*!< LPTIM Base Msp DeInit Callback               */
-  void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare match Callback                       */
-  void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload match Callback                   */
-  void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< External trigger event detection Callback    */
-  void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare register write complete Callback     */
-  void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload register write complete Callback */
-  void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim);        /*!< Up-counting direction change Callback        */
-  void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim);      /*!< Down-counting direction change Callback      */
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-} LPTIM_HandleTypeDef;
-
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL LPTIM Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_LPTIM_MSPINIT_CB_ID          = 0x00U,    /*!< LPTIM Base Msp Init Callback ID                  */
-  HAL_LPTIM_MSPDEINIT_CB_ID        = 0x01U,    /*!< LPTIM Base Msp DeInit Callback ID                */
-  HAL_LPTIM_COMPARE_MATCH_CB_ID    = 0x02U,    /*!< Compare match Callback ID                        */
-  HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,    /*!< Auto-reload match Callback ID                    */
-  HAL_LPTIM_TRIGGER_CB_ID          = 0x04U,    /*!< External trigger event detection Callback ID     */
-  HAL_LPTIM_COMPARE_WRITE_CB_ID    = 0x05U,    /*!< Compare register write complete Callback ID      */
-  HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U,    /*!< Auto-reload register write complete Callback ID  */
-  HAL_LPTIM_DIRECTION_UP_CB_ID     = 0x07U,    /*!< Up-counting direction change Callback ID         */
-  HAL_LPTIM_DIRECTION_DOWN_CB_ID   = 0x08U,    /*!< Down-counting direction change Callback ID       */
-} HAL_LPTIM_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL TIM Callback pointer definition
-  */
-typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< pointer to the LPTIM callback function */
-
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
-  * @{
-  */
-
-/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
-  * @{
-  */
-#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        0x00000000U
-#define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
-  * @{
-  */
-#define LPTIM_PRESCALER_DIV1                    0x00000000U
-#define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
-#define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
-#define LPTIM_PRESCALER_DIV8                    (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
-#define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
-#define LPTIM_PRESCALER_DIV32                   (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
-#define LPTIM_PRESCALER_DIV64                   (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
-#define LPTIM_PRESCALER_DIV128                  LPTIM_CFGR_PRESC
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
-  * @{
-  */
-
-#define LPTIM_OUTPUTPOLARITY_HIGH               0x00000000U
-#define LPTIM_OUTPUTPOLARITY_LOW                LPTIM_CFGR_WAVPOL
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
-  * @{
-  */
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION  0x00000000U
-#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_CKFLT_0
-#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_CKFLT_1
-#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_CKFLT
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
-  * @{
-  */
-#define LPTIM_CLOCKPOLARITY_RISING              0x00000000U
-#define LPTIM_CLOCKPOLARITY_FALLING             LPTIM_CFGR_CKPOL_0
-#define LPTIM_CLOCKPOLARITY_RISING_FALLING      LPTIM_CFGR_CKPOL_1
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
-  * @{
-  */
-#define LPTIM_TRIGSOURCE_SOFTWARE               0x0000FFFFU
-#define LPTIM_TRIGSOURCE_0                      0x00000000U
-#define LPTIM_TRIGSOURCE_1                      LPTIM_CFGR_TRIGSEL_0
-#define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
-#define LPTIM_TRIGSOURCE_3                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
-#define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
-#define LPTIM_TRIGSOURCE_5                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
-#define LPTIM_TRIGSOURCE_6                      (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
-#define LPTIM_TRIGSOURCE_7                      LPTIM_CFGR_TRIGSEL
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
-  * @{
-  */
-#define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
-#define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
-#define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
-  * @{
-  */
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  0x00000000U
-#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
-#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
-#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
-  * @{
-  */
-
-#define LPTIM_UPDATE_IMMEDIATE                  0x00000000U
-#define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
-  * @{
-  */
-
-#define LPTIM_COUNTERSOURCE_INTERNAL            0x00000000U
-#define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
-  * @{
-  */
-
-#define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
-#define LPTIM_FLAG_UP                            LPTIM_ISR_UP
-#define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
-#define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
-#define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
-#define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
-#define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
-  * @{
-  */
-#define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
-#define LPTIM_IT_UP                              LPTIM_IER_UPIE
-#define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
-#define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
-#define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
-#define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
-#define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
-  * @{
-  */
-
-/** @brief Reset LPTIM handle state.
-  * @param  __HANDLE__ LPTIM handle
-  * @retval None
-  */
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
-                                                        (__HANDLE__)->State             = HAL_LPTIM_STATE_RESET; \
-                                                        (__HANDLE__)->MspInitCallback   = NULL;                  \
-                                                        (__HANDLE__)->MspDeInitCallback = NULL;                  \
-                                                      } while(0)
-#else
-#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Enable the LPTIM peripheral.
-  * @param  __HANDLE__ LPTIM handle
-  * @retval None
-  */
-#define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
-
-/**
-  * @brief  Disable the LPTIM peripheral.
-  * @param  __HANDLE__ LPTIM handle
-  * @note   The following sequence is required to solve LPTIM disable HW limitation.
-  *         Please check Errata Sheet ES0335 for more details under "MCU may remain
-  *         stuck in LPTIM interrupt when entering Stop mode" section.
-  * @note   Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
-  *         check for TIMEOUT.
-  * @retval None
-  */
-#define __HAL_LPTIM_DISABLE(__HANDLE__)   LPTIM_Disable(__HANDLE__)
-
-/**
-  * @brief  Start the LPTIM peripheral in Continuous mode.
-  * @param  __HANDLE__ LPTIM handle
-  * @retval None
-  */
-#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
-/**
-  * @brief  Start the LPTIM peripheral in single mode.
-  * @param  __HANDLE__ LPTIM handle
-  * @retval None
-  */
-#define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
-
-/**
-  * @brief  Write the passed parameter in the Autoreload register.
-  * @param  __HANDLE__ LPTIM handle
-  * @param  __VALUE__ Autoreload value
-  * @retval None
-  * @note   The ARR register can only be modified when the LPTIM instance is enabled.
-  */
-#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
-
-/**
-  * @brief  Write the passed parameter in the Compare register.
-  * @param  __HANDLE__ LPTIM handle
-  * @param  __VALUE__ Compare value
-  * @retval None
-  * @note   The CMP register can only be modified when the LPTIM instance is enabled.
-  */
-#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
-
-/**
-  * @brief  Check whether the specified LPTIM flag is set or not.
-  * @param  __HANDLE__ LPTIM handle
-  * @param  __FLAG__ LPTIM flag to check
-  *            This parameter can be a value of:
-  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
-  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
-  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
-  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
-  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
-  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
-  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
-  * @retval The state of the specified flag (SET or RESET).
-  */
-#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clear the specified LPTIM flag.
-  * @param  __HANDLE__ LPTIM handle.
-  * @param  __FLAG__ LPTIM flag to clear.
-  *            This parameter can be a value of:
-  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
-  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
-  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
-  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
-  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
-  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
-  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
-  * @retval None.
-  */
-#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ICR  = (__FLAG__))
-
-/**
-  * @brief  Enable the specified LPTIM interrupt.
-  * @param  __HANDLE__ LPTIM handle.
-  * @param  __INTERRUPT__ LPTIM interrupt to set.
-  *            This parameter can be a value of:
-  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
-  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
-  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
-  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
-  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
-  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
-  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
-  * @retval None.
-  * @note   The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
-  */
-#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified LPTIM interrupt.
-  * @param  __HANDLE__ LPTIM handle.
-  * @param  __INTERRUPT__ LPTIM interrupt to set.
-  *            This parameter can be a value of:
-  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
-  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
-  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
-  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
-  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
-  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
-  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
-  * @retval None.
-  * @note   The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
-  */
-#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
-
-/**
-  * @brief  Check whether the specified LPTIM interrupt source is enabled or not.
-  * @param  __HANDLE__ LPTIM handle.
-  * @param  __INTERRUPT__ LPTIM interrupt to check.
-  *            This parameter can be a value of:
-  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
-  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
-  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
-  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
-  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
-  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
-  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
-  * @retval Interrupt status.
-  */
-
-#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
-                                                                & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
-  * @brief  Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR\
-                                                        |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR\
-                                                        &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable event on the LPTIM Wake-up Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR\
-                                                        |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable event on the LPTIM Wake-up Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR\
-                                                        &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
-  * @{
-  */
-
-/** @addtogroup LPTIM_Exported_Functions_Group1
-  *  @brief    Initialization and Configuration functions.
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
-HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
-
-/* MSP functions  *************************************************************/
-void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Exported_Functions_Group2
-  *  @brief   Start-Stop operation functions.
-  * @{
-  */
-/* Start/Stop operation functions  *********************************************/
-/* ################################# PWM Mode ################################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################# One Pulse Mode ##############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################## Set once Mode ##############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################### Encoder Mode ##############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################# Time out  Mode ##############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################## Counter Mode ###############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
-HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
-HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Exported_Functions_Group3
-  *  @brief  Read operation functions.
-  * @{
-  */
-/* Reading operation functions ************************************************/
-uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
-uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
-uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Exported_Functions_Group4
-  *  @brief  LPTIM IRQ handler and callback functions.
-  * @{
-  */
-/* LPTIM IRQ functions  *******************************************************/
-void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
-
-/* CallBack functions  ********************************************************/
-void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
-                                             pLPTIM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Group5
-  *  @brief   Peripheral State functions.
-  * @{
-  */
-/* Peripheral State functions  ************************************************/
-HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Types LPTIM Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
-  * @{
-  */
-
-#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
-                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
-
-
-#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
-
-#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
-
-#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)  (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
-                                                 ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
-
-#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
-                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
-                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
-                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
-
-#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
-                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
-                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
-
-#define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))
-
-#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
-                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
-                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
-
-#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
-                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
-                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
-                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
-
-#define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
-                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
-
-#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
-                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
-
-#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)     ((__AUTORELOAD__) <= 0x0000FFFFUL)
-
-#define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFFUL)
-
-#define IS_LPTIM_PERIOD(__PERIOD__)             ((__PERIOD__) <= 0x0000FFFFUL)
-
-#define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFFUL)
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
-  * @{
-  */
-void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* LPTIM1 */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_LPTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd.h
deleted file mode 100644
index 54f346257f..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd.h
+++ /dev/null
@@ -1,1002 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_pcd.h
-  * @author  MCD Application Team
-  * @brief   Header file of PCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_PCD_H
-#define STM32L0xx_HAL_PCD_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_usb.h"
-
-#if defined (USB)
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCD
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup PCD_Exported_Types PCD Exported Types
-  * @{
-  */
-
-/**
-  * @brief  PCD State structure definition
-  */
-typedef enum
-{
-  HAL_PCD_STATE_RESET   = 0x00,
-  HAL_PCD_STATE_READY   = 0x01,
-  HAL_PCD_STATE_ERROR   = 0x02,
-  HAL_PCD_STATE_BUSY    = 0x03,
-  HAL_PCD_STATE_TIMEOUT = 0x04
-} PCD_StateTypeDef;
-
-/* Device LPM suspend state */
-typedef enum
-{
-  LPM_L0 = 0x00, /* on */
-  LPM_L1 = 0x01, /* LPM L1 sleep */
-  LPM_L2 = 0x02, /* suspend */
-  LPM_L3 = 0x03, /* off */
-} PCD_LPM_StateTypeDef;
-
-typedef enum
-{
-  PCD_LPM_L0_ACTIVE = 0x00, /* on */
-  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
-} PCD_LPM_MsgTypeDef;
-
-typedef enum
-{
-  PCD_BCD_ERROR                     = 0xFF,
-  PCD_BCD_CONTACT_DETECTION         = 0xFE,
-  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
-  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
-  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
-  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
-
-} PCD_BCD_MsgTypeDef;
-
-
-
-
-
-typedef USB_TypeDef        PCD_TypeDef;
-typedef USB_CfgTypeDef     PCD_InitTypeDef;
-typedef USB_EPTypeDef      PCD_EPTypeDef;
-
-
-/**
-  * @brief  PCD Handle Structure definition
-  */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-typedef struct __PCD_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-{
-  PCD_TypeDef             *Instance;   /*!< Register base address             */
-  PCD_InitTypeDef         Init;        /*!< PCD required parameters           */
-  __IO uint8_t            USB_Address; /*!< USB Address                       */
-  PCD_EPTypeDef           IN_ep[8];   /*!< IN endpoint parameters             */
-  PCD_EPTypeDef           OUT_ep[8];  /*!< OUT endpoint parameters            */
-  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status             */
-  __IO PCD_StateTypeDef   State;       /*!< PCD communication state           */
-  __IO  uint32_t          ErrorCode;   /*!< PCD Error code                    */
-  uint32_t                Setup[12];   /*!< Setup packet buffer               */
-  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                         */
-  uint32_t                BESL;
-
-
-  uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .
-                                       This parameter can be set to ENABLE or DISABLE        */
-
-  uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.
-                                       This parameter can be set to ENABLE or DISABLE        */
-  void                    *pData;      /*!< Pointer to upper stack Handler */
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-  void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */
-  void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */
-  void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */
-  void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */
-  void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */
-  void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */
-  void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */
-
-  void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */
-  void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */
-  void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */
-  void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */
-  void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */
-  void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */
-
-  void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */
-  void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-} PCD_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Include PCD HAL Extended module */
-#include "stm32l0xx_hal_pcd_ex.h"
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
-  * @{
-  */
-
-/** @defgroup PCD_Speed PCD Speed
-  * @{
-  */
-#define PCD_SPEED_FULL               USBD_FS_SPEED
-/**
-  * @}
-  */
-
-/** @defgroup PCD_PHY_Module PCD PHY Module
-  * @{
-  */
-#define PCD_PHY_ULPI                 1U
-#define PCD_PHY_EMBEDDED             2U
-#define PCD_PHY_UTMI                 3U
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Error_Code_definition PCD Error Code definition
-  * @brief  PCD Error Code definition
-  * @{
-  */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-#define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
-  *  @brief macros to handle interrupts and specific clock configurations
-  * @{
-  */
-
-
-#define __HAL_PCD_ENABLE(__HANDLE__)                                  (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__)                                 (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)                 ((USB_ReadInterrupts((__HANDLE__)->Instance)\
-                                                                        & (__INTERRUPT__)) == (__INTERRUPT__))
-
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)               (((__HANDLE__)->Instance->ISTR)\
-                                                                       &= (uint16_t)(~(__INTERRUPT__)))
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                             EXTI->IMR |= USB_WAKEUP_EXTI_LINE
-#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                            EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCD_Exported_Functions PCD Exported Functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  ********************************/
-/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
-  * @brief  HAL USB OTG PCD Callback ID enumeration definition
-  * @{
-  */
-typedef enum
-{
-  HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */
-  HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */
-  HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */
-  HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */
-  HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */
-  HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */
-  HAL_PCD_DISCONNECT_CB_ID   = 0x07,      /*!< USB PCD Disconnect callback ID   */
-
-  HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */
-  HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */
-
-} HAL_PCD_CallbackIDTypeDef;
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
-  * @brief  HAL USB OTG PCD Callback pointer definition
-  * @{
-  */
-
-typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */
-typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */
-typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */
-typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
-typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */
-typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */
-typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */
-
-/**
-  * @}
-  */
-
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
-                                           HAL_PCD_CallbackIDTypeDef CallbackID,
-                                           pPCD_CallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
-                                             HAL_PCD_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
-                                                       pPCD_DataOutStageCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
-                                                      pPCD_DataInStageCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
-                                                       pPCD_IsoOutIncpltCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
-                                                      pPCD_IsoInIncpltCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
-                                              pPCD_BcdCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
-                                              pPCD_LpmCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* I/O operation functions  ***************************************************/
-/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  **********************************************/
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
-                                  uint16_t ep_mps, uint8_t ep_type);
-
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
-                                     uint8_t *pBuf, uint32_t len);
-
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
-                                      uint8_t *pBuf, uint32_t len);
-
-
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-
-uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  ************************************************/
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
-  * @{
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PCD_Private_Constants PCD Private Constants
-  * @{
-  */
-/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
-  * @{
-  */
-
-
-#define USB_WAKEUP_EXTI_LINE                                          (0x1U << 18)  /*!< USB FS EXTI Line WakeUp Interrupt */
-
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_EP0_MPS PCD EP0 MPS
-  * @{
-  */
-#define PCD_EP0MPS_64                                                 EP_MPS_64
-#define PCD_EP0MPS_32                                                 EP_MPS_32
-#define PCD_EP0MPS_16                                                 EP_MPS_16
-#define PCD_EP0MPS_08                                                 EP_MPS_8
-/**
-  * @}
-  */
-
-/** @defgroup PCD_ENDP PCD ENDP
-  * @{
-  */
-#define PCD_ENDP0                                                     0U
-#define PCD_ENDP1                                                     1U
-#define PCD_ENDP2                                                     2U
-#define PCD_ENDP3                                                     3U
-#define PCD_ENDP4                                                     4U
-#define PCD_ENDP5                                                     5U
-#define PCD_ENDP6                                                     6U
-#define PCD_ENDP7                                                     7U
-/**
-  * @}
-  */
-
-/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
-  * @{
-  */
-#define PCD_SNG_BUF                                                   0U
-#define PCD_DBL_BUF                                                   1U
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
-  * @{
-  */
-
-/********************  Bit definition for USB_COUNTn_RX register  *************/
-#define USB_CNTRX_NBLK_MSK                    (0x1FU << 10)
-#define USB_CNTRX_BLSIZE                      (0x1U << 15)
-
-/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue)  (*(__IO uint16_t *)\
-                                                    (&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
-
-/* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum)             (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
-
-/* ENDPOINT transfer */
-#define USB_EP0StartXfer                           USB_EPStartXfer
-
-/**
-  * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wType Endpoint Type.
-  * @retval None
-  */
-#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum))\
-                                                              & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
-
-
-/**
-  * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval Endpoint Type
-  */
-#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
-
-/**
-  * @brief free buffer used from the application realizing it to the line
-  *         toggles bit SW_BUF in the double buffered endpoint register
-  * @param USBx USB device.
-  * @param   bEpNum, bDir
-  * @retval None
-  */
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \
-  do { \
-    if ((bDir) == 0U) \
-    { \
-      /* OUT double buffered endpoint */ \
-      PCD_TX_DTOG((USBx), (bEpNum)); \
-    } \
-    else if ((bDir) == 1U) \
-    { \
-      /* IN double buffered endpoint */ \
-      PCD_RX_DTOG((USBx), (bEpNum)); \
-    } \
-  } while(0)
-
-/**
-  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wState new state
-  * @retval None
-  */
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
-    /* toggle first bit ? */ \
-    if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPTX_DTOG1; \
-    } \
-    /* toggle second bit ?  */ \
-    if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPTX_DTOG2; \
-    } \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
-  } while(0) /* PCD_SET_EP_TX_STATUS */
-
-/**
-  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wState new state
-  * @retval None
-  */
-#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
-    /* toggle first bit ? */ \
-    if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPRX_DTOG1; \
-    } \
-    /* toggle second bit ? */ \
-    if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPRX_DTOG2; \
-    } \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
-  } while(0) /* PCD_SET_EP_RX_STATUS */
-
-/**
-  * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wStaterx new state.
-  * @param  wStatetx new state.
-  * @retval None
-  */
-#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
-    /* toggle first bit ? */ \
-    if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPRX_DTOG1; \
-    } \
-    /* toggle second bit ? */ \
-    if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPRX_DTOG2; \
-    } \
-    /* toggle first bit ? */ \
-    if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPTX_DTOG1; \
-    } \
-    /* toggle second bit ?  */ \
-    if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPTX_DTOG2; \
-    } \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
-  } while(0) /* PCD_SET_EP_TXRX_STATUS */
-
-/**
-  * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
-  *         /STAT_RX[1:0])
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval status
-  */
-#define PCD_GET_EP_TX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
-#define PCD_GET_EP_RX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
-
-/**
-  * @brief  sets directly the VALID tx/rx-status into the endpoint register
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_EP_TX_VALID(USBx, bEpNum)      (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
-#define PCD_SET_EP_RX_VALID(USBx, bEpNum)      (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
-
-/**
-  * @brief  checks stall condition in an endpoint.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval TRUE = endpoint in stall condition.
-  */
-#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
-#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
-
-/**
-  * @brief  set & clear EP_KIND bit.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_EP_KIND(USBx, bEpNum) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
-  } while(0) /* PCD_SET_EP_KIND */
-
-#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
-  } while(0) /* PCD_CLEAR_EP_KIND */
-
-/**
-  * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_OUT_STATUS(USBx, bEpNum)       PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)     PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
-  * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_BULK_EP_DBUF(USBx, bEpNum)     PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum)   PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
-  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
-  } while(0) /* PCD_CLEAR_RX_EP_CTR */
-
-#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
-  } while(0) /* PCD_CLEAR_TX_EP_CTR */
-
-/**
-  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_RX_DTOG(USBx, bEpNum) \
-  do { \
-    uint16_t _wEPVal; \
-    \
-    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
-  } while(0) /* PCD_RX_DTOG */
-
-#define PCD_TX_DTOG(USBx, bEpNum) \
-  do { \
-    uint16_t _wEPVal; \
-    \
-    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
-  } while(0) /* PCD_TX_DTOG */
-/**
-  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
-    \
-    if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
-    { \
-      PCD_RX_DTOG((USBx), (bEpNum)); \
-    } \
-  } while(0) /* PCD_CLEAR_RX_DTOG */
-
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
-    \
-    if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
-    { \
-      PCD_TX_DTOG((USBx), (bEpNum)); \
-    } \
-  } while(0) /* PCD_CLEAR_TX_DTOG */
-
-/**
-  * @brief  Sets address in an endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  bAddr Address.
-  * @retval None
-  */
-#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
-  } while(0) /* PCD_SET_EP_ADDRESS */
-
-/**
-  * @brief  Gets address in an endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
-                                                    + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
-
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
-                                                    + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
-
-
-/**
-  * @brief  sets address of the tx/rx buffer.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wAddr address to be set (must be word aligned).
-  * @retval None
-  */
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
-  do { \
-    __IO uint16_t *_wRegVal; \
-    uint32_t _wRegBase = (uint32_t)USBx; \
-    \
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \
-    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
-    *_wRegVal = ((wAddr) >> 1) << 1; \
-  } while(0) /* PCD_SET_EP_TX_ADDRESS */
-
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
-  do { \
-    __IO uint16_t *_wRegVal; \
-    uint32_t _wRegBase = (uint32_t)USBx; \
-    \
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \
-    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
-    *_wRegVal = ((wAddr) >> 1) << 1; \
-  } while(0) /* PCD_SET_EP_RX_ADDRESS */
-
-/**
-  * @brief  Gets address of the tx/rx buffer.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval address of the buffer.
-  */
-#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
-  * @brief  Sets counter of rx buffer with no. of blocks.
-  * @param  pdwReg Register pointer
-  * @param  wCount Counter.
-  * @param  wNBlocks no. of Blocks.
-  * @retval None
-  */
-#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
-  do { \
-    (wNBlocks) = (wCount) >> 5; \
-    if (((wCount) & 0x1fU) == 0U) \
-    { \
-      (wNBlocks)--; \
-    } \
-    *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
-  } while(0) /* PCD_CALC_BLK32 */
-
-#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
-  do { \
-    (wNBlocks) = (wCount) >> 1; \
-    if (((wCount) & 0x1U) != 0U) \
-    { \
-      (wNBlocks)++; \
-    } \
-    *(pdwReg) = (uint16_t)((wNBlocks) << 10); \
-  } while(0) /* PCD_CALC_BLK2 */
-
-#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
-  do { \
-    uint32_t wNBlocks; \
-    if ((wCount) == 0U) \
-    { \
-      *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
-      *(pdwReg) |= USB_CNTRX_BLSIZE; \
-    } \
-    else if((wCount) <= 62U) \
-    { \
-      PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
-    } \
-    else \
-    { \
-      PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
-    } \
-  } while(0) /* PCD_SET_EP_CNT_RX_REG */
-
-#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
-  do { \
-    uint32_t _wRegBase = (uint32_t)(USBx); \
-    __IO uint16_t *pdwReg; \
-    \
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \
-    pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
-    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
-  } while(0)
-
-/**
-  * @brief  sets counter for the tx/rx buffer.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wCount Counter value.
-  * @retval None
-  */
-#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
-  do { \
-    uint32_t _wRegBase = (uint32_t)(USBx); \
-    __IO uint16_t *_wRegVal; \
-    \
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \
-    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
-    *_wRegVal = (uint16_t)(wCount); \
-  } while(0)
-
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
-  do { \
-    uint32_t _wRegBase = (uint32_t)(USBx); \
-    __IO uint16_t *_wRegVal; \
-    \
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \
-    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
-    PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
-  } while(0)
-
-/**
-  * @brief  gets counter of the tx buffer.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval Counter value
-  */
-#define PCD_GET_EP_TX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
-#define PCD_GET_EP_RX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
-
-/**
-  * @brief  Sets buffer 0/1 address in a double buffer endpoint.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wBuf0Addr buffer 0 address.
-  * @retval Counter value
-  */
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
-  do { \
-    PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
-  } while(0) /* PCD_SET_EP_DBUF0_ADDR */
-
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
-  do { \
-    PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
-  } while(0) /* PCD_SET_EP_DBUF1_ADDR */
-
-/**
-  * @brief  Sets addresses in a double buffer endpoint.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wBuf0Addr: buffer 0 address.
-  * @param  wBuf1Addr = buffer 1 address.
-  * @retval None
-  */
-#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
-  do { \
-    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
-    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
-  } while(0) /* PCD_SET_EP_DBUF_ADDR */
-
-/**
-  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum)    (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum)    (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
-  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  bDir endpoint dir  EP_DBUF_OUT = OUT
-  *         EP_DBUF_IN  = IN
-  * @param  wCount: Counter value
-  * @retval None
-  */
-#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
-  do { \
-    if ((bDir) == 0U) \
-      /* OUT endpoint */ \
-    { \
-      PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
-    } \
-    else \
-    { \
-      if ((bDir) == 1U) \
-      { \
-        /* IN endpoint */ \
-        PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
-      } \
-    } \
-  } while(0) /* SetEPDblBuf0Count*/
-
-#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
-  do { \
-    uint32_t _wBase = (uint32_t)(USBx); \
-    __IO uint16_t *_wEPRegVal; \
-    \
-    if ((bDir) == 0U) \
-    { \
-      /* OUT endpoint */ \
-      PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
-    } \
-    else \
-    { \
-      if ((bDir) == 1U) \
-      { \
-        /* IN endpoint */ \
-        _wBase += (uint32_t)(USBx)->BTABLE; \
-        _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
-        *_wEPRegVal = (uint16_t)(wCount); \
-      } \
-    } \
-  } while(0) /* SetEPDblBuf1Count */
-
-#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
-  do { \
-    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
-    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
-  } while(0) /* PCD_SET_EP_DBUF_CNT */
-
-/**
-  * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum)     (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum)     (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined (USB) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_PCD_H */
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd_ex.h
deleted file mode 100644
index dec2d8c658..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd_ex.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_pcd_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of PCD HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_PCD_EX_H
-#define STM32L0xx_HAL_PCD_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-#if defined (USB)
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCDEx
-  * @{
-  */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
-  * @{
-  */
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
-  * @{
-  */
-
-
-
-HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
-                                       uint16_t ep_kind, uint32_t pmaadress);
-
-
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
-
-
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
-void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined (USB) */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L0xx_HAL_PCD_EX_H */
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h
deleted file mode 100644
index 6f49e72d4d..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h
+++ /dev/null
@@ -1,460 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_pwr.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_PWR_H
-#define __STM32L0xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWR PWR
-  * @{
-  */
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
-  * @{
-  */ 
-
-#if defined(PWR_PVD_SUPPORT)
-/**
-  * @brief  PWR PVD configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
-                            This parameter can be a value of @ref PWR_PVD_detection_level */
-
-  uint32_t Mode;       /*!< Mode: Specifies the operating mode for the selected pins.
-                            This parameter can be a value of @ref PWR_PVD_Mode */
-}PWR_PVDTypeDef;
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup PWR_Private
-  * @{
-  */ 
-
-#if defined(PWR_PVD_SUPPORT)
-#define PWR_EXTI_LINE_PVD      EXTI_FTSR_TR16  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
-  * @{
-  */
-
-/** @defgroup PWR_register_alias_address PWR Register alias address
-  * @{
-  */
-#define PWR_WAKEUP_PIN1                PWR_CSR_EWUP1
-#if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
-#else
-#define PWR_WAKEUP_PIN2                PWR_CSR_EWUP2
-#endif
-#if defined (STM32L010x4) || defined (STM32L010x6) || defined (STM32L011xx) || defined (STM32L021xx) || \
-    defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L071xx) || defined (STM32L072xx) || \
-    defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define PWR_WAKEUP_PIN3                PWR_CSR_EWUP3
-#endif
-/**
-  * @}
-  */
-
-#if defined(PWR_PVD_SUPPORT)
-/** @defgroup PWR_PVD_detection_level PVD detection level
-  * @{
-  */
-#define PWR_PVDLEVEL_0                 PWR_CR_PLS_LEV0
-#define PWR_PVDLEVEL_1                 PWR_CR_PLS_LEV1
-#define PWR_PVDLEVEL_2                 PWR_CR_PLS_LEV2
-#define PWR_PVDLEVEL_3                 PWR_CR_PLS_LEV3
-#define PWR_PVDLEVEL_4                 PWR_CR_PLS_LEV4
-#define PWR_PVDLEVEL_5                 PWR_CR_PLS_LEV5
-#define PWR_PVDLEVEL_6                 PWR_CR_PLS_LEV6
-#define PWR_PVDLEVEL_7                 PWR_CR_PLS_LEV7  /* External input analog voltage 
-                                                           (Compare internally to VREFINT) */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVD_Mode PWR PVD Mode
-  * @{
-  */
-#define PWR_PVD_MODE_NORMAL                 (0x00000000U)   /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING              (0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING             (0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING      (0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING           (0x00020001U)   /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING          (0x00020002U)   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   (0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection */
-/**
-  * @}
-  */
-#endif /* PWR_PVD_SUPPORT */
-
-/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
-  * @{
-  */
-#define PWR_MAINREGULATOR_ON           (0x00000000U)
-#define PWR_LOWPOWERREGULATOR_ON       PWR_CR_LPSDSR
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
-  * @{
-  */
-#define PWR_SLEEPENTRY_WFI             (0x01U)
-#define PWR_SLEEPENTRY_WFE             (0x02U)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
-  * @{
-  */
-#define PWR_STOPENTRY_WFI              (0x01U)
-#define PWR_STOPENTRY_WFE              (0x02U)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
-  * @{
-  */
-
-#define PWR_REGULATOR_VOLTAGE_SCALE1   PWR_CR_VOS_0
-#define PWR_REGULATOR_VOLTAGE_SCALE2   PWR_CR_VOS_1
-#define PWR_REGULATOR_VOLTAGE_SCALE3   PWR_CR_VOS
-
-#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
-                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
-                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Flag PWR Flag
-  * @{
-  */
-#define PWR_FLAG_WU                    PWR_CSR_WUF
-#define PWR_FLAG_SB                    PWR_CSR_SBF
-#if defined(PWR_PVD_SUPPORT)
-#define PWR_FLAG_PVDO                  PWR_CSR_PVDO
-#endif
-#define PWR_FLAG_VREFINTRDY            PWR_CSR_VREFINTRDYF
-#define PWR_FLAG_VOS                   PWR_CSR_VOSF
-#define PWR_FLAG_REGLP                 PWR_CSR_REGLPF
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Exported_Macro PWR Exported Macros
-  * @{
-  */
-/** @brief  macros configure the main internal regulator output voltage.
-  *         When exiting Low Power Run Mode or during dynamic voltage scaling configuration,
-  *         the reference manual recommends to poll PWR_FLAG_REGLP bit to wait for the regulator 
-  *         to reach main mode (resp. to get stabilized) for a transition from 0 to 1. 
-  *         Only then the clock can be increased.
-  *
-  * @param  __REGULATOR__ specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption when the device does
-  *         not operate at the maximum frequency (refer to the datasheets for more details).
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
-  *                                                System frequency up to 32 MHz.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
-  *                                                System frequency up to 16 MHz.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
-  *                                                System frequency up to 4.2 MHz
-  * @retval None
-  */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
-
-/** @brief  Check PWR flag is set or not.
-  * @param  __FLAG__ specifies the flag to check.
-  *           This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
-  *                  was received from the WKUP pin or from the RTC alarm (Alarm B),
-  *                  RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
-  *                  An additional wakeup event is detected if the WKUP pin is enabled
-  *                  (by setting the EWUP bit) when the WKUP pin level is already high.
-  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
-  *                  resumed from StandBy mode.
-  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
-  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
-  *                  For this reason, this bit is equal to 0 after Standby or reset
-  *                  until the PVDE bit is set. Not available on L0 Value line.
-  *            @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
-  *                 This bit indicates the state of the internal voltage reference, VREFINT.
-  *            @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
-  *                 the internal regulator to be ready after the voltage range is changed.
-  *                 The VOSF bit indicates that the regulator has reached the voltage level
-  *                 defined with bits VOS of PWR_CR register.
-  *            @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
-  *                 mode, this bit stays at 1 until the regulator is ready in main mode.
-  *                 A polling on this bit is recommended to wait for the regulator main mode.
-  *                 This bit is reset by hardware when the regulator is ready.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_FLAG(__FLAG__)                  ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the PWR pending flags.
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag
-  *            @arg PWR_FLAG_SB: StandBy flag
-  */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__)                SET_BIT(PWR->CR, (__FLAG__) << 2U)
-
-#if defined(PWR_PVD_SUPPORT)
-/**
-  * @brief Enable interrupt on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable interrupt on PVD Exti Line 16. 
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Enable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief  PVD EXTI line configuration: set falling edge trigger.  
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief  PVD EXTI line configuration: set rising edge trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising Trigger.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   do { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } while(0);
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0);
-
-/**
-  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
-  * @retval EXTI PVD Line Status.
-  */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG()       (EXTI->PR & (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Clear the PVD EXTI flag.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()     (EXTI->PR = (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Generate a Software interrupt on selected EXTI line.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Generate a Software interrupt on selected EXTI line.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()            SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
-
-#endif /* PWR_PVD_SUPPORT */
-
-/**
-  * @}
-  */
-
-/** @addtogroup PWR_Private
-  * @{
-  */
-#if defined(PWR_PVD_SUPPORT)
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
-                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
-                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
-                               ((MODE) == PWR_PVD_MODE_NORMAL)) 
-#endif /* PWR_PVD_SUPPORT */
-
-#if defined (STM32L010x6) || defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
-                                ((PIN) == PWR_WAKEUP_PIN2) || \
-                                ((PIN) == PWR_WAKEUP_PIN3))
-#elif defined (STM32L010xB) || defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx)
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
-                                ((PIN) == PWR_WAKEUP_PIN2))
-#elif defined (STM32L010x8) || defined (STM32L031xx) || defined (STM32L041xx)
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
-                                ((PIN) == PWR_WAKEUP_PIN2))
-#elif defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
-                                ((PIN) == PWR_WAKEUP_PIN3))
-#endif
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
-                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-
-/**
-  * @}
-  */
-
-/* Include PWR HAL Extension module */
-#include "stm32l0xx_hal_pwr_ex.h"
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-  
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Exported_Functions_Group2 Low Power modes configuration functions
-  * @{
-  */
-
-#if defined(PWR_PVD_SUPPORT)
-/* PVD control functions  ************************************************/
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
-#endif
-
-/* WakeUp pins configuration functions ****************************************/
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Define the private group ***********************************/
-/**************************************************************/
-/** @defgroup PWR_Private PWR Private
-  * @{
-  */
-/**
-  * @}
-  */
-/**************************************************************/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L0xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h
deleted file mode 100644
index e7e7f2514e..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_pwr_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_PWR_EX_H
-#define __STM32L0xx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWREx PWREx
-  * @{
-  */
-
-/** @defgroup PWREx_Exported_Macros PWREx Exported Macros
- * @{
- */
-
-/** @brief  Macros to enable the Deep-sleep mode with Flash memory kept off.
-  * @note   When entering low power mode (stop or standby only), if DS_EE_KOFF and RUN_PD of
-  *         FLASH_ACR register are both set , the Flash memory will not be woken up 
-  *         when exiting from deep-sleep mode.
-  */
-#define __HAL_PWR_FLASHWAKEUP_ENABLE()      CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF)
-
-/** @brief  Macros to disable the Deep-sleep mode with Flash memory kept off.
-  * @note   When entering low power mode (stop or standby only), if DS_EE_KOFF and RUN_PD of
-  *         FLASH_ACR register are both set , the Flash memory will not be woken up 
-  *         when exiting from deep-sleep mode.
-  */
-#define __HAL_PWR_FLASHWAKEUP_DISABLE()     SET_BIT(PWR->CR, PWR_CR_DSEEKOFF)
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
- * @{
- */
-uint32_t HAL_PWREx_GetVoltageRange(void);
-void HAL_PWREx_EnableFastWakeUp(void);
-void HAL_PWREx_DisableFastWakeUp(void);
-void HAL_PWREx_EnableUltraLowPower(void);
-void HAL_PWREx_DisableUltraLowPower(void);
-void HAL_PWREx_EnableLowPowerRunMode(void);
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
-/**
-  * @}
-  */
-
-/* Define the private group ***********************************/
-/**************************************************************/
-/** @defgroup PWREx_Private PWREx Private
-  * @{
-  */
-/**
-  * @}
-  */
-/**************************************************************/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_PWR_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h
deleted file mode 100644
index d98afcefda..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h
+++ /dev/null
@@ -1,1741 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_rcc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_RCC_H
-#define __STM32L0xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCC
-  * @{
-  */
-
-/** @addtogroup RCC_Private_Constants
-  * @{
-  */
-
-/** @defgroup RCC_Timeout RCC Timeout
-  * @{
-  */
-
-/* Disable Backup domain write protection state change timeout */
-#define RCC_DBP_TIMEOUT_VALUE      (100U)       /* 100 ms */
-/* LSE state change timeout */
-#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
-#define CLOCKSWITCH_TIMEOUT_VALUE  (5000U)  /* 5 s    */
-#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define MSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
-#define HSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
-#define LSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
-#if defined(RCC_HSI48_SUPPORT)
-#define HSI48_TIMEOUT_VALUE        (2U)      /* 2 ms (minimum Tick + 1) */
-#endif /* RCC_HSI48_SUPPORT */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
-  * @brief RCC registers bit address in the alias region
-  * @{
-  */
-#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define RCC_CR_OFFSET             (RCC_OFFSET + 0x00U)
-/* --- CFGR Register ---*/
-/* Alias word address of I2SSRC bit */
-#define RCC_CFGR_OFFSET           (RCC_OFFSET + 0x08U)
-/* --- CSR Register ---*/
-#define RCC_CSR_OFFSET            (RCC_OFFSET + 0x74U)
-
-/* CR register byte 3 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS      (0x40023802U)
-
-/* CIER register byte 0 (Bits[0:8]) base address */
-#define CIER_BYTE0_ADDRESS        ((uint32_t)(RCC_BASE + 0x10U + 0x00U))
-/**
-  * @}
-  */
-
-
-/* Defines used for Flags */
-#define CR_REG_INDEX                     ((uint8_t)1)
-#define CSR_REG_INDEX                    ((uint8_t)2)
-#define CRRCR_REG_INDEX                  ((uint8_t)3)
-
-#define RCC_FLAG_MASK                    ((uint8_t)0x1F)
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_Private_Macros
-  * @{
-  */
-#if defined(RCC_HSI48_SUPPORT)
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                               || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE)   == RCC_OSCILLATORTYPE_HSE)   || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI)   == RCC_OSCILLATORTYPE_HSI)   || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI)   == RCC_OSCILLATORTYPE_LSI)   || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE)   == RCC_OSCILLATORTYPE_LSE)   || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI)   == RCC_OSCILLATORTYPE_MSI))
-
-#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
-#else
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
-#endif /* RCC_HSI48_SUPPORT */
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
-                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
-                             ((__HSE__) == RCC_HSE_BYPASS))
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
-                             ((__LSE__) == RCC_LSE_BYPASS))
-#if defined(RCC_CR_HSIOUTEN)
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF)  || ((__HSI__) == RCC_HSI_ON)     || \
-                             ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN)  || \
-                             ((__HSI__) == (RCC_HSI_OUTEN|RCC_HSI_ON)) || ((__HSI__) == (RCC_HSI_OUTEN|RCC_HSI_DIV4)))
-#else
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
-                             ((__HSI__) == RCC_HSI_DIV4))
-#endif /* RCC_CR_HSIOUTEN */
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
-#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
-#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__)  (((__RANGE__) == RCC_MSIRANGE_0) || \
-                                            ((__RANGE__) == RCC_MSIRANGE_1) || \
-                                            ((__RANGE__) == RCC_MSIRANGE_2) || \
-                                            ((__RANGE__) == RCC_MSIRANGE_3) || \
-                                            ((__RANGE__) == RCC_MSIRANGE_4) || \
-                                            ((__RANGE__) == RCC_MSIRANGE_5) || \
-                                            ((__RANGE__) == RCC_MSIRANGE_6))
-#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
-
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
-                             ((__PLL__) == RCC_PLL_ON))
-#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
-                                 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
-
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3)  || ((__MUL__) == RCC_PLL_MUL4)  || \
-                                 ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL8)  || \
-                                 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \
-                                 ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \
-                                 ((__MUL__) == RCC_PLL_MUL48))
-#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
-                               (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
-                               (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
-                               (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \
-                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
-                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
-                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV512))
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
-                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
-                               ((__PCLK__) == RCC_HCLK_DIV16))
-#if defined(RCC_MCO3_SUPPORT)
-#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) || ((__MCO__) == RCC_MCO2) || ((__MCO__) == RCC_MCO3))
-#else
-#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) || ((__MCO__) == RCC_MCO2))
-
-#endif /* RCC_MCO3_SUPPORT */
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
-                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
-                                ((__DIV__) == RCC_MCODIV_16))
-#if defined(RCC_CFGR_MCOSEL_HSI48)
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
-                                      ((__SOURCE__) == RCC_MCO1SOURCE_HSI)  || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
-                                      ((__SOURCE__) == RCC_MCO1SOURCE_HSE)  || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
-                                      ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
-                                      ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
-#else
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
-                                      ((__SOURCE__) == RCC_MCO1SOURCE_HSI)  || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
-                                      ((__SOURCE__) == RCC_MCO1SOURCE_HSE)  || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
-                                      ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
-#endif /* RCC_CFGR_MCOSEL_HSI48 */
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK)   || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)      || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)      || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
-
-/**
-  * @}
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Types RCC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RCC PLL configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PLLState;      /*!< PLLState: The new state of the PLL.
-                              This parameter can be a value of @ref RCC_PLL_Config */
-
-  uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
-                              This parameter must be a value of @ref RCC_PLL_Clock_Source */
-
-  uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
-                              This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
-
-  uint32_t PLLDIV;        /*!< PLLDIV: Division factor for PLL VCO input clock
-                              This parameter must be a value of @ref RCC_PLL_Division_Factor*/
-} RCC_PLLInitTypeDef;
-
-/**
-  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
-  */
-typedef struct
-{
-  uint32_t OscillatorType;        /*!< The oscillators to be configured.
-                                       This parameter can be a value of @ref RCC_Oscillator_Type */
-
-  uint32_t HSEState;              /*!< The new state of the HSE.
-                                       This parameter can be a value of @ref RCC_HSE_Config */
-
-  uint32_t LSEState;              /*!< The new state of the LSE.
-                                       This parameter can be a value of @ref RCC_LSE_Config */
-
-  uint32_t HSIState;              /*!< The new state of the HSI.
-                                       This parameter can be a value of @ref RCC_HSI_Config */
-
-  uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-
-  uint32_t LSIState;              /*!< The new state of the LSI.
-                                       This parameter can be a value of @ref RCC_LSI_Config */
-
-#if defined(RCC_HSI48_SUPPORT)
-  uint32_t HSI48State;            /*!< The new state of the HSI48.
-                                       This parameter can be a value of @ref RCC_HSI48_Config */
-
-#endif /* RCC_HSI48_SUPPORT */
-  uint32_t MSIState;              /*!< The new state of the MSI.
-                                       This parameter can be a value of @ref RCC_MSI_Config */
-
-  uint32_t MSICalibrationValue;   /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-
-  uint32_t MSIClockRange;         /*!< The MSI  frequency  range.
-                                        This parameter can be a value of @ref RCC_MSI_Clock_Range */
-
-  RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */
-
-} RCC_OscInitTypeDef;
-
-/**
-  * @brief  RCC System, AHB and APB busses clock configuration structure definition
-  */
-typedef struct
-{
-  uint32_t ClockType;             /*!< The clock to be configured.
-                                       This parameter can be a value of @ref RCC_System_Clock_Type */
-
-  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
-                                       This parameter can be a value of @ref RCC_System_Clock_Source */
-
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_AHB_Clock_Source */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-} RCC_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
-  * @{
-  */
-
-#define RCC_PLLSOURCE_HSI           RCC_CFGR_PLLSRC_HSI        /*!< HSI clock selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC_HSE        /*!< HSE clock selected as PLL entry clock source */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
-  * @{
-  */
-#define RCC_OSCILLATORTYPE_NONE            (0x00000000U)
-#define RCC_OSCILLATORTYPE_HSE             (0x00000001U)
-#define RCC_OSCILLATORTYPE_HSI             (0x00000002U)
-#define RCC_OSCILLATORTYPE_LSE             (0x00000004U)
-#define RCC_OSCILLATORTYPE_LSI             (0x00000008U)
-#define RCC_OSCILLATORTYPE_MSI             (0x00000010U)
-#if defined(RCC_HSI48_SUPPORT)
-#define RCC_OSCILLATORTYPE_HSI48           (0x00000020U)
-#endif /* RCC_HSI48_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Config HSE Config
-  * @{
-  */
-#define RCC_HSE_OFF                      (0x00000000U)                     /*!< HSE clock deactivation */
-#define RCC_HSE_ON                       RCC_CR_HSEON                               /*!< HSE clock activation */
-#define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Config LSE Config
-  * @{
-  */
-#define RCC_LSE_OFF                      (0x00000000U)                       /*!< LSE clock deactivation */
-#define RCC_LSE_ON                       RCC_CSR_LSEON                                /*!< LSE clock activation */
-#define RCC_LSE_BYPASS                   ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON)) /*!< External clock source for LSE clock */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Config HSI Config
-  * @{
-  */
-#define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */
-#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
-#define RCC_HSI_DIV4                     (RCC_CR_HSIDIVEN | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */
-#if defined(RCC_CR_HSIOUTEN)
-#define RCC_HSI_OUTEN                    RCC_CR_HSIOUTEN                  /*!< HSI_OUTEN clock activation */
-                                                                          /* This value is to be used in combination with RCC_HSI_ON/RCC_HSI_DIV4 */
-#endif /* RCC_CR_HSIOUTEN */
-
-#define RCC_HSICALIBRATION_DEFAULT       (0x10U)         /* Default HSI calibration trimming value */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
-  * @{
-  */
-
-#define RCC_MSIRANGE_0                   RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz  */
-#define RCC_MSIRANGE_1                   RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
-#define RCC_MSIRANGE_2                   RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
-#define RCC_MSIRANGE_3                   RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
-#define RCC_MSIRANGE_4                   RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz   */
-#define RCC_MSIRANGE_5                   RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz   */
-#define RCC_MSIRANGE_6                   RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz   */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Config LSI Config
-  * @{
-  */
-#define RCC_LSI_OFF                      (0x00000000U)   /*!< LSI clock deactivation */
-#define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MSI_Config MSI Config
-  * @{
-  */
-#define RCC_MSI_OFF                      (0x00000000U)
-#define RCC_MSI_ON                       (0x00000001U)
-
-#define RCC_MSICALIBRATION_DEFAULT       (0x00000000U)   /* Default MSI calibration trimming value */
-
-/**
-  * @}
-  */
-
-#if defined(RCC_HSI48_SUPPORT)
-/** @defgroup RCC_HSI48_Config HSI48 Config
-  * @{
-  */
-#define RCC_HSI48_OFF               ((uint8_t)0x00)
-#define RCC_HSI48_ON                ((uint8_t)0x01)
-
-/**
-  * @}
-  */
-#endif /* RCC_HSI48_SUPPORT */
-
-/** @defgroup RCC_PLL_Config PLL Config
-  * @{
-  */
-#define RCC_PLL_NONE                      (0x00000000U)  /*!< PLL is not configured */
-#define RCC_PLL_OFF                       (0x00000001U)  /*!< PLL deactivation */
-#define RCC_PLL_ON                        (0x00000002U)  /*!< PLL activation */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
-  * @{
-  */
-#define RCC_CLOCKTYPE_SYSCLK             (0x00000001U) /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK               (0x00000002U) /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1              (0x00000004U) /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2              (0x00000008U) /*!< PCLK2 to configure */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_MSI             RCC_CFGR_SW_MSI /*!< MSI selected as system clock */
-#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
-#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
-#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_STATUS_MSI      RCC_CFGR_SWS_MSI            /*!< MSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI            /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE            /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL            /*!< PLL used as system clock */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
-  * @{
-  */
-#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
-#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
-#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
-#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
-#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
-#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
-#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
-  * @{
-  */
-#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
-#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
-#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
-#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
-#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
-  * @{
-  */
-#define RCC_RTC_HSE_DIV_2               (0x00000000U) /*!< HSE is divided by 2 for RTC clock  */
-#define RCC_RTC_HSE_DIV_4               RCC_CR_RTCPRE_0       /*!< HSE is divided by 4 for RTC clock  */
-#define RCC_RTC_HSE_DIV_8               RCC_CR_RTCPRE_1       /*!< HSE is divided by 8 for RTC clock  */
-#define RCC_RTC_HSE_DIV_16              RCC_CR_RTCPRE         /*!< HSE is divided by 16 for RTC clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
-  * @{
-  */
-#define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)                 /*!< No clock */
-#define RCC_RTCCLKSOURCE_LSE             RCC_CSR_RTCSEL_LSE                  /*!< LSE oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_LSI             RCC_CSR_RTCSEL_LSI                  /*!< LSI oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIVX        RCC_CSR_RTCSEL_HSE                         /*!< HSE oscillator clock divided by X used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV2        (RCC_RTC_HSE_DIV_2  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 2 used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV4        (RCC_RTC_HSE_DIV_4  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 4 used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV8        (RCC_RTC_HSE_DIV_8  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 8 used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV16       (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 16 used as RTC clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Division_Factor PLL Division Factor
-  * @{
-  */
-
-#define RCC_PLL_DIV2                    RCC_CFGR_PLLDIV2
-#define RCC_PLL_DIV3                    RCC_CFGR_PLLDIV3
-#define RCC_PLL_DIV4                    RCC_CFGR_PLLDIV4
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor
-  * @{
-  */
-
-#define RCC_PLL_MUL3                    RCC_CFGR_PLLMUL3
-#define RCC_PLL_MUL4                    RCC_CFGR_PLLMUL4
-#define RCC_PLL_MUL6                    RCC_CFGR_PLLMUL6
-#define RCC_PLL_MUL8                    RCC_CFGR_PLLMUL8
-#define RCC_PLL_MUL12                   RCC_CFGR_PLLMUL12
-#define RCC_PLL_MUL16                   RCC_CFGR_PLLMUL16
-#define RCC_PLL_MUL24                   RCC_CFGR_PLLMUL24
-#define RCC_PLL_MUL32                   RCC_CFGR_PLLMUL32
-#define RCC_PLL_MUL48                   RCC_CFGR_PLLMUL48
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO_Index MCO Index
-  * @{
-  */
-#define RCC_MCO1                         (0x00000000U)
-#define RCC_MCO2                         (0x00000001U)
-#if defined(RCC_MCO3_SUPPORT)
-#define RCC_MCO3                         (0x00000002U)
-#if defined(RCC_MCO3_AF0_SUPPORT)
-#define MCO3_GPIO_AF                      GPIO_AF0_MCO
-#else
-#define MCO3_GPIO_AF                      GPIO_AF2_MCO
-#endif /* RCC_MCO3_AF0_SUPPORT */
-#endif /* RCC_MCO3_SUPPORT */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
-  * @{
-  */
-#define RCC_MCODIV_1                    RCC_CFGR_MCO_PRE_1
-#define RCC_MCODIV_2                    RCC_CFGR_MCO_PRE_2
-#define RCC_MCODIV_4                    RCC_CFGR_MCO_PRE_4
-#define RCC_MCODIV_8                    RCC_CFGR_MCO_PRE_8
-#define RCC_MCODIV_16                   RCC_CFGR_MCO_PRE_16
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
-  * @{
-  */
-#define RCC_MCO1SOURCE_NOCLOCK           RCC_CFGR_MCO_NOCLOCK
-#define RCC_MCO1SOURCE_SYSCLK            RCC_CFGR_MCO_SYSCLK
-#define RCC_MCO1SOURCE_MSI               RCC_CFGR_MCO_MSI
-#define RCC_MCO1SOURCE_HSI               RCC_CFGR_MCO_HSI
-#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO_LSE
-#define RCC_MCO1SOURCE_LSI               RCC_CFGR_MCO_LSI
-#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO_HSE
-#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO_PLL
-#if defined(RCC_CFGR_MCOSEL_HSI48)
-#define RCC_MCO1SOURCE_HSI48             RCC_CFGR_MCO_HSI48
-#endif /* RCC_CFGR_MCOSEL_HSI48 */
-
-/**
-  * @}
-  */
-/** @defgroup RCC_Interrupt Interrupts
-  * @{
-  */
-#define RCC_IT_LSIRDY                    RCC_CIFR_LSIRDYF   /*!< LSI Ready Interrupt flag */
-#define RCC_IT_LSERDY                    RCC_CIFR_LSERDYF   /*!< LSE Ready Interrupt flag */
-#define RCC_IT_HSIRDY                    RCC_CIFR_HSIRDYF   /*!< HSI Ready Interrupt flag */
-#define RCC_IT_HSERDY                    RCC_CIFR_HSERDYF   /*!< HSE Ready Interrupt flag */
-#define RCC_IT_PLLRDY                    RCC_CIFR_PLLRDYF   /*!< PLL Ready Interrupt flag */
-#define RCC_IT_MSIRDY                    RCC_CIFR_MSIRDYF   /*!< MSI Ready Interrupt flag */
-#define RCC_IT_LSECSS                    RCC_CIFR_CSSLSEF   /*!< LSE Clock Security System Interrupt flag */
-#if defined(RCC_HSECSS_SUPPORT)
-#define RCC_IT_CSS                       RCC_CIFR_CSSHSEF   /*!< Clock Security System Interrupt flag */
-#endif /* RCC_HSECSS_SUPPORT */
-#if defined(RCC_HSI48_SUPPORT)
-#define RCC_IT_HSI48RDY                  RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
-#endif /* RCC_HSI48_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Flag Flags
-  *        Elements values convention: XXXYYYYYb
-  *           - YYYYY  : Flag position in the register
-  *           - XXX  : Register index
-  *                 - 001: CR register
-  *                 - 010: CSR register
-  *                 - 011: CRRCR register (*)
-  * (*)   Applicable only for STM32L052xx, STM32L053xx, (...), STM32L073xx & STM32L082xx
-  * @{
-  */
-/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_Pos))     /*!< Internal High Speed clock ready flag */
-#define RCC_FLAG_HSIDIV                  ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIDIVF_Pos))    /*!< HSI16 divider flag */
-#define RCC_FLAG_MSIRDY                  ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_MSIRDY_Pos))     /*!< MSI clock ready flag */
-#define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_Pos))     /*!< External High Speed clock ready flag */
-#define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_Pos))     /*!< PLL clock ready flag */
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_Pos))   /*!< Internal Low Speed oscillator Ready */
-#define RCC_FLAG_LSERDY                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSERDY_Pos))   /*!< External Low Speed oscillator Ready */
-#define RCC_FLAG_LSECSS                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSECSSD_Pos))  /*!< CSS on LSE failure Detection */
-#define RCC_FLAG_OBLRST                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_Pos))  /*!< Options bytes loading reset flag */
-#define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_Pos))  /*!< PIN reset flag */
-#define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_Pos))  /*!< POR/PDR reset flag */
-#define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_Pos))  /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
-#if defined(RCC_CSR_FWRSTF)
-#define RCC_FLAG_FWRST                   ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_FWRSTF_Pos))   /*!< RCC flag FW reset */
-#endif /* RCC_CSR_FWRSTF */
-/* Flags in the CRRCR register */
-#if defined(RCC_HSI48_SUPPORT)
-#define RCC_FLAG_HSI48RDY                ((uint8_t)((CRRCR_REG_INDEX << 5) | RCC_CRRCR_HSI48RDY_Pos))  /*!< HSI48 clock ready flag */
-#endif /* RCC_HSI48_SUPPORT */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_MIF_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-
-#define __HAL_RCC_DMA1_CLK_DISABLE()          CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
-#define __HAL_RCC_MIF_CLK_DISABLE()           CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
-#define __HAL_RCC_CRC_CLK_DISABLE()           CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
-  * @brief  Enable or disable the IOPORT peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-
-#define __HAL_RCC_GPIOA_CLK_DISABLE()        CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
-#define __HAL_RCC_GPIOB_CLK_DISABLE()        CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
-#define __HAL_RCC_GPIOC_CLK_DISABLE()        CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
-#define __HAL_RCC_GPIOH_CLK_DISABLE()        CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_WWDG_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_PWR_CLK_ENABLE()     SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
-
-#define __HAL_RCC_WWDG_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_PWR_CLK_DISABLE()     CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SYSCFG_CLK_ENABLE()   SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
-#define __HAL_RCC_DBGMCU_CLK_ENABLE()   SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
-
-#define __HAL_RCC_SYSCFG_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
-#define __HAL_RCC_DBGMCU_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the AHB peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U)
-#define __HAL_RCC_MIF_IS_CLK_ENABLED()         (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != 0U)
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != 0U)
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == 0U)
-#define __HAL_RCC_MIF_IS_CLK_DISABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) == 0U)
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == 0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_IOPORT_Peripheral_Clock_Enable_Disable_Status IOPORT Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the IOPORT peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()        (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != 0U)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()        (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != 0U)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()        (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != 0U)
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()        (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != 0U)
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == 0U)
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == 0U)
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == 0U)
-#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) == 0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the APB1 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != 0U)
-#define __HAL_RCC_PWR_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != 0U)
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) == 0U)
-#define __HAL_RCC_PWR_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) == 0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the APB2 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
-#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != 0U)
-#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
-#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) == 0U)
-
-/**
-  * @}
-  */
-
- /** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
-  * @brief  Force or release AHB peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB_FORCE_RESET()     (RCC->AHBRSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_DMA1_FORCE_RESET()    SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
-#define __HAL_RCC_MIF_FORCE_RESET()     SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
-#define __HAL_RCC_CRC_FORCE_RESET()     SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
-
-#define __HAL_RCC_AHB_RELEASE_RESET()     (RCC->AHBRSTR = 0x00000000U)
-#define __HAL_RCC_CRC_RELEASE_RESET()     CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
-#define __HAL_RCC_DMA1_RELEASE_RESET()    CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
-#define __HAL_RCC_MIF_RELEASE_RESET()     CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
-  * @brief  Force or release IOPORT peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_IOP_FORCE_RESET()     (RCC->IOPRSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_GPIOA_FORCE_RESET()   SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_FORCE_RESET()   SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_FORCE_RESET()   SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
-#define __HAL_RCC_GPIOH_FORCE_RESET()   SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
-
-#define __HAL_RCC_IOP_RELEASE_RESET()   (RCC->IOPRSTR = 0x00000000U)
-#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
-#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_WWDG_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_PWR_FORCE_RESET()      SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
-
-#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00000000U)
-#define __HAL_RCC_WWDG_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_PWR_RELEASE_RESET()    CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_DBGMCU_FORCE_RESET()   SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
-#define __HAL_RCC_SYSCFG_FORCE_RESET()   SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
-
-#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00000000U)
-#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
-#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral activated clocks remain enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
-#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
-#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
-
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
-#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
-#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral activated clocks remain enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()    SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()    SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()    SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()    SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral activated clocks remain enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
-
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR,  (RCC_APB1SMENR_WWDGSMEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR,  (RCC_APB1SMENR_PWRSMEN))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral activated clocks remain enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
-#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
-
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR,   (RCC_APB2SMENR_SYSCFGSMEN))
-#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR,   (RCC_APB2SMENR_DBGMCUSMEN))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != 0U)
-#define __HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != 0U)
-#define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != 0U)
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != 0U)
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == 0U)
-#define __HAL_RCC_MIF_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) == 0U)
-#define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == 0U)
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == 0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable_Status IOPORT Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the IOPORT peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != 0U)
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != 0U)
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != 0U)
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != 0U)
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == 0U)
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == 0U)
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == 0U)
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) == 0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != 0U)
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != 0U)
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) == 0U)
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) == 0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
-#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != 0U)
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
-#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) == 0U)
-
-/**
-  * @}
-  */
-/** @defgroup RCC_HSI_Configuration HSI Configuration
-  * @{
-  */
-
-/** @brief  Macro to enable or disable the Internal High Speed oscillator (HSI).
-  * @note     After enabling the HSI, the application software should wait on
-  *           HSIRDY flag to be set indicating that HSI clock is stable and can
-  *           be used to clock the PLL and/or system clock.
-  * @note     HSI can not be stopped if it is used directly or through the PLL
-  *           as system clock. In this case, you have to select another source
-  *           of the system clock then stop the HSI.
-  * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.
-  * @param    __STATE__ specifies the new state of the HSI.
-  *           This parameter can be one of the following values:
-  *            @arg @ref RCC_HSI_OFF turn OFF the HSI oscillator
-  *            @arg @ref RCC_HSI_ON turn ON the HSI oscillator
-  *            @arg @ref RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
-  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.
-  */
-#define __HAL_RCC_HSI_CONFIG(__STATE__) \
-                  MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
-
-/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
-  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
-  *         It is used (enabled by hardware) as system clock source after startup
-  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
-  *         of the HSE used directly or indirectly as system clock (if the Clock
-  *         Security System CSS is enabled).
-  * @note   HSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the HSI.
-  * @note   After enabling the HSI, the application software should wait on HSIRDY
-  *         flag to be set indicating that HSI clock is stable and can be used as
-  *         system clock source.
-  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.
-  */
-#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
-#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
-
-/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal HSI RC.
-  * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
-  *         (default is RCC_HSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between 0 and 0x1F.
-  */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
-          (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_ICSCR_HSITRIM_Pos))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Configuration  LSI Configuration
-  * @{
-  */
-
-/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
-  * @note   After enabling the LSI, the application software should wait on
-  *         LSIRDY flag to be set indicating that LSI clock is stable and can
-  *         be used to clock the IWDG and/or the RTC.
-  */
-#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
-
-/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
-  * @note   LSI can not be disabled if the IWDG is running.
-  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
-  *         clock cycles.
-  */
-#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Configuration HSE Configuration
-  * @{
-  */
-
-/**
-  * @brief  Macro to configure the External High Speed oscillator (HSE).
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
-  *         supported by this macro. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
-  *         software should wait on HSERDY flag to be set indicating that HSE clock
-  *         is stable and can be used to clock the PLL and/or system clock.
-  * @note   HSE state can not be changed if it is used directly or through the
-  *         PLL as system clock. In this case, you have to select another source
-  *         of the system clock then change the HSE state (ex. disable it).
-  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
-  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
-  *         was previously enabled you have to enable it again after calling this
-  *         function.
-  * @param  __STATE__ specifies the new state of the HSE.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
-  *                              6 HSE oscillator clock cycles.
-  *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
-  *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
-  */
-#define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
-                    do{                                                     \
-                      __IO uint32_t tmpreg;                                 \
-                      if ((__STATE__) == RCC_HSE_ON)                        \
-                      {                                                     \
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
-                      }                                                     \
-                      else if ((__STATE__) == RCC_HSE_BYPASS)               \
-                      {                                                     \
-                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
-                      }                                                     \
-                      else                                                  \
-                      {                                                     \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
-                        /* Delay after an RCC peripheral clock */           \
-                        tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON);           \
-                        UNUSED(tmpreg);                                     \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
-                      }                                                     \
-                    }while(0)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Configuration LSE Configuration
-  * @{
-  */
-
-/**
-  * @brief  Macro to configure the External Low Speed oscillator (LSE).
-  * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
-  * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using
-  *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).
-  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
-  *         software should wait on LSERDY flag to be set indicating that LSE clock
-  *         is stable and can be used to clock the RTC.
-  * @param  __STATE__ specifies the new state of the LSE.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
-  *                              6 LSE oscillator clock cycles.
-  *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
-  *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
-  */
-#define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
-                    do{                                                     \
-                      if ((__STATE__) == RCC_LSE_ON)                        \
-                      {                                                     \
-                        SET_BIT(RCC->CSR, RCC_CSR_LSEON);                   \
-                      }                                                     \
-                      else if ((__STATE__) == RCC_LSE_OFF)                  \
-                      {                                                     \
-                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);                 \
-                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);                \
-                      }                                                     \
-                      else if ((__STATE__) == RCC_LSE_BYPASS)               \
-                      {                                                     \
-                        SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);                  \
-                        SET_BIT(RCC->CSR, RCC_CSR_LSEON);                   \
-                      }                                                     \
-                      else                                                  \
-                      {                                                     \
-                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);                 \
-                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);                \
-                      }                                                     \
-                    }while(0)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MSI_Configuration  MSI Configuration
-  * @{
-  */
-
-/** @brief  Macro to enable Internal Multi Speed oscillator (MSI).
-  * @note   After enabling the MSI, the application software should wait on MSIRDY
-  *         flag to be set indicating that MSI clock is stable and can be used as
-  *         system clock source.
-  */
-#define __HAL_RCC_MSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_MSION)
-
-/** @brief  Macro to disable the Internal Multi Speed oscillator (MSI).
-  * @note   The MSI is stopped by hardware when entering STOP and STANDBY modes.
-  *         It is used (enabled by hardware) as system clock source after startup
-  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
-  *         of the HSE used directly or indirectly as system clock (if the Clock
-  *         Security System CSS is enabled).
-  * @note   MSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the MSI.
-  * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
-  *         clock cycles.
-  */
-#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
-
-/** @brief  Macro adjusts Internal Multi Speed oscillator (MSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal MSI RC.
-  *         Refer to the Application Note AN3300 for more details on how to
-  *         calibrate the MSI.
-  * @param  _MSICALIBRATIONVALUE_ specifies the calibration trimming value.
-  *         (default is RCC_MSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between 0 and 0xFF.
-  */
-#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
-          (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << RCC_ICSCR_MSITRIM_Pos))
-
-/* @brief  Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
-  * @note     After restart from Reset or wakeup from STANDBY, the MSI clock is
-  *           around 2.097 MHz. The MSI clock does not change after wake-up from
-  *           STOP mode.
-  * @note    The MSI clock range can be modified on the fly.
-  * @param  _MSIRANGEVALUE_ specifies the MSI Clock range.
-  *   This parameter must be one of the following values:
-  *     @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
-  *     @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
-  *     @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
-  *     @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
-  *     @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
-  *     @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
-  *     @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
-  */
-#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \
-          RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
-
-/** @brief  Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
-  * @retval MSI clock range.
-  *         This parameter must be one of the following values:
-  *     @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
-  *     @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
-  *     @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
-  *     @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
-  *     @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
-  *     @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
-  *     @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
-  */
-#define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Configuration PLL Configuration
-  * @{
-  */
-
-/** @brief Macro to enable the main PLL.
-  * @note   After enabling the main PLL, the application software should wait on
-  *         PLLRDY flag to be set indicating that PLL clock is stable and can
-  *         be used as system clock source.
-  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
-
-/** @brief Macro to disable the main PLL.
-  * @note   The main PLL can not be disabled if it is used as system clock source
-  */
-#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
-
-/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
-  * @note   This function must be used only when the main PLL is disabled.
-  *
-  * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
-  * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_PLL_MUL3   PLLVCO = PLL clock entry x 3
-  *             @arg @ref RCC_PLL_MUL4   PLLVCO = PLL clock entry x 4
-  *             @arg @ref RCC_PLL_MUL6   PLLVCO = PLL clock entry x 6
-  *             @arg @ref RCC_PLL_MUL8   PLLVCO = PLL clock entry x 8
-  *             @arg @ref RCC_PLL_MUL12  PLLVCO = PLL clock entry x 12
-  *             @arg @ref RCC_PLL_MUL16  PLLVCO = PLL clock entry x 16
-  *             @arg @ref RCC_PLL_MUL24  PLLVCO = PLL clock entry x 24
-  *             @arg @ref RCC_PLL_MUL32  PLLVCO = PLL clock entry x 32
-  *             @arg @ref RCC_PLL_MUL48  PLLVCO = PLL clock entry x 48
-  * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in Range 1,
-  *       48 MHz when the product is in Range 2and 24 MHz when the product is in Range 3.
-  *
-  * @param  __PLLDIV__ specifies the division factor for PLL VCO input clock
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2
-  *             @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3
-  *             @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4
-  *
-  */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
-          MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__)))
-
-/** @brief  Get oscillator clock selected as PLL input clock
-  * @retval The clock source used for PLL entry. The returned value can be one
-  *         of the following:
-  *             @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
-  *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
-  */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Get_Clock_source Get Clock source
-  * @{
-  */
-
-/**
-  * @brief  Macro to configure the system clock source.
-  * @param  __SYSCLKSOURCE__ specifies the system clock source.
-  *          This parameter can be one of the following values:
-  *              @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
-  *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
-  *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
-  *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
-  */
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
-                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
-
-/** @brief  Macro to get the clock source used as system clock.
-  * @retval The clock source used as system clock. The returned value can be one
-  *         of the following:
-  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock
-  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
-  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
-  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
-  */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
-  * @{
-  */
-
-/** @brief  Macro to configure the MCO clock.
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK      No clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_SYSCLK       System Clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_HSI          HSI oscillator clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_MSI          MSI oscillator clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_LSI          LSI clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_LSE          LSE clock selected as MCO clock
-  @if STM32L052xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L053xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L062xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L063xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L072xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L073xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L082xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L083xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @endif
-  * @param  __MCODIV__ specifies the MCO clock prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
-  *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
-  *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
-  *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
-  *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
-  */
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
-                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
-
-/**
-  * @}
-  */
-
-  /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
-  * @{
-  */
-
-/** @brief Macro to configure the RTC clock (RTCCLK).
-  * @note   As the RTC clock configuration bits are in the Backup domain and write
-  *         access is denied to this domain after reset, you have to enable write
-  *         access using the Power Backup Access macro before to configure
-  *         the RTC clock source (to be done once after reset).
-  * @note   Once the RTC clock is configured it cannot be changed unless the
-  *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
-  *         a Power On Reset (POR).
-  * @note   RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
-  *
-  * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock
-  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
-  *         work in STOP and STANDBY modes, and can be used as wakeup source.
-  *         However, when the HSE clock is used as RTC clock source, the RTC
-  *         cannot be used in STOP and STANDBY modes.
-  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
-  *         RTC clock source).
-  */
-#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
-            if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)          \
-            {                                                                             \
-              MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE));  \
-            }                                                                             \
-          } while (0)
-
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
-                                      __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__);      \
-                                      RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
-                                    } while (0)
-
-/** @brief Macro to get the RTC clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
-  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
-  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
-  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
-  */
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
-
-/**
-  * @brief   Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
-  *
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref RCC_RTC_HSE_DIV_2  HSE divided by 2 selected as RTC clock
-  *         @arg @ref RCC_RTC_HSE_DIV_4  HSE divided by 4 selected as RTC clock
-  *         @arg @ref RCC_RTC_HSE_DIV_8  HSE divided by 8 selected as RTC clock
-  *         @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock
-  *
-  */
-#define  __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
-
-/** @brief Macro to enable the the RTC clock.
-  * @note   These macros must be used only after the RTC clock source was selected.
-  */
-#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
-
-/** @brief Macro to disable the the RTC clock.
-  * @note  These macros must be used only after the RTC clock source was selected.
-  */
-#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
-
-/** @brief  Macro to force the Backup domain reset.
-  * @note   This function resets the RTC peripheral (including the backup registers)
-  *         and the RTC clock source selection in RCC_CSR register.
-  * @note   The BKPSRAM is not affected by this reset.
-  */
-#define __HAL_RCC_BACKUPRESET_FORCE()  SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
-
-/** @brief  Macros to release the Backup domain reset.
-  */
-#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
-  * @brief macros to manage the specified RCC Flags and interrupts.
-  * @{
-  */
-
-/** @brief Enable RCC interrupt.
-  * @note   The CSS interrupt doesn't have an enable bit; once the CSS is enabled
-  *         and if the HSE clock fails, the CSS interrupt occurs and an NMI is
-  *         automatically generated. The NMI will be executed indefinitely, and
-  *         since NMI has higher priority than any other IRQ (and main program)
-  *         the application will be stacked in the NMI ISR unless the CSS interrupt
-  *         pending bit is cleared.
-  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
-  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
-  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
-  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
-  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
-  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
-  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt
-  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices)
-  */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt.
-  * @note   The CSS interrupt doesn't have an enable bit; once the CSS is enabled
-  *         and if the HSE clock fails, the CSS interrupt occurs and an NMI is
-  *         automatically generated. The NMI will be executed indefinitely, and
-  *         since NMI has higher priority than any other IRQ (and main program)
-  *         the application will be stacked in the NMI ISR unless the CSS interrupt
-  *         pending bit is cleared.
-  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
-  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
-  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
-  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
-  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
-  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
-  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt
-  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices)
-  */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
-
-/** @brief Clear the RCC's interrupt pending bits.
-  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
-  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
-  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
-  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
-  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
-  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
-  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt
-  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices)
-  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
-  */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
-
-/** @brief  Check the RCC's interrupt has occurred or not.
-  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
-  *         This parameter can be one of the following values:
-  *     @arg @ref RCC_IT_LSIRDY LSI ready interrupt
-  *     @arg @ref RCC_IT_LSERDY LSE ready interrupt
-  *     @arg @ref RCC_IT_HSIRDY HSI ready interrupt
-  *     @arg @ref RCC_IT_HSERDY HSE ready interrupt
-  *     @arg @ref RCC_IT_PLLRDY PLL ready interrupt
-  *     @arg @ref RCC_IT_MSIRDY MSI ready interrupt
-  *     @arg @ref RCC_IT_LSECSS LSE CSS interrupt
-  *     @arg @ref RCC_IT_CSS Clock Security System interrupt
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-
-/** @brief Set RMVF bit to clear the reset flags.
-  *         The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
-  *         RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
-  */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
-
-/** @brief  Check RCC flag is set or not.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *     @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
-  *     @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready (not available on all devices)
-  *     @arg @ref RCC_FLAG_HSIDIV HSI16 divider flag
-  *     @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
-  *     @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
-  *     @arg @ref RCC_FLAG_PLLRDY PLL clock ready
-  *     @arg @ref RCC_FLAG_LSECSS LSE oscillator clock CSS detected
-  *     @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
-  *     @arg @ref RCC_FLAG_FWRST Firewall reset
-  *     @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
-  *     @arg @ref RCC_FLAG_OBLRST Option Byte Loader (OBL) reset
-  *     @arg @ref RCC_FLAG_PINRST Pin reset
-  *     @arg @ref RCC_FLAG_PORRST POR/PDR reset
-  *     @arg @ref RCC_FLAG_SFTRST Software reset
-  *     @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
-  *     @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
-  *     @arg @ref RCC_FLAG_LPWRRST Low Power reset
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#if defined(RCC_HSI48_SUPPORT)
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == CSR_REG_INDEX) ? RCC->CSR :RCC->CRRCR)))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0U ) ? 1U : 0U )
-#else
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : RCC->CSR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0U ) ? 1U : 0U )
-#endif /* RCC_HSI48_SUPPORT */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Include RCC HAL Extension module */
-#include "stm32l0xx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-HAL_StatusTypeDef HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group2
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-#if defined(RCC_HSECSS_SUPPORT)
-void              HAL_RCC_EnableCSS(void);
-/* CSS NMI IRQ handler */
-void              HAL_RCC_NMI_IRQHandler(void);
-/* User Callbacks in non blocking mode (IT mode) */
-void              HAL_RCC_CSSCallback(void);
-#endif /* RCC_HSECSS_SUPPORT */
-uint32_t          HAL_RCC_GetSysClockFreq(void);
-uint32_t          HAL_RCC_GetHCLKFreq(void);
-uint32_t          HAL_RCC_GetPCLK1Freq(void);
-uint32_t          HAL_RCC_GetPCLK2Freq(void);
-void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
-void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h
deleted file mode 100644
index f192cc91dd..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h
+++ /dev/null
@@ -1,2021 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_rcc_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_RCC_EX_H
-#define __STM32L0xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCCEx
-  * @{
-  */
-
-/** @addtogroup RCCEx_Private_Constants
- * @{
- */
-
-
-#if defined(CRS)
-/* CRS IT Error Mask */
-#define  RCC_CRS_IT_ERROR_MASK  ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
-
-/* CRS Flag Error Mask */
-#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
-
-#endif /* CRS */
-/**
-  * @}
-  */
-
-/** @addtogroup RCCEx_Private_Macros
-  * @{
-  */
-#if defined (STM32L052xx) || defined(STM32L062xx)
-#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
-                                                 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1))
-#elif defined (STM32L053xx) || defined(STM32L063xx)
-#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
-                                                 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD))
-#elif defined (STM32L072xx) || defined(STM32L082xx)
-#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
-                                                 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_I2C3 ))
-#elif defined (STM32L073xx) || defined(STM32L083xx)
-#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC  |  \
-                                                 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_I2C3 | \
-                                                 RCC_PERIPHCLK_LCD))
-#endif
-
-#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) || \
-    defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4)
-#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                  RCC_PERIPHCLK_I2C1   |  RCC_PERIPHCLK_RTC    | \
-                                                  RCC_PERIPHCLK_LPTIM1))
-#elif defined(STM32L051xx)
-#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
-                                                 RCC_PERIPHCLK_LPTIM1))
-#elif defined(STM32L071xx) || defined(STM32L081xx)
-#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
-                                                 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3))
-#endif
-
-#if defined (RCC_CCIPR_USART1SEL)
-#define IS_RCC_USART1CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
-                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
-                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
-                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
-#endif /* RCC_CCIPR_USART1SEL */
-
-#define IS_RCC_USART2CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
-                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
-                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
-                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
-
-#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
-                                             ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
-                                             ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
-                                             ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
-
-#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
-                                          ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
-                                          ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
-
-#if defined(RCC_CCIPR_I2C3SEL)
-#define IS_RCC_I2C3CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
-                                           ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
-                                           ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
-#endif /* RCC_CCIPR_I2C3SEL */
-
-#if defined(USB)
-#define IS_RCC_USBCLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
-                                          ((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
-#endif /* USB */
-
-#if defined(RNG)
-#define IS_RCC_RNGCLKSOURCE(_SOURCE_)  (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) || \
-                                      ((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
-#endif /* RNG */
-
-#if defined(RCC_CCIPR_HSI48SEL)
-#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) || ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
-#endif /* RCC_CCIPR_HSI48SEL */
-
-#define IS_RCC_LPTIMCLK(__LPTIMCLK_)     (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
-                                          ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI)   || \
-                                          ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI)   || \
-                                          ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
-
-#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
-                                             ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
-
-#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
-                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
-
-#if defined(CRS)
-
-#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
-                                          ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE)  || \
-                                          ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
-#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1)  || ((_DIV_) == RCC_CRS_SYNC_DIV2)  || \
-                                    ((_DIV_) == RCC_CRS_SYNC_DIV4)  || ((_DIV_) == RCC_CRS_SYNC_DIV8)  || \
-                                    ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
-                                    ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
-#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
-                                              ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
-#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU))
-#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU))
-#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU))
-#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
-                                        ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
-#endif /* CRS */
-/**
-  * @}
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RCC extended clocks structure definition
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection;                /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  uint32_t RTCClockSelection;         /*!< specifies the RTC clock source.
-                                       This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
-
-#if defined(LCD)
-
-  uint32_t LCDClockSelection;         /*!< specifies the LCD clock source.
-                                       This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
-
-#endif /* LCD */
-#if defined(RCC_CCIPR_USART1SEL)
-  uint32_t Usart1ClockSelection;   /*!< USART1 clock source
-                                        This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-#endif /* RCC_CCIPR_USART1SEL */
-  uint32_t Usart2ClockSelection;   /*!< USART2 clock source
-                                        This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
-
-  uint32_t Lpuart1ClockSelection;  /*!< LPUART1 clock source
-                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
-
-  uint32_t I2c1ClockSelection;     /*!< I2C1 clock source
-                                        This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
-
-#if defined(RCC_CCIPR_I2C3SEL)
-  uint32_t I2c3ClockSelection;     /*!< I2C3 clock source
-                                        This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
-#endif /* RCC_CCIPR_I2C3SEL */
-  uint32_t LptimClockSelection;    /*!< LPTIM1 clock source
-                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
-#if defined(USB)
-  uint32_t UsbClockSelection;      /*!< Specifies USB and RNG Clock  Selection
-                                        This parameter can be a value of @ref RCCEx_USB_Clock_Source */
-#endif /* USB */
-} RCC_PeriphCLKInitTypeDef;
-
-#if defined (CRS)
-/**
-  * @brief RCC_CRS Init structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
-                                     This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
-
-  uint32_t Source;                /*!< Specifies the SYNC signal source.
-                                     This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
-
-  uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
-                                     This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
-
-  uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
-                                      It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
-                                     This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
-
-  uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
-                                     This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
-
-  uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
-                                     This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
-
-}RCC_CRSInitTypeDef;
-
-/**
-  * @brief RCC_CRS Synchronization structure definition
-  */
-typedef struct
-{
-  uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
-                                     This parameter must be a number between 0 and 0xFFFF */
-
-  uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
-                                     This parameter must be a number between 0 and 0x3F */
-
-  uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter
-                                                                    value latched in the time of the last SYNC event.
-                                    This parameter must be a number between 0 and 0xFFFF */
-
-  uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
-                                                                    frequency error counter latched in the time of the last SYNC event.
-                                                                    It shows whether the actual frequency is below or above the target.
-                                    This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
-
-}RCC_CRSSynchroInfoTypeDef;
-
-#endif /* CRS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
-  * @{
-  */
-
-
-/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
-  * @{
-  */
-#define RCC_EXTI_LINE_LSECSS             (EXTI_IMR_IM19)         /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_Periph_Clock_Selection  RCCEx Periph Clock Selection
-  * @{
-  */
-#if defined(RCC_CCIPR_USART1SEL)
-#define RCC_PERIPHCLK_USART1           (0x00000001U)
-#endif /* RCC_CCIPR_USART1SEL */
-#define RCC_PERIPHCLK_USART2           (0x00000002U)
-#define RCC_PERIPHCLK_LPUART1          (0x00000004U)
-#define RCC_PERIPHCLK_I2C1             (0x00000008U)
-#define RCC_PERIPHCLK_I2C2             (0x00000010U)
-#define RCC_PERIPHCLK_RTC              (0x00000020U)
-#if defined(USB)
-#define RCC_PERIPHCLK_USB              (0x00000040U)
-#endif /* USB */
-#define RCC_PERIPHCLK_LPTIM1           (0x00000080U)
-#if defined(LCD)
-#define RCC_PERIPHCLK_LCD              (0x00000800U)
-#endif /* LCD */
-#if defined(RCC_CCIPR_I2C3SEL)
-#define RCC_PERIPHCLK_I2C3             (0x00000100U)
-#endif /* RCC_CCIPR_I2C3SEL */
-
-/**
-  * @}
-  */
-
-#if defined (RCC_CCIPR_USART1SEL)
-/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
-  * @{
-  */
-#define RCC_USART1CLKSOURCE_PCLK2        (0x00000000U)
-#define RCC_USART1CLKSOURCE_SYSCLK       RCC_CCIPR_USART1SEL_0
-#define RCC_USART1CLKSOURCE_HSI          RCC_CCIPR_USART1SEL_1
-#define RCC_USART1CLKSOURCE_LSE          (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
-/**
-  * @}
-  */
-#endif /* RCC_CCIPR_USART1SEL */
-
-/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
-  * @{
-  */
-#define RCC_USART2CLKSOURCE_PCLK1        (0x00000000U)
-#define RCC_USART2CLKSOURCE_SYSCLK       RCC_CCIPR_USART2SEL_0
-#define RCC_USART2CLKSOURCE_HSI          RCC_CCIPR_USART2SEL_1
-#define RCC_USART2CLKSOURCE_LSE          (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source
-  * @{
-  */
-#define RCC_LPUART1CLKSOURCE_PCLK1        (0x00000000U)
-#define RCC_LPUART1CLKSOURCE_SYSCLK       RCC_CCIPR_LPUART1SEL_0
-#define RCC_LPUART1CLKSOURCE_HSI          RCC_CCIPR_LPUART1SEL_1
-#define RCC_LPUART1CLKSOURCE_LSE          (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
-  * @{
-  */
-#define RCC_I2C1CLKSOURCE_PCLK1          (0x00000000U)
-#define RCC_I2C1CLKSOURCE_SYSCLK         RCC_CCIPR_I2C1SEL_0
-#define RCC_I2C1CLKSOURCE_HSI            RCC_CCIPR_I2C1SEL_1
-/**
-  * @}
-  */
-
-#if defined(RCC_CCIPR_I2C3SEL)
-
-/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
-  * @{
-  */
-#define RCC_I2C3CLKSOURCE_PCLK1          (0x00000000U)
-#define RCC_I2C3CLKSOURCE_SYSCLK         RCC_CCIPR_I2C3SEL_0
-#define RCC_I2C3CLKSOURCE_HSI            RCC_CCIPR_I2C3SEL_1
-/**
-  * @}
-  */
-#endif /* RCC_CCIPR_I2C3SEL */
-
-/** @defgroup RCCEx_TIM_PRescaler_Selection  RCCEx TIM Prescaler Selection
-  * @{
-  */
-#define RCC_TIMPRES_DESACTIVATED        ((uint8_t)0x00)
-#define RCC_TIMPRES_ACTIVATED           ((uint8_t)0x01)
-/**
-  * @}
-  */
-
-#if defined(USB)
-/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
-  * @{
-  */
-#define RCC_USBCLKSOURCE_HSI48           RCC_CCIPR_HSI48SEL
-#define RCC_USBCLKSOURCE_PLL             (0x00000000U)
-/**
-  * @}
-  */
-#endif /* USB */
-
-#if defined(RNG)
-/** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source
-  * @{
-  */
-#define RCC_RNGCLKSOURCE_HSI48           RCC_CCIPR_HSI48SEL
-#define RCC_RNGCLKSOURCE_PLLCLK          (0x00000000U)
-/**
-  * @}
-  */
-#endif /* RNG */
-
-#if defined(RCC_CCIPR_HSI48SEL)
-/** @defgroup RCCEx_HSI48M_Clock_Source RCCEx HSI48M Clock Source
-  * @{
-  */
-#define RCC_FLAG_HSI48                   SYSCFG_CFGR3_VREFINT_RDYF
-
-#define RCC_HSI48M_PLL                   (0x00000000U)
-#define RCC_HSI48M_HSI48                 RCC_CCIPR_HSI48SEL
-
-/**
-  * @}
-  */
-#endif /* RCC_CCIPR_HSI48SEL */
-
-/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
-  * @{
-  */
-#define RCC_LPTIM1CLKSOURCE_PCLK1        (0x00000000U)
-#define RCC_LPTIM1CLKSOURCE_LSI          RCC_CCIPR_LPTIM1SEL_0
-#define RCC_LPTIM1CLKSOURCE_HSI          RCC_CCIPR_LPTIM1SEL_1
-#define RCC_LPTIM1CLKSOURCE_LSE          RCC_CCIPR_LPTIM1SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_StopWakeUp_Clock RCCEx StopWakeUp Clock
-  * @{
-  */
-
-#define RCC_STOP_WAKEUPCLOCK_MSI         (0x00000000U)
-#define RCC_STOP_WAKEUPCLOCK_HSI         RCC_CFGR_STOPWUCK
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_LSEDrive_Configuration RCCEx LSE Drive Configuration
-  * @{
-  */
-
-#define RCC_LSEDRIVE_LOW                 (0x00000000U)
-#define RCC_LSEDRIVE_MEDIUMLOW           RCC_CSR_LSEDRV_0
-#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_CSR_LSEDRV_1
-#define RCC_LSEDRIVE_HIGH                RCC_CSR_LSEDRV
-/**
-  * @}
-  */
-
-#if defined(CRS)
-
-/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
-  * @{
-  */
-#define RCC_CRS_NONE      (0x00000000U)
-#define RCC_CRS_TIMEOUT   (0x00000001U)
-#define RCC_CRS_SYNCOK    (0x00000002U)
-#define RCC_CRS_SYNCWARN  (0x00000004U)
-#define RCC_CRS_SYNCERR   (0x00000008U)
-#define RCC_CRS_SYNCMISS  (0x00000010U)
-#define RCC_CRS_TRIMOVF   (0x00000020U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source
-  * @{
-  */
-#define RCC_CRS_SYNC_SOURCE_GPIO       (0x00000000U) /*!< Synchro Signal source GPIO */
-#define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
-#define RCC_CRS_SYNC_SOURCE_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider
-  * @{
-  */
-#define RCC_CRS_SYNC_DIV1        (0x00000000U)                   /*!< Synchro Signal not divided (default) */
-#define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
-#define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
-#define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
-#define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
-#define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
-#define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
-#define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity
-  * @{
-  */
-#define RCC_CRS_SYNC_POLARITY_RISING   (0x00000000U) /*!< Synchro Active on rising edge (default) */
-#define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value
-  * @{
-  */
-#define RCC_CRS_RELOADVALUE_DEFAULT    (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
-                                                                    to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value
-  * @{
-  */
-#define RCC_CRS_ERRORLIMIT_DEFAULT     (0x00000022U) /*!< Default Frequency error limit */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye
-  * @{
-  */
-#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
-                                                                      The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
-                                                                      corresponds to a higher output frequency */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction
-  * @{
-  */
-#define RCC_CRS_FREQERRORDIR_UP        (0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */
-#define RCC_CRS_FREQERRORDIR_DOWN      CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
-  * @{
-  */
-#define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE           /*!< SYNC event OK */
-#define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE         /*!< SYNC warning */
-#define RCC_CRS_IT_ERR                 CRS_CR_ERRIE              /*!< Error */
-#define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE            /*!< Expected SYNC */
-#define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE              /*!< SYNC error */
-#define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE              /*!< SYNC missed */
-#define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE              /*!< Trimming overflow or underflow */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
-  * @{
-  */
-#define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF           /*!< SYNC event OK flag     */
-#define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF         /*!< SYNC warning flag      */
-#define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF              /*!< Error flag        */
-#define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF            /*!< Expected SYNC flag     */
-#define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR           /*!< SYNC error */
-#define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS          /*!< SYNC missed*/
-#define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF           /*!< Trimming overflow or underflow */
-
-/**
-  * @}
-  */
-
-#endif /* CRS */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
- * @{
- */
-
-/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#if defined(STM32L062xx) || defined(STM32L063xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) || defined(STM32L021xx)
-#define __HAL_RCC_AES_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_AES_CLK_DISABLE()         CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
-
-#define __HAL_RCC_AES_IS_CLK_ENABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) != 0U)
-#define __HAL_RCC_AES_IS_CLK_DISABLED()       (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) == 0U)
-
-#endif /* STM32L062xx || STM32L063xx || STM32L072xx  || STM32L073xx || STM32L081xx || STM32L082xx  || STM32L083xx || STM32L041xx || STM32L021xx */
-
-#if !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-#define __HAL_RCC_TSC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TSC_CLK_DISABLE()            CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
-
-#define __HAL_RCC_TSC_IS_CLK_ENABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != 0U)
-#define __HAL_RCC_TSC_IS_CLK_DISABLED()       (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == 0U)
-
-#define __HAL_RCC_RNG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_RNG_CLK_DISABLE()           CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN))
-
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != 0U)
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()       (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == 0U)
-#endif /* !(STM32L010xB) && !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
-  * @brief  Enable or disable the IOPORT peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(GPIOE)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOE_CLK_DISABLE()        CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIOEEN))
-
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()        (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != 0U)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == 0U)
-
-#endif /* GPIOE */
-#if defined(GPIOD)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_GPIOD_CLK_DISABLE()        CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIODEN))
-
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()        (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != 0U)
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == 0U)
-
-#endif  /* GPIOD */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#if !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-#define __HAL_RCC_USB_CLK_ENABLE()        SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
-#define __HAL_RCC_USB_CLK_DISABLE()       CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
-
-#define __HAL_RCC_USB_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN) != 0U)
-#define __HAL_RCC_USB_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN) == 0U)
-
-#define __HAL_RCC_CRS_CLK_ENABLE()     SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN))
-#define __HAL_RCC_CRS_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR,(RCC_APB1ENR_CRSEN))
-
-#define __HAL_RCC_CRS_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) != 0U)
-#define __HAL_RCC_CRS_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) == 0U)
-
-#endif /* !(STM32L010xB) && !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
-
-
-#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
-#define __HAL_RCC_LCD_CLK_ENABLE()          SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
-#define __HAL_RCC_LCD_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
-
-#define __HAL_RCC_LCD_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN) != 0U)
-#define __HAL_RCC_LCD_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN) == 0U)
-
-#endif /* STM32L053xx || STM32L063xx || STM32L073xx  || STM32L083xx */
-
-#if defined(STM32L053xx) || defined(STM32L063xx) \
- || defined(STM32L052xx) || defined(STM32L062xx) \
- || defined(STM32L051xx)
-#define __HAL_RCC_TIM2_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM6_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_SPI2_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_DAC_CLK_ENABLE()     SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
-
-#define __HAL_RCC_TIM2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_SPI2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_DAC_CLK_DISABLE()     CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
-
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != 0U)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) != 0U)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) != 0U)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U)
-#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != 0U)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != 0U)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != 0U)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) != 0U)
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != 0U)
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == 0U)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) == 0U)
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) == 0U)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U)
-#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == 0U)
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == 0U)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == 0U)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) == 0U)
-#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == 0U)
-
-#endif /* STM32L053xx  || STM32L063xx  ||  */
-       /* STM32L052xx  || STM32L062xx  ||  */
-       /* STM32L051xx                      */
-
-#if defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) || \
-    defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
-#define __HAL_RCC_TIM2_CLK_ENABLE()     SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_USART2_CLK_ENABLE()   SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_LPUART1_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_ENABLE()     SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()   SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
-
-#define __HAL_RCC_TIM2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_USART2_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
-
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != 0U)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U)
-#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != 0U)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != 0U)
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != 0U)
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == 0U)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED()   (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U)
-#define __HAL_RCC_LPUART1_IS_CLK_DISABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == 0U)
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == 0U)
-#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()   (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == 0U)
-
-#endif /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4 || */
-       /* STM32L011xx || STM32L021xx || STM32L031xx || STM32L041xx   */
-
-
-#if defined(STM32L073xx) || defined(STM32L083xx) \
- || defined(STM32L072xx) || defined(STM32L082xx) \
- || defined(STM32L071xx) || defined(STM32L081xx)
-#define __HAL_RCC_TIM2_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM6_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_SPI2_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_USART4_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
-#define __HAL_RCC_USART5_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
-#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_I2C3_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_DAC_CLK_ENABLE()     SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
-
-#define __HAL_RCC_TIM2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_SPI2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_USART4_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
-#define __HAL_RCC_USART5_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
-#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_DAC_CLK_DISABLE()     CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
-
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != 0U)
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) != 0U)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) != 0U)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) != 0U)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) != 0U)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U)
-#define __HAL_RCC_USART4_IS_CLK_ENABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) != 0U)
-#define __HAL_RCC_USART5_IS_CLK_ENABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) != 0U)
-#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != 0U)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != 0U)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != 0U)
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) != 0U)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) != 0U)
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != 0U)
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == 0U)
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) == 0U)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) == 0U)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) == 0U)
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) == 0U)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U)
-#define __HAL_RCC_USART4_IS_CLK_DISABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) == 0U)
-#define __HAL_RCC_USART5_IS_CLK_DISABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) == 0U)
-#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == 0U)
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == 0U)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == 0U)
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) == 0U)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) == 0U)
-#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()  (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == 0U)
-
-#endif /* STM32L071xx  ||  STM32L081xx  || */
-       /* STM32L072xx  ||  STM32L082xx  || */
-       /* STM32L073xx  ||  STM32L083xx     */
-
- /**
-  * @}
-  */
-
-#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) \
- || defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) \
- || defined(STM32L051xx) || defined(STM32L071xx) || defined(STM32L081xx) || defined(STM32L031xx) \
- || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L010xB) \
- || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4)
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM21_CLK_ENABLE()    SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx)
-#define __HAL_RCC_TIM22_CLK_ENABLE()    SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
-#endif
-#define __HAL_RCC_ADC1_CLK_ENABLE()     SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_SPI1_CLK_ENABLE()     SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_USART1_CLK_ENABLE()   SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
-
-#define __HAL_RCC_TIM21_CLK_DISABLE()    CLEAR_BIT(RCC->APB2ENR,  (RCC_APB2ENR_TIM21EN))
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx)
-#define __HAL_RCC_TIM22_CLK_DISABLE()    CLEAR_BIT(RCC->APB2ENR,  (RCC_APB2ENR_TIM22EN))
-#endif
-#define __HAL_RCC_ADC1_CLK_DISABLE()     CLEAR_BIT(RCC->APB2ENR,  (RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_SPI1_CLK_DISABLE()     CLEAR_BIT(RCC->APB2ENR,  (RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_USART1_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR,  (RCC_APB2ENR_USART1EN))
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L010xB) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
-#define __HAL_RCC_FIREWALL_CLK_ENABLE()  SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
-#define __HAL_RCC_FIREWALL_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR,  (RCC_APB2ENR_MIFIEN))
-#endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L010x8) && !(STM32L010xB) && !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */
-
-#define __HAL_RCC_TIM21_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM21EN) != 0U)
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx)
-#define __HAL_RCC_TIM22_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM22EN) != 0U)
-#endif
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN) != 0U)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED()   (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
-
-#define __HAL_RCC_TIM21_IS_CLK_DISABLED()    (READ_BIT(RCC->APB2ENR,  (RCC_APB2ENR_TIM21EN) == 0U)
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx)
-#define __HAL_RCC_TIM22_IS_CLK_DISABLED()    (READ_BIT(RCC->APB2ENR,  (RCC_APB2ENR_TIM22EN) == 0U)
-#endif
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR,  (RCC_APB2ENR_ADC1EN) == 0U)
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR,  (RCC_APB2ENR_SPI1EN) == 0U)
-#define __HAL_RCC_USART1_IS_CLK_DISABLED()   (READ_BIT(RCC->APB2ENR,  (RCC_APB2ENR_USART1EN) == 0U)
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L010xB) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
-#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED()  (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MIFIEN) != 0U)
-#define __HAL_RCC_FIREWALL_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR,  (RCC_APB2ENR_MIFIEN) == 0U)
-#endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L010x8) && !(STM32L010xB) && !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */
-
-#endif /* STM32L053xx  || STM32L063xx  || STM32L073xx  ||  STM32L083xx  || */
-       /* STM32L052xx  || STM32L062xx  || STM32L072xx  ||  STM32L082xx  || */
-       /* STM32L051xx  || STM32L071xx  || STM32L081xx  ||  STM32L031xx  || */
-       /* STM32L041xx  || STM32L011xx  || STM32L021xx  || STM32L010xB   || */
-       /* STM32L010x8  || STM32L010x6  || STM32L010x4                      */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
-  * @brief  Force or release AHB peripheral reset.
-  * @{
-  */
-#if defined(STM32L062xx) || defined(STM32L063xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) || defined(STM32L021xx)
-#define __HAL_RCC_AES_FORCE_RESET()     SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
-#define __HAL_RCC_AES_RELEASE_RESET()   CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
-#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx  || STM32L083xx || STM32L041xx || STM32L021xx*/
-
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L010xB) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-#define __HAL_RCC_TSC_FORCE_RESET()        SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
-#define __HAL_RCC_TSC_RELEASE_RESET()      CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
-#define __HAL_RCC_RNG_FORCE_RESET()        SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()      CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
-#endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L010x8) && !(STM32L010xB) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
-  * @brief  Force or release IOPORT peripheral reset.
-  * @{
-  */
-#if defined(STM32L073xx) || defined(STM32L083xx) \
- || defined(STM32L072xx) || defined(STM32L082xx) \
- || defined(STM32L071xx) || defined(STM32L081xx) \
- || defined(STM32L010xB)
-#define __HAL_RCC_GPIOE_FORCE_RESET()   SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOERST))
-
-#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIOERST))
-
-#endif /* STM32L071xx  ||  STM32L081xx  || */
-       /* STM32L072xx  ||  STM32L082xx  || */
-       /* STM32L073xx  ||  STM32L083xx  || */
-       /* STM32L010xB                      */
-#if !defined(STM32L010x4) && !defined(STM32L010x6) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
-#define __HAL_RCC_GPIOD_FORCE_RESET()   SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIODRST))
-#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIODRST))
-#endif  /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-
-#if defined(STM32L053xx) || defined(STM32L063xx) \
- || defined(STM32L052xx) || defined(STM32L062xx) \
- || defined(STM32L051xx)
-#define __HAL_RCC_TIM2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM6_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_LPTIM1_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_USART2_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_LPUART1_FORCE_RESET()  SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_SPI2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_DAC_FORCE_RESET()      SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_LPTIM1_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_USART2_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_LPUART1_RELEASE_RESET()  CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_SPI2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
-#endif /* STM32L053xx  || STM32L063xx  || */
-       /* STM32L052xx  || STM32L062xx  || */
-       /* STM32L051xx                     */
-#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) || \
-    defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4)
-#define __HAL_RCC_TIM2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_LPTIM1_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_USART2_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_LPUART1_FORCE_RESET()  SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_LPTIM1_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_USART2_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_LPUART1_RELEASE_RESET()  CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
-#endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx || */
-       /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4    */
-
-#if defined(STM32L073xx) || defined(STM32L083xx) \
- || defined(STM32L072xx) || defined(STM32L082xx) \
- || defined(STM32L071xx) || defined(STM32L081xx)
-#define __HAL_RCC_TIM2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM6_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_LPTIM1_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_USART2_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART4_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
-#define __HAL_RCC_USART5_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
-#define __HAL_RCC_LPUART1_FORCE_RESET()  SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_SPI2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_DAC_FORCE_RESET()      SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_LPTIM1_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_USART2_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART4_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
-#define __HAL_RCC_USART5_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
-#define __HAL_RCC_LPUART1_RELEASE_RESET()  CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_SPI2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
-#endif /* STM32L071xx  ||  STM32L081xx  || */
-       /* STM32L072xx  ||  STM32L082xx  || */
-       /* STM32L073xx  ||  STM32L083xx  || */
-
-#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && \
-    !defined(STM32L051xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
-    !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4)
-#define __HAL_RCC_USB_FORCE_RESET()        SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
-#define __HAL_RCC_USB_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
-#define __HAL_RCC_CRS_FORCE_RESET()        SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_CRSRST))
-#define __HAL_RCC_CRS_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR,(RCC_APB1RSTR_CRSRST))
-#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && */
-       /* !(STM32L051xx) && !(STM32L071xx) && !(STM32L081xx) && !(STM32L010xB) && */
-       /* !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) && */
-
-#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
-#define __HAL_RCC_LCD_FORCE_RESET()           SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
-#define __HAL_RCC_LCD_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
-#endif /* STM32L053xx || STM32L063xx || STM32L073xx  || STM32L083xx */
-
-/**
-  * @}
-  */
-
-#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) \
- || defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) \
- || defined(STM32L051xx) || defined(STM32L071xx) || defined(STM32L081xx)
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_USART1_FORCE_RESET()     SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_ADC1_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
-#define __HAL_RCC_SPI1_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_TIM21_FORCE_RESET()      SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
-#define __HAL_RCC_TIM22_FORCE_RESET()      SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
-
-#define __HAL_RCC_USART1_RELEASE_RESET()     CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_ADC1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
-#define __HAL_RCC_SPI1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_TIM21_RELEASE_RESET()      CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
-#define __HAL_RCC_TIM22_RELEASE_RESET()      CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
-
-#endif /* STM32L051xx  || STM32L071xx  ||  STM32L081xx ||  STM32L052xx  ||    */
-       /* STM32L062xx  || STM32L072xx  ||  STM32L082xx ||  STM32L053xx  ||    */
-       /* STM32L063xx  || STM32L073xx  ||  STM32L083xx                        */
-
-#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) || \
-    defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4)
-#define __HAL_RCC_ADC1_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
-#define __HAL_RCC_SPI1_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_TIM21_FORCE_RESET()      SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx)
-#define __HAL_RCC_TIM22_FORCE_RESET()      SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
-#endif
-#define __HAL_RCC_ADC1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
-#define __HAL_RCC_SPI1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_TIM21_RELEASE_RESET()      CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx)
-#define __HAL_RCC_TIM22_RELEASE_RESET()      CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
-#endif
-#endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx || */
-       /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4    */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && \
-    !defined(STM32L051xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && !defined(STM32L010xB) && \
-    !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4)
-#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE()           SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()           SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
-#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE()          CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()          CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
-
-#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) != 0U)
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) != 0U)
-#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) == 0U)
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) == 0U)
-#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && */
-       /* !(STM32L051xx) && !(STM32L071xx) && !(STM32L081xx) &&!(STM32L010xB)  && */
-       /* !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) && */
-
-#if defined(STM32L062xx) || defined(STM32L063xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx)
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()          SET_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()         CLEAR_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
-
-#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->AHBLPENR, RCC_AHBSMENR_CRYPSMEN) != 0U)
-#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->AHBLPENR, RCC_AHBSMENR_CRYPSMEN) == 0U)
-#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx || STM32L041xx */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(STM32L073xx) || defined(STM32L083xx) \
- || defined(STM32L072xx) || defined(STM32L082xx) \
- || defined(STM32L071xx) || defined(STM32L081xx) \
- || defined(STM32L010xB)
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()         SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOESMEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()        CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIOESMEN))
-
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()        (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) != 0U)
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()       (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == 0U)
-#endif /* STM32L071xx  ||  STM32L081xx  || */
-       /* STM32L072xx  ||  STM32L082xx  || */
-       /* STM32L073xx  ||  STM32L083xx  || */
-       /* STM32L010xB                      */
-#if !defined(STM32L010x4) && !defined(STM32L010x6) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIODSMEN))
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIODSMEN))
-
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()        (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) != 0U)
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()       (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == 0U)
-#endif  /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#if defined(STM32L053xx) || defined(STM32L063xx) \
- || defined(STM32L052xx) || defined(STM32L062xx) \
- || defined(STM32L051xx)
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
-
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != 0U)
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) != 0U)
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) != 0U)
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != 0U)
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != 0U)
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != 0U)
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) != 0U)
-#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) != 0U)
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != 0U)
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == 0U)
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) == 0U)
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) == 0U)
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == 0U)
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == 0U)
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == 0U)
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) == 0U)
-#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) == 0U)
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == 0U)
-#endif /* STM32L053xx  ||  STM32L063xx || */
-       /* STM32L052xx  || STM32L062xx  || */
-       /* STM32L051xx                     */
-
-#if defined(STM32L073xx) || defined(STM32L083xx) \
- || defined(STM32L072xx) || defined(STM32L082xx) \
- || defined(STM32L071xx) || defined(STM32L081xx)
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
-#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
-#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
-
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != 0U)
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) != 0U)
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) != 0U)
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) != 0U)
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) != 0U)
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != 0U)
-#define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) != 0U)
-#define __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) != 0U)
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != 0U)
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != 0U)
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) != 0U)
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) != 0U)
-#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) != 0U)
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != 0U)
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == 0U)
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) == 0U)
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) == 0U)
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) == 0U)
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) == 0U)
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == 0U)
-#define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) == 0U)
-#define __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) == 0U)
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == 0U)
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == 0U)
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) == 0U)
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) == 0U)
-#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) == 0U)
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == 0U)
-#endif /*  STM32L071xx  ||  STM32L081xx  || */
-       /*  STM32L072xx  ||  STM32L082xx  || */
-       /*  STM32L073xx  ||  STM32L083xx     */
-
-#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) || \
-    defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4)
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
-
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != 0U)
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != 0U)
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != 0U)
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != 0U)
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != 0U)
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == 0U)
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == 0U)
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == 0U)
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == 0U)
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == 0U)
-
-#endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx */
-       /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4 */
-
-#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && \
-    !defined(STM32L051xx) && !defined(STM32L071xx) && !defined(STM32L081xx)  && \
-    !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4)
-#define __HAL_RCC_USB_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
-#define __HAL_RCC_USB_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
-#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
-#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
-
-#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED()        (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USBSMEN) != 0U)
-#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED()       (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USBSMEN) == 0U)
-#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()        (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_CRSSMEN) != 0U)
-#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()       (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_CRSSMEN) == 0U)
-#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && */
-       /* !(STM32L051xx) && !(STM32L071xx) && !(STM32L081xx) && !(STM32L010xB) && */
-       /* !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4)                  */
-
-#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
-#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
-#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
-
-#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED()        (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LCDSMEN) != 0U)
-#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED()       (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LCDSMEN) == 0U)
-#endif /* STM32L053xx || STM32L063xx || STM32L073xx  || STM32L083xx */
-
-/**
-  * @}
-  */
-
-#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) \
- || defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) \
- || defined(STM32L051xx) || defined(STM32L071xx) || defined(STM32L081xx) || defined(STM32L031xx) \
- || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L010xB) \
- || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4)
-
-/** @defgroup RCCEx_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx)
-#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
-#endif
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
-
-#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_TIM21SMEN))
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx)
-#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_TIM22SMEN))
-#endif
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_ADC1SMEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_SPI1SMEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_USART1SMEN))
-
-#define __HAL_RCC_TIM21_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM21SMEN) != 0U)
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx)
-#define __HAL_RCC_TIM22_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM22SMEN) != 0U)
-#endif
-#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADC1SMEN) != 0U)
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
-
-#define __HAL_RCC_TIM21_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_TIM21SMEN) == 0U)
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx)
-#define __HAL_RCC_TIM22_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_TIM22SMEN) == 0U)
-#endif
-#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_ADC1SMEN) == 0U)
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_SPI1SMEN) == 0U)
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_USART1SMEN) == 0U)
-
-/**
-  * @}
-  */
-
-#endif /* STM32L053xx  || STM32L063xx  ||  STM32L073xx  ||  STM32L083xx  || */
-       /* STM32L052xx  || STM32L062xx  ||  STM32L072xx  ||  STM32L082xx  || */
-       /* STM32L051xx  || STM32L071xx  ||  STM32L081xx  ||  STM32L031xx  || */
-       /* STM32L041xx  || STM32L011xx  ||  STM32L021xx  ||  STM32L010xB  || */
-       /* STM32L010x8  || STM32L010x6  ||  STM32L010x4                      */
-
-
-/**
-  * @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
-  * @retval None
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
-  * @retval None
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Enable event on RCC LSE CSS EXTI Line 19.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Disable event on RCC LSE CSS EXTI Line 19.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
-
-
-/**
-  * @brief  RCC LSE CSS EXTI line configuration: set falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
-
-
-/**
-  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
-
-
-/**
-  * @brief  RCC LSE CSS EXTI line configuration: set rising edge trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief  RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
-  do {                                                      \
-    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
-    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
-  do {                                                       \
-    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
-    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
-  * @retval EXTI RCC LSE CSS Line Status.
-  */
-#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
-
-/**
-  * @brief Clear the RCC LSE CSS EXTI flag.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
-
-/**
-  * @brief Generate a Software interrupt on selected EXTI line.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
-
-
-#if defined(LCD)
-
-/** @defgroup RCCEx_LCD_Configuration LCD Configuration
-  * @brief  Macros to configure clock source of LCD peripherals.
-  * @{
-  */
-
-/** @brief Macro to configures LCD clock (LCDCLK).
-  *  @note   LCD and RTC use the same configuration
-  *  @note   LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
-  *          LCD clock source.
-  *
-  *  @param  __LCD_CLKSOURCE__ specifies the LCD clock source.
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
-  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
-  */
-#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
-
-/** @brief Macro to get the LCD clock source.
-  */
-#define __HAL_RCC_GET_LCD_SOURCE()              __HAL_RCC_GET_RTC_SOURCE()
-
-/** @brief Macro to get the LCD clock pre-scaler.
-  */
-#define  __HAL_RCC_GET_LCD_HSE_PRESCALER()      __HAL_RCC_GET_RTC_HSE_PRESCALER()
-
-/**
-  * @}
-  */
-
-#endif /* LCD */
-
-/** @brief Macro to configure the I2C1 clock (I2C1CLK).
-  *
-  * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
-  *            @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
-  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
-  */
-#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
-
-/** @brief  Macro to get the I2C1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
-  *            @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
-  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
-  */
-#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
-
-#if defined(RCC_CCIPR_I2C3SEL)
-/** @brief Macro to configure the I2C3 clock (I2C3CLK).
-  *
-  * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
-  *            @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
-  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
-  */
-#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
-
-/** @brief  Macro to get the I2C3 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
-  *            @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
-  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
-  */
-#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
-
-#endif /* RCC_CCIPR_I2C3SEL */
-
-#if defined (RCC_CCIPR_USART1SEL)
-/** @brief Macro to configure the USART1 clock (USART1CLK).
-  *
-  * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
-  */
-#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
-
-/** @brief  Macro to get the USART1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
-  */
-#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
-#endif /* RCC_CCIPR_USART1SEL */
-
-/** @brief Macro to configure the USART2 clock (USART2CLK).
-  *
-  * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
-  */
-#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
-
-/** @brief  Macro to get the USART2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
-  */
-#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
-
-/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
-  *
-  * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
-  */
-#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
-
-/** @brief  Macro to get the LPUART1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
-  */
-#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
-
-/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
-  *
-  * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI  selected as LPTIM1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  LSI  selected as LPTIM1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE  selected as LPTIM1 clock
-  */
-#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
-
-/** @brief  Macro to get the LPTIM1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPUART1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  System Clock selected as LPUART1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPUART1 clock
-  */
-#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
-
-#if defined(USB)
-/** @brief  Macro to configure the USB clock (USBCLK).
-  * @param  __USB_CLKSOURCE__ specifies the USB clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as USB clock
-  *            @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
-  */
-#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USB_CLKSOURCE__))
-
-/** @brief  Macro to get the USB clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as USB clock
-  *            @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
-  */
-#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
-#endif /* USB */
-
-#if defined(RNG)
-/** @brief  Macro to configure the RNG clock (RNGCLK).
-  * @param  __RNG_CLKSOURCE__ specifies the USB clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_PLLCLK PLL Clock selected as RNG clock
-  */
-#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNG_CLKSOURCE__))
-
-/** @brief  Macro to get the RNG clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_PLLCLK PLL Clock selected as RNG clock
-  */
-#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
-#endif /* RNG */
-
-#if defined(RCC_CCIPR_HSI48SEL)
-/** @brief Macro to select the HSI48M clock source
-  * @note   This macro can be replaced by either __HAL_RCC_RNG_CONFIG or
-  *         __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources.
-  *
-  * @param  __HSI48M_CLKSOURCE__ specifies the HSI48M clock source dedicated for
-  *          USB an RNG peripherals.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_HSI48M_PLL A dedicated 48MHZ PLL output.
-  *            @arg @ref RCC_HSI48M_HSI48 48MHZ issued from internal HSI48 oscillator.
-  */
-#define __HAL_RCC_HSI48M_CONFIG(__HSI48M_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48M_CLKSOURCE__))
-
-/** @brief  Macro to get the HSI48M clock source.
-  * @note   This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or
-  *         __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources.
-  * @retval The clock source can be one of the following values:
-  *           @arg @ref RCC_HSI48M_PLL A dedicated 48MHZ PLL output.
-  *            @arg @ref RCC_HSI48M_HSI48 48MHZ issued from internal HSI48 oscillator.
-  */
-#define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
-#endif /* RCC_CCIPR_HSI48SEL */
-
-/**
-  * @brief    Macro to enable the force of the Internal High Speed oscillator (HSI)
-  *           in STOP mode to be quickly available as kernel clock for USART and I2C.
-  * @note     The Enable of this function has not effect on the HSION bit.
-  */
-#define __HAL_RCC_HSISTOP_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSIKERON)
-
-/**
-  * @brief    Macro to disable the force of the Internal High Speed oscillator (HSI)
-  *           in STOP mode to be quickly available as kernel clock for USART and I2C.
-  * @retval None
-  */
-#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
-
-/**
-  * @brief  Macro to configures the External Low Speed oscillator (LSE) drive capability.
-  * @param  __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
-  *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
-  *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
-  *            @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
-  * @retval None
-  */
-#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->CSR,\
-        RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
-
-/**
-  * @brief  Macro to configures the wake up from stop clock.
-  * @param  __RCC_STOPWUCLK__ specifies the clock source used after wake up from stop
-  *   This parameter can be one of the following values:
-  *     @arg @ref RCC_STOP_WAKEUPCLOCK_MSI    MSI selected as system clock source
-  *     @arg @ref RCC_STOP_WAKEUPCLOCK_HSI    HSI selected as system clock source
-  * @retval None
-  */
-#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
-        RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
-
-#if defined(CRS)
-/**
-  * @brief  Enables the specified CRS interrupts.
-  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
-  *          This parameter can be any combination of the following values:
-  *              @arg @ref RCC_CRS_IT_SYNCOK
-  *              @arg @ref RCC_CRS_IT_SYNCWARN
-  *              @arg @ref RCC_CRS_IT_ERR
-  *              @arg @ref RCC_CRS_IT_ESYNC
-  * @retval None
-  */
-#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
-
-/**
-  * @brief  Disables the specified CRS interrupts.
-  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
-  *          This parameter can be any combination of the following values:
-  *              @arg @ref RCC_CRS_IT_SYNCOK
-  *              @arg @ref RCC_CRS_IT_SYNCWARN
-  *              @arg @ref RCC_CRS_IT_ERR
-  *              @arg @ref RCC_CRS_IT_ESYNC
-  * @retval None
-  */
-#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR,(__INTERRUPT__))
-
-/** @brief  Check the CRS interrupt has occurred or not.
-  * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
-  *         This parameter can be one of the following values:
-  *              @arg @ref RCC_CRS_IT_SYNCOK
-  *              @arg @ref RCC_CRS_IT_SYNCWARN
-  *              @arg @ref RCC_CRS_IT_ERR
-  *              @arg @ref RCC_CRS_IT_ESYNC
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)     ((CRS->CR & (__INTERRUPT__))? SET : RESET)
-
-/** @brief  Clear the CRS interrupt pending bits
-  *         bits to clear the selected interrupt pending bits.
-  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
-  *         This parameter can be any combination of the following values:
-  *              @arg @ref RCC_CRS_IT_SYNCOK
-  *              @arg @ref RCC_CRS_IT_SYNCWARN
-  *              @arg @ref RCC_CRS_IT_ERR
-  *              @arg @ref RCC_CRS_IT_ESYNC
-  *              @arg @ref RCC_CRS_IT_TRIMOVF
-  *              @arg @ref RCC_CRS_IT_SYNCERR
-  *              @arg @ref RCC_CRS_IT_SYNCMISS
-  */
-#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
-                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
-                                                 { \
-                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
-                                                 } \
-                                                 else \
-                                                 { \
-                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
-                                                 } \
-                                               } while(0)
-
-/**
-  * @brief  Checks whether the specified CRS flag is set or not.
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be one of the following values:
-  *              @arg @ref RCC_CRS_FLAG_SYNCOK
-  *              @arg @ref RCC_CRS_FLAG_SYNCWARN
-  *              @arg @ref RCC_CRS_FLAG_ERR
-  *              @arg @ref RCC_CRS_FLAG_ESYNC
-  *              @arg @ref RCC_CRS_FLAG_TRIMOVF
-  *              @arg @ref RCC_CRS_FLAG_SYNCERR
-  *              @arg @ref RCC_CRS_FLAG_SYNCMISS
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  ((CRS->ISR & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clears the CRS specified FLAG.
-  * @param __FLAG__ specifies the flag to clear.
-  *          This parameter can be one of the following values:
-  *              @arg @ref RCC_CRS_FLAG_SYNCOK
-  *              @arg @ref RCC_CRS_FLAG_SYNCWARN
-  *              @arg @ref RCC_CRS_FLAG_ERR
-  *              @arg @ref RCC_CRS_FLAG_ESYNC
-  *              @arg @ref RCC_CRS_FLAG_TRIMOVF
-  *              @arg @ref RCC_CRS_FLAG_SYNCERR
-  *              @arg @ref RCC_CRS_FLAG_SYNCMISS
-  * @retval None
-  */
-#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
-                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
-                                                 { \
-                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
-                                                 } \
-                                                 else \
-                                                 { \
-                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \
-                                                 } \
-                                               } while(0)
-
-/**
-  * @brief  Enables the oscillator clock for frequency error counter.
-  * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
-  * @retval None
-  */
-#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
-
-/**
-  * @brief  Disables the oscillator clock for frequency error counter.
-  * @retval None
-  */
-#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE()  CLEAR_BIT(CRS->CR, CRS_CR_CEN)
-
-/**
-  * @brief  Enables the automatic hardware adjustment of TRIM bits.
-  * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
-  * @retval None
-  */
-#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
-
-/**
-  * @brief  Enables or disables the automatic hardware adjustment of TRIM bits.
-  * @retval None
-  */
-#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()  CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
-
-/**
-  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
-  * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency
-  *             of the synchronization source after prescaling. It is then decreased by one in order to
-  *             reach the expected synchronization on the zero value. The formula is the following:
-  *             RELOAD = (fTARGET / fSYNC) -1
-  * @param  __FTARGET__ Target frequency (value in Hz)
-  * @param  __FSYNC__   Synchronization signal frequency (value in Hz)
-  * @retval None
-  */
-#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1)
-
-#endif /* CRS */
-
-
-#if defined(RCC_CR_HSIOUTEN)
-/** @brief  Enable he HSI OUT .
-  * @note   After reset, the HSI output is not available
-  */
-
-#define __HAL_RCC_HSI_OUT_ENABLE()   SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)
-
-/** @brief  Disable the HSI OUT .
-  * @note   After reset, the HSI output is not available
-  */
-
-#define __HAL_RCC_HSI_OUT_DISABLE()  CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)
-
-#endif /* RCC_CR_HSIOUTEN */
-
-#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)\
-     || defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx)
-
-/**
-  * @brief  Enable the Internal High Speed oscillator for USB (HSI48).
-  * @note   After enabling the HSI48, the application software should wait on
-  *         HSI48RDY flag to be set indicating that HSI48 clock is stable and can
-  *         be used to clock the USB.
-  * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_HSI48_ENABLE()  do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);            \
-                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);       \
-                                       SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);  \
-                                  } while (0)
-/**
-  * @brief  Disable the Internal High Speed oscillator for USB (HSI48).
-  */
-#define __HAL_RCC_HSI48_DISABLE()  do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);   \
-                                        CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);  \
-                                   } while (0)
-
-/** @brief  Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_HSI48_ON  HSI48 enabled
-  *            @arg @ref RCC_HSI48_OFF HSI48 disabled
-  */
-#define __HAL_RCC_GET_HSI48_STATE() \
-                  (((uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)) != 0U) ? RCC_HSI48_ON : RCC_HSI48_OFF)
-
-/** @brief  Enable or disable the HSI48M DIV6 OUT .
-  * @note   After reset, the HSI48Mhz (divided by 6) output is not available
-  */
-
-#define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE()   SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
-#define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE()  CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
-
-#endif /* STM32L071xx  ||  STM32L081xx  || */
-       /* STM32L072xx  ||  STM32L082xx  || */
-       /* STM32L073xx  ||  STM32L083xx     */
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
-
-void              HAL_RCCEx_EnableLSECSS(void);
-void              HAL_RCCEx_DisableLSECSS(void);
-void              HAL_RCCEx_EnableLSECSS_IT(void);
-void              HAL_RCCEx_LSECSS_IRQHandler(void);
-void              HAL_RCCEx_LSECSS_Callback(void);
-
-
-#if defined(SYSCFG_CFGR3_ENREF_HSI48)
-void HAL_RCCEx_EnableHSI48_VREFINT(void);
-void HAL_RCCEx_DisableHSI48_VREFINT(void);
-#endif /* SYSCFG_CFGR3_ENREF_HSI48 */
-
-/**
-  * @}
-  */
-
-#if defined(CRS)
-
-/** @addtogroup RCCEx_Exported_Functions_Group3
-  * @{
-  */
-
-void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
-void              HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
-void              HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
-uint32_t          HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
-void              HAL_RCCEx_CRS_IRQHandler(void);
-void              HAL_RCCEx_CRS_SyncOkCallback(void);
-void              HAL_RCCEx_CRS_SyncWarnCallback(void);
-void              HAL_RCCEx_CRS_ExpectedSyncCallback(void);
-void              HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
-
-/**
-  * @}
-  */
-
-#endif /* CRS */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rng.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rng.h
deleted file mode 100644
index 4de9dc5e53..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rng.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_rng.h
-  * @author  MCD Application Team
-  * @brief   Header file of RNG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_RNG_H
-#define STM32L0xx_HAL_RNG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#if defined (RNG)
-
-/** @defgroup RNG RNG
-  * @brief RNG HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Types RNG Exported Types
-  * @{
-  */
-
-/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
-  * @{
-  */
-typedef enum
-{
-  HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
-  HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
-  HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */
-  HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
-  HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
-
-} HAL_RNG_StateTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
-  * @{
-  */
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-typedef struct  __RNG_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-{
-  RNG_TypeDef                 *Instance;    /*!< Register base address   */
-
-  HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
-
-  __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
-
-  __IO  uint32_t              ErrorCode;    /*!< RNG Error code          */
-
-  uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
-
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-  void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit);  /*!< RNG Data Ready Callback    */
-  void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng);                            /*!< RNG Error Callback         */
-
-  void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng);                          /*!< RNG Msp Init callback      */
-  void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng);                        /*!< RNG Msp DeInit callback    */
-#endif  /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-} RNG_HandleTypeDef;
-
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL RNG Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_RNG_ERROR_CB_ID                   = 0x00U,     /*!< RNG Error Callback ID          */
-
-  HAL_RNG_MSPINIT_CB_ID                 = 0x01U,     /*!< RNG MspInit callback ID        */
-  HAL_RNG_MSPDEINIT_CB_ID               = 0x02U      /*!< RNG MspDeInit callback ID      */
-
-} HAL_RNG_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL RNG Callback pointer definition
-  */
-typedef  void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng);                                  /*!< pointer to a common RNG callback function */
-typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit);   /*!< pointer to an RNG Data Ready specific callback function */
-
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Constants RNG Exported Constants
-  * @{
-  */
-
-/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
-  * @{
-  */
-#define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
-#define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
-#define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
-  * @{
-  */
-#define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
-#define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
-#define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Error_Definition   RNG Error Definition
-  * @{
-  */
-#define  HAL_RNG_ERROR_NONE             0x00000000U    /*!< No error          */
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-#define  HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U    /*!< Invalid Callback error  */
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-#define  HAL_RNG_ERROR_TIMEOUT          0x00000002U    /*!< Timeout error     */
-#define  HAL_RNG_ERROR_BUSY             0x00000004U    /*!< Busy error        */
-#define  HAL_RNG_ERROR_SEED             0x00000008U    /*!< Seed error        */
-#define  HAL_RNG_ERROR_CLOCK            0x00000010U    /*!< Clock error       */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RNG_Exported_Macros RNG Exported Macros
-  * @{
-  */
-
-/** @brief Reset RNG handle state
-  * @param  __HANDLE__ RNG Handle
-  * @retval None
-  */
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
-                                                       (__HANDLE__)->MspInitCallback = NULL;            \
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                    } while(0U)
-#else
-#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Enables the RNG peripheral.
-  * @param  __HANDLE__ RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
-
-/**
-  * @brief  Disables the RNG peripheral.
-  * @param  __HANDLE__ RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
-
-/**
-  * @brief  Check the selected RNG flag status.
-  * @param  __HANDLE__ RNG Handle
-  * @param  __FLAG__ RNG flag
-  *          This parameter can be one of the following values:
-  *            @arg RNG_FLAG_DRDY:  Data ready
-  *            @arg RNG_FLAG_CECS:  Clock error current status
-  *            @arg RNG_FLAG_SECS:  Seed error current status
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clears the selected RNG flag status.
-  * @param  __HANDLE__ RNG handle
-  * @param  __FLAG__ RNG flag to clear
-  * @note   WARNING: This is a dummy macro for HAL code alignment,
-  *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
-  * @retval None
-  */
-#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
-
-/**
-  * @brief  Enables the RNG interrupts.
-  * @param  __HANDLE__ RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
-
-/**
-  * @brief  Disables the RNG interrupts.
-  * @param  __HANDLE__ RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
-
-/**
-  * @brief  Checks whether the specified RNG interrupt has occurred or not.
-  * @param  __HANDLE__ RNG Handle
-  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg RNG_IT_DRDY: Data ready interrupt
-  *            @arg RNG_IT_CEI: Clock error interrupt
-  *            @arg RNG_IT_SEI: Seed error interrupt
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Clear the RNG interrupt status flags.
-  * @param  __HANDLE__ RNG Handle
-  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to clear.
-  *          This parameter can be one of the following values:
-  *            @arg RNG_IT_CEI: Clock error interrupt
-  *            @arg RNG_IT_SEI: Seed error interrupt
-  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
-  * @retval None
-  */
-#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Functions RNG Exported Functions
-  * @{
-  */
-
-/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
-HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
-                                           pRNG_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
-  * @{
-  */
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef
-                                 *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef
-                                    *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
-
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
-  * @{
-  */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-uint32_t             HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RNG_Private_Macros RNG Private Macros
-  * @{
-  */
-#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
-                       ((IT) == RNG_IT_SEI))
-
-#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
-                           ((FLAG) == RNG_FLAG_CECS) || \
-                           ((FLAG) == RNG_FLAG_SECS))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* RNG */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L0xx_HAL_RNG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h
deleted file mode 100644
index eec2e55c50..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h
+++ /dev/null
@@ -1,948 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_rtc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RTC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_RTC_H
-#define STM32L0xx_HAL_RTC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTC RTC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Types RTC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
-  HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
-  HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
-  HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
-  HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
-
-} HAL_RTCStateTypeDef;
-
-/**
-  * @brief  RTC Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
-                                 This parameter can be a value of @ref RTC_Hour_Formats */
-
-  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-
-  uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
-
-  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
-                                 This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
-
-  uint32_t OutPutRemap;    /*!< Specifies the remap for RTC output.
-                                 This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
-
-  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
-                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-
-  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
-                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-} RTC_InitTypeDef;
-
-/**
-  * @brief  RTC Time structure definition
-  */
-typedef struct
-{
-  uint8_t Hours;            /*!< Specifies the RTC Time Hour.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
-
-  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
-                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */
-
-  uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
-                                 This parameter corresponds to a time unit range between [0-1] Second
-                                 with [1 Sec / SecondFraction +1] granularity */
-
-  uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
-                                 corresponding to Synchronous pre-scaler factor value (PREDIV_S)
-                                 This parameter corresponds to a time unit range between [0-1] Second
-                                 with [1 Sec / SecondFraction +1] granularity.
-                                 This field will be used only by HAL_RTC_GetTime function */
-
-  uint32_t DayLightSaving;  /*!< This interface is deprecated. To manage Daylight
-                                 Saving Time, please use HAL_RTC_DST_xxx functions */
-
-  uint32_t StoreOperation;  /*!< This interface is deprecated. To manage Daylight
-                                 Saving Time, please use HAL_RTC_DST_xxx functions */
-} RTC_TimeTypeDef;
-
-/**
-  * @brief  RTC Date structure definition
-  */
-typedef struct
-{
-  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
-                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
-  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
-                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
-  uint8_t Date;     /*!< Specifies the RTC Date.
-                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
-  uint8_t Year;     /*!< Specifies the RTC Date Year.
-                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-
-} RTC_DateTypeDef;
-
-/**
-  * @brief  RTC Alarm structure definition
-  */
-typedef struct
-{
-  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
-
-  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
-                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
-  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
-                                      This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
-
-  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
-                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
-  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
-                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
-                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-
-  uint32_t Alarm;                /*!< Specifies the alarm .
-                                      This parameter can be a value of @ref RTC_Alarms_Definitions */
-} RTC_AlarmTypeDef;
-
-/**
-  * @brief  RTC Handle Structure definition
-  */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-typedef struct __RTC_HandleTypeDef
-#else
-typedef struct
-#endif
-{
-  RTC_TypeDef               *Instance;  /*!< Register base address    */
-
-  RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
-
-  HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
-
-  __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-  void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Alarm A Event callback         */
-
-  void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Alarm B Event callback         */
-
-  void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc);        /*!< RTC TimeStamp Event callback       */
-
-  void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc);      /*!< RTC WakeUpTimer Event callback     */
-
-#if defined(RTC_TAMPER1_SUPPORT)
-  void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Tamper 1 Event callback        */
-#endif
-
-  void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Tamper 2 Event callback        */
-
-#if defined(RTC_TAMPER3_SUPPORT)
-  void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Tamper 3 Event callback        */
-#endif
-
-  void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc);               /*!< RTC Msp Init callback              */
-
-  void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc);             /*!< RTC Msp DeInit callback            */
-
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-
-} RTC_HandleTypeDef;
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL LPTIM Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_RTC_ALARM_A_EVENT_CB_ID           = 0x00U,    /*!< RTC Alarm A Event Callback ID      */
-  HAL_RTC_ALARM_B_EVENT_CB_ID           = 0x01U,    /*!< RTC Alarm B Event Callback ID      */
-  HAL_RTC_TIMESTAMP_EVENT_CB_ID         = 0x02U,    /*!< RTC TimeStamp Event Callback ID    */
-  HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       = 0x03U,    /*!< RTC WakeUp Timer Event Callback ID */
-#if defined(RTC_TAMPER1_SUPPORT)
-  HAL_RTC_TAMPER1_EVENT_CB_ID           = 0x04U,    /*!< RTC Tamper 1 Callback ID           */
-#endif
-  HAL_RTC_TAMPER2_EVENT_CB_ID           = 0x05U,    /*!< RTC Tamper 2 Callback ID           */
-#if defined(RTC_TAMPER3_SUPPORT)
-  HAL_RTC_TAMPER3_EVENT_CB_ID           = 0x06U,    /*!< RTC Tamper 3 Callback ID           */
-#endif
-  HAL_RTC_MSPINIT_CB_ID                 = 0x0EU,    /*!< RTC Msp Init callback ID           */
-  HAL_RTC_MSPDEINIT_CB_ID               = 0x0FU     /*!< RTC Msp DeInit callback ID         */
-} HAL_RTC_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL RTC Callback pointer definition
-  */
-typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to an RTC callback function */
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants RTC Exported Constants
-  * @{
-  */
-
-/** @defgroup RTC_Hour_Formats RTC Hour Formats
-  * @{
-  */
-#define RTC_HOURFORMAT_24              (0x00000000U)
-#define RTC_HOURFORMAT_12              RTC_CR_FMT
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
-  * @{
-  */
-#define RTC_OUTPUT_POLARITY_HIGH       (0x00000000U)
-#define RTC_OUTPUT_POLARITY_LOW        RTC_CR_POL
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
-  * @{
-  */
-#define RTC_OUTPUT_TYPE_OPENDRAIN      (0x00000000U)
-#define RTC_OUTPUT_TYPE_PUSHPULL       RTC_OR_ALARMOUTTYPE
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
-  * @{
-  */
-#define RTC_OUTPUT_REMAP_NONE              (0x00000000U)
-#define RTC_OUTPUT_REMAP_POS1              RTC_OR_OUT_RMP
-/**
-  * @}
-  */
-
-/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
-  * @{
-  */
-#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
-  * @{
-  */
-#define RTC_DAYLIGHTSAVING_SUB1H       RTC_CR_SUB1H
-#define RTC_DAYLIGHTSAVING_ADD1H       RTC_CR_ADD1H
-#define RTC_DAYLIGHTSAVING_NONE        (0x00000000U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
-  * @{
-  */
-#define RTC_STOREOPERATION_RESET        (0x00000000U)
-#define RTC_STOREOPERATION_SET          RTC_CR_BKP
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
-  * @{
-  */
-#define RTC_FORMAT_BIN   (0x000000000U)
-#define RTC_FORMAT_BCD   (0x000000001U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
-  * @{
-  */
-
-/* Coded in BCD format */
-#define RTC_MONTH_JANUARY              ((uint8_t)0x01)
-#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
-#define RTC_MONTH_MARCH                ((uint8_t)0x03)
-#define RTC_MONTH_APRIL                ((uint8_t)0x04)
-#define RTC_MONTH_MAY                  ((uint8_t)0x05)
-#define RTC_MONTH_JUNE                 ((uint8_t)0x06)
-#define RTC_MONTH_JULY                 ((uint8_t)0x07)
-#define RTC_MONTH_AUGUST               ((uint8_t)0x08)
-#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
-#define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
-#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
-#define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
-  * @{
-  */
-#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
-#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
-#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
-#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
-#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
-#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
-#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
-  * @{
-  */
-#define RTC_ALARMDATEWEEKDAYSEL_DATE      (0x00000000U)
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   RTC_ALRMAR_WDSEL
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
-  * @{
-  */
-#define RTC_ALARMMASK_NONE             (0x00000000U)
-#define RTC_ALARMMASK_DATEWEEKDAY       RTC_ALRMAR_MSK4
-#define RTC_ALARMMASK_HOURS             RTC_ALRMAR_MSK3
-#define RTC_ALARMMASK_MINUTES           RTC_ALRMAR_MSK2
-#define RTC_ALARMMASK_SECONDS           RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL               ((uint32_t) (RTC_ALARMMASK_NONE        | \
-                                                     RTC_ALARMMASK_DATEWEEKDAY | \
-                                                     RTC_ALARMMASK_HOURS       | \
-                                                     RTC_ALARMMASK_MINUTES     | \
-                                                     RTC_ALARMMASK_SECONDS))
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
-  * @{
-  */
-#define RTC_ALARM_A                       RTC_CR_ALRAE
-#define RTC_ALARM_B                       RTC_CR_ALRBE
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
-* @{
-*/
-#define RTC_ALARMSUBSECONDMASK_ALL        (0x00000000U)                                                                 /*!< All Alarm SS fields are masked.
-                                                                                                                                    There is no comparison on sub seconds
-                                                                                                                                    for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1      RTC_ALRMASSR_MASKSS_0                                                                 /*!< SS[14:1] are don't care in Alarm
-                                                                                                                                    comparison. Only SS[0] is compared.    */
-#define RTC_ALARMSUBSECONDMASK_SS14_2      RTC_ALRMASSR_MASKSS_1                                                                 /*!< SS[14:2] are don't care in Alarm
-                                                                                                                                     comparison. Only SS[1:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1))                          /*!< SS[14:3] are don't care in Alarm
-                                                                                                                                     comparison. Only SS[2:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_4      RTC_ALRMASSR_MASKSS_2                                                                 /*!< SS[14:4] are don't care in Alarm
-                                                                                                                                     comparison. Only SS[3:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2))                          /*!< SS[14:5] are don't care in Alarm
-                                                                                                                                      comparison. Only SS[4:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2))                          /*!< SS[14:6] are don't care in Alarm
-                                                                                                                                      comparison. Only SS[5:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2))  /*!< SS[14:7] are don't care in Alarm
-                                                                                                                                `     comparison. Only SS[6:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_8      RTC_ALRMASSR_MASKSS_3                                                                 /*!< SS[14:8] are don't care in Alarm
-                                                                                                                                      comparison. Only SS[7:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3))                          /*!< SS[14:9] are don't care in Alarm
-                                                                                                                                      comparison. Only SS[8:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3))                          /*!< SS[14:10] are don't care in Alarm
-                                                                                                                                      comparison. Only SS[9:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3))  /*!< SS[14:11] are don't care in Alarm
-                                                                                                                                      comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t) (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))                          /*!< SS[14:12] are don't care in Alarm
-                                                                                                                                      comparison.Only SS[11:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))  /*!< SS[14:13] are don't care in Alarm
-                                                                                                                                      comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))  /*!< SS[14] is don't care in Alarm
-                                                                                                                                      comparison.Only SS[13:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_NONE        RTC_ALRMASSR_MASKSS                                                                   /*!< SS[14:0] are compared and must match
-                                                                                                                                      to activate alarm. */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
-  * @{
-  */
-#define RTC_IT_TS                         RTC_CR_TSIE        /*!< Enable Timestamp Interrupt    */
-#define RTC_IT_WUT                        RTC_CR_WUTIE       /*!< Enable Wakeup timer Interrupt */
-#define RTC_IT_ALRA                       RTC_CR_ALRAIE      /*!< Enable Alarm A Interrupt      */
-#define RTC_IT_ALRB                       RTC_CR_ALRBIE      /*!< Enable Alarm B Interrupt      */
-#define RTC_IT_TAMP                       RTC_TAMPCR_TAMPIE  /*!< Enable all Tamper Interrupt   */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define RTC_IT_TAMP1                      RTC_TAMPCR_TAMP1IE /*!< Enable Tamper 1 Interrupt     */
-#endif
-#define RTC_IT_TAMP2                      RTC_TAMPCR_TAMP2IE /*!< Enable Tamper 2 Interrupt     */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
-  * @{
-  */
-#define RTC_FLAG_RECALPF                  RTC_ISR_RECALPF
-#define RTC_FLAG_TAMP2F                   RTC_ISR_TAMP2F
-#if defined(RTC_TAMPER1_SUPPORT)
-#define RTC_FLAG_TAMP1F                   RTC_ISR_TAMP1F
-#endif
-#define RTC_FLAG_TSOVF                    RTC_ISR_TSOVF
-#define RTC_FLAG_TSF                      RTC_ISR_TSF
-#if defined(RTC_ISR_ITSF)
-#define RTC_FLAG_ITSF                     RTC_ISR_ITSF
-#endif
-#define RTC_FLAG_WUTF                     RTC_ISR_WUTF
-#define RTC_FLAG_ALRBF                    RTC_ISR_ALRBF
-#define RTC_FLAG_ALRAF                    RTC_ISR_ALRAF
-#define RTC_FLAG_INITF                    RTC_ISR_INITF
-#define RTC_FLAG_RSF                      RTC_ISR_RSF
-#define RTC_FLAG_INITS                    RTC_ISR_INITS
-#define RTC_FLAG_SHPF                     RTC_ISR_SHPF
-#define RTC_FLAG_WUTWF                    RTC_ISR_WUTWF
-#define RTC_FLAG_ALRBWF                   RTC_ISR_ALRBWF
-#define RTC_FLAG_ALRAWF                   RTC_ISR_ALRAWF
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RTC_Exported_Macros RTC Exported Macros
-  * @{
-  */
-
-/** @brief Reset RTC handle state
-  * @param  __HANDLE__ RTC handle.
-  * @retval None
-  */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
-                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
-                                                      (__HANDLE__)->MspInitCallback = NULL;\
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
-                                                     }while(0)
-#else
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Disable the write protection for RTC registers.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
-                        do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xCAU;   \
-                            (__HANDLE__)->Instance->WPR = 0x53U;   \
-                          } while(0U)
-
-/**
-  * @brief  Enable the write protection for RTC registers.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
-                        do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xFFU;   \
-                          } while(0U)
-
-/**
-  * @brief  Enable the RTC ALARMA peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
-
-/**
-  * @brief  Disable the RTC ALARMA peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
-
-/**
-  * @brief  Enable the RTC ALARMB peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
-
-/**
-  * @brief  Disable the RTC ALARMB peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
-
-/**
-  * @brief  Enable the RTC Alarm interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
-  *          This parameter can be any combination of the following values:
-  *             @arg RTC_IT_ALRA: Alarm A interrupt
-  *             @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Alarm interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)  (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != 0U)? 1U : 0U)
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-
-/**
-  * @brief  Get the selected RTC Alarm's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_ALRAF
-  *            @arg RTC_FLAG_ALRBF
-  *            @arg RTC_FLAG_ALRAWF
-  *            @arg RTC_FLAG_ALRBWF
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
-
-/**
-  * @brief  Clear the RTC Alarm's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_ALRAF
-  *             @arg RTC_FLAG_ALRBF
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Enable interrupt on the RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable event on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable event on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
-                                                             __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
-                                                             __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
-                                                           } while(0U)
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
-                                                             __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
-                                                             __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
-                                                           } while(0U)
-
-/**
-  * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Clear the RTC Alarm associated Exti line flag.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @}
-  */
-
-/* Include RTC HAL Extended module */
-#include "stm32l0xx_hal_rtc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
-  * @{
-  */
-
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-
-void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
-  * @{
-  */
-/* RTC Time and Date functions ************************************************/
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-
-/* RTC Daylight Saving Time functions *****************************************/
-void              HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
-uint32_t          HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
-  * @{
-  */
-/* RTC Alarm functions ********************************************************/
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @defgroup  RTC_Exported_Functions_Group4 Peripheral Control functions
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
-  * @{
-  */
-/* Peripheral State functions *************************************************/
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Constants RTC Private Constants
-  * @{
-  */
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK  ((uint32_t) (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
-                                           RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
-                                           RTC_TR_SU))
-#define RTC_DR_RESERVED_MASK  ((uint32_t) (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
-                                           RTC_DR_MT | RTC_DR_MU | RTC_DR_DT  | \
-                                           RTC_DR_DU))
-#define RTC_INIT_MASK           (0xFFFFFFFFU)
-#define RTC_RSF_MASK            ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
-
-#define RTC_TIMEOUT_VALUE  1000U
-
-#define RTC_EXTI_LINE_ALARM_EVENT             (EXTI_IMR_IM17)  /*!< External interrupt line connected to the RTC Alarm event */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTC_Private_Macros RTC Private Macros
-  * @{
-  */
-
-/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
-  * @{
-  */
-
-#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
-                                        ((FORMAT) == RTC_HOURFORMAT_24))
-
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
-                                ((POL) == RTC_OUTPUT_POLARITY_LOW))
-
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
-                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-
-#define IS_RTC_OUTPUT_REMAP(REMAP)   (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
-                                      ((REMAP) == RTC_OUTPUT_REMAP_POS1))
-
-#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || \
-                                  ((PM) == RTC_HOURFORMAT12_PM))
-
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
-                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
-                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
-
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
-                                           ((OPERATION) == RTC_STOREOPERATION_SET))
-
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-
-#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99U)
-
-#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1U) && ((MONTH) <= 12U))
-
-#define IS_RTC_DATE(DATE)              (((DATE) >= 1U) && ((DATE) <= 31U))
-
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0U) && ((DATE) <= 31U))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
-                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-
-#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0U)
-
-#define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
-
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
-
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
-
-#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7FU)
-
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFFU)
-
-#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0U) && ((HOUR) <= 12U))
-
-#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23U)
-
-#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59U)
-
-#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59U)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions -------------------------------------------------------------*/
-/** @defgroup RTC_Private_Functions RTC Private Functions
-  * @{
-  */
-HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
-uint8_t            RTC_ByteToBcd2(uint8_t Value);
-uint8_t            RTC_Bcd2ToByte(uint8_t Value);
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h
deleted file mode 100644
index 6e4c166188..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h
+++ /dev/null
@@ -1,1348 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_rtc_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of RTC HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_RTC_EX_H
-#define STM32L0xx_HAL_RTC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTCEx RTCEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RTC Tamper structure definition
-  */
-typedef struct
-{
-  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
-
-  uint32_t Interrupt;                   /*!< Specifies the Tamper Interrupt.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Interrupt_Definitions */
-
-  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
-
-  uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_EraseBackUp_Definitions */
-
-  uint32_t MaskFlag;                     /*!< Specifies the Tamper Flag masking.
-                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions   */
-
-  uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
-
-  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
-
-  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
-
-  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
-
-  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
-                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
-} RTC_TamperTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
-  * @{
-  */
-#define RTC_OUTPUT_DISABLE             (0x00000000U)
-#define RTC_OUTPUT_ALARMA              RTC_CR_OSEL_0
-#define RTC_OUTPUT_ALARMB              RTC_CR_OSEL_1
-#define RTC_OUTPUT_WAKEUP              RTC_CR_OSEL
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definition
-  * @{
-  */
-#define RTC_BKP_DR0                       (0x00000000U)
-#define RTC_BKP_DR1                       (0x00000001U)
-#define RTC_BKP_DR2                       (0x00000002U)
-#define RTC_BKP_DR3                       (0x00000003U)
-#define RTC_BKP_DR4                       (0x00000004U)
-/**
-  * @}
-  */
-
-
-/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
-  * @{
-  */
-#define RTC_TIMESTAMPEDGE_RISING        (0x00000000U)
-#define RTC_TIMESTAMPEDGE_FALLING       RTC_CR_TSEDGE
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
-  * @{
-  */
-#define RTC_TIMESTAMPPIN_DEFAULT              (0x00000000U)
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definition
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E
-#endif /* RTC_TAMPER1_SUPPORT */
-
-#define RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E
-
-#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-
-/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define RTC_TAMPER1_INTERRUPT                RTC_TAMPCR_TAMP1IE
-#endif /* RTC_TAMPER1_SUPPORT */
-
-
-#define RTC_TAMPER2_INTERRUPT                RTC_TAMPCR_TAMP2IE
-
-#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_TAMPER3_INTERRUPT                RTC_TAMPCR_TAMP3IE
-#endif /* RTC_TAMPER3_SUPPORT */
-#define RTC_ALL_TAMPER_INTERRUPT             RTC_TAMPCR_TAMPIE
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions
-  * @{
-  */
-#define RTC_TAMPERTRIGGER_RISINGEDGE       (0x00000000U)
-#define RTC_TAMPERTRIGGER_FALLINGEDGE      (0x00000002U)
-#define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
-#define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions
-* @{
-*/
-#define RTC_TAMPER_ERASE_BACKUP_ENABLE               (0x00000000U)
-#define RTC_TAMPER_ERASE_BACKUP_DISABLE              (0x00020000U)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions
-* @{
-*/
-#define RTC_TAMPERMASK_FLAG_DISABLE               (0x00000000U)
-#define RTC_TAMPERMASK_FLAG_ENABLE                (0x00040000U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions
-  * @{
-  */
-#define RTC_TAMPERFILTER_DISABLE   (0x00000000U)  /*!< Tamper filter is disabled */
-
-#define RTC_TAMPERFILTER_2SAMPLE   RTC_TAMPCR_TAMPFLT_0    /*!< Tamper is activated after 2
-                                                                consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE   RTC_TAMPCR_TAMPFLT_1    /*!< Tamper is activated after 4
-                                                                consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE   RTC_TAMPCR_TAMPFLT      /*!< Tamper is activated after 8
-                                                                consecutive samples at the active leve. */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions
-  * @{
-  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  (0x00000000U)                                         /*!< Each of the tamper inputs are sampled
-                                                                                                                    with a frequency =  RTCCLK / 32768 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  RTC_TAMPCR_TAMPFREQ_0                                          /*!< Each of the tamper inputs are sampled
-                                                                                                                    with a frequency =  RTCCLK / 16384 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   RTC_TAMPCR_TAMPFREQ_1                                          /*!< Each of the tamper inputs are sampled
-                                                                                                                    with a frequency =  RTCCLK / 8192  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1))   /*!< Each of the tamper inputs are sampled
-                                                                                                                    with a frequency =  RTCCLK / 4096  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   RTC_TAMPCR_TAMPFREQ_2                                          /*!< Each of the tamper inputs are sampled
-                                                                                                                    with a frequency =  RTCCLK / 2048  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_2))   /*!< Each of the tamper inputs are sampled
-                                                                                                                    with a frequency =  RTCCLK / 1024  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t) (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2))   /*!< Each of the tamper inputs are sampled
-                                                                                                                    with a frequency =  RTCCLK / 512   */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1 | \
-                                                 RTC_TAMPCR_TAMPFREQ_2))                                       /*!< Each of the tamper inputs are sampled
-                                                                                                                    with a frequency =  RTCCLK / 256   */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions
-  * @{
-  */
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK  (0x00000000U)                                     /*!< Tamper pins are pre-charged before
-                                                                                                            sampling during 1 RTCCLK cycle  */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK  RTC_TAMPCR_TAMPPRCH_0                                      /*!< Tamper pins are pre-charged before
-                                                                                                             sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK  RTC_TAMPCR_TAMPPRCH_1                                      /*!< Tamper pins are pre-charged before
-                                                                                                             sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)(RTC_TAMPCR_TAMPPRCH_0 | RTC_TAMPCR_TAMPPRCH_1)) /*!< Tamper pins are pre-charged before
-                                                                                                             sampling during 8 RTCCLK cycles */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStampOnTamperDetection Definitions
-  * @{
-  */
-#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  RTC_TAMPCR_TAMPTS       /*!< TimeStamp on Tamper Detection event saved        */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE (0x00000000U)  /*!< TimeStamp on Tamper Detection event is not saved */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions
-  * @{
-  */
-#define RTC_TAMPER_PULLUP_ENABLE  (0x00000000U)  /*!< Tamper pins are pre-charged before sampling */
-#define RTC_TAMPER_PULLUP_DISABLE  RTC_TAMPCR_TAMPPUDIS   /*!< Tamper pins pre-charge is disabled          */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
-  * @{
-  */
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        (0x00000000U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         RTC_CR_WUCKSEL_0
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         RTC_CR_WUCKSEL_1
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t) (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1))
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      RTC_CR_WUCKSEL_2
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t) (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
-  * @{
-  */
-#define RTC_SMOOTHCALIB_PERIOD_32SEC   (0x00000000U)   /*!< If RTCCLK = 32768 Hz, Smooth calibation
-                                                                     period is 32s,  else 2exp20 RTCCLK pulses */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC   RTC_CALR_CALW16          /*!< If RTCCLK = 32768 Hz, Smooth calibation
-                                                                     period is 16s, else 2exp19 RTCCLK pulses */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC    RTC_CALR_CALW8           /*!< If RTCCLK = 32768 Hz, Smooth calibation
-                                                                     period is 8s, else 2exp18 RTCCLK pulses */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
-  * @{
-  */
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET    RTC_CALR_CALP            /*!< The number of RTCCLK pulses added
-                                                                        during a X -second window = Y - CALM[8:0]
-                                                                        with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  (0x00000000U)   /*!< The number of RTCCLK pulses subbstited
-                                                                        during a 32-second window = CALM[8:0] */
-
-/**
-  * @}
-  */
-/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
- * @{
- */
-#define RTC_CALIBOUTPUT_512HZ            (0x00000000U)
-#define RTC_CALIBOUTPUT_1HZ              RTC_CR_COSEL
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions
-  * @{
-  */
-#define RTC_SHIFTADD1S_RESET      (0x00000000U)
-#define RTC_SHIFTADD1S_SET        RTC_SHIFTR_ADD1S
-/**
-  * @}
-  */
-/** @defgroup RTCEx_Interrupts_Definitions RTCEx Interrupts Definitions
-* @{
-*/
-#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_IT_TAMP3                      RTC_TAMPCR_TAMP3IE  /*!< Enable Tamper 3 Interrupt     */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Flags_Definitions RTCEx Flags Definitions
-  * @{
-  */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_FLAG_TAMP3F                   RTC_ISR_TAMP3F
-#endif
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
-  * @{
-  */
-
-/* ---------------------------------WAKEUPTIMER---------------------------------*/
-/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
-  * @{
-  */
-/**
-  * @brief  Enable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
-
-/**
-  * @brief  Disable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
-
-/**
-  * @brief  Enable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT: WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT: WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != 0U) ? 1U : 0U)
-
-/**
-  * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-
-/**
-  * @brief  Get the selected RTC WakeUpTimer's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_WUTF
-  *             @arg RTC_FLAG_WUTWF
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
-
-/**
-  * @brief  Clear the RTC Wake Up timer's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_WUTF
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/* WAKE-UP TIMER EXTI */
-/* ------------------ */
-/**
-  * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable event on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable event on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
-                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \
-                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
-                                                                 } while(0U)
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * This parameter can be:
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
-                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();  \
-                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
-                                                                  } while(0U)
-
-/**
-  * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief Clear the RTC WakeUp Timer associated Exti line flag.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-/**
-  * @}
-  */
-
-/* ---------------------------------TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Timestamp RTC Timestamp
-  * @{
-  */
-/**
-  * @brief  Enable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
-
-/**
-  * @brief  Disable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
-
-/**
-  * @brief  Enable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != 0U) ? 1U : 0U)
-
-/**
-  * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-
-/**
-  * @brief  Get the selected RTC TimeStamp's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TSF
-  *            @arg RTC_FLAG_TSOVF
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
-
-/**
-  * @brief  Clear the RTC Time Stamp's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param __FLAG__ specifies the RTC TimeStamp Flag to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TSF
-  *             @arg RTC_FLAG_TSOVF
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)          ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-
-/**
-  * @}
-  */
-
-/* ---------------------------------TAMPER------------------------------------*/
-/** @defgroup RTCEx_Tamper RTC Tamper
-  * @{
-  */
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
-  * @brief  Enable the RTC Tamper1 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
-
-/**
-  * @brief  Disable the RTC Tamper1 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
-  * @brief  Enable the RTC Tamper2 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
-
-/**
-  * @brief  Disable the RTC Tamper2 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
-  * @brief  Enable the RTC Tamper3 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
-
-/**
-  * @brief  Disable the RTC Tamper3 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
-#endif /* RTC_TAMPER3_SUPPORT */
-
-
-/**************************************************************************************************/
-
-#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
-
-/**
-  * @brief  Enable the RTC Tamper interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
-  *          This parameter can be any combination of the following values:
-  *             @arg  RTC_IT_TAMP: All tampers interrupts
-  *             @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *             @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Tamper interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg  RTC_IT_TAMP: All tampers interrupts
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
-
-#elif defined(RTC_TAMPER1_SUPPORT)
-
-/**
-  * @brief  Enable the RTC Tamper interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
-  *          This parameter can be any combination of the following values:
-  *             @arg  RTC_IT_TAMP: All tampers interrupts
-  *             @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Tamper interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg  RTC_IT_TAMP: All tampers interrupts
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
-
-#elif defined(RTC_TAMPER3_SUPPORT)
-
-
-/**
-  * @brief  Enable the RTC Tamper interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
-  *          This parameter can be any combination of the following values:
-  *             @arg  RTC_IT_TAMP: All tampers interrupts
-  *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *             @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Tamper interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg  RTC_IT_TAMP: All tampers interrupts
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
-
-#endif
-
-/**************************************************************************************************/
-
-#if  defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)    (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U) : \
-                                                               ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U) : \
-                                                               (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != 0U) ? 1U : 0U))
-
-#elif defined(RTC_TAMPER1_SUPPORT)
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)    (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U) : \
-                                                               (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U))
-
-#elif defined(RTC_TAMPER3_SUPPORT)
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)    (((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U) : \
-                                                               (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != 0U) ? 1U : 0U))
-
-
-#endif
-
-/**************************************************************************************************/
-
-#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP: All tampers interrupts
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-
-
-/**
-  * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
-  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
-  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
-
-/**
-  * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
-  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
-  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-#elif defined(RTC_TAMPER1_SUPPORT)
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP: All tampers interrupts
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-
-
-/**
-  * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
-  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
-
-/**
-  * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
-  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-#elif defined(RTC_TAMPER3_SUPPORT)
-
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP: All tampers interrupts
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-
-
-/**
-  * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
-  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
-
-/**
-  * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
-  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-#endif
-
-
-/**************************************************************************************************/
-
-/**
-  * @}
-  */
-
-/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
-  * @{
-  */
-
-/* TAMPER TIMESTAMP EXTI */
-/* --------------------- */
-/**
-  * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
-                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();  \
-                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
-                                                                      } while(0U)
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
-                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();  \
-                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
-                                                                       } while(0U)
-
-/**
-  * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-/**
-  * @}
-  */
-
-/* ------------------------------Calibration----------------------------------*/
-/** @defgroup RTCEx_Calibration RTC Calibration
-  * @{
-  */
-
-/**
-  * @brief  Enable the RTC calibration output.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
-
-/**
-  * @brief  Disable the calibration output.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
-
-
-/**
-  * @brief  Enable the clock reference detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
-
-/**
-  * @brief  Disable the clock reference detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
-
-
-/**
-  * @brief  Get the selected RTC shift operation's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC shift operation Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_SHPF
-  * @retval None
-  */
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
-  * @{
-  */
-
-/* RTC TimeStamp and Tamper functions *****************************************/
-/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-
-#if defined(RTC_TAMPER1_SUPPORT)
-void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-#endif /* RTC_TAMPER1_SUPPORT */
-void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-#if defined(RTC_TAMPER3_SUPPORT)
-void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
-#endif /* RTC_TAMPER3_SUPPORT */
-void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#if defined(RTC_TAMPER1_SUPPORT)
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#endif /* RTC_TAMPER1_SUPPORT */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#if defined(RTC_TAMPER3_SUPPORT)
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-/* RTC Wake-up functions ******************************************************/
-/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Extended Control functions ************************************************/
-/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
- * @{
- */
-
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/* Extended RTC features functions *******************************************/
-/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
- * @{
- */
-void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
-  * @{
-  */
-
-/* Masks Definition */
-
-#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
-
-#define RTC_FLAGS_MASK          ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
-                                             RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF       | \
-                                             RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF      | \
-                                             RTC_FLAG_INITF | RTC_FLAG_RSF                        | \
-                                             RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF      | \
-                                             RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
-
-#define RTC_TAMPCR_TAMPXE     ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
-#define RTC_TAMPCR_TAMPXIE    ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | \
-                                           RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
-
-#elif defined(RTC_TAMPER1_SUPPORT)
-
-#define RTC_FLAGS_MASK          ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP1F| \
-                                             RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF       | \
-                                             RTC_FLAG_ALRBF | RTC_FLAG_ALRAF                     | \
-                                             RTC_FLAG_INITF | RTC_FLAG_RSF | RTC_FLAG_INITS      | \
-                                             RTC_FLAG_SHPF | RTC_FLAG_WUTWF |RTC_FLAG_ALRBWF     | \
-                                             RTC_FLAG_ALRAWF))
-
-#define RTC_TAMPCR_TAMPXE     ((uint32_t) (RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
-#define RTC_TAMPCR_TAMPXIE    ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | \
-                                           RTC_ALL_TAMPER_INTERRUPT))
-
-#elif defined(RTC_TAMPER3_SUPPORT)
-
-#define RTC_FLAGS_MASK          ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
-                                             RTC_FLAG_TSOVF | RTC_FLAG_TSF                        | \
-                                             RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF      | \
-                                             RTC_FLAG_INITF | RTC_FLAG_RSF                        | \
-                                             RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF      | \
-                                             RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
-
-#define RTC_TAMPCR_TAMPXE     ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E))
-#define RTC_TAMPCR_TAMPXIE    ((uint32_t) (RTC_TAMPER2_INTERRUPT | \
-                                           RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
-#endif
-
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  (EXTI_IMR_IM19)  /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       (EXTI_IMR_IM20)  /*!< External interrupt line 20 Connected to the RTC Wakeup event */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
-  * @{
-  */
-
-/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
-  * @{
-  */
-
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
-                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
-                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
-                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))
-
-#define IS_RTC_BKP(BKP)                   ((BKP) < (uint32_t) RTC_BKP_NUMBER)
-
-#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
-                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-
-#define  IS_RTC_TAMPER(TAMPER)  ((((TAMPER) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((TAMPER) != 0U))
-
-#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((INTERRUPT) != 0U))
-
-#define IS_RTC_TIMESTAMP_PIN(PIN)  (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
-
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
-
-#define IS_RTC_TAMPER_ERASE_MODE(MODE)             (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
-                                                    ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
-
-#define IS_RTC_TAMPER_MASKFLAG_STATE(STATE)        (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \
-                                                    ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE))
-
-#define IS_RTC_TAMPER_FILTER(FILTER)  (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
-                                       ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
-                                       ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
-                                       ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
-
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
-                                          ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
-
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
-                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
-                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
-                                                   ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
-
-#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
-                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
-
-#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
-                                           ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
-
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= RTC_WUTR_WUT)
-
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
-                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
-                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
-
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
-                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
-
-
-/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions RTCEx Smooth calib Minus pulses Definitions
-  * @{
-  */
-#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
-/**
-  * @}
-  */
-
-
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
-                                 ((SEL) == RTC_SHIFTADD1S_SET))
-
-
-
-/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value RTCEx Substract Fraction Of Second Value
-  * @{
-  */
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
-/**
-  * @}
-  */
-#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
-                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard.h
deleted file mode 100644
index ff66e40c6e..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard.h
+++ /dev/null
@@ -1,1145 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_smartcard.h
-  * @author  MCD Application Team
-  * @brief   Header file of SMARTCARD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_SMARTCARD_H
-#define STM32L0xx_HAL_SMARTCARD_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined (STM32L010x4) && !defined (STM32L010x6)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SMARTCARD
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
-  * @{
-  */
-
-/**
-  * @brief SMARTCARD Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
-                                           The baud rate register is computed using the following formula:
-                                              Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))
-                                           where usart_ker_ckpres is the USART input clock divided by a prescaler */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter @ref SMARTCARD_Word_Length can only be
-                                           set to 9 (8 data + 1 parity bits). */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits.
-                                           This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
-
-  uint16_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref SMARTCARD_Parity
-                                           @note The parity is enabled by default (PCE is forced to 1).
-                                                 Since the WordLength is forced to 8 bits + parity, M is
-                                                 forced to 1 and the parity bit is the 9th bit. */
-
-  uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref SMARTCARD_Mode */
-
-  uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
-
-  uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */
-
-  uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */
-
-  uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote
-                                           is selected. Selecting the single sample method increases
-                                           the receiver tolerance to clock deviations. This parameter can be a value
-                                           of @ref SMARTCARD_OneBit_Sampling. */
-
-  uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler.
-                                           This parameter can be any value from 0x01 to 0x1F. Prescaler value is
-                                           multiplied by 2 to give the division factor of the source clock frequency */
-
-  uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
-
-  uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
-                                           in case of parity error.
-                                           This parameter can be a value of @ref SMARTCARD_NACK_Enable */
-
-  uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
-                                            This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
-
-  uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
-                                           it is used to implement the Character Wait Time (CWT) and
-                                           Block Wait Time (BWT). It is coded over 24 bits. */
-
-  uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
-                                           This parameter can be any value from 0x0 to 0xFF */
-
-  uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
-                                            receive and transmit mode). When set to 0, retransmission is
-                                            disabled. Otherwise, its maximum value is 7 (before signalling
-                                            an error) */
-
-} SMARTCARD_InitTypeDef;
-
-/**
-  * @brief  SMARTCARD advanced features initialization structure definition
-  */
-typedef struct
-{
-  uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
-                                           advanced features may be initialized at the same time. This parameter
-                                           can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
-
-  uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
-                                           This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
-
-  uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
-                                           This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
-
-  uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
-                                           vs negative/inverted logic).
-                                           This parameter can be a value of @ref SMARTCARD_Data_Inv */
-
-  uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
-                                           This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
-
-  uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
-                                           This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
-
-  uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
-                                           This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
-
-  uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
-                                           This parameter can be a value of @ref SMARTCARD_MSB_First */
-
-  uint16_t TxCompletionIndication;    /*!< Specifies which transmission completion indication is used: before (when
-                                           relevant flag is available) or once guard time period has elapsed.
-                                           This parameter can be a value
-                                           of @ref SMARTCARDEx_Transmission_Completion_Indication. */
-} SMARTCARD_AdvFeatureInitTypeDef;
-
-/**
-  * @brief HAL SMARTCARD State definition
-  * @note  HAL SMARTCARD State value is a combination of 2 different substates:
-  *        gState and RxState (see @ref SMARTCARD_State_Definition).
-  *        - gState contains SMARTCARD state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (Peripheral busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */
-typedef uint32_t HAL_SMARTCARD_StateTypeDef;
-
-/**
-  * @brief  SMARTCARD handle Structure definition
-  */
-typedef struct __SMARTCARD_HandleTypeDef
-{
-  USART_TypeDef                     *Instance;             /*!< USART registers base address                          */
-
-  SMARTCARD_InitTypeDef             Init;                  /*!< SmartCard communication parameters                    */
-
-  SMARTCARD_AdvFeatureInitTypeDef   AdvancedInit;          /*!< SmartCard advanced features initialization parameters */
-
-  uint8_t                           *pTxBuffPtr;           /*!< Pointer to SmartCard Tx transfer Buffer               */
-
-  uint16_t                          TxXferSize;            /*!< SmartCard Tx Transfer size                            */
-
-  __IO uint16_t                     TxXferCount;           /*!< SmartCard Tx Transfer Counter                         */
-
-  uint8_t                           *pRxBuffPtr;           /*!< Pointer to SmartCard Rx transfer Buffer               */
-
-  uint16_t                          RxXferSize;            /*!< SmartCard Rx Transfer size                            */
-
-  __IO uint16_t                     RxXferCount;           /*!< SmartCard Rx Transfer Counter                         */
-
-
-  void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Rx IRQ handler                    */
-
-  void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Tx IRQ handler                    */
-
-  DMA_HandleTypeDef                 *hdmatx;               /*!< SmartCard Tx DMA Handle parameters                    */
-
-  DMA_HandleTypeDef                 *hdmarx;               /*!< SmartCard Rx DMA Handle parameters                    */
-
-  HAL_LockTypeDef                   Lock;                  /*!< Locking object                                        */
-
-  __IO HAL_SMARTCARD_StateTypeDef   gState;                /*!< SmartCard state information related to global
-                                                                Handle management and also related to Tx operations.
-                                                                This parameter can be a value
-                                                                of @ref HAL_SMARTCARD_StateTypeDef                    */
-
-  __IO HAL_SMARTCARD_StateTypeDef   RxState;               /*!< SmartCard state information related to Rx operations.
-                                                                This parameter can be a value
-                                                                of @ref HAL_SMARTCARD_StateTypeDef                    */
-
-  __IO uint32_t                     ErrorCode;             /*!< SmartCard Error code                                  */
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Tx Complete Callback             */
-
-  void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Rx Complete Callback             */
-
-  void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);             /*!< SMARTCARD Error Callback                   */
-
-  void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Abort Complete Callback          */
-
-  void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
-
-  void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);  /*!< SMARTCARD Abort Receive Complete Callback  */
-
-  void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);           /*!< SMARTCARD Msp Init callback                */
-
-  void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Msp DeInit callback              */
-#endif  /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-} SMARTCARD_HandleTypeDef;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL SMARTCARD Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SMARTCARD_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SMARTCARD Tx Complete Callback ID             */
-  HAL_SMARTCARD_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SMARTCARD Rx Complete Callback ID             */
-  HAL_SMARTCARD_ERROR_CB_ID                   = 0x02U,    /*!< SMARTCARD Error Callback ID                   */
-  HAL_SMARTCARD_ABORT_COMPLETE_CB_ID          = 0x03U,    /*!< SMARTCARD Abort Complete Callback ID          */
-  HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U,    /*!< SMARTCARD Abort Transmit Complete Callback ID */
-  HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x05U,    /*!< SMARTCARD Abort Receive Complete Callback ID  */
-
-  HAL_SMARTCARD_MSPINIT_CB_ID                 = 0x08U,    /*!< SMARTCARD MspInit callback ID                 */
-  HAL_SMARTCARD_MSPDEINIT_CB_ID               = 0x09U     /*!< SMARTCARD MspDeInit callback ID               */
-
-} HAL_SMARTCARD_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SMARTCARD Callback pointer definition
-  */
-typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard);  /*!< pointer to an SMARTCARD callback function */
-
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-/**
-  * @brief  SMARTCARD clock sources
-  */
-typedef enum
-{
-  SMARTCARD_CLOCKSOURCE_PCLK1     = 0x00U, /*!< PCLK1 clock source         */
-  SMARTCARD_CLOCKSOURCE_PCLK2     = 0x01U, /*!< PCLK2 clock source         */
-  SMARTCARD_CLOCKSOURCE_HSI       = 0x02U, /*!< HSI clock source           */
-  SMARTCARD_CLOCKSOURCE_SYSCLK    = 0x04U, /*!< SYSCLK clock source        */
-  SMARTCARD_CLOCKSOURCE_LSE       = 0x08U, /*!< LSE clock source           */
-  SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U  /*!< undefined clock source     */
-} SMARTCARD_ClockSourceTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
-  * @{
-  */
-
-/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
-  * @{
-  */
-#define HAL_SMARTCARD_STATE_RESET            0x00000000U                     /*!< Peripheral is not initialized. Value
-                                                                                  is allowed for gState and RxState */
-#define HAL_SMARTCARD_STATE_READY            0x00000020U                     /*!< Peripheral Initialized and ready for
-                                                                                  use. Value is allowed for gState
-                                                                                  and RxState                       */
-#define HAL_SMARTCARD_STATE_BUSY             0x00000024U                     /*!< an internal process is ongoing
-                                                                                  Value is allowed for gState only  */
-#define HAL_SMARTCARD_STATE_BUSY_TX          0x00000021U                     /*!< Data Transmission process is ongoing
-                                                                                  Value is allowed for gState only  */
-#define HAL_SMARTCARD_STATE_BUSY_RX          0x00000022U                     /*!< Data Reception process is ongoing
-                                                                                  Value is allowed for RxState only */
-#define HAL_SMARTCARD_STATE_BUSY_TX_RX       0x00000023U                     /*!< Data Transmission and Reception
-                                                                                  process is ongoing Not to be used for
-                                                                                  neither gState nor RxState.
-                                                                                  Value is result of combination (Or)
-                                                                                  between gState and RxState values */
-#define HAL_SMARTCARD_STATE_TIMEOUT          0x000000A0U                     /*!< Timeout state
-                                                                                  Value is allowed for gState only  */
-#define HAL_SMARTCARD_STATE_ERROR            0x000000E0U                     /*!< Error
-                                                                                  Value is allowed for gState only  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
-  * @{
-  */
-#define HAL_SMARTCARD_ERROR_NONE             (0x00000000U)         /*!< No error                */
-#define HAL_SMARTCARD_ERROR_PE               (0x00000001U)         /*!< Parity error            */
-#define HAL_SMARTCARD_ERROR_NE               (0x00000002U)         /*!< Noise error             */
-#define HAL_SMARTCARD_ERROR_FE               (0x00000004U)         /*!< frame error             */
-#define HAL_SMARTCARD_ERROR_ORE              (0x00000008U)         /*!< Overrun error           */
-#define HAL_SMARTCARD_ERROR_DMA              (0x00000010U)         /*!< DMA transfer error      */
-#define HAL_SMARTCARD_ERROR_RTO              (0x00000020U)         /*!< Receiver TimeOut error  */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U)         /*!< Invalid Callback error  */
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
-  * @{
-  */
-#define SMARTCARD_WORDLENGTH_9B             USART_CR1_M0                    /*!< SMARTCARD frame length */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
-  * @{
-  */
-#define SMARTCARD_STOPBITS_0_5              USART_CR2_STOP_0                /*!< SMARTCARD frame with 0.5 stop bit  */
-#define SMARTCARD_STOPBITS_1_5              USART_CR2_STOP                  /*!< SMARTCARD frame with 1.5 stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Parity SMARTCARD Parity
-  * @{
-  */
-#define SMARTCARD_PARITY_EVEN               USART_CR1_PCE                   /*!< SMARTCARD frame even parity */
-#define SMARTCARD_PARITY_ODD                (USART_CR1_PCE | USART_CR1_PS)  /*!< SMARTCARD frame odd parity  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
-  * @{
-  */
-#define SMARTCARD_MODE_RX                   USART_CR1_RE                    /*!< SMARTCARD RX mode        */
-#define SMARTCARD_MODE_TX                   USART_CR1_TE                    /*!< SMARTCARD TX mode        */
-#define SMARTCARD_MODE_TX_RX                (USART_CR1_TE |USART_CR1_RE)    /*!< SMARTCARD RX and TX mode */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
-  * @{
-  */
-#define SMARTCARD_POLARITY_LOW              0x00000000U                     /*!< SMARTCARD frame low polarity  */
-#define SMARTCARD_POLARITY_HIGH             USART_CR2_CPOL                  /*!< SMARTCARD frame high polarity */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
-  * @{
-  */
-#define SMARTCARD_PHASE_1EDGE               0x00000000U                     /*!< SMARTCARD frame phase on first clock transition  */
-#define SMARTCARD_PHASE_2EDGE               USART_CR2_CPHA                  /*!< SMARTCARD frame phase on second clock transition */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
-  * @{
-  */
-#define SMARTCARD_LASTBIT_DISABLE           0x00000000U                     /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
-#define SMARTCARD_LASTBIT_ENABLE            USART_CR2_LBCL                  /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
-  * @{
-  */
-#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    0x00000000U                     /*!< SMARTCARD frame one-bit sample disabled */
-#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     USART_CR3_ONEBIT                /*!< SMARTCARD frame one-bit sample enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
-  * @{
-  */
-#define SMARTCARD_NACK_DISABLE              0x00000000U                     /*!< SMARTCARD NACK transmission disabled  */
-#define SMARTCARD_NACK_ENABLE               USART_CR3_NACK                  /*!< SMARTCARD NACK transmission enabled */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
-  * @{
-  */
-#define SMARTCARD_TIMEOUT_DISABLE           0x00000000U                     /*!< SMARTCARD receiver timeout disabled */
-#define SMARTCARD_TIMEOUT_ENABLE            USART_CR2_RTOEN                 /*!< SMARTCARD receiver timeout enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_TXINV_DISABLE  0x00000000U                  /*!< TX pin active level inversion disable */
-#define SMARTCARD_ADVFEATURE_TXINV_ENABLE   USART_CR2_TXINV              /*!< TX pin active level inversion enable  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_RXINV_DISABLE  0x00000000U                  /*!< RX pin active level inversion disable */
-#define SMARTCARD_ADVFEATURE_RXINV_ENABLE   USART_CR2_RXINV              /*!< RX pin active level inversion enable  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  0x00000000U                /*!< Binary data inversion disable */
-#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   USART_CR2_DATAINV          /*!< Binary data inversion enable  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_SWAP_DISABLE   0x00000000U                  /*!< TX/RX pins swap disable */
-#define SMARTCARD_ADVFEATURE_SWAP_ENABLE    USART_CR2_SWAP               /*!< TX/RX pins swap enable  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   0x00000000U                /*!< RX overrun enable  */
-#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  USART_CR3_OVRDIS           /*!< RX overrun disable */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   0x00000000U           /*!< DMA enable on Reception Error  */
-#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  USART_CR3_DDRE        /*!< DMA disable on Reception Error */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      0x00000000U           /*!< Most significant bit sent/received first disable */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       USART_CR2_MSBFIRST    /*!< Most significant bit sent/received first enable  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
-  * @{
-  */
-#define SMARTCARD_RXDATA_FLUSH_REQUEST      USART_RQR_RXFRQ              /*!< Receive data flush request */
-#define SMARTCARD_TXDATA_FLUSH_REQUEST      USART_RQR_TXFRQ              /*!< Transmit data flush request */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
-  * @{
-  */
-#define SMARTCARD_IT_MASK                   0x001FU   /*!< SMARTCARD interruptions flags mask  */
-#define SMARTCARD_CR_MASK                   0x00E0U   /*!< SMARTCARD control register mask     */
-#define SMARTCARD_CR_POS                    5U        /*!< SMARTCARD control register position */
-#define SMARTCARD_ISR_MASK                  0x1F00U   /*!< SMARTCARD ISR register mask         */
-#define SMARTCARD_ISR_POS                   8U        /*!< SMARTCARD ISR register position     */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
-  * @{
-  */
-
-/** @brief  Reset SMARTCARD handle states.
-  * @param  __HANDLE__ SMARTCARD handle.
-  * @retval None
-  */
-#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
-                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
-                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
-                                                            (__HANDLE__)->MspInitCallback = NULL;                 \
-                                                            (__HANDLE__)->MspDeInitCallback = NULL;               \
-                                                          } while(0U)
-#else
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
-                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
-                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
-                                                          } while(0U)
-#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS  */
-
-/** @brief  Flush the Smartcard Data registers.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                      \
-  do{                                                                     \
-    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
-    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
-  } while(0U)
-
-/** @brief  Clear the specified SMARTCARD pending flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
-  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
-  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
-  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
-  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
-  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
-  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
-  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
-  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief  Clear the SMARTCARD PE pending flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
-
-/** @brief  Clear the SMARTCARD FE pending flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
-
-/** @brief  Clear the SMARTCARD NE pending flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
-
-/** @brief  Clear the SMARTCARD ORE pending flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
-
-/** @brief  Clear the SMARTCARD IDLE pending flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
-
-/** @brief  Check whether the specified Smartcard flag is set or not.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
-  *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
-  *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
-  *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
-  *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
-  *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
-  *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
-  *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
-  *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
-  *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag
-  *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
-  *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
-  *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
-  *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Enable the specified SmartCard interrupt.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
-  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
-  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
-  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
-  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before
-  *                                          guard time interrupt (when interruption available)
-  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
-  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
-  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
-  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
-                                                                  SMARTCARD_CR_POS) == 1U)?\
-                                                                ((__HANDLE__)->Instance->CR1 |= (1UL <<\
-                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
-                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
-                                                                  SMARTCARD_CR_POS) == 2U)?\
-                                                                ((__HANDLE__)->Instance->CR2 |= (1UL <<\
-                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
-                                                                ((__HANDLE__)->Instance->CR3 |= (1UL <<\
-                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-
-/** @brief  Disable the specified SmartCard interrupt.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
-  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
-  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
-  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
-  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard
-  *                                          time interrupt (when interruption available)
-  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
-  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
-  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
-  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
-                                                                  SMARTCARD_CR_POS) == 1U)?\
-                                                                ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
-                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
-                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
-                                                                  SMARTCARD_CR_POS) == 2U)?\
-                                                                ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
-                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
-                                                                ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
-                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-
-/** @brief  Check whether the specified SmartCard interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
-  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
-  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
-  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
-  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time
-  *                                          interrupt (when interruption available)
-  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
-  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
-  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
-  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\
-                                                           (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
-                                                               & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
-                                                           ? SET : RESET)
-
-/** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
-  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
-  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
-  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
-  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time
-  *                                          interrupt (when interruption available)
-  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
-  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
-  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
-  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
-                                                                       SMARTCARD_CR_POS) == 0x01U)?\
-                                                                     (__HANDLE__)->Instance->CR1 : \
-                                                                     (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
-                                                                        SMARTCARD_CR_POS) == 0x02U)?\
-                                                                      (__HANDLE__)->Instance->CR2 : \
-                                                                      (__HANDLE__)->Instance->CR3)) &\
-                                                                    (0x01UL << (((uint16_t)(__INTERRUPT__))\
-                                                                                & SMARTCARD_IT_MASK)))  != 0U)\
-                                                                  ? SET : RESET)
-
-/** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
-  *                       to clear the corresponding interrupt.
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
-  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
-  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
-  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
-  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag
-  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
-  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
-  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
-  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
-
-/** @brief  Set a specific SMARTCARD request flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __REQ__ specifies the request flag to set
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
-  *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
-  * @retval None
-  */
-#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-
-/** @brief  Enable the SMARTCARD one bit sample method.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief  Disable the SMARTCARD one bit sample method.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
-                                                            &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable the USART associated to the SMARTCARD Handle.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
-
-/** @brief  Disable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
-
-/**
-  * @}
-  */
-
-/* Private macros -------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
-  * @{
-  */
-
-/** @brief  Report the SMARTCARD clock source.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __CLOCKSOURCE__ output variable.
-  * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
-  */
-#if defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L010xB) || defined (STM32L010x8)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
-  do {                                                         \
-    if((__HANDLE__)->Instance == USART2)                       \
-    {                                                          \
-      switch(__HAL_RCC_GET_USART2_SOURCE())                    \
-      {                                                        \
-        case RCC_USART2CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
-          break;                                               \
-        default:                                               \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
-          break;                                               \
-      }                                                        \
-    }                                                          \
-    else                                                       \
-    {                                                          \
-      (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
-    }                                                          \
-  } while(0U)
-
-#else /* (STM32L031xx) || defined (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) || defined (STM32L010xB) || defined (STM32L010x8)*/
-
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
-  do {                                                         \
-    if((__HANDLE__)->Instance == USART1)                       \
-    {                                                          \
-      switch(__HAL_RCC_GET_USART1_SOURCE())                    \
-      {                                                        \
-        case RCC_USART1CLKSOURCE_PCLK2:                        \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
-          break;                                               \
-        default:                                               \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
-          break;                                               \
-      }                                                        \
-    }                                                          \
-    else if((__HANDLE__)->Instance == USART2)                  \
-    {                                                          \
-      switch(__HAL_RCC_GET_USART2_SOURCE())                    \
-      {                                                        \
-        case RCC_USART2CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
-          break;                                               \
-        default:                                               \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
-          break;                                               \
-      }                                                        \
-    }                                                          \
-    else                                                       \
-    {                                                          \
-      (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
-    }                                                          \
-  } while(0U)
-#endif /* (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx) || (STM32L010xB) || (STM32L010x8)*/
-
-
-/** @brief  Check the Baud rate range.
-  * @note   The maximum Baud Rate is derived from the maximum clock on L0 (32 MHz)
-  *         divided by the oversampling used on the SMARTCARD (i.e. 16).
-  * @param  __BAUDRATE__ Baud rate set by the configuration function.
-  * @retval Test result (TRUE or FALSE)
-  */
-#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 2000001U)
-
-/** @brief  Check the block length range.
-  * @note   The maximum SMARTCARD block length is 0xFF.
-  * @param  __LENGTH__ block length.
-  * @retval Test result (TRUE or FALSE)
-  */
-#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
-
-/** @brief  Check the receiver timeout value.
-  * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
-  * @param  __TIMEOUTVALUE__ receiver timeout value.
-  * @retval Test result (TRUE or FALSE)
-  */
-#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
-
-/** @brief  Check the SMARTCARD autoretry counter value.
-  * @note   The maximum number of retransmissions is 0x7.
-  * @param  __COUNT__ number of retransmissions.
-  * @retval Test result (TRUE or FALSE)
-  */
-#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7U)
-
-/** @brief Ensure that SMARTCARD frame length is valid.
-  * @param __LENGTH__ SMARTCARD frame length.
-  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
-  */
-#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
-
-/** @brief Ensure that SMARTCARD frame number of stop bits is valid.
-  * @param __STOPBITS__ SMARTCARD frame number of stop bits.
-  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
-  */
-#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
-                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
-
-/** @brief Ensure that SMARTCARD frame parity is valid.
-  * @param __PARITY__ SMARTCARD frame parity.
-  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
-  */
-#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
-                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))
-
-/** @brief Ensure that SMARTCARD communication mode is valid.
-  * @param __MODE__ SMARTCARD communication mode.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
-
-/** @brief Ensure that SMARTCARD frame polarity is valid.
-  * @param __CPOL__ SMARTCARD frame polarity.
-  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
-  */
-#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
-                                         || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
-
-/** @brief Ensure that SMARTCARD frame phase is valid.
-  * @param __CPHA__ SMARTCARD frame phase.
-  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
-  */
-#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
-
-/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
-  * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
-  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
-  */
-#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
-                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
-
-/** @brief Ensure that SMARTCARD frame sampling is valid.
-  * @param __ONEBIT__ SMARTCARD frame sampling.
-  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
-  */
-#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
-                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
-
-/** @brief Ensure that SMARTCARD NACK transmission setting is valid.
-  * @param __NACK__ SMARTCARD NACK transmission setting.
-  * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
-  */
-#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
-                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))
-
-/** @brief Ensure that SMARTCARD receiver timeout setting is valid.
-  * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
-  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
-  */
-#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
-                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
-
-/** @brief Ensure that SMARTCARD advanced features initialization is valid.
-  * @param __INIT__ SMARTCARD advanced features initialization.
-  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
-                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
-                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
-                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
-                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
-                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
-                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
-                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
-
-/** @brief Ensure that SMARTCARD frame TX inversion setting is valid.
-  * @param __TXINV__ SMARTCARD frame TX inversion setting.
-  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
-                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
-
-/** @brief Ensure that SMARTCARD frame RX inversion setting is valid.
-  * @param __RXINV__ SMARTCARD frame RX inversion setting.
-  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
-                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
-
-/** @brief Ensure that SMARTCARD frame data inversion setting is valid.
-  * @param __DATAINV__ SMARTCARD frame data inversion setting.
-  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
-                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
-
-/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
-  * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
-  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
-                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
-
-/** @brief Ensure that SMARTCARD frame overrun setting is valid.
-  * @param __OVERRUN__ SMARTCARD frame overrun setting.
-  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
-  */
-#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
-                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
-
-/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
-  * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
-  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
-                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
-
-/** @brief Ensure that SMARTCARD frame MSB first setting is valid.
-  * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
-  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
-                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
-
-/** @brief Ensure that SMARTCARD request parameter is valid.
-  * @param __PARAM__ SMARTCARD request parameter.
-  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
-  */
-#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
-                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
-
-/**
-  * @}
-  */
-
-/* Include SMARTCARD HAL Extended module */
-#include "stm32l0xx_hal_smartcard_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARD_Exported_Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-/** @addtogroup SMARTCARD_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
-                                                 HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
-                                                 pSMARTCARD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
-                                                   HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup SMARTCARD_Exported_Functions_Group2
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
-                                         uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
-                                        uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
-  * @}
-  */
-
-/* Peripheral State and Error functions ***************************************/
-/** @addtogroup SMARTCARD_Exported_Functions_Group4
-  * @{
-  */
-
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
-uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* !defined (STM32L010x4) && !defined (STM32L010x6) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_SMARTCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard_ex.h
deleted file mode 100644
index 1488633922..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard_ex.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_smartcard_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of SMARTCARD HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_SMARTCARD_EX_H
-#define STM32L0xx_HAL_SMARTCARD_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined (STM32L010x4) && !defined (STM32L010x6)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SMARTCARDEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
-  * @{
-  */
-#if defined(USART_TCBGT_SUPPORT)
-#define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
-#endif /* USART_TCBGT_SUPPORT */
-#define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_NO_INIT                 0x00000000U    /*!< No advanced feature initialization                  */
-#define SMARTCARD_ADVFEATURE_TXINVERT_INIT           0x00000001U    /*!< TX pin active level inversion                       */
-#define SMARTCARD_ADVFEATURE_RXINVERT_INIT           0x00000002U    /*!< RX pin active level inversion                       */
-#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         0x00000004U    /*!< Binary data inversion                               */
-#define SMARTCARD_ADVFEATURE_SWAP_INIT               0x00000008U    /*!< TX/RX pins swap                                     */
-#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U    /*!< RX overrun disable                                  */
-#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U    /*!< DMA disable on Reception Error                      */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           0x00000080U    /*!< Most significant bit sent/received first            */
-#if defined(USART_TCBGT_SUPPORT)
-#define SMARTCARD_ADVFEATURE_TXCOMPLETION            0x00000100U    /*!< TX completion indication before of after guard time */
-#endif /* USART_TCBGT_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the ISR register
-  * @{
-  */
-#if defined(USART_TCBGT_SUPPORT)
-#define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT         /*!< SMARTCARD transmission complete before guard time completion */
-#endif /* USART_TCBGT_SUPPORT */
-#define SMARTCARD_FLAG_REACK          USART_ISR_REACK         /*!< SMARTCARD receive enable acknowledge flag  */
-#define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK         /*!< SMARTCARD transmit enable acknowledge flag */
-#define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY          /*!< SMARTCARD busy flag                        */
-#define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF          /*!< SMARTCARD end of block flag                */
-#define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF          /*!< SMARTCARD receiver timeout flag            */
-#define SMARTCARD_FLAG_TXE            USART_ISR_TXE           /*!< SMARTCARD transmit data register empty     */
-#define SMARTCARD_FLAG_TC             USART_ISR_TC            /*!< SMARTCARD transmission complete            */
-#define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE          /*!< SMARTCARD read data register not empty     */
-#define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE          /*!< SMARTCARD idle line detection              */
-#define SMARTCARD_FLAG_ORE            USART_ISR_ORE           /*!< SMARTCARD overrun error                    */
-#define SMARTCARD_FLAG_NE             USART_ISR_NE            /*!< SMARTCARD noise error                      */
-#define SMARTCARD_FLAG_FE             USART_ISR_FE            /*!< SMARTCARD frame error                      */
-#define SMARTCARD_FLAG_PE             USART_ISR_PE            /*!< SMARTCARD parity error                     */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
-  *        Elements values convention: 000ZZZZZ0XXYYYYYb
-  *           - YYYYY  : Interrupt source position in the XX register (5 bits)
-  *           - XX  : Interrupt source register (2 bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  *           - ZZZZZ  : Flag position in the ISR register(5 bits)
-  * @{
-  */
-#define SMARTCARD_IT_PE                     0x0028U           /*!< SMARTCARD parity error interruption                 */
-#define SMARTCARD_IT_TXE                    0x0727U           /*!< SMARTCARD transmit data register empty interruption */
-#define SMARTCARD_IT_TC                     0x0626U           /*!< SMARTCARD transmission complete interruption        */
-#define SMARTCARD_IT_RXNE                   0x0525U           /*!< SMARTCARD read data register not empty interruption */
-#define SMARTCARD_IT_IDLE                   0x0424U           /*!< SMARTCARD idle line detection interruption          */
-
-#define SMARTCARD_IT_ERR                    0x0060U           /*!< SMARTCARD error interruption         */
-#define SMARTCARD_IT_ORE                    0x0300U           /*!< SMARTCARD overrun error interruption */
-#define SMARTCARD_IT_NE                     0x0200U           /*!< SMARTCARD noise error interruption   */
-#define SMARTCARD_IT_FE                     0x0100U           /*!< SMARTCARD frame error interruption   */
-
-#define SMARTCARD_IT_EOB                    0x0C3BU           /*!< SMARTCARD end of block interruption     */
-#define SMARTCARD_IT_RTO                    0x0B3AU           /*!< SMARTCARD receiver timeout interruption */
-#if defined(USART_TCBGT_SUPPORT)
-#define SMARTCARD_IT_TCBGT                  0x1978U           /*!< SMARTCARD transmission complete before guard time completion interruption */
-#endif /* USART_TCBGT_SUPPORT */
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
-  * @{
-  */
-#define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
-#define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
-#define SMARTCARD_CLEAR_NEF                 USART_ICR_NCF     /*!< SMARTCARD noise error detected clear flag  */
-#define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
-#define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
-#define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
-#if defined(USART_TCBGT_SUPPORT)
-#define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
-#endif /* USART_TCBGT_SUPPORT */
-#define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
-#define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported macros -----------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
-  * @{
-  */
-
-/** @brief  Set the Transmission Completion flag
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @note  If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
-  *        AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
-  *        to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
-  * @retval None
-  */
-#if defined(USART_TCBGT_SUPPORT)
-#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \
-  do {                                                                                                       \
-    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
-    {                                                                                                        \
-      (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                      \
-    }                                                                                                        \
-    else                                                                                                     \
-    {                                                                                                        \
-      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
-    }                                                                                                        \
-  } while(0U)
-#else
-#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)         \
-  do {                                                                \
-    (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
-  } while(0U)
-#endif /* USART_TCBGT_SUPPORT */
-
-/** @brief  Return the transmission completion flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
-  *        When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
-  *        reported.
-  * @retval Transmission completion flag
-  */
-#if defined(USART_TCBGT_SUPPORT)
-#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)  \
-  (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))
-#else
-#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)    (SMARTCARD_FLAG_TC)
-#endif /* USART_TCBGT_SUPPORT */
-
-
-/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
-  * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
-  * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
-  */
-#if defined(USART_TCBGT_SUPPORT)
-#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
-                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))
-#else
-#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
-#endif /* USART_TCBGT_SUPPORT */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARDEx_Exported_Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-/* IO operation methods *******************************************************/
-
-/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* Peripheral Control functions ***********************************************/
-void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
-void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
-HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARDEx_Exported_Functions_Group2
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* !defined (STM32L010x4) && !defined (STM32L010x6) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_SMARTCARD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus.h
deleted file mode 100644
index 08851e6586..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus.h
+++ /dev/null
@@ -1,791 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_smbus.h
-  * @author  MCD Application Team
-  * @brief   Header file of SMBUS HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_SMBUS_H
-#define STM32L0xx_HAL_SMBUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SMBUS
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
-  * @{
-  */
-
-/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
-  * @brief  SMBUS Configuration Structure definition
-  * @{
-  */
-typedef struct
-{
-  uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
-                                        This parameter calculated by referring to SMBUS initialization section
-                                        in Reference manual */
-  uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
-                                        This parameter can be a value of @ref SMBUS_Analog_Filter */
-
-  uint32_t OwnAddress1;            /*!< Specifies the first device own address.
-                                        This parameter can be a 7-bit or 10-bit address. */
-
-  uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
-                                        This parameter can be a value of @ref SMBUS_addressing_mode */
-
-  uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
-                                        This parameter can be a value of @ref SMBUS_dual_addressing_mode */
-
-  uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
-                                        This parameter can be a 7-bit address. */
-
-  uint32_t OwnAddress2Masks;       /*!< Specifies the acknowledge mask address second device own address
-                                        if dual addressing mode is selected
-                                        This parameter can be a value of @ref SMBUS_own_address2_masks. */
-
-  uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
-                                        This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
-
-  uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
-                                        This parameter can be a value of @ref SMBUS_nostretch_mode */
-
-  uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
-                                        This parameter can be a value of @ref SMBUS_packet_error_check_mode */
-
-  uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
-                                        This parameter can be a value of @ref SMBUS_peripheral_mode */
-
-  uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
-                                        (Enable bits and different timeout values)
-                                        This parameter calculated by referring to SMBUS initialization section
-                                        in Reference manual */
-} SMBUS_InitTypeDef;
-/**
-  * @}
-  */
-
-/** @defgroup HAL_state_definition HAL state definition
-  * @brief  HAL State definition
-  * @{
-  */
-#define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
-#define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
-#define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
-#define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
-#define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
-#define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
-#define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
-#define HAL_SMBUS_STATE_LISTEN          (0x00000008U)  /*!< Address Listen Mode is ongoing                */
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
-  * @brief  SMBUS Error Code definition
-  * @{
-  */
-#define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
-#define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
-#define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
-#define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
-#define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
-#define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
-#define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
-#define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
-#define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-#define HAL_SMBUS_ERROR_INVALID_CALLBACK  (0x00000100U)  /*!< Invalid Callback error   */
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-#define HAL_SMBUS_ERROR_INVALID_PARAM    (0x00000200U)   /*!< Invalid Parameters error */
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
-  * @brief  SMBUS handle Structure definition
-  * @{
-  */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-typedef struct __SMBUS_HandleTypeDef
-#else
-typedef struct
-#endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-{
-  I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
-
-  SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
-
-  uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
-
-  uint16_t                     XferSize;        /*!< SMBUS transfer size                */
-
-  __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
-
-  __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
-
-  __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
-
-  HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
-
-  __IO uint32_t                State;           /*!< SMBUS communication state          */
-
-  __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
-
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-  void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Master Tx Transfer completed callback */
-  void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Master Rx Transfer completed callback */
-  void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Slave Tx Transfer completed callback  */
-  void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Slave Rx Transfer completed callback  */
-  void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Listen Complete callback              */
-  void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Error callback                        */
-
-  void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
-  /*!< SMBUS Slave Address Match callback */
-
-  void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Msp Init callback                     */
-  void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Msp DeInit callback                   */
-
-#endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-} SMBUS_HandleTypeDef;
-
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL SMBUS Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< SMBUS Master Tx Transfer completed callback ID  */
-  HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< SMBUS Master Rx Transfer completed callback ID  */
-  HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< SMBUS Slave Tx Transfer completed callback ID   */
-  HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< SMBUS Slave Rx Transfer completed callback ID   */
-  HAL_SMBUS_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< SMBUS Listen Complete callback ID               */
-  HAL_SMBUS_ERROR_CB_ID                   = 0x05U,    /*!< SMBUS Error callback ID                         */
-
-  HAL_SMBUS_MSPINIT_CB_ID                 = 0x06U,    /*!< SMBUS Msp Init callback ID                      */
-  HAL_SMBUS_MSPDEINIT_CB_ID               = 0x07U     /*!< SMBUS Msp DeInit callback ID                    */
-
-} HAL_SMBUS_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SMBUS Callback pointer definition
-  */
-typedef  void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
-/*!< pointer to an SMBUS callback function */
-typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
-                                            uint16_t AddrMatchCode);
-/*!< pointer to an SMBUS Address Match callback function */
-
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
-  * @{
-  */
-
-/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
-  * @{
-  */
-#define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
-#define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
-  * @{
-  */
-#define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
-#define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
-  * @{
-  */
-
-#define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
-#define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
-  * @{
-  */
-
-#define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
-#define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
-#define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
-#define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
-#define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
-#define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
-#define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
-#define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
-/**
-  * @}
-  */
-
-
-/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
-  * @{
-  */
-#define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
-#define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
-  * @{
-  */
-#define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
-#define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
-  * @{
-  */
-#define SMBUS_PEC_DISABLE                       (0x00000000U)
-#define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
-  * @{
-  */
-#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
-#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
-#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
-  * @{
-  */
-
-#define  SMBUS_SOFTEND_MODE                     (0x00000000U)
-#define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
-#define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
-#define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
-  * @{
-  */
-
-#define  SMBUS_NO_STARTSTOP                     (0x00000000U)
-#define  SMBUS_GENERATE_STOP                    (uint32_t)(0x80000000U | I2C_CR2_STOP)
-#define  SMBUS_GENERATE_START_READ              (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-#define  SMBUS_GENERATE_START_WRITE             (uint32_t)(0x80000000U | I2C_CR2_START)
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
-  * @{
-  */
-
-/* List of XferOptions in usage of :
- * 1- Restart condition when direction change
- * 2- No Restart condition in other use cases
- */
-#define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
-#define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
-#define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
-#define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
-#define  SMBUS_FIRST_FRAME_WITH_PEC             ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
-#define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
-#define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
-
-/* List of XferOptions in usage of :
- * 1- Restart condition in all use cases (direction change or not)
- */
-#define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
-#define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
-#define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
-#define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
-  * @brief SMBUS Interrupt definition
-  *        Elements values convention: 0xXXXXXXXX
-  *           - XXXXXXXX  : Interrupt control mask
-  * @{
-  */
-#define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
-#define SMBUS_IT_TCI                            I2C_CR1_TCIE
-#define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
-#define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
-#define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
-#define SMBUS_IT_RXI                            I2C_CR1_RXIE
-#define SMBUS_IT_TXI                            I2C_CR1_TXIE
-#define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
-                                                 SMBUS_IT_NACKI | SMBUS_IT_TXI)
-#define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
-                                                 SMBUS_IT_RXI)
-#define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
-#define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
-  * @brief Flag definition
-  *        Elements values convention: 0xXXXXYYYY
-  *           - XXXXXXXX  : Flag mask
-  * @{
-  */
-
-#define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
-#define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
-#define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
-#define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
-#define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
-#define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
-#define  SMBUS_FLAG_TC                          I2C_ISR_TC
-#define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
-#define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
-#define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
-#define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
-#define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
-#define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
-#define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
-#define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
-#define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros ------------------------------------------------------------*/
-/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
-  * @{
-  */
-
-/** @brief  Reset SMBUS handle state.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @retval None
-  */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)           do{                                               \
-                                                                 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;  \
-                                                                 (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                 (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                               } while(0)
-#else
-#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)         ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-
-/** @brief  Enable the specified SMBUS interrupts.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
-  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
-  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
-  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
-  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
-  *
-  * @retval None
-  */
-#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
-
-/** @brief  Disable the specified SMBUS interrupts.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
-  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
-  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
-  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
-  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
-  *
-  * @retval None
-  */
-#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
-/** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
-  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
-  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
-  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
-  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
-  *
-  * @retval The new state of __IT__ (SET or RESET).
-  */
-#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
-  ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified SMBUS flag is set or not.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
-  *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
-  *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
-  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref SMBUS_FLAG_AF      NACK received flag
-  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
-  *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
-  *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
-  *            @arg @ref SMBUS_FLAG_BERR    Bus error
-  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
-  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
-  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
-  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
-  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
-  *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
-  *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
-  *
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define SMBUS_FLAG_MASK  (0x0001FFFFU)
-#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
-  (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
-    ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
-
-/** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref SMBUS_FLAG_AF      NACK received flag
-  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
-  *            @arg @ref SMBUS_FLAG_BERR    Bus error
-  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
-  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
-  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
-  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
-  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
-  *
-  * @retval None
-  */
-#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief  Enable the specified SMBUS peripheral.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @retval None
-  */
-#define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief  Disable the specified SMBUS peripheral.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @retval None
-  */
-#define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @retval None
-  */
-#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
-
-/**
-  * @}
-  */
-
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
-  * @{
-  */
-
-#define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
-                                                         ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
-
-#define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
-
-#define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
-                                                         ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
-
-#define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
-                                                         ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
-
-#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK07))
-
-#define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
-                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))
-
-#define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
-                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
-
-#define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
-                                                         ((PEC) == SMBUS_PEC_ENABLE))
-
-#define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)   || \
-                                                         ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
-                                                         ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
-
-#define IS_SMBUS_TRANSFER_MODE(MODE)                 (((MODE) == SMBUS_RELOAD_MODE)                          || \
-                                                      ((MODE) == SMBUS_AUTOEND_MODE)                         || \
-                                                      ((MODE) == SMBUS_SOFTEND_MODE)                         || \
-                                                      ((MODE) == SMBUS_SENDPEC_MODE)                         || \
-                                                      ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
-                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
-                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
-                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
-                                                                  SMBUS_RELOAD_MODE )))
-
-
-#define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
-                                                         ((REQUEST) == SMBUS_GENERATE_START_READ)        || \
-                                                         ((REQUEST) == SMBUS_GENERATE_START_WRITE)       || \
-                                                         ((REQUEST) == SMBUS_NO_STARTSTOP))
-
-
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)   (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
-                                                      ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
-                                                      ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
-                                                      ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
-                                                      ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
-                                                      ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC)              || \
-                                                      ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
-                                                      ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
-
-#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)             || \
-                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)    || \
-                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)           || \
-                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
-
-#define SMBUS_RESET_CR1(__HANDLE__)                    ((__HANDLE__)->Instance->CR1 &= \
-                                                        (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
-                                                                               I2C_CR1_PECEN)))
-#define SMBUS_RESET_CR2(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 &= \
-                                                        (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
-                                                                               I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
-                                                                               I2C_CR2_RD_WRN)))
-
-#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
-                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
-                                                                       (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
-                                                                      (~I2C_CR2_RD_WRN)) : \
-                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & \
-                                                                        (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
-                                                                       (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-
-#define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
-#define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
-#define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
-#define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
-
-#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
-                                                          ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
-#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__)          ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
-
-#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
-#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
-
-/**
-  * @}
-  */
-
-/* Include SMBUS HAL Extended module */
-#include "stm32l0xx_hal_smbus_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
-  * @{
-  */
-
-/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
-                                             HAL_SMBUS_CallbackIDTypeDef CallbackID,
-                                             pSMBUS_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
-                                               HAL_SMBUS_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
-                                                 pSMBUS_AddrCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-
-/* IO operation functions  *****************************************************/
-/** @addtogroup Blocking_mode_Polling Blocking mode Polling
-  * @{
-  */
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
-                                          uint32_t Timeout);
-/**
-  * @}
-  */
-
-/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
-  * @{
-  */
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
-                                               uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
-                                              uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
-                                              uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
-                                             uint32_t XferOptions);
-
-HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
-/**
-  * @}
-  */
-
-/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
-  * @{
-  */
-/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
-void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
-
-/**
-  * @}
-  */
-
-/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
-  *  @{
-  */
-
-/* Peripheral State and Errors functions  **************************************************/
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32l0xx_hal_smbus.c file */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L0xx_HAL_SMBUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus_ex.h
deleted file mode 100644
index 1f0e6f25b8..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus_ex.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_smbus_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of SMBUS HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_SMBUS_EX_H
-#define STM32L0xx_HAL_SMBUS_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SMBUSEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
-  * @{
-  */
-#define SMBUS_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
-#if defined(SYSCFG_CFGR2_I2C_PB6_FMP)
-#define SMBUS_FASTMODEPLUS_PB6            SYSCFG_CFGR2_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
-#define SMBUS_FASTMODEPLUS_PB7            SYSCFG_CFGR2_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
-#else
-#define SMBUS_FASTMODEPLUS_PB6            (uint32_t)(0x00000004U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported   */
-#define SMBUS_FASTMODEPLUS_PB7            (uint32_t)(0x00000008U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported   */
-#endif /* SYSCFG_CFGR2_I2C_PB6_FMP */
-#if defined(SYSCFG_CFGR2_I2C_PB8_FMP)
-#define SMBUS_FASTMODEPLUS_PB8            SYSCFG_CFGR2_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
-#define SMBUS_FASTMODEPLUS_PB9            SYSCFG_CFGR2_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
-#else
-#define SMBUS_FASTMODEPLUS_PB8            (uint32_t)(0x00000010U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported   */
-#define SMBUS_FASTMODEPLUS_PB9            (uint32_t)(0x00000012U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported   */
-#endif /* SYSCFG_CFGR2_I2C_PB8_FMP */
-#if defined(SYSCFG_CFGR2_I2C1_FMP)
-#define SMBUS_FASTMODEPLUS_I2C1           SYSCFG_CFGR2_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
-#else
-#define SMBUS_FASTMODEPLUS_I2C1           (uint32_t)(0x00000100U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported  */
-#endif /* SYSCFG_CFGR2_I2C1_FMP */
-#if defined(SYSCFG_CFGR2_I2C2_FMP)
-#define SMBUS_FASTMODEPLUS_I2C2           SYSCFG_CFGR2_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
-#else
-#define SMBUS_FASTMODEPLUS_I2C2           (uint32_t)(0x00000200U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported  */
-#endif /* SYSCFG_CFGR2_I2C2_FMP */
-#if defined(SYSCFG_CFGR2_I2C3_FMP)
-#define SMBUS_FASTMODEPLUS_I2C3           SYSCFG_CFGR2_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
-#else
-#define SMBUS_FASTMODEPLUS_I2C3           (uint32_t)(0x00000400U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported  */
-#endif /* SYSCFG_CFGR2_I2C3_FMP */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
-  * @{
-  */
-
-/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus);
-/**
-  * @}
-  */
-
-/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
-  * @{
-  */
-#if  (defined(SYSCFG_CFGR2_I2C_PB6_FMP) || defined(SYSCFG_CFGR2_I2C_PB7_FMP)) || (defined(SYSCFG_CFGR2_I2C_PB8_FMP) || defined(SYSCFG_CFGR2_I2C_PB9_FMP)) || (defined(SYSCFG_CFGR2_I2C1_FMP)) || defined(SYSCFG_CFGR2_I2C2_FMP) || defined(SYSCFG_CFGR2_I2C3_FMP)
-void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
-void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
-#endif /* Fast Mode Plus Availability */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
-  * @{
-  */
-#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FMP_NOT_SUPPORTED) != SMBUS_FMP_NOT_SUPPORTED) && \
-                                           ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6))  == SMBUS_FASTMODEPLUS_PB6)  || \
-                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7))  == SMBUS_FASTMODEPLUS_PB7)  || \
-                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8))  == SMBUS_FASTMODEPLUS_PB8)  || \
-                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9))  == SMBUS_FASTMODEPLUS_PB9)  || \
-                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
-                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
-                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3)))
-/**
-  * @}
-  */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32l0xx_hal_smbus_ex.c file */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_SMBUS_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h
deleted file mode 100644
index 31244f6cbb..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h
+++ /dev/null
@@ -1,736 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_spi.h
-  * @author  MCD Application Team
-  * @brief   Header file of SPI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_SPI_H
-#define STM32L0xx_HAL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
-  * @{
-  */
-
-/**
-  * @brief  SPI Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Mode;                /*!< Specifies the SPI operating mode.
-                                     This parameter can be a value of @ref SPI_Mode */
-
-  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
-                                     This parameter can be a value of @ref SPI_Direction */
-
-  uint32_t DataSize;            /*!< Specifies the SPI data size.
-                                     This parameter can be a value of @ref SPI_Data_Size */
-
-  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
-                                     This parameter can be a value of @ref SPI_Clock_Polarity */
-
-  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
-                                     This parameter can be a value of @ref SPI_Clock_Phase */
-
-  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
-                                     hardware (NSS pin) or by software using the SSI bit.
-                                     This parameter can be a value of @ref SPI_Slave_Select_management */
-
-  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
-                                     used to configure the transmit and receive SCK clock.
-                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
-                                     @note The communication clock is derived from the master
-                                     clock. The slave clock does not need to be set. */
-
-  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
-  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
-                                     This parameter can be a value of @ref SPI_TI_mode */
-
-  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
-                                     This parameter can be a value of @ref SPI_CRC_Calculation */
-
-  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
-                                     This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
-} SPI_InitTypeDef;
-
-/**
-  * @brief  HAL SPI State structure definition
-  */
-typedef enum
-{
-  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
-  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
-  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
-  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
-  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
-  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
-  HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
-} HAL_SPI_StateTypeDef;
-
-/**
-  * @brief  SPI handle Structure definition
-  */
-typedef struct __SPI_HandleTypeDef
-{
-  SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
-
-  SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
-
-  uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
-
-  uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
-
-  __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
-
-  uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
-
-  uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
-
-  __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
-
-  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */
-
-  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */
-
-  DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
-
-  DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
-
-  HAL_LockTypeDef            Lock;           /*!< Locking object                           */
-
-  __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
-
-  __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Tx Completed callback          */
-  void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Rx Completed callback          */
-  void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);           /*!< SPI TxRx Completed callback        */
-  void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Tx Half Completed callback     */
-  void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Rx Half Completed callback     */
-  void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI TxRx Half Completed callback   */
-  void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);              /*!< SPI Error callback                 */
-  void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Abort callback                 */
-  void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);            /*!< SPI Msp Init callback              */
-  void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Msp DeInit callback            */
-
-#endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */
-} SPI_HandleTypeDef;
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  HAL SPI Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SPI_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SPI Tx Completed callback ID         */
-  HAL_SPI_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SPI Rx Completed callback ID         */
-  HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02U,    /*!< SPI TxRx Completed callback ID       */
-  HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< SPI Tx Half Completed callback ID    */
-  HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< SPI Rx Half Completed callback ID    */
-  HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05U,    /*!< SPI TxRx Half Completed callback ID  */
-  HAL_SPI_ERROR_CB_ID                   = 0x06U,    /*!< SPI Error callback ID                */
-  HAL_SPI_ABORT_CB_ID                   = 0x07U,    /*!< SPI Abort callback ID                */
-  HAL_SPI_MSPINIT_CB_ID                 = 0x08U,    /*!< SPI Msp Init callback ID             */
-  HAL_SPI_MSPDEINIT_CB_ID               = 0x09U     /*!< SPI Msp DeInit callback ID           */
-
-} HAL_SPI_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SPI Callback pointer definition
-  */
-typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
-
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
-  * @{
-  */
-
-/** @defgroup SPI_Error_Code SPI Error Code
-  * @{
-  */
-#define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
-#define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
-#define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
-#define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
-#define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
-#define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
-#define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY Flag             */
-#define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define HAL_SPI_ERROR_INVALID_CALLBACK  (0x00000080U)   /*!< Invalid Callback error                 */
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Mode SPI Mode
-  * @{
-  */
-#define SPI_MODE_SLAVE                  (0x00000000U)
-#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Direction SPI Direction Mode
-  * @{
-  */
-#define SPI_DIRECTION_2LINES            (0x00000000U)
-#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Data_Size SPI Data Size
-  * @{
-  */
-#define SPI_DATASIZE_8BIT               (0x00000000U)
-#define SPI_DATASIZE_16BIT              SPI_CR1_DFF
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
-  * @{
-  */
-#define SPI_POLARITY_LOW                (0x00000000U)
-#define SPI_POLARITY_HIGH               SPI_CR1_CPOL
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
-  * @{
-  */
-#define SPI_PHASE_1EDGE                 (0x00000000U)
-#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
-  * @{
-  */
-#define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              (0x00000000U)
-#define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
-  * @{
-  */
-#define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
-#define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
-  * @{
-  */
-#define SPI_FIRSTBIT_MSB                (0x00000000U)
-#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
-/**
-  * @}
-  */
-
-/** @defgroup SPI_TI_mode SPI TI Mode
-  * @{
-  */
-#define SPI_TIMODE_DISABLE              (0x00000000U)
-#define SPI_TIMODE_ENABLE               SPI_CR2_FRF
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
-  * @{
-  */
-#define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
-#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
-  * @{
-  */
-#define SPI_IT_TXE                      SPI_CR2_TXEIE
-#define SPI_IT_RXNE                     SPI_CR2_RXNEIE
-#define SPI_IT_ERR                      SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Flags_definition SPI Flags Definition
-  * @{
-  */
-#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
-#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
-#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
-#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
-#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
-#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_MASK                   (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
-                                         | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
-  * @{
-  */
-
-/** @brief  Reset SPI handle state.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
-                                                                    (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                  } while(0)
-#else
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-
-/** @brief  Enable the specified SPI interrupts.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief  Disable the specified SPI interrupts.
-  * @param  __HANDLE__ specifies the SPI handle.
-  *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief  Check whether the specified SPI interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
-                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
-  *            @arg SPI_FLAG_CRCERR: CRC error flag
-  *            @arg SPI_FLAG_MODF: Mode fault flag
-  *            @arg SPI_FLAG_OVR: Overrun flag
-  *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the SPI CRCERR pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-
-/** @brief  Clear the SPI MODF pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
-  do{                                                    \
-    __IO uint32_t tmpreg_modf = 0x00U;                   \
-    tmpreg_modf = (__HANDLE__)->Instance->SR;            \
-    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
-    UNUSED(tmpreg_modf);                                 \
-  } while(0U)
-
-/** @brief  Clear the SPI OVR pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
-  do{                                              \
-    __IO uint32_t tmpreg_ovr = 0x00U;              \
-    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
-    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
-    UNUSED(tmpreg_ovr);                            \
-  } while(0U)
-
-/** @brief  Clear the SPI FRE pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
-  do{                                              \
-    __IO uint32_t tmpreg_fre = 0x00U;              \
-    tmpreg_fre = (__HANDLE__)->Instance->SR;       \
-    UNUSED(tmpreg_fre);                            \
-  }while(0U)
-
-/** @brief  Enable the SPI peripheral.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/** @brief  Disable the SPI peripheral.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
-  * @{
-  */
-
-/** @brief  Set the SPI transmit-only mode.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief  Set the SPI receive-only mode.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief  Reset the CRC calculation of the SPI.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
-                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __SR__  copy of SPI SR register.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
-  *            @arg SPI_FLAG_CRCERR: CRC error flag
-  *            @arg SPI_FLAG_MODF: Mode fault flag
-  *            @arg SPI_FLAG_OVR: Overrun flag
-  *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag
-  * @retval SET or RESET.
-  */
-#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
-                                          ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI Interrupt is set or not.
-  * @param  __CR2__  copy of SPI CR2 register.
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval SET or RESET.
-  */
-#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
-                                                     (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks if SPI Mode parameter is in allowed range.
-  * @param  __MODE__ specifies the SPI Mode.
-  *         This parameter can be a value of @ref SPI_Mode
-  * @retval None
-  */
-#define IS_SPI_MODE(__MODE__)      (((__MODE__) == SPI_MODE_SLAVE)   || \
-                                    ((__MODE__) == SPI_MODE_MASTER))
-
-/** @brief  Checks if SPI Direction Mode parameter is in allowed range.
-  * @param  __MODE__ specifies the SPI Direction Mode.
-  *         This parameter can be a value of @ref SPI_Direction
-  * @retval None
-  */
-#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)        || \
-                                    ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
-                                    ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief  Checks if SPI Direction Mode parameter is 2 lines.
-  * @param  __MODE__ specifies the SPI Direction Mode.
-  * @retval None
-  */
-#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
-
-/** @brief  Checks if SPI Direction Mode parameter is 1 or 2 lines.
-  * @param  __MODE__ specifies the SPI Direction Mode.
-  * @retval None
-  */
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
-                                                    ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief  Checks if SPI Data Size parameter is in allowed range.
-  * @param  __DATASIZE__ specifies the SPI Data Size.
-  *         This parameter can be a value of @ref SPI_Data_Size
-  * @retval None
-  */
-#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_8BIT))
-
-/** @brief  Checks if SPI Serial clock steady state parameter is in allowed range.
-  * @param  __CPOL__ specifies the SPI serial clock steady state.
-  *         This parameter can be a value of @ref SPI_Clock_Polarity
-  * @retval None
-  */
-#define IS_SPI_CPOL(__CPOL__)      (((__CPOL__) == SPI_POLARITY_LOW) || \
-                                    ((__CPOL__) == SPI_POLARITY_HIGH))
-
-/** @brief  Checks if SPI Clock Phase parameter is in allowed range.
-  * @param  __CPHA__ specifies the SPI Clock Phase.
-  *         This parameter can be a value of @ref SPI_Clock_Phase
-  * @retval None
-  */
-#define IS_SPI_CPHA(__CPHA__)      (((__CPHA__) == SPI_PHASE_1EDGE) || \
-                                    ((__CPHA__) == SPI_PHASE_2EDGE))
-
-/** @brief  Checks if SPI Slave Select parameter is in allowed range.
-  * @param  __NSS__ specifies the SPI Slave Select management parameter.
-  *         This parameter can be a value of @ref SPI_Slave_Select_management
-  * @retval None
-  */
-#define IS_SPI_NSS(__NSS__)        (((__NSS__) == SPI_NSS_SOFT)       || \
-                                    ((__NSS__) == SPI_NSS_HARD_INPUT) || \
-                                    ((__NSS__) == SPI_NSS_HARD_OUTPUT))
-
-/** @brief  Checks if SPI Baudrate prescaler parameter is in allowed range.
-  * @param  __PRESCALER__ specifies the SPI Baudrate prescaler.
-  *         This parameter can be a value of @ref SPI_BaudRate_Prescaler
-  * @retval None
-  */
-#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
-
-/** @brief  Checks if SPI MSB LSB transmission parameter is in allowed range.
-  * @param  __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
-  *         This parameter can be a value of @ref SPI_MSB_LSB_transmission
-  * @retval None
-  */
-#define IS_SPI_FIRST_BIT(__BIT__)  (((__BIT__) == SPI_FIRSTBIT_MSB) || \
-                                    ((__BIT__) == SPI_FIRSTBIT_LSB))
-
-/** @brief  Checks if SPI TI mode parameter is in allowed range.
-  * @param  __MODE__ specifies the SPI TI mode.
-  *         This parameter can be a value of @ref SPI_TI_mode
-  * @retval None
-  */
-#define IS_SPI_TIMODE(__MODE__)    (((__MODE__) == SPI_TIMODE_DISABLE) || \
-                                    ((__MODE__) == SPI_TIMODE_ENABLE))
-
-/** @brief  Checks if SPI CRC calculation enabled state is in allowed range.
-  * @param  __CALCULATION__ specifies the SPI CRC calculation enable state.
-  *         This parameter can be a value of @ref SPI_CRC_Calculation
-  * @retval None
-  */
-#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
-                                                 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
-
-/** @brief  Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
-  * @param  __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
-  *         This parameter must be a number between Min_Data = 0 and Max_Data = 65535
-  * @retval None
-  */
-#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U)    && \
-                                               ((__POLYNOMIAL__) <= 0xFFFFU) && \
-                                              (((__POLYNOMIAL__)&0x1U) != 0U))
-
-/** @brief  Checks if DMA handle is valid.
-  * @param  __HANDLE__ specifies a DMA Handle.
-  * @retval None
-  */
-#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
-
-/** @brief  Checks if a data address is 16bit aligned.
-  * @param  __DATA__ specifies a data address.
-  * @retval None
-  */
-#define IS_SPI_16BIT_ALIGNED_ADDRESS(__DATA__) (((uint32_t)(__DATA__) % 2U) == 0U)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  ***************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
-                                          uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-                                             uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-                                              uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h
deleted file mode 100644
index a9cdb7b8a6..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h
+++ /dev/null
@@ -1,1828 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_tim.h
-  * @author  MCD Application Team
-  * @brief   Header file of TIM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_TIM_H
-#define STM32L0xx_HAL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIM
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
-  * @{
-  */
-
-/**
-  * @brief  TIM Time base Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t CounterMode;       /*!< Specifies the counter mode.
-                                   This parameter can be a value of @ref TIM_Counter_Mode */
-
-  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
-                                   Auto-Reload Register at the next update event.
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
-
-  uint32_t ClockDivision;     /*!< Specifies the clock division.
-                                   This parameter can be a value of @ref TIM_ClockDivision */
-
-  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
-                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
-} TIM_Base_InitTypeDef;
-
-/**
-  * @brief  TIM Output Compare Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
-                               This parameter can be a value of @ref TIM_Output_Fast_State
-                               @note This parameter is valid only in PWM1 and PWM2 mode. */
-} TIM_OC_InitTypeDef;
-
-/**
-  * @brief  TIM One Pulse Mode Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;   /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
-
-/**
-  * @brief  TIM Input Capture Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
-                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
-                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t ICFilter;     /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/**
-  * @brief  TIM Encoder Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Encoder_Mode */
-
-  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
-
-  uint32_t IC1Selection;  /*!< Specifies the input.
-                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
-
-  uint32_t IC2Selection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-/**
-  * @brief  Clock Configuration Handle Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockSource;     /*!< TIM clock sources
-                                 This parameter can be a value of @ref TIM_Clock_Source */
-  uint32_t ClockPolarity;   /*!< TIM clock polarity
-                                 This parameter can be a value of @ref TIM_Clock_Polarity */
-  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
-                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
-  uint32_t ClockFilter;     /*!< TIM clock filter
-                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_ClockConfigTypeDef;
-
-/**
-  * @brief  TIM Clear Input Configuration Handle Structure definition
-  */
-typedef struct
-{
-  uint32_t ClearInputState;      /*!< TIM clear Input state
-                                      This parameter can be ENABLE or DISABLE */
-  uint32_t ClearInputSource;     /*!< TIM clear Input sources
-                                      This parameter can be a value of @ref TIM_ClearInput_Source */
-  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
-                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
-  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
-                                      This parameter must be 0: When OCRef clear feature is used with ETR source,
-                                      ETR prescaler must be off */
-  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
-                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_ClearInputConfigTypeDef;
-
-/**
-  * @brief  TIM Master configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
-                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
-  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
-                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
-                                        @note When the Master/slave mode is enabled, the effect of
-                                        an event on the trigger input (TRGI) is delayed to allow a
-                                        perfect synchronization between the current timer and its
-                                        slaves (through TRGO). It is not mandatory in case of timer
-                                        synchronization mode. */
-} TIM_MasterConfigTypeDef;
-
-/**
-  * @brief  TIM Slave configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t  SlaveMode;         /*!< Slave mode selection
-                                    This parameter can be a value of @ref TIM_Slave_Mode */
-  uint32_t  InputTrigger;      /*!< Input Trigger source
-                                    This parameter can be a value of @ref TIM_Trigger_Selection */
-  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
-                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
-  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
-                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
-  uint32_t  TriggerFilter;     /*!< Input trigger filter
-                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
-
-} TIM_SlaveConfigTypeDef;
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
-  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
-  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
-  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
-  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
-} HAL_TIM_StateTypeDef;
-
-/**
-  * @brief  TIM Channel States definition
-  */
-typedef enum
-{
-  HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */
-  HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */
-  HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */
-} HAL_TIM_ChannelStateTypeDef;
-
-/**
-  * @brief  DMA Burst States definition
-  */
-typedef enum
-{
-  HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */
-  HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */
-  HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */
-} HAL_TIM_DMABurstStateTypeDef;
-
-/**
-  * @brief  HAL Active channel structures definition
-  */
-typedef enum
-{
-  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
-  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
-  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
-  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
-  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
-} HAL_TIM_ActiveChannel;
-
-/**
-  * @brief  TIM Time Base Handle Structure definition
-  */
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-typedef struct __TIM_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-{
-  TIM_TypeDef                        *Instance;         /*!< Register base address                             */
-  TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */
-  HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */
-  DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array
-                                                             This array is accessed by a @ref DMA_Handle_index */
-  HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */
-  __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */
-  __IO HAL_TIM_ChannelStateTypeDef   ChannelState[4];   /*!< TIM channel operation state                       */
-  __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
-  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
-  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
-  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
-  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
-  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
-  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
-  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
-  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
-  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
-  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
-  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
-  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
-  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
-  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
-  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
-  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
-  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
-  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
-  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
-  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
-  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-} TIM_HandleTypeDef;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL TIM Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                              */
-  , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                            */
-  , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                */
-  , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                              */
-  , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                */
-  , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                              */
-  , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                               */
-  , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                             */
-  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                         */
-  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                       */
-  , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                           */
-  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                         */
-  , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
-  , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
-  , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
-  , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
-
-  , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
-  , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
-  , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
-  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID           */
-  , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
-  , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
-} HAL_TIM_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL TIM Callback pointer definition
-  */
-typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
-
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
-  * @{
-  */
-
-/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
-  * @{
-  */
-#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
-#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
-  * @{
-  */
-#define TIM_DMABASE_CR1                    0x00000000U
-#define TIM_DMABASE_CR2                    0x00000001U
-#define TIM_DMABASE_SMCR                   0x00000002U
-#define TIM_DMABASE_DIER                   0x00000003U
-#define TIM_DMABASE_SR                     0x00000004U
-#define TIM_DMABASE_EGR                    0x00000005U
-#define TIM_DMABASE_CCMR1                  0x00000006U
-#define TIM_DMABASE_CCMR2                  0x00000007U
-#define TIM_DMABASE_CCER                   0x00000008U
-#define TIM_DMABASE_CNT                    0x00000009U
-#define TIM_DMABASE_PSC                    0x0000000AU
-#define TIM_DMABASE_ARR                    0x0000000BU
-#define TIM_DMABASE_CCR1                   0x0000000DU
-#define TIM_DMABASE_CCR2                   0x0000000EU
-#define TIM_DMABASE_CCR3                   0x0000000FU
-#define TIM_DMABASE_CCR4                   0x00000010U
-#define TIM_DMABASE_DCR                    0x00000012U
-#define TIM_DMABASE_DMAR                   0x00000013U
-#define TIM_DMABASE_OR                     0x00000014U
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Event_Source TIM Event Source
-  * @{
-  */
-#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
-#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
-#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
-#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
-#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
-#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
-  * @{
-  */
-#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
-  * @{
-  */
-#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
-  * @{
-  */
-#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
-  * @{
-  */
-#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
-#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
-#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
-#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
-#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClockDivision TIM Clock Division
-  * @{
-  */
-#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
-#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
-#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State
-  * @{
-  */
-#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
-#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
-  * @{
-  */
-#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
-#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
-  * @{
-  */
-#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
-#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
-  * @{
-  */
-#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
-#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
-  * @{
-  */
-#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
-#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
-  * @{
-  */
-#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
-#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
-#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
-  * @{
-  */
-#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
-#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
-  * @{
-  */
-#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
-  * @{
-  */
-#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
-#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
-#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
-  * @{
-  */
-#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
-#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
-  * @{
-  */
-#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
-#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
-#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
-  * @{
-  */
-#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
-#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
-#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
-#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
-#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
-#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_sources TIM DMA Sources
-  * @{
-  */
-#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
-#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
-#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
-#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
-#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
-#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Flag_definition TIM Flag Definition
-  * @{
-  */
-#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
-#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
-#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
-#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
-#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
-#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
-#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
-#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
-#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
-#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Channel TIM Channel
-  * @{
-  */
-#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
-#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
-#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
-#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
-#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Source TIM Clock Source
-  * @{
-  */
-#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
-#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
-#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
-#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
-#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
-#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
-#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
-#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
-#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
-#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
-  * @{
-  */
-#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
-  * @{
-  */
-#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
-#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
-  * @{
-  */
-#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
-  * @{
-  */
-#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
-#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
-  * @{
-  */
-#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
-#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
-#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
-#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
-#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
-#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
-#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
-#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
-  * @{
-  */
-#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
-#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Slave_Mode TIM Slave mode
-  * @{
-  */
-#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
-#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
-#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
-#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
-#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
-  * @{
-  */
-#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
-#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
-#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
-#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
-#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
-#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
-#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
-#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
-  * @{
-  */
-#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
-#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
-#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
-#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
-#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
-#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
-#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
-#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
-#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
-  * @{
-  */
-#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
-#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
-#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
-  * @{
-  */
-#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
-#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
-  * @{
-  */
-#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
-#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
-  * @{
-  */
-#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */
-#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Handle_index TIM DMA Handle Index
-  * @{
-  */
-#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
-  * @}
-  */
-
-/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
-  * @{
-  */
-#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
-#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
-  * @{
-  */
-
-/** @brief  Reset TIM handle state.
-  * @param  __HANDLE__ TIM handle.
-  * @retval None
-  */
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
-                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
-                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
-                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;            \
-                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
-                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;            \
-                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
-                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;            \
-                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
-                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
-                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
-                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
-                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
-                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
-                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
-                                                     } while(0)
-#else
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
-                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
-                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
-                                                     } while(0)
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Enable the TIM peripheral.
-  * @param  __HANDLE__ TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
-  * @brief  Disable the TIM peripheral.
-  * @param  __HANDLE__ TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
-  do { \
-    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
-    { \
-      (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
-    } \
-  } while(0)
-
-/** @brief  Enable the specified TIM interrupt.
-  * @param  __HANDLE__ specifies the TIM Handle.
-  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
-/** @brief  Disable the specified TIM interrupt.
-  * @param  __HANDLE__ specifies the TIM Handle.
-  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-
-/** @brief  Enable the specified DMA request.
-  * @param  __HANDLE__ specifies the TIM Handle.
-  * @param  __DMA__ specifies the TIM DMA request to enable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: Update DMA request
-  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
-  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
-  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
-  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
-  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
-
-/** @brief  Disable the specified DMA request.
-  * @param  __HANDLE__ specifies the TIM Handle.
-  * @param  __DMA__ specifies the TIM DMA request to disable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: Update DMA request
-  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
-  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
-  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
-  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
-  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-
-/** @brief  Check whether the specified TIM interrupt flag is set or not.
-  * @param  __HANDLE__ specifies the TIM Handle.
-  * @param  __FLAG__ specifies the TIM interrupt flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
-  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
-  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
-  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
-  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
-  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
-  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
-  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
-  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
-  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the specified TIM interrupt flag.
-  * @param  __HANDLE__ specifies the TIM Handle.
-  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
-  *        This parameter can be one of the following values:
-  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
-  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
-  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
-  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
-  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
-  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
-  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
-  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
-  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
-  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/**
-  * @brief  Check whether the specified TIM interrupt source is enabled or not.
-  * @param  __HANDLE__ TIM handle
-  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  * @retval The state of TIM_IT (SET or RESET).
-  */
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
-                                                             == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Clear the TIM interrupt pending bits.
-  * @param  __HANDLE__ TIM handle
-  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  * @retval None
-  */
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-/**
-  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
-  * @param  __HANDLE__ TIM handle.
-  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
-  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
-  *       or Encoder mode.
-  */
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-
-/**
-  * @brief  Set the TIM Prescaler on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __PRESC__ specifies the Prescaler new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-/**
-  * @brief  Set the TIM Counter Register value on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __COUNTER__ specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
-  * @brief  Get the TIM Counter Register value on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @retval 16-bit value of the timer counter register (TIMx_CNT)
-  */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
-
-/**
-  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __AUTORELOAD__ specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
-  do{                                                    \
-    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
-    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
-  } while(0)
-
-/**
-  * @brief  Get the TIM Autoreload Register value on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @retval 16-bit value of the timer auto-reload register(TIMx_ARR)
-  */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
-
-/**
-  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CKD__ specifies the clock division value.
-  *          This parameter can be one of the following value:
-  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
-  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
-  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
-  * @retval None
-  */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
-  do{                                                   \
-    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
-    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
-    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
-  } while(0)
-
-/**
-  * @brief  Get the TIM Clock Division value on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @retval The clock division can be one of the following values:
-  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
-  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
-  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
-  */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
-  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
-  *         function.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPSC_DIV1: no prescaler
-  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
-  do{                                                    \
-    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
-    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
-  } while(0)
-
-/**
-  * @brief  Get the TIM Input Capture prescaler on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
-  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
-  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
-  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
-  * @retval The input capture prescaler can be one of the following values:
-  *            @arg TIM_ICPSC_DIV1: no prescaler
-  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
-   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
-
-/**
-  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __COMPARE__ specifies the Capture Compare register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
-   ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
-
-/**
-  * @brief  Get the TIM Capture Compare Register value on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
-  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
-  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
-  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
-  * @retval 16-bit value of the capture/compare register (TIMx_CCRy)
-  */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
-   ((__HANDLE__)->Instance->CCR4))
-
-/**
-  * @brief  Set the TIM Output compare preload.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
-   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
-
-/**
-  * @brief  Reset the TIM Output compare preload.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
-   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
-
-/**
-  * @brief  Enable fast mode for a given channel.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @note  When fast mode is enabled an active edge on the trigger input acts
-  *        like a compare match on CCx output. Delay to sample the trigger
-  *        input and to activate CCx output is reduced to 3 clock cycles.
-  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
-   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
-
-/**
-  * @brief  Disable fast mode for a given channel.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @note  When fast mode is disabled CCx output behaves normally depending
-  *        on counter and CCRx values even when the trigger is ON. The minimum
-  *        delay to activate CCx output when an active edge occurs on the
-  *        trigger input is 5 clock cycles.
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
-   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
-
-/**
-  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
-  * @param  __HANDLE__ TIM handle.
-  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
-  *        overflow/underflow generates an update interrupt or DMA request (if
-  *        enabled)
-  * @retval None
-  */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
-
-/**
-  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
-  * @param  __HANDLE__ TIM handle.
-  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
-  *        following events generate an update interrupt or DMA request (if
-  *        enabled):
-  *           _ Counter overflow underflow
-  *           _ Setting the UG bit
-  *           _ Update generation through the slave mode controller
-  * @retval None
-  */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
-
-/**
-  * @brief  Set the TIM Capture x input polarity on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __POLARITY__ Polarity for TIx source
-  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
-  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
-  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
-  * @retval None
-  */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
-  do{                                                                     \
-    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
-    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
-  }while(0)
-
-/**
-  * @}
-  */
-/* End of exported macros ----------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
-  * @{
-  */
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
-   channels have been disabled */
-#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-/**
-  * @}
-  */
-/* End of private constants --------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
-  * @{
-  */
-#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
-                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
-
-#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
-                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
-                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
-                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
-                                   ((__BASE__) == TIM_DMABASE_SR)    || \
-                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
-                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
-                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
-                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
-                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
-                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
-                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
-                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
-                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
-                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
-                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
-                                   ((__BASE__) == TIM_DMABASE_OR))
-
-#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
-                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
-                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
-                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
-                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
-                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
-                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
-                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
-
-#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
-                                            ((__STATE__) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
-                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
-                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
-
-#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
-                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
-                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
-                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
-                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
-                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
-                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
-                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_2))
-
-#define IS_TIM_PERIOD(__PERIOD__)      ((__PERIOD__) <= 0xFFFFU)
-
-#define IS_TIM_PRESCALER(__PRESCALER__)      ((__PRESCALER__) <= 0xFFFFU)
-
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
-                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
-                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
-                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
-                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
-                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
-                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
-                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
-                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
-                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
-                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
-                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
-                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
-
-#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
-                                   ((__MODE__) == TIM_OCMODE_PWM2))
-
-#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
-                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
-                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
-                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
-                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
-                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
-
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
-                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
-                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
-                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
-                                                 ((__SELECTION__) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
-                                                               ((__SELECTION__) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
-
-#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
-                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
-                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
-                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
-                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
-
-#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
-
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
-   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
-   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
-
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
-   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
-
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
-   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
-
-#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
-   (__HANDLE__)->ChannelState[3])
-
-#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
-   ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
-
-#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
-                                                                       (__HANDLE__)->ChannelState[0]  = (__CHANNEL_STATE__);  \
-                                                                       (__HANDLE__)->ChannelState[1]  = (__CHANNEL_STATE__);  \
-                                                                       (__HANDLE__)->ChannelState[2]  = (__CHANNEL_STATE__);  \
-                                                                       (__HANDLE__)->ChannelState[3]  = (__CHANNEL_STATE__);  \
-                                                                     } while(0)
-
-/**
-  * @}
-  */
-/* End of private macros -----------------------------------------------------*/
-
-/* Include TIM HAL Extended module */
-#include "stm32l0xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
-  *  @brief   Time Base functions
-  * @{
-  */
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
-  *  @brief   TIM Output Compare functions
-  * @{
-  */
-/* Timer Output Compare functions *********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
-  *  @brief   TIM PWM functions
-  * @{
-  */
-/* Timer PWM functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
-  *  @brief   TIM Input Capture functions
-  * @{
-  */
-/* Timer Input Capture functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
-  *  @brief   TIM One Pulse functions
-  * @{
-  */
-/* Timer One Pulse functions **************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
-  *  @brief   TIM Encoder functions
-  * @{
-  */
-/* Timer Encoder functions ****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
-                                            uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
-  *  @brief   IRQ handler management
-  * @{
-  */
-/* Interrupt Handler functions  ***********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
-  *  @brief   Peripheral Control functions
-  * @{
-  */
-/* Control functions  *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
-                                                 uint32_t OutputChannel,  uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
-                                           uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
-                                                   uint32_t BurstLength,  uint32_t DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
-                                                  uint32_t  BurstLength, uint32_t  DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
-  *  @brief   TIM Callbacks functions
-  * @{
-  */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
-                                           pTIM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
-  *  @brief  Peripheral State functions
-  * @{
-  */
-/* Peripheral State functions  ************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/* Peripheral Channel state functions  ************************************************/
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel);
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIM_Private_Functions TIM Private Functions
-  * @{
-  */
-void TIM_DMAError(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-void TIM_ResetCallback(TIM_HandleTypeDef *htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-/* End of private functions --------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h
deleted file mode 100644
index 28e7fe92c1..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_tim_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of TIM HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_TIM_EX_H
-#define STM32L0xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIMEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup TIMEx_Remap TIM Extended Remapping
-  * @{
-  */
-#define TIM2_ETR_GPIO                     0x00000000U                               /*!< TIM2 ETR input is connected to ORed GPIOs */
-#if defined(RCC_HSI48_SUPPORT)
-#define TIM2_ETR_HSI48                    TIM2_OR_ETR_RMP_2                         /*!< TIM2 ETR input is connected to HSI48 clock */
-#endif /* RCC_HSI48_SUPPORT */
-#define TIM2_ETR_HSI16                    (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0)   /*!< TIM2 ETR input is connected to HSI16 clock */
-#define TIM2_ETR_LSE                      (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0)   /*!< TIM2 ETR input is connected to LSE clock */
-#if defined(COMP1) && defined(COMP2)
-#define TIM2_ETR_COMP2_OUT                (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1)   /*!< TIM2 ETR input is connected to COMP2_OUT */
-#define TIM2_ETR_COMP1_OUT                TIM2_OR_ETR_RMP                           /*!< TIM2 ETR input is connected to COMP1_OUT */
-#endif /* COMP1 && COMP2 */
-
-#define TIM2_TI4_GPIO                     0x00000000U                               /*!< TIM2 TI4 input connected to ORed GPIOs */
-#if defined(COMP1) && defined(COMP2)
-#define TIM2_TI4_COMP2                    TIM2_OR_TI4_RMP_0                         /*!< TIM2 TI4 input connected to COMP2_OUT */
-#define TIM2_TI4_COMP1                    TIM2_OR_TI4_RMP_1                         /*!< TIM2 TI4 input connected to COMP1_OUT */
-#endif /* COMP1 && COMP2 */
-
-#if defined(TIM3)
-#if defined(USB)
-#define TIM3_TI4_USB_NOE                  0x00000000U                               /*!< USB_NOE selected selected for PC9 (AF2) remapping */
-#endif /* USB */
-
-#define TIM3_TI4_GPIOC9_AF2               TIM3_OR_TI4_RMP                           /*!< TIM3_CH4 selected for PC9 (AF2) remapping */
-#define TIM3_TI2_GPIO_DEF                 0x00000000U                               /*!< TIM3_CH2 selected for PB5 (AF4) remapping */
-#define TIM3_TI2_GPIOB5_AF4               TIM3_OR_TI2_RMP                           /*!< TIM22_CH2 selected for PB5 (AF4) remapping */
-
-#if defined(USB)
-#define TIM3_TI1_USB_SOF                  0x00000000U                               /*!< TIM3 TI1 input connected to USB_SOF */
-#endif /* USB */
-
-#define TIM3_TI1_GPIO                     TIM3_OR_TI1_RMP                           /*!< TIM3 TI1 input connected to ORed GPIOs */
-#define TIM3_ETR_GPIO                     0x00000000U                               /*!< TIM3 ETR input connected to ORed GPIOs */
-#define TIM3_ETR_HSI                      TIM3_OR_ETR_RMP_1                         /*!< TIM3_ETR input is connected to HSI48 clock */
-#endif /* TIM3 */
-
-#define TIM21_ETR_GPIO                    0x00000000U                               /*!< TIM21 ETR input connected to ORed GPIOs */
-#if defined(COMP1) && defined(COMP2)
-#define TIM21_ETR_COMP2_OUT               TIM21_OR_ETR_RMP_0                        /*!< TIM21 ETR input connected to COMP2_OUT */
-#define TIM21_ETR_COMP1_OUT               TIM21_OR_ETR_RMP_1                        /*!< TIM21 ETR input connected to COMP1_OUT */
-#endif /* COMP1 && COMP2 */
-#define TIM21_ETR_LSE                     TIM21_OR_ETR_RMP                          /*!< TIM21 ETR input connected to LSE clock */
-
-#define TIM21_TI1_GPIO                    0x00000000U                               /*!< TIM21 TI1 input connected to ORed GPIOs */
-#define TIM21_TI1_MCO                     TIM21_OR_TI1_RMP                          /*!< TIM21 TI1 input connected to MCO clock */
-#define TIM21_TI1_RTC_WKUT_IT             TIM21_OR_TI1_RMP_0                        /*!< TIM21 TI1 input connected to RTC WAKEUP interrupt */
-#define TIM21_TI1_HSE_RTC                 TIM21_OR_TI1_RMP_1                        /*!< TIM21 TI1 input connected to HSE_RTC clock */
-#define TIM21_TI1_MSI                     (TIM21_OR_TI1_RMP_0 | TIM21_OR_TI1_RMP_1) /*!< TIM21 TI1 input connected to MSI clock */
-#define TIM21_TI1_LSE                     TIM21_OR_TI1_RMP_2                        /*!< TIM21 TI1 input connected to LSE clock */
-#define TIM21_TI1_LSI                     (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0) /*!< TIM21 TI1 input connected to LSI clock */
-#if defined(COMP1)
-#define TIM21_TI1_COMP1_OUT               (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1) /*!< TIM21 TI1 input connected to COMP1_OUT */
-#endif /* COMP1 */
-
-#define TIM21_TI2_GPIO                    0x00000000U                               /*!< TIM21 TI2 input connected to ORed GPIOs */
-#if defined(COMP2)
-#define TIM21_TI2_COMP2_OUT               TIM21_OR_TI2_RMP                          /*!< TIM21 TI2 input connected to COMP2_OUT */
-#endif /* COMP2 */
-
-#if defined(TIM22)
-#define TIM22_ETR_GPIO                    0x00000000U                               /*!< TIM22 ETR input is connected to ORed GPIOs */
-#if defined(COMP1) && defined(COMP2)
-#define TIM22_ETR_COMP2_OUT               TIM22_OR_ETR_RMP_0                        /*!< TIM22 ETR input is connected to COMP2_OUT */
-#define TIM22_ETR_COMP1_OUT               TIM22_OR_ETR_RMP_1                        /*!< TIM22 ETR input is connected to COMP1_OUT */
-#endif /* COMP1 && COMP2 */
-#define TIM22_ETR_LSE                     TIM22_OR_ETR_RMP                          /*!< TIM22 ETR input is connected to LSE clock */
-
-#define TIM22_TI1_GPIO                   0x00000000U                                /*!< TIM22 TI1 input is connected to ORed GPIOs */
-#if defined(COMP1) && defined(COMP2)
-#define TIM22_TI1_COMP2_OUT               TIM22_OR_TI1_RMP_0                        /*!< TIM22 TI1 input is connected to COMP2_OUT */
-#define TIM22_TI1_COMP1_OUT               TIM22_OR_TI1_RMP_1                        /*!< TIM22 TI1 input is connected to COMP1_OUT */
-#endif /* COMP1 && COMP2 */
-#endif /* TIM22 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-/* End of exported macro -----------------------------------------------------*/
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
-  * @{
-  */
-#if defined(TIM3) && defined(TIM22)
-
-#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__)               \
-  ((((__INSTANCE__) == TIM2)   &&  ((__TIM_REMAP__) <=  (TIM2_OR_TI4_RMP  | TIM2_OR_ETR_RMP))) || \
-   (((__INSTANCE__) == TIM22)  &&  ((__TIM_REMAP__) <=  (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \
-   (((__INSTANCE__) == TIM21)  &&  ((__TIM_REMAP__) <=  (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))) || \
-   (((__INSTANCE__) == TIM3)   &&  ((__TIM_REMAP__) <=  (TIM3_OR_ETR_RMP  | TIM3_OR_TI1_RMP  | TIM3_OR_TI2_RMP | TIM3_OR_TI4_RMP))))
-
-#define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__)     \
-  ((((__INSTANCE__) == TIM2)  &&  (((__CHANNEL__) == TIM_CHANNEL_1)   ||   \
-                                   ((__CHANNEL__) == TIM_CHANNEL_2)   ||   \
-                                   ((__CHANNEL__) == TIM_CHANNEL_3)   ||   \
-                                   ((__CHANNEL__) == TIM_CHANNEL_4))) ||   \
-   (((__INSTANCE__) == TIM3) &&   (((__CHANNEL__) == TIM_CHANNEL_1)   ||   \
-                                   ((__CHANNEL__) == TIM_CHANNEL_2)   ||   \
-                                   ((__CHANNEL__) == TIM_CHANNEL_3)   ||   \
-                                   ((__CHANNEL__) == TIM_CHANNEL_4))) ||   \
-   (((__INSTANCE__) == TIM21) &&  (((__CHANNEL__) == TIM_CHANNEL_1)   ||   \
-                                   ((__CHANNEL__) == TIM_CHANNEL_2))) ||   \
-   (((__INSTANCE__) == TIM22) &&  (((__CHANNEL__) == TIM_CHANNEL_1)   ||   \
-                                   ((__CHANNEL__) == TIM_CHANNEL_2))))
-
-#elif defined(TIM22)
-
-#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__)               \
-  ((((__INSTANCE__) == TIM2)   &&  ((__TIM_REMAP__) <=  (TIM2_OR_TI4_RMP  | TIM2_OR_ETR_RMP))) || \
-   (((__INSTANCE__) == TIM22)  &&  ((__TIM_REMAP__) <=  (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \
-   (((__INSTANCE__) == TIM21)  &&  ((__TIM_REMAP__) <=  (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))))
-
-#define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__)     \
-  ((((__INSTANCE__) == TIM2)  &&   (((__CHANNEL__) == TIM_CHANNEL_1)   || \
-                                    ((__CHANNEL__) == TIM_CHANNEL_2)   || \
-                                    ((__CHANNEL__) == TIM_CHANNEL_3)   || \
-                                    ((__CHANNEL__) == TIM_CHANNEL_4))) || \
-   (((__INSTANCE__) == TIM21)  &&  (((__CHANNEL__) == TIM_CHANNEL_1)   || \
-                                    ((__CHANNEL__) == TIM_CHANNEL_2))) || \
-   (((__INSTANCE__) == TIM22)  &&  (((__CHANNEL__) == TIM_CHANNEL_1)   || \
-                                    ((__CHANNEL__) == TIM_CHANNEL_2))))
-#else
-
-#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__)               \
-  ((((__INSTANCE__) == TIM2)   &&  ((__TIM_REMAP__) <=  (TIM2_OR_TI4_RMP  | TIM2_OR_ETR_RMP))) || \
-   (((__INSTANCE__) == TIM21)  &&  ((__TIM_REMAP__) <=  (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))))
-
-#define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__)     \
-  ((((__INSTANCE__) == TIM2)  &&   (((__CHANNEL__) == TIM_CHANNEL_1)   || \
-                                    ((__CHANNEL__) == TIM_CHANNEL_2)   || \
-                                    ((__CHANNEL__) == TIM_CHANNEL_3)   || \
-                                    ((__CHANNEL__) == TIM_CHANNEL_4))) || \
-   (((__INSTANCE__) == TIM21)  &&  (((__CHANNEL__) == TIM_CHANNEL_1)   || \
-                                    ((__CHANNEL__) == TIM_CHANNEL_2))))
-#endif /* TIM3 && TIM22 */
-
-/**
-  * @}
-  */
-/* End of private macro ------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
-  * @{
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
-  *  @brief    Peripheral Control functions
-  * @{
-  */
-/* Extended Control functions  ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
-                                                        TIM_MasterConfigTypeDef *sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* End of exported functions -------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L0xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tsc.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tsc.h
deleted file mode 100644
index 69ccfebfae..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tsc.h
+++ /dev/null
@@ -1,800 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_tsc.h
-  * @author  MCD Application Team
-  * @brief   Header file of TSC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_TSC_H
-#define STM32L0xx_HAL_TSC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-#if defined(TSC)
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TSC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TSC_Exported_Types TSC Exported Types
-  * @{
-  */
-
-/**
-  * @brief TSC state structure definition
-  */
-typedef enum
-{
-  HAL_TSC_STATE_RESET  = 0x00UL, /*!< TSC registers have their reset value */
-  HAL_TSC_STATE_READY  = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */
-  HAL_TSC_STATE_BUSY   = 0x02UL, /*!< TSC initialization or acquisition is on-going */
-  HAL_TSC_STATE_ERROR  = 0x03UL  /*!< Acquisition is completed with max count error */
-} HAL_TSC_StateTypeDef;
-
-/**
-  * @brief TSC group status structure definition
-  */
-typedef enum
-{
-  TSC_GROUP_ONGOING   = 0x00UL, /*!< Acquisition on group is on-going or not started */
-  TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */
-} TSC_GroupStatusTypeDef;
-
-/**
-  * @brief TSC init structure definition
-  */
-typedef struct
-{
-  uint32_t CTPulseHighLength;       /*!< Charge-transfer high pulse length
-                                         This parameter can be a value of @ref TSC_CTPulseHL_Config  */
-  uint32_t CTPulseLowLength;        /*!< Charge-transfer low pulse length
-                                         This parameter can be a value of @ref TSC_CTPulseLL_Config  */
-  FunctionalState SpreadSpectrum;   /*!< Spread spectrum activation
-                                         This parameter can be set to ENABLE or DISABLE. */
-  uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
-                                         This parameter must be a number between Min_Data = 0 and Max_Data = 127 */
-  uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
-                                         This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
-  uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
-                                         This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
-  uint32_t MaxCountValue;           /*!< Max count value
-                                         This parameter can be a value of @ref TSC_MaxCount_Value  */
-  uint32_t IODefaultMode;           /*!< IO default mode
-                                         This parameter can be a value of @ref TSC_IO_Default_Mode  */
-  uint32_t SynchroPinPolarity;      /*!< Synchro pin polarity
-                                         This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
-  uint32_t AcquisitionMode;         /*!< Acquisition mode
-                                         This parameter can be a value of @ref TSC_Acquisition_Mode  */
-  FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation
-                                         This parameter can be set to ENABLE or DISABLE. */
-  uint32_t ChannelIOs;              /*!< Channel IOs mask */
-  uint32_t ShieldIOs;               /*!< Shield IOs mask */
-  uint32_t SamplingIOs;             /*!< Sampling IOs mask */
-} TSC_InitTypeDef;
-
-/**
-  * @brief TSC IOs configuration structure definition
-  */
-typedef struct
-{
-  uint32_t ChannelIOs;  /*!< Channel IOs mask */
-  uint32_t ShieldIOs;   /*!< Shield IOs mask */
-  uint32_t SamplingIOs; /*!< Sampling IOs mask */
-} TSC_IOConfigTypeDef;
-
-/**
-  * @brief  TSC handle Structure definition
-  */
-#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-typedef struct __TSC_HandleTypeDef
-#else
-typedef struct
-#endif  /* USE_HAL_TSC_REGISTER_CALLBACKS */
-{
-  TSC_TypeDef               *Instance;  /*!< Register base address      */
-  TSC_InitTypeDef           Init;       /*!< Initialization parameters  */
-  __IO HAL_TSC_StateTypeDef State;      /*!< Peripheral state           */
-  HAL_LockTypeDef           Lock;       /*!< Lock feature               */
-  __IO uint32_t             ErrorCode;  /*!< TSC Error code             */
-
-#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-  void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc);   /*!< TSC Conversion complete callback  */
-  void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc);      /*!< TSC Error callback                */
-
-  void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc);    /*!< TSC Msp Init callback             */
-  void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc);  /*!< TSC Msp DeInit callback           */
-
-#endif  /* USE_HAL_TSC_REGISTER_CALLBACKS */
-} TSC_HandleTypeDef;
-
-enum
-{
-  TSC_GROUP1_IDX = 0x00UL,
-  TSC_GROUP2_IDX,
-  TSC_GROUP3_IDX,
-  TSC_GROUP4_IDX,
-  TSC_GROUP5_IDX,
-  TSC_GROUP6_IDX,
-  TSC_GROUP7_IDX,
-  TSC_GROUP8_IDX,
-  TSC_NB_OF_GROUPS
-};
-
-#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL TSC Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_TSC_CONV_COMPLETE_CB_ID           = 0x00UL,  /*!< TSC Conversion completed callback ID  */
-  HAL_TSC_ERROR_CB_ID                   = 0x01UL,  /*!< TSC Error callback ID                 */
-
-  HAL_TSC_MSPINIT_CB_ID                 = 0x02UL,  /*!< TSC Msp Init callback ID              */
-  HAL_TSC_MSPDEINIT_CB_ID               = 0x03UL   /*!< TSC Msp DeInit callback ID            */
-
-} HAL_TSC_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL TSC Callback pointer definition
-  */
-typedef  void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */
-
-#endif  /* USE_HAL_TSC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TSC_Exported_Constants TSC Exported Constants
-  * @{
-  */
-
-/** @defgroup TSC_Error_Code_definition TSC Error Code definition
-  * @brief  TSC Error Code definition
-  * @{
-  */
-#define HAL_TSC_ERROR_NONE      0x00000000UL    /*!< No error              */
-#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-#define HAL_TSC_ERROR_INVALID_CALLBACK  0x00000001UL    /*!< Invalid Callback error */
-#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
-  * @{
-  */
-#define TSC_CTPH_1CYCLE         0x00000000UL                                                    /*!< Charge transfer pulse high during 1 cycle (PGCLK)   */
-#define TSC_CTPH_2CYCLES        TSC_CR_CTPH_0                                                   /*!< Charge transfer pulse high during 2 cycles (PGCLK)  */
-#define TSC_CTPH_3CYCLES        TSC_CR_CTPH_1                                                   /*!< Charge transfer pulse high during 3 cycles (PGCLK)  */
-#define TSC_CTPH_4CYCLES        (TSC_CR_CTPH_1 | TSC_CR_CTPH_0)                                 /*!< Charge transfer pulse high during 4 cycles (PGCLK)  */
-#define TSC_CTPH_5CYCLES        TSC_CR_CTPH_2                                                   /*!< Charge transfer pulse high during 5 cycles (PGCLK)  */
-#define TSC_CTPH_6CYCLES        (TSC_CR_CTPH_2 | TSC_CR_CTPH_0)                                 /*!< Charge transfer pulse high during 6 cycles (PGCLK)  */
-#define TSC_CTPH_7CYCLES        (TSC_CR_CTPH_2 | TSC_CR_CTPH_1)                                 /*!< Charge transfer pulse high during 7 cycles (PGCLK)  */
-#define TSC_CTPH_8CYCLES        (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)                 /*!< Charge transfer pulse high during 8 cycles (PGCLK)  */
-#define TSC_CTPH_9CYCLES        TSC_CR_CTPH_3                                                   /*!< Charge transfer pulse high during 9 cycles (PGCLK)  */
-#define TSC_CTPH_10CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_0)                                 /*!< Charge transfer pulse high during 10 cycles (PGCLK) */
-#define TSC_CTPH_11CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_1)                                 /*!< Charge transfer pulse high during 11 cycles (PGCLK) */
-#define TSC_CTPH_12CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)                 /*!< Charge transfer pulse high during 12 cycles (PGCLK) */
-#define TSC_CTPH_13CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_2)                                 /*!< Charge transfer pulse high during 13 cycles (PGCLK) */
-#define TSC_CTPH_14CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0)                 /*!< Charge transfer pulse high during 14 cycles (PGCLK) */
-#define TSC_CTPH_15CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1)                 /*!< Charge transfer pulse high during 15 cycles (PGCLK) */
-#define TSC_CTPH_16CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */
-/**
-  * @}
-  */
-
-/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
-  * @{
-  */
-#define TSC_CTPL_1CYCLE         0x00000000UL                                                     /*!< Charge transfer pulse low during 1 cycle (PGCLK)   */
-#define TSC_CTPL_2CYCLES        TSC_CR_CTPL_0                                                    /*!< Charge transfer pulse low during 2 cycles (PGCLK)  */
-#define TSC_CTPL_3CYCLES        TSC_CR_CTPL_1                                                    /*!< Charge transfer pulse low during 3 cycles (PGCLK)  */
-#define TSC_CTPL_4CYCLES        (TSC_CR_CTPL_1 | TSC_CR_CTPL_0)                                  /*!< Charge transfer pulse low during 4 cycles (PGCLK)  */
-#define TSC_CTPL_5CYCLES        TSC_CR_CTPL_2                                                    /*!< Charge transfer pulse low during 5 cycles (PGCLK)  */
-#define TSC_CTPL_6CYCLES        (TSC_CR_CTPL_2 | TSC_CR_CTPL_0)                                  /*!< Charge transfer pulse low during 6 cycles (PGCLK)  */
-#define TSC_CTPL_7CYCLES        (TSC_CR_CTPL_2 | TSC_CR_CTPL_1)                                  /*!< Charge transfer pulse low during 7 cycles (PGCLK)  */
-#define TSC_CTPL_8CYCLES        (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)                  /*!< Charge transfer pulse low during 8 cycles (PGCLK)  */
-#define TSC_CTPL_9CYCLES        TSC_CR_CTPL_3                                                    /*!< Charge transfer pulse low during 9 cycles (PGCLK)  */
-#define TSC_CTPL_10CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_0)                                  /*!< Charge transfer pulse low during 10 cycles (PGCLK) */
-#define TSC_CTPL_11CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_1)                                  /*!< Charge transfer pulse low during 11 cycles (PGCLK) */
-#define TSC_CTPL_12CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)                  /*!< Charge transfer pulse low during 12 cycles (PGCLK) */
-#define TSC_CTPL_13CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_2)                                  /*!< Charge transfer pulse low during 13 cycles (PGCLK) */
-#define TSC_CTPL_14CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0)                  /*!< Charge transfer pulse low during 14 cycles (PGCLK) */
-#define TSC_CTPL_15CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1)                  /*!< Charge transfer pulse low during 15 cycles (PGCLK) */
-#define TSC_CTPL_16CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)  /*!< Charge transfer pulse low during 16 cycles (PGCLK) */
-/**
-  * @}
-  */
-
-/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
-  * @{
-  */
-#define TSC_SS_PRESC_DIV1       0x00000000UL  /*!< Spread Spectrum Prescaler Div1 */
-#define TSC_SS_PRESC_DIV2       TSC_CR_SSPSC  /*!< Spread Spectrum Prescaler Div2 */
-/**
-  * @}
-  */
-
-/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
-  * @{
-  */
-#define TSC_PG_PRESC_DIV1       0x00000000UL                                        /*!< Pulse Generator HCLK Div1   */
-#define TSC_PG_PRESC_DIV2       TSC_CR_PGPSC_0                                      /*!< Pulse Generator HCLK Div2   */
-#define TSC_PG_PRESC_DIV4       TSC_CR_PGPSC_1                                      /*!< Pulse Generator HCLK Div4   */
-#define TSC_PG_PRESC_DIV8       (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0)                   /*!< Pulse Generator HCLK Div8   */
-#define TSC_PG_PRESC_DIV16      TSC_CR_PGPSC_2                                      /*!< Pulse Generator HCLK Div16  */
-#define TSC_PG_PRESC_DIV32      (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0)                   /*!< Pulse Generator HCLK Div32  */
-#define TSC_PG_PRESC_DIV64      (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1)                   /*!< Pulse Generator HCLK Div64  */
-#define TSC_PG_PRESC_DIV128     (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0)  /*!< Pulse Generator HCLK Div128 */
-/**
-  * @}
-  */
-
-/** @defgroup TSC_MaxCount_Value Max Count Value
-  * @{
-  */
-#define TSC_MCV_255             0x00000000UL                   /*!< 255 maximum number of charge transfer pulses   */
-#define TSC_MCV_511             TSC_CR_MCV_0                   /*!< 511 maximum number of charge transfer pulses   */
-#define TSC_MCV_1023            TSC_CR_MCV_1                   /*!< 1023 maximum number of charge transfer pulses  */
-#define TSC_MCV_2047            (TSC_CR_MCV_1 | TSC_CR_MCV_0)  /*!< 2047 maximum number of charge transfer pulses  */
-#define TSC_MCV_4095            TSC_CR_MCV_2                   /*!< 4095 maximum number of charge transfer pulses  */
-#define TSC_MCV_8191            (TSC_CR_MCV_2 | TSC_CR_MCV_0)  /*!< 8191 maximum number of charge transfer pulses  */
-#define TSC_MCV_16383           (TSC_CR_MCV_2 | TSC_CR_MCV_1)  /*!< 16383 maximum number of charge transfer pulses */
-/**
-  * @}
-  */
-
-/** @defgroup TSC_IO_Default_Mode IO Default Mode
-  * @{
-  */
-#define TSC_IODEF_OUT_PP_LOW    0x00000000UL /*!< I/Os are forced to output push-pull low */
-#define TSC_IODEF_IN_FLOAT      TSC_CR_IODEF /*!< I/Os are in input floating              */
-/**
-  * @}
-  */
-
-/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
-  * @{
-  */
-#define TSC_SYNC_POLARITY_FALLING  0x00000000UL   /*!< Falling edge only           */
-#define TSC_SYNC_POLARITY_RISING   TSC_CR_SYNCPOL /*!< Rising edge and high level  */
-/**
-  * @}
-  */
-
-/** @defgroup TSC_Acquisition_Mode Acquisition Mode
-  * @{
-  */
-#define TSC_ACQ_MODE_NORMAL     0x00000000UL  /*!< Normal acquisition mode (acquisition starts as soon as START bit is set)                                                              */
-#define TSC_ACQ_MODE_SYNCHRO    TSC_CR_AM     /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */
-/**
-  * @}
-  */
-
-/** @defgroup TSC_interrupts_definition Interrupts definition
-  * @{
-  */
-#define TSC_IT_EOA              TSC_IER_EOAIE /*!< End of acquisition interrupt enable */
-#define TSC_IT_MCE              TSC_IER_MCEIE /*!< Max count error interrupt enable    */
-/**
-  * @}
-  */
-
-/** @defgroup TSC_flags_definition Flags definition
-  * @{
-  */
-#define TSC_FLAG_EOA            TSC_ISR_EOAF /*!< End of acquisition flag */
-#define TSC_FLAG_MCE            TSC_ISR_MCEF /*!< Max count error flag    */
-/**
-  * @}
-  */
-
-/** @defgroup TSC_Group_definition Group definition
-  * @{
-  */
-#define TSC_GROUP1              (0x1UL << TSC_GROUP1_IDX)
-#define TSC_GROUP2              (0x1UL << TSC_GROUP2_IDX)
-#define TSC_GROUP3              (0x1UL << TSC_GROUP3_IDX)
-#define TSC_GROUP4              (0x1UL << TSC_GROUP4_IDX)
-#define TSC_GROUP5              (0x1UL << TSC_GROUP5_IDX)
-#define TSC_GROUP6              (0x1UL << TSC_GROUP6_IDX)
-#define TSC_GROUP7              (0x1UL << TSC_GROUP7_IDX)
-#define TSC_GROUP8              (0x1UL << TSC_GROUP8_IDX)
-
-#define TSC_GROUP1_IO1          TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */
-#define TSC_GROUP1_IO2          TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */
-#define TSC_GROUP1_IO3          TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */
-#define TSC_GROUP1_IO4          TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */
-
-#define TSC_GROUP2_IO1          TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */
-#define TSC_GROUP2_IO2          TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */
-#define TSC_GROUP2_IO3          TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */
-#define TSC_GROUP2_IO4          TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */
-
-#define TSC_GROUP3_IO1          TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */
-#define TSC_GROUP3_IO2          TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */
-#define TSC_GROUP3_IO3          TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */
-#define TSC_GROUP3_IO4          TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */
-
-#define TSC_GROUP4_IO1          TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */
-#define TSC_GROUP4_IO2          TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */
-#define TSC_GROUP4_IO3          TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */
-#define TSC_GROUP4_IO4          TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */
-
-#define TSC_GROUP5_IO1          TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */
-#define TSC_GROUP5_IO2          TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */
-#define TSC_GROUP5_IO3          TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */
-#define TSC_GROUP5_IO4          TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */
-
-#define TSC_GROUP6_IO1          TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */
-#define TSC_GROUP6_IO2          TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */
-#define TSC_GROUP6_IO3          TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */
-#define TSC_GROUP6_IO4          TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */
-
-#define TSC_GROUP7_IO1          TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */
-#define TSC_GROUP7_IO2          TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */
-#define TSC_GROUP7_IO3          TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */
-#define TSC_GROUP7_IO4          TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */
-
-#define TSC_GROUP8_IO1          TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */
-#define TSC_GROUP8_IO2          TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */
-#define TSC_GROUP8_IO3          TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */
-#define TSC_GROUP8_IO4          TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup TSC_Exported_Macros TSC Exported Macros
-  * @{
-  */
-
-/** @brief Reset TSC handle state.
-  * @param  __HANDLE__ TSC handle
-  * @retval None
-  */
-#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__)                   do{                                                   \
-                                                                       (__HANDLE__)->State = HAL_TSC_STATE_RESET;       \
-                                                                       (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                     } while(0)
-#else
-#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__)                   ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
-#endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */
-
-/**
-  * @brief Enable the TSC peripheral.
-  * @param  __HANDLE__ TSC handle
-  * @retval None
-  */
-#define __HAL_TSC_ENABLE(__HANDLE__)                               ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
-
-/**
-  * @brief Disable the TSC peripheral.
-  * @param  __HANDLE__ TSC handle
-  * @retval None
-  */
-#define __HAL_TSC_DISABLE(__HANDLE__)                              ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE))
-
-/**
-  * @brief Start acquisition.
-  * @param  __HANDLE__ TSC handle
-  * @retval None
-  */
-#define __HAL_TSC_START_ACQ(__HANDLE__)                            ((__HANDLE__)->Instance->CR |= TSC_CR_START)
-
-/**
-  * @brief Stop acquisition.
-  * @param  __HANDLE__ TSC handle
-  * @retval None
-  */
-#define __HAL_TSC_STOP_ACQ(__HANDLE__)                             ((__HANDLE__)->Instance->CR &= (~TSC_CR_START))
-
-/**
-  * @brief Set IO default mode to output push-pull low.
-  * @param  __HANDLE__ TSC handle
-  * @retval None
-  */
-#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__)                   ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF))
-
-/**
-  * @brief Set IO default mode to input floating.
-  * @param  __HANDLE__ TSC handle
-  * @retval None
-  */
-#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__)                    ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
-
-/**
-  * @brief Set synchronization polarity to falling edge.
-  * @param  __HANDLE__ TSC handle
-  * @retval None
-  */
-#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__)                    ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL))
-
-/**
-  * @brief Set synchronization polarity to rising edge and high level.
-  * @param  __HANDLE__ TSC handle
-  * @retval None
-  */
-#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__)               ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
-
-/**
-  * @brief Enable TSC interrupt.
-  * @param  __HANDLE__ TSC handle
-  * @param  __INTERRUPT__ TSC interrupt
-  * @retval None
-  */
-#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__)             ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
-
-/**
-  * @brief Disable TSC interrupt.
-  * @param  __HANDLE__ TSC handle
-  * @param  __INTERRUPT__ TSC interrupt
-  * @retval None
-  */
-#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__)            ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
-
-/** @brief Check whether the specified TSC interrupt source is enabled or not.
-  * @param  __HANDLE__ TSC Handle
-  * @param  __INTERRUPT__ TSC interrupt
-  * @retval SET or RESET
-  */
-#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)         ((((__HANDLE__)->Instance->IER\
-                                                                      & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\
-                                                                    RESET)
-
-/**
-  * @brief Check whether the specified TSC flag is set or not.
-  * @param  __HANDLE__ TSC handle
-  * @param  __FLAG__ TSC flag
-  * @retval SET or RESET
-  */
-#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__)                   ((((__HANDLE__)->Instance->ISR\
-                                                                      & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
-
-/**
-  * @brief Clear the TSC's pending flag.
-  * @param  __HANDLE__ TSC handle
-  * @param  __FLAG__ TSC flag
-  * @retval None
-  */
-#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/**
-  * @brief Enable schmitt trigger hysteresis on a group of IOs.
-  * @param  __HANDLE__ TSC handle
-  * @param  __GX_IOY_MASK__ IOs mask
-  * @retval None
-  */
-#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__)   ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
-
-/**
-  * @brief Disable schmitt trigger hysteresis on a group of IOs.
-  * @param  __HANDLE__ TSC handle
-  * @param  __GX_IOY_MASK__ IOs mask
-  * @retval None
-  */
-#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__)  ((__HANDLE__)->Instance->IOHCR\
-                                                                    &= (~(__GX_IOY_MASK__)))
-
-/**
-  * @brief Open analog switch on a group of IOs.
-  * @param  __HANDLE__ TSC handle
-  * @param  __GX_IOY_MASK__ IOs mask
-  * @retval None
-  */
-#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__)  ((__HANDLE__)->Instance->IOASCR\
-                                                                    &= (~(__GX_IOY_MASK__)))
-
-/**
-  * @brief Close analog switch on a group of IOs.
-  * @param  __HANDLE__ TSC handle
-  * @param  __GX_IOY_MASK__ IOs mask
-  * @retval None
-  */
-#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
-
-/**
-  * @brief Enable a group of IOs in channel mode.
-  * @param  __HANDLE__ TSC handle
-  * @param  __GX_IOY_MASK__ IOs mask
-  * @retval None
-  */
-#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__)      ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
-
-/**
-  * @brief Disable a group of channel IOs.
-  * @param  __HANDLE__ TSC handle
-  * @param  __GX_IOY_MASK__ IOs mask
-  * @retval None
-  */
-#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__)     ((__HANDLE__)->Instance->IOCCR\
-                                                                    &= (~(__GX_IOY_MASK__)))
-
-/**
-  * @brief Enable a group of IOs in sampling mode.
-  * @param  __HANDLE__ TSC handle
-  * @param  __GX_IOY_MASK__ IOs mask
-  * @retval None
-  */
-#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__)     ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
-
-/**
-  * @brief Disable a group of sampling IOs.
-  * @param  __HANDLE__ TSC handle
-  * @param  __GX_IOY_MASK__ IOs mask
-  * @retval None
-  */
-#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__)))
-
-/**
-  * @brief Enable acquisition groups.
-  * @param  __HANDLE__ TSC handle
-  * @param  __GX_MASK__ Groups mask
-  * @retval None
-  */
-#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
-
-/**
-  * @brief Disable acquisition groups.
-  * @param  __HANDLE__ TSC handle
-  * @param  __GX_MASK__ Groups mask
-  * @retval None
-  */
-#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__)))
-
-/** @brief Gets acquisition group status.
-  * @param  __HANDLE__ TSC Handle
-  * @param  __GX_INDEX__ Group index
-  * @retval SET or RESET
-  */
-#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
-  ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \
-    (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup TSC_Private_Macros TSC Private Macros
-  * @{
-  */
-
-#define IS_TSC_CTPH(__VALUE__)          (((__VALUE__) == TSC_CTPH_1CYCLE)   || \
-                                         ((__VALUE__) == TSC_CTPH_2CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPH_3CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPH_4CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPH_5CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPH_6CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPH_7CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPH_8CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPH_9CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPH_10CYCLES) || \
-                                         ((__VALUE__) == TSC_CTPH_11CYCLES) || \
-                                         ((__VALUE__) == TSC_CTPH_12CYCLES) || \
-                                         ((__VALUE__) == TSC_CTPH_13CYCLES) || \
-                                         ((__VALUE__) == TSC_CTPH_14CYCLES) || \
-                                         ((__VALUE__) == TSC_CTPH_15CYCLES) || \
-                                         ((__VALUE__) == TSC_CTPH_16CYCLES))
-
-#define IS_TSC_CTPL(__VALUE__)          (((__VALUE__) == TSC_CTPL_1CYCLE)   || \
-                                         ((__VALUE__) == TSC_CTPL_2CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPL_3CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPL_4CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPL_5CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPL_6CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPL_7CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPL_8CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPL_9CYCLES)  || \
-                                         ((__VALUE__) == TSC_CTPL_10CYCLES) || \
-                                         ((__VALUE__) == TSC_CTPL_11CYCLES) || \
-                                         ((__VALUE__) == TSC_CTPL_12CYCLES) || \
-                                         ((__VALUE__) == TSC_CTPL_13CYCLES) || \
-                                         ((__VALUE__) == TSC_CTPL_14CYCLES) || \
-                                         ((__VALUE__) == TSC_CTPL_15CYCLES) || \
-                                         ((__VALUE__) == TSC_CTPL_16CYCLES))
-
-#define IS_TSC_SS(__VALUE__)            (((FunctionalState)(__VALUE__) == DISABLE)\
-                                         || ((FunctionalState)(__VALUE__) == ENABLE))
-
-#define IS_TSC_SSD(__VALUE__)           (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL)))
-
-#define IS_TSC_SS_PRESC(__VALUE__)      (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2))
-
-#define IS_TSC_PG_PRESC(__VALUE__)      (((__VALUE__) == TSC_PG_PRESC_DIV1)  || \
-                                         ((__VALUE__) == TSC_PG_PRESC_DIV2)  || \
-                                         ((__VALUE__) == TSC_PG_PRESC_DIV4)  || \
-                                         ((__VALUE__) == TSC_PG_PRESC_DIV8)  || \
-                                         ((__VALUE__) == TSC_PG_PRESC_DIV16) || \
-                                         ((__VALUE__) == TSC_PG_PRESC_DIV32) || \
-                                         ((__VALUE__) == TSC_PG_PRESC_DIV64) || \
-                                         ((__VALUE__) == TSC_PG_PRESC_DIV128))
-
-#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__)    ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \
-                                                          ((__CTPL__) > TSC_CTPL_2CYCLES)) ||   \
-                                                         (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \
-                                                          ((__CTPL__) > TSC_CTPL_1CYCLE))  ||   \
-                                                         (((__PGPSC__) > TSC_PG_PRESC_DIV2)  && \
-                                                          (((__CTPL__) == TSC_CTPL_1CYCLE) ||   \
-                                                           ((__CTPL__) > TSC_CTPL_1CYCLE))))
-
-#define IS_TSC_MCV(__VALUE__)           (((__VALUE__) == TSC_MCV_255)  || \
-                                         ((__VALUE__) == TSC_MCV_511)  || \
-                                         ((__VALUE__) == TSC_MCV_1023) || \
-                                         ((__VALUE__) == TSC_MCV_2047) || \
-                                         ((__VALUE__) == TSC_MCV_4095) || \
-                                         ((__VALUE__) == TSC_MCV_8191) || \
-                                          ((__VALUE__) == TSC_MCV_16383))
-
-#define IS_TSC_IODEF(__VALUE__)         (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
-
-#define IS_TSC_SYNC_POL(__VALUE__)      (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\
-                                         || ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
-
-#define IS_TSC_ACQ_MODE(__VALUE__)      (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))
-
-#define IS_TSC_MCE_IT(__VALUE__)        (((FunctionalState)(__VALUE__) == DISABLE)\
-                                         || ((FunctionalState)(__VALUE__) == ENABLE))
-
-#define IS_TSC_GROUP_INDEX(__VALUE__)   (((__VALUE__) == 0UL)\
-                                         || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))
-
-#define IS_TSC_GROUP(__VALUE__)         (((__VALUE__) == 0UL)                               ||\
-                                         (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\
-                                         (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\
-                                         (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\
-                                         (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\
-                                         (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\
-                                         (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\
-                                         (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\
-                                         (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\
-                                         (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\
-                                         (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\
-                                         (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\
-                                         (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\
-                                         (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\
-                                         (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\
-                                         (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\
-                                         (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\
-                                         (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\
-                                         (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\
-                                         (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\
-                                         (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\
-                                         (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\
-                                         (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\
-                                         (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\
-                                         (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\
-                                         (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\
-                                         (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\
-                                         (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\
-                                         (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\
-                                         (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\
-                                         (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\
-                                         (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\
-                                         (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TSC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc);
-HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
-void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc);
-void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID,
-                                           pTSC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc);
-HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc);
-HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc);
-HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc);
-HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc);
-TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index);
-uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index);
-/**
-  * @}
-  */
-
-/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config);
-HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice);
-/**
-  * @}
-  */
-
-/** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc);
-/**
-  * @}
-  */
-
-/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-/******* TSC IRQHandler and Callbacks used in Interrupt mode */
-void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc);
-void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc);
-void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* TSC */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_TSC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h
deleted file mode 100644
index 889f33e0d6..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h
+++ /dev/null
@@ -1,1591 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_uart.h
-  * @author  MCD Application Team
-  * @brief   Header file of UART HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_UART_H
-#define STM32L0xx_HAL_UART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup UART
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Types UART Exported Types
-  * @{
-  */
-
-/**
-  * @brief UART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                /*!< This member configures the UART communication baud rate.
-                                         The baud rate register is computed using the following formula:
-                                         LPUART:
-                                         =======
-                                         Baud Rate Register = ((256 * lpuart_ker_ck) / ((huart->Init.BaudRate)))
-                                         where lpuart_ker_ck is the UART input clock
-                                         UART:
-                                         =====
-                                         - If oversampling is 16 or in LIN mode,
-                                            Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate)))
-                                         - If oversampling is 8,
-                                            Baud Rate Register[15:4] = ((2 * uart_ker_ck) /
-                                                                        ((huart->Init.BaudRate)))[15:4]
-                                            Baud Rate Register[3] =  0
-                                            Baud Rate Register[2:0] =  (((2 * uart_ker_ck) /
-                                                                        ((huart->Init.BaudRate)))[3:0]) >> 1
-                                         where uart_ker_ck is the UART input clock */
-
-  uint32_t WordLength;              /*!< Specifies the number of data bits transmitted or received in a frame.
-                                         This parameter can be a value of @ref UARTEx_Word_Length. */
-
-  uint32_t StopBits;                /*!< Specifies the number of stop bits transmitted.
-                                         This parameter can be a value of @ref UART_Stop_Bits. */
-
-  uint32_t Parity;                  /*!< Specifies the parity mode.
-                                         This parameter can be a value of @ref UART_Parity
-                                         @note When parity is enabled, the computed parity is inserted
-                                               at the MSB position of the transmitted data (9th bit when
-                                               the word length is set to 9 data bits; 8th bit when the
-                                               word length is set to 8 data bits). */
-
-  uint32_t Mode;                    /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                         This parameter can be a value of @ref UART_Mode. */
-
-  uint32_t HwFlowCtl;               /*!< Specifies whether the hardware flow control mode is enabled
-                                         or disabled.
-                                         This parameter can be a value of @ref UART_Hardware_Flow_Control. */
-
-  uint32_t OverSampling;            /*!< Specifies whether the Over sampling 8 is enabled or disabled,
-                                         to achieve higher speed (up to f_PCLK/8).
-                                         This parameter can be a value of @ref UART_Over_Sampling. */
-
-  uint32_t OneBitSampling;          /*!< Specifies whether a single sample or three samples' majority vote is selected.
-                                         Selecting the single sample method increases the receiver tolerance to clock
-                                         deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
-
-
-} UART_InitTypeDef;
-
-/**
-  * @brief  UART Advanced Features initialization structure definition
-  */
-typedef struct
-{
-  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
-                                       Advanced Features may be initialized at the same time .
-                                       This parameter can be a value of
-                                       @ref UART_Advanced_Features_Initialization_Type. */
-
-  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
-                                       This parameter can be a value of @ref UART_Tx_Inv. */
-
-  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
-                                       This parameter can be a value of @ref UART_Rx_Inv. */
-
-  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
-                                       vs negative/inverted logic).
-                                       This parameter can be a value of @ref UART_Data_Inv. */
-
-  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
-                                       This parameter can be a value of @ref UART_Rx_Tx_Swap. */
-
-  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
-                                       This parameter can be a value of @ref UART_Overrun_Disable. */
-
-  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
-                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
-
-  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
-                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
-
-  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
-                                       detection is carried out.
-                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
-
-  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
-                                       This parameter can be a value of @ref UART_MSB_First. */
-} UART_AdvFeatureInitTypeDef;
-
-/**
-  * @brief HAL UART State definition
-  * @note  HAL UART State value is a combination of 2 different substates:
-  *        gState and RxState (see @ref UART_State_Definition).
-  *        - gState contains UART state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized. HAL UART Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (Peripheral busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */
-typedef uint32_t HAL_UART_StateTypeDef;
-
-/**
-  * @brief UART clock sources definition
-  */
-typedef enum
-{
-  UART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */
-  UART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */
-  UART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */
-  UART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */
-  UART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
-  UART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
-} UART_ClockSourceTypeDef;
-
-/**
-  * @brief HAL UART Reception type definition
-  * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.
-  *        It is expected to admit following values :
-  *           HAL_UART_RECEPTION_STANDARD         = 0x00U,
-  *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,
-  *           HAL_UART_RECEPTION_TORTO            = 0x02U,
-  *           HAL_UART_RECEPTION_TOCHARMATCH      = 0x03U,
-  */
-typedef uint32_t HAL_UART_RxTypeTypeDef;
-
-/**
-  * @brief  UART handle Structure definition
-  */
-typedef struct __UART_HandleTypeDef
-{
-  USART_TypeDef            *Instance;                /*!< UART registers base address        */
-
-  UART_InitTypeDef         Init;                     /*!< UART communication parameters      */
-
-  UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */
-
-  uint8_t                  *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
-
-  uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */
-
-  __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */
-
-  uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */
-
-  uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */
-
-  __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */
-
-  uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */
-
-  __IO HAL_UART_RxTypeTypeDef ReceptionType;         /*!< Type of ongoing reception          */
-
-  void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
-
-  void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
-
-  DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef           Lock;                    /*!< Locking object                     */
-
-  __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management
-                                                          and also related to Tx operations. This parameter
-                                                          can be a value of @ref HAL_UART_StateTypeDef */
-
-  __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations. This
-                                                          parameter can be a value of @ref HAL_UART_StateTypeDef */
-
-  __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
-  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
-  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
-  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
-  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
-  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
-  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
-  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
-  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
-  void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback     */
-
-  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
-  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
-#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-} UART_HandleTypeDef;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL UART Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
-  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
-  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
-  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
-  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
-  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
-  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
-  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
-  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
-
-  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
-  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
-
-} HAL_UART_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL UART Callback pointer definition
-  */
-typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
-typedef  void (*pUART_RxEventCallbackTypeDef)
-(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
-
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported Constants
-  * @{
-  */
-
-/** @defgroup UART_State_Definition UART State Code Definition
-  * @{
-  */
-#define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized
-                                                          Value is allowed for gState and RxState */
-#define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use
-                                                          Value is allowed for gState and RxState */
-#define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing
-                                                          Value is allowed for gState only */
-#define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing
-                                                          Value is allowed for gState only */
-#define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing
-                                                          Value is allowed for RxState only */
-#define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing
-                                                          Not to be used for neither gState nor RxState.Value is result
-                                                          of combination (Or) between gState and RxState values */
-#define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state
-                                                          Value is allowed for gState only */
-#define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error
-                                                          Value is allowed for gState only */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Error_Definition   UART Error Definition
-  * @{
-  */
-#define  HAL_UART_ERROR_NONE             (0x00000000U)    /*!< No error                */
-#define  HAL_UART_ERROR_PE               (0x00000001U)    /*!< Parity error            */
-#define  HAL_UART_ERROR_NE               (0x00000002U)    /*!< Noise error             */
-#define  HAL_UART_ERROR_FE               (0x00000004U)    /*!< Frame error             */
-#define  HAL_UART_ERROR_ORE              (0x00000008U)    /*!< Overrun error           */
-#define  HAL_UART_ERROR_DMA              (0x00000010U)    /*!< DMA transfer error      */
-#define  HAL_UART_ERROR_RTO              (0x00000020U)    /*!< Receiver Timeout error  */
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define  HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)    /*!< Invalid Callback error  */
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
-  * @{
-  */
-#define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
-#define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */
-#define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
-#define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Parity  UART Parity
-  * @{
-  */
-#define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */
-#define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */
-#define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
-  * @{
-  */
-#define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */
-#define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */
-#define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */
-#define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Mode UART Transfer Mode
-  * @{
-  */
-#define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */
-#define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */
-#define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
-/**
-  * @}
-  */
-
-/** @defgroup UART_State  UART State
-  * @{
-  */
-#define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */
-#define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
-  * @{
-  */
-#define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */
-#define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
-  * @{
-  */
-#define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */
-#define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
-  * @{
-  */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection
-                                                                              on start bit              */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection
-                                                                              on falling edge           */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection
-                                                                              on 0x7F frame detection   */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection
-                                                                              on 0x55 frame detection   */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
-  * @{
-  */
-#define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */
-#define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_LIN    UART Local Interconnection Network mode
-  * @{
-  */
-#define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */
-#define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
-  * @{
-  */
-#define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */
-#define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_DMA_Tx    UART DMA Tx
-  * @{
-  */
-#define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */
-#define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_DMA_Rx   UART DMA Rx
-  * @{
-  */
-#define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */
-#define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
-  * @{
-  */
-#define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */
-#define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
-  * @{
-  */
-#define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */
-#define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Request_Parameters UART Request Parameters
-  * @{
-  */
-#define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
-#define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */
-#define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */
-#define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
-#define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
-  * @{
-  */
-#define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */
-#define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */
-#define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */
-#define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */
-#define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */
-#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */
-#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */
-#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */
-#define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
-  * @{
-  */
-#define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */
-#define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
-  * @{
-  */
-#define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */
-#define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
-  * @{
-  */
-#define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */
-#define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
-  * @{
-  */
-#define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */
-#define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
-  * @{
-  */
-#define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */
-#define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */
-/**
-  * @}
-  */
-
-/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
-  * @{
-  */
-#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */
-/**
-  * @}
-  */
-
-/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
-  * @{
-  */
-#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */
-#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */
-/**
-  * @}
-  */
-
-/** @defgroup UART_MSB_First   UART Advanced Feature MSB First
-  * @{
-  */
-#define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received
-                                                                         first disable                      */
-#define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received
-                                                                         first enable                       */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
-  * @{
-  */
-#define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */
-#define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
-  * @{
-  */
-#define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */
-#define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
-  * @{
-  */
-#define UART_CR2_ADDRESS_LSB_POS             24U             /*!< UART address-matching LSB position in CR2 register */
-/**
-  * @}
-  */
-
-/** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
-  * @{
-  */
-#define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                     */
-#define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                   */
-#define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register
-                                                                         not empty or RXFIFO is not empty            */
-/**
-  * @}
-  */
-
-/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
-  * @{
-  */
-#define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */
-#define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
-  * @{
-  */
-#define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB
-                                                          position in CR1 register */
-/**
-  * @}
-  */
-
-/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
-  * @{
-  */
-#define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB
-                                                          position in CR1 register */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
-  * @{
-  */
-#define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */
-/**
-  * @}
-  */
-
-/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
-  * @{
-  */
-#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Flags     UART Status Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the ISR register
-  * @{
-  */
-#define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */
-#define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */
-#define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */
-#define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */
-#define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */
-#define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */
-#define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */
-#define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */
-#define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */
-#define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */
-#define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */
-#define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */
-#define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */
-#define UART_FLAG_TXE                       USART_ISR_TXE           /*!< UART transmit data register empty         */
-#define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */
-#define UART_FLAG_RXNE                      USART_ISR_RXNE          /*!< UART read data register not empty         */
-#define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */
-#define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */
-#define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */
-#define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */
-#define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Interrupt_definition   UART Interrupts Definition
-  *        Elements values convention: 000ZZZZZ0XXYYYYYb
-  *           - YYYYY  : Interrupt source position in the XX register (5bits)
-  *           - XX  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  *           - ZZZZZ  : Flag position in the ISR register(5bits)
-  *        Elements values convention: 000000000XXYYYYYb
-  *           - YYYYY  : Interrupt source position in the XX register (5bits)
-  *           - XX  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  *        Elements values convention: 0000ZZZZ00000000b
-  *           - ZZZZ  : Flag position in the ISR register(4bits)
-  * @{
-  */
-#define UART_IT_PE                          0x0028U              /*!< UART parity error interruption                 */
-#define UART_IT_TXE                         0x0727U              /*!< UART transmit data register empty interruption */
-#define UART_IT_TC                          0x0626U              /*!< UART transmission complete interruption        */
-#define UART_IT_RXNE                        0x0525U              /*!< UART read data register not empty interruption */
-#define UART_IT_IDLE                        0x0424U              /*!< UART idle interruption                         */
-#define UART_IT_LBD                         0x0846U              /*!< UART LIN break detection interruption          */
-#define UART_IT_CTS                         0x096AU              /*!< UART CTS interruption                          */
-#define UART_IT_CM                          0x112EU              /*!< UART character match interruption              */
-#define UART_IT_WUF                         0x1476U              /*!< UART wake-up from stop mode interruption       */
-#define UART_IT_RTO                         0x0B3AU              /*!< UART receiver timeout interruption             */
-
-#define UART_IT_ERR                         0x0060U              /*!< UART error interruption                        */
-
-#define UART_IT_ORE                         0x0300U              /*!< UART overrun error interruption                */
-#define UART_IT_NE                          0x0200U              /*!< UART noise error interruption                  */
-#define UART_IT_FE                          0x0100U              /*!< UART frame error interruption                  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
-  * @{
-  */
-#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
-#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
-#define UART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise Error detected Clear Flag   */
-#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
-#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
-#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
-#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
-#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
-#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
-#define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
-#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_RECEPTION_TYPE_Values  UART Reception type values
-  * @{
-  */
-#define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */
-#define HAL_UART_RECEPTION_TOIDLE            (0x00000001U)             /*!< Reception till completion or IDLE event  */
-#define HAL_UART_RECEPTION_TORTO             (0x00000002U)             /*!< Reception till completion or RTO event   */
-#define HAL_UART_RECEPTION_TOCHARMATCH       (0x00000003U)             /*!< Reception till completion or CM event    */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
-  * @{
-  */
-
-/** @brief  Reset UART handle states.
-  * @param  __HANDLE__ UART handle.
-  * @retval None
-  */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
-                                                       (__HANDLE__)->MspInitCallback = NULL;             \
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
-                                                     } while(0U)
-#else
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
-                                                     } while(0U)
-#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
-
-/** @brief  Flush the UART Data registers.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
-  do{                \
-    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
-    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
-  }  while(0U)
-
-/** @brief  Clear the specified UART pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
-  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
-  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
-  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
-  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
-  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
-  *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag
-  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
-  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
-  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
-  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief  Clear the UART PE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
-
-/** @brief  Clear the UART FE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
-
-/** @brief  Clear the UART NE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
-
-/** @brief  Clear the UART ORE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
-
-/** @brief  Clear the UART IDLE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
-
-
-/** @brief  Check whether the specified UART flag is set or not.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
-  *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
-  *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
-  *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
-  *            @arg @ref UART_FLAG_SBKF  Send Break flag
-  *            @arg @ref UART_FLAG_CMF   Character match flag
-  *            @arg @ref UART_FLAG_BUSY  Busy flag
-  *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
-  *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
-  *            @arg @ref UART_FLAG_CTS   CTS Change flag
-  *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
-  *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
-  *            @arg @ref UART_FLAG_TC    Transmission Complete flag
-  *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
-  *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag
-  *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
-  *            @arg @ref UART_FLAG_ORE   Overrun Error flag
-  *            @arg @ref UART_FLAG_NE    Noise Error flag
-  *            @arg @ref UART_FLAG_FE    Framing Error flag
-  *            @arg @ref UART_FLAG_PE    Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Enable the specified UART interrupt.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
-  *            @arg @ref UART_IT_CM    Character match interrupt
-  *            @arg @ref UART_IT_CTS   CTS change interrupt
-  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
-  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
-  *            @arg @ref UART_IT_TC    Transmission complete interrupt
-  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
-  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
-  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
-  *            @arg @ref UART_IT_PE    Parity Error interrupt
-  *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (\
-                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
-                                                           ((__HANDLE__)->Instance->CR1 |= (1U <<\
-                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
-                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
-                                                           ((__HANDLE__)->Instance->CR2 |= (1U <<\
-                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
-                                                           ((__HANDLE__)->Instance->CR3 |= (1U <<\
-                                                               ((__INTERRUPT__) & UART_IT_MASK))))
-
-/** @brief  Disable the specified UART interrupt.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
-  *            @arg @ref UART_IT_CM    Character match interrupt
-  *            @arg @ref UART_IT_CTS   CTS change interrupt
-  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
-  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
-  *            @arg @ref UART_IT_TC    Transmission complete interrupt
-  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
-  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
-  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
-  *            @arg @ref UART_IT_PE    Parity Error interrupt
-  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (\
-                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
-                                                           ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
-                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
-                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
-                                                           ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
-                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
-                                                               ((__INTERRUPT__) & UART_IT_MASK))))
-
-/** @brief  Check whether the specified UART interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @param  __INTERRUPT__ specifies the UART interrupt to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
-  *            @arg @ref UART_IT_CM    Character match interrupt
-  *            @arg @ref UART_IT_CTS   CTS change interrupt
-  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
-  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
-  *            @arg @ref UART_IT_TC    Transmission complete interrupt
-  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
-  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
-  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
-  *            @arg @ref UART_IT_PE    Parity Error interrupt
-  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
-                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
-
-/** @brief  Check whether the specified UART interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @param  __INTERRUPT__ specifies the UART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
-  *            @arg @ref UART_IT_CM    Character match interrupt
-  *            @arg @ref UART_IT_CTS   CTS change interrupt
-  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
-  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
-  *            @arg @ref UART_IT_TC    Transmission complete interrupt
-  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
-  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
-  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
-  *            @arg @ref UART_IT_PE    Parity Error interrupt
-  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
-                                                                (__HANDLE__)->Instance->CR1 : \
-                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
-                                                                 (__HANDLE__)->Instance->CR2 : \
-                                                                 (__HANDLE__)->Instance->CR3)) & (1U <<\
-                                                                     (((uint16_t)(__INTERRUPT__)) &\
-                                                                      UART_IT_MASK)))  != RESET) ? SET : RESET)
-
-/** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
-  *                       to clear the corresponding interrupt
-  *          This parameter can be one of the following values:
-  *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag
-  *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag
-  *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag
-  *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag
-  *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag
-  *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag
-  *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag
-  *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag
-  *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag
-  *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag
-  *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-/** @brief  Set a specific UART request flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @param  __REQ__ specifies the request flag to set
-  *          This parameter can be one of the following values:
-  *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
-  *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
-  *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
-  *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
-  *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
-  * @retval None
-  */
-#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-
-/** @brief  Enable the UART one bit sample method.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief  Disable the UART one bit sample method.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
-
-/** @brief  Enable UART.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief  Disable UART.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/** @brief  Enable CTS flow control.
-  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled
-  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
-  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)               \
-  do{                                                             \
-    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;               \
-  } while(0U)
-
-/** @brief  Disable CTS flow control.
-  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled
-  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
-  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)               \
-  do{                                                              \
-    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);             \
-  } while(0U)
-
-/** @brief  Enable RTS flow control.
-  * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled
-  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
-  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)              \
-  do{                                                            \
-    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;              \
-  } while(0U)
-
-/** @brief  Disable RTS flow control.
-  * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled
-  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
-  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)              \
-  do{                                                             \
-    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);            \
-  } while(0U)
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup UART_Private_Macros   UART Private Macros
-  * @{
-  */
-
-/** @brief  BRR division operation to set BRR register with LPUART.
-  * @param  __PCLK__ LPUART clock.
-  * @param  __BAUD__ Baud rate set by the user.
-  * @retval Division result
-  */
-#define UART_DIV_LPUART(__PCLK__, __BAUD__)      (((((uint64_t)(__PCLK__)*256U)) + ((__BAUD__)/2U)) / (__BAUD__))
-
-/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
-  * @param  __PCLK__ UART clock.
-  * @param  __BAUD__ Baud rate set by the user.
-  * @retval Division result
-  */
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__)   ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
-
-/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
-  * @param  __PCLK__ UART clock.
-  * @param  __BAUD__ Baud rate set by the user.
-  * @retval Division result
-  */
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__)  (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
-
-/** @brief  Check whether or not UART instance is Low Power UART.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
-  */
-#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
-
-/** @brief  Check UART Baud rate.
-  * @param  __BAUDRATE__ Baudrate specified by the user.
-  *         The maximum Baud Rate is derived from the maximum clock on L0 (i.e. 32 MHz)
-  *         divided by the smallest oversampling used on the USART (i.e. 8)
-  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
-  */
-#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001U)
-
-/** @brief  Check UART assertion time.
-  * @param  __TIME__ 5-bit value assertion time.
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
-
-/** @brief  Check UART deassertion time.
-  * @param  __TIME__ 5-bit value deassertion time.
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
-
-/**
-  * @brief Ensure that UART frame number of stop bits is valid.
-  * @param __STOPBITS__ UART frame number of stop bits.
-  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
-  */
-#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
-                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
-                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
-                                        ((__STOPBITS__) == UART_STOPBITS_2))
-
-/**
-  * @brief Ensure that LPUART frame number of stop bits is valid.
-  * @param __STOPBITS__ LPUART frame number of stop bits.
-  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
-  */
-#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
-                                          ((__STOPBITS__) == UART_STOPBITS_2))
-
-/**
-  * @brief Ensure that UART frame parity is valid.
-  * @param __PARITY__ UART frame parity.
-  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
-  */
-#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
-                                    ((__PARITY__) == UART_PARITY_EVEN) || \
-                                    ((__PARITY__) == UART_PARITY_ODD))
-
-/**
-  * @brief Ensure that UART hardware flow control is valid.
-  * @param __CONTROL__ UART hardware flow control.
-  * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
-  */
-#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
-  (((__CONTROL__) == UART_HWCONTROL_NONE) || \
-   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
-   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
-   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
-
-/**
-  * @brief Ensure that UART communication mode is valid.
-  * @param __MODE__ UART communication mode.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
-
-/**
-  * @brief Ensure that UART state is valid.
-  * @param __STATE__ UART state.
-  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
-  */
-#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
-                                  ((__STATE__) == UART_STATE_ENABLE))
-
-/**
-  * @brief Ensure that UART oversampling is valid.
-  * @param __SAMPLING__ UART oversampling.
-  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
-  */
-#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
-                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))
-
-/**
-  * @brief Ensure that UART frame sampling is valid.
-  * @param __ONEBIT__ UART frame sampling.
-  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
-  */
-#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
-                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
-
-/**
-  * @brief Ensure that UART auto Baud rate detection mode is valid.
-  * @param __MODE__ UART auto Baud rate detection mode.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
-                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
-                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
-                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
-
-/**
-  * @brief Ensure that UART receiver timeout setting is valid.
-  * @param __TIMEOUT__ UART receiver timeout setting.
-  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
-  */
-#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
-                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
-
-/** @brief  Check the receiver timeout value.
-  * @note   The maximum UART receiver timeout value is 0xFFFFFF.
-  * @param  __TIMEOUTVALUE__ receiver timeout value.
-  * @retval Test result (TRUE or FALSE)
-  */
-#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
-
-/**
-  * @brief Ensure that UART LIN state is valid.
-  * @param __LIN__ UART LIN state.
-  * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
-  */
-#define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
-                                     ((__LIN__) == UART_LIN_ENABLE))
-
-/**
-  * @brief Ensure that UART LIN break detection length is valid.
-  * @param __LENGTH__ UART LIN break detection length.
-  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
-  */
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
-                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
-
-/**
-  * @brief Ensure that UART DMA TX state is valid.
-  * @param __DMATX__ UART DMA TX state.
-  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
-  */
-#define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
-                                       ((__DMATX__) == UART_DMA_TX_ENABLE))
-
-/**
-  * @brief Ensure that UART DMA RX state is valid.
-  * @param __DMARX__ UART DMA RX state.
-  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
-  */
-#define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
-                                       ((__DMARX__) == UART_DMA_RX_ENABLE))
-
-/**
-  * @brief Ensure that UART half-duplex state is valid.
-  * @param __HDSEL__ UART half-duplex state.
-  * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
-  */
-#define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
-                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
-
-/**
-  * @brief Ensure that UART wake-up method is valid.
-  * @param __WAKEUP__ UART wake-up method .
-  * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
-  */
-#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
-                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
-
-/**
-  * @brief Ensure that UART request parameter is valid.
-  * @param __PARAM__ UART request parameter.
-  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
-  */
-#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
-                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
-                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
-                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
-                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
-
-/**
-  * @brief Ensure that UART advanced features initialization is valid.
-  * @param __INIT__ UART advanced features initialization.
-  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
-                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
-                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
-                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
-                                                            UART_ADVFEATURE_SWAP_INIT              | \
-                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
-                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
-                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
-                                                            UART_ADVFEATURE_MSBFIRST_INIT))
-
-/**
-  * @brief Ensure that UART frame TX inversion setting is valid.
-  * @param __TXINV__ UART frame TX inversion setting.
-  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
-                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
-
-/**
-  * @brief Ensure that UART frame RX inversion setting is valid.
-  * @param __RXINV__ UART frame RX inversion setting.
-  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
-                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
-
-/**
-  * @brief Ensure that UART frame data inversion setting is valid.
-  * @param __DATAINV__ UART frame data inversion setting.
-  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
-                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
-
-/**
-  * @brief Ensure that UART frame RX/TX pins swap setting is valid.
-  * @param __SWAP__ UART frame RX/TX pins swap setting.
-  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
-                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
-
-/**
-  * @brief Ensure that UART frame overrun setting is valid.
-  * @param __OVERRUN__ UART frame overrun setting.
-  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
-  */
-#define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
-                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
-
-/**
-  * @brief Ensure that UART auto Baud rate state is valid.
-  * @param __AUTOBAUDRATE__ UART auto Baud rate state.
-  * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
-                                                            UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
-                                                           ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
-
-/**
-  * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
-  * @param __DMA__ UART DMA enabling or disabling on error setting.
-  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
-                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
-
-/**
-  * @brief Ensure that UART frame MSB first setting is valid.
-  * @param __MSBFIRST__ UART frame MSB first setting.
-  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
-                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
-
-/**
-  * @brief Ensure that UART stop mode state is valid.
-  * @param __STOPMODE__ UART stop mode state.
-  * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
-                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
-
-/**
-  * @brief Ensure that UART mute mode state is valid.
-  * @param __MUTE__ UART mute mode state.
-  * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
-  */
-#define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
-                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
-
-/**
-  * @brief Ensure that UART wake-up selection is valid.
-  * @param __WAKE__ UART wake-up selection.
-  * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
-  */
-#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
-                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
-                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
-
-/**
-  * @brief Ensure that UART driver enable polarity is valid.
-  * @param __POLARITY__ UART driver enable polarity.
-  * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
-  */
-#define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
-                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))
-
-
-/**
-  * @}
-  */
-
-/* Include UART HAL Extended module */
-#include "stm32l0xx_hal_uart_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Functions UART Exported Functions
-  * @{
-  */
-
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
-                                            pUART_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
-
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
-
-void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
-HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
-
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
-  * @{
-  */
-
-/* Peripheral State and Errors functions  **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions -----------------------------------------------------------*/
-/** @addtogroup UART_Private_Functions UART Private Functions
-  * @{
-  */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-void              UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
-                                              uint32_t Tickstart, uint32_t Timeout);
-void              UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-
-/**
-  * @}
-  */
-
-/* Private variables -----------------------------------------------------------*/
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_UART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h
deleted file mode 100644
index bb978bdd90..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h
+++ /dev/null
@@ -1,453 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_uart_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of UART HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_UART_EX_H
-#define STM32L0xx_HAL_UART_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup UARTEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  UART wake up from stop mode parameters
-  */
-typedef struct
-{
-  uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
-                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
-                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
-                                    be filled up. */
-
-  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
-                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
-
-  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
-} UART_WakeUpTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
-  * @{
-  */
-
-/** @defgroup UARTEx_Word_Length UARTEx Word Length
-  * @{
-  */
-#define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
-#define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
-#define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
-/**
-  * @}
-  */
-
-/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
-  * @{
-  */
-#define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
-#define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UARTEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup UARTEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
-                                   uint32_t DeassertionTime);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UARTEx_Exported_Functions_Group2
-  * @{
-  */
-
-void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UARTEx_Exported_Functions_Group3
-  * @{
-  */
-
-/* Peripheral Control functions  **********************************************/
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
-
-HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart);
-
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
-
-
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
-                                           uint32_t Timeout);
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
-  * @{
-  */
-
-/** @brief  Report the UART clock source.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @param  __CLOCKSOURCE__ output variable.
-  * @retval UART clocking source, written in __CLOCKSOURCE__.
-  */
-#if defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L010xB) || defined (STM32L010x8) || defined (STM32L010x6) || defined (STM32L010x4)
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
-  do {                                                        \
-    if((__HANDLE__)->Instance == USART2)                      \
-    {                                                         \
-      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
-      {                                                       \
-        case RCC_USART2CLKSOURCE_PCLK1:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else if((__HANDLE__)->Instance == LPUART1)                \
-    {                                                         \
-      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
-      {                                                       \
-        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_HSI:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_LSE:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else                                                      \
-    {                                                         \
-      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
-    }                                                         \
-  } while(0)
-
-#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx)
-
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
-  do {                                                        \
-    if((__HANDLE__)->Instance == USART1)                      \
-    {                                                         \
-      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
-      {                                                       \
-        case RCC_USART1CLKSOURCE_PCLK2:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else if((__HANDLE__)->Instance == USART2)                 \
-    {                                                         \
-      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
-      {                                                       \
-        case RCC_USART2CLKSOURCE_PCLK1:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else if((__HANDLE__)->Instance == LPUART1)                \
-    {                                                         \
-      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
-      {                                                       \
-        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_HSI:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_LSE:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else                                                      \
-    {                                                         \
-      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
-    }                                                         \
-  } while(0)
-
-#else
-
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
-  do {                                                        \
-    if((__HANDLE__)->Instance == USART1)                      \
-    {                                                         \
-      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
-      {                                                       \
-        case RCC_USART1CLKSOURCE_PCLK2:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else if((__HANDLE__)->Instance == USART2)                 \
-    {                                                         \
-      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
-      {                                                       \
-        case RCC_USART2CLKSOURCE_PCLK1:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else if((__HANDLE__)->Instance == USART4)                 \
-    {                                                         \
-      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
-    }                                                         \
-    else if((__HANDLE__)->Instance == USART5)                 \
-    {                                                         \
-      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
-    }                                                         \
-    else if((__HANDLE__)->Instance == LPUART1)                \
-    {                                                         \
-      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
-      {                                                       \
-        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_HSI:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_LSE:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-      }                                                       \
-    }                                                         \
-    else                                                      \
-    {                                                         \
-      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
-    }                                                         \
-  } while(0)
-#endif /* (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx) || (STM32L010xB) || (STM32L010x8) || (STM32L010x6) || (STM32L010x4)*/
-
-
-/** @brief  Report the UART mask to apply to retrieve the received data
-  *         according to the word length and to the parity bits activation.
-  * @note   If PCE = 1, the parity bit is not included in the data extracted
-  *         by the reception API().
-  *         This masking operation is not carried out in the case of
-  *         DMA transfers.
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
-  */
-#define UART_MASK_COMPUTATION(__HANDLE__)                             \
-  do {                                                                \
-    if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
-    {                                                                 \
-      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x01FFU ;                                \
-      }                                                               \
-      else                                                            \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x00FFU ;                                \
-      }                                                               \
-    }                                                                 \
-    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
-    {                                                                 \
-      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x00FFU ;                                \
-      }                                                               \
-      else                                                            \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x007FU ;                                \
-      }                                                               \
-    }                                                                 \
-    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
-    {                                                                 \
-      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x007FU ;                                \
-      }                                                               \
-      else                                                            \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x003FU ;                                \
-      }                                                               \
-    }                                                                 \
-    else                                                              \
-    {                                                                 \
-      (__HANDLE__)->Mask = 0x0000U;                                   \
-    }                                                                 \
-  } while(0U)
-
-/**
-  * @brief Ensure that UART frame length is valid.
-  * @param __LENGTH__ UART frame length.
-  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
-  */
-#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
-                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
-                                         ((__LENGTH__) == UART_WORDLENGTH_9B))
-
-/**
-  * @brief Ensure that UART wake-up address length is valid.
-  * @param __ADDRESS__ UART wake-up address length.
-  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
-  */
-#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
-                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_UART_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart.h
deleted file mode 100644
index 355c7a2520..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart.h
+++ /dev/null
@@ -1,784 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_usart.h
-  * @author  MCD Application Team
-  * @brief   Header file of USART HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_USART_H
-#define STM32L0xx_HAL_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup USART
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup USART_Exported_Types USART Exported Types
-  * @{
-  */
-
-/**
-  * @brief USART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                              Baud Rate Register[15:4] = ((2 * fclk_pres) /
-                                              ((huart->Init.BaudRate)))[15:4]
-                                              Baud Rate Register[3]    = 0
-                                              Baud Rate Register[2:0]  =  (((2 * fclk_pres) /
-                                              ((huart->Init.BaudRate)))[3:0]) >> 1
-                                              where fclk_pres is the USART input clock frequency
-                                           @note  Oversampling by 8 is systematically applied to
-                                                  achieve high baud rates. */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref USARTEx_Word_Length. */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref USART_Stop_Bits. */
-
-  uint32_t Parity;                   /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref USART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
-
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_Mode. */
-
-  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref USART_Clock_Polarity. */
-
-  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref USART_Clock_Phase. */
-
-  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref USART_Last_Bit. */
-
-} USART_InitTypeDef;
-
-/**
-  * @brief HAL USART State structures definition
-  */
-typedef enum
-{
-  HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized                  */
-  HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use       */
-  HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                 */
-  HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing           */
-  HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing              */
-  HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
-  HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                  */
-  HAL_USART_STATE_ERROR             = 0x04U     /*!< Error                                          */
-} HAL_USART_StateTypeDef;
-
-/**
-  * @brief  USART clock sources definitions
-  */
-typedef enum
-{
-  USART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source     */
-  USART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source     */
-  USART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source       */
-  USART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source    */
-  USART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
-  USART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
-} USART_ClockSourceTypeDef;
-
-/**
-  * @brief  USART handle Structure definition
-  */
-typedef struct __USART_HandleTypeDef
-{
-  USART_TypeDef                 *Instance;               /*!< USART registers base address        */
-
-  USART_InitTypeDef             Init;                    /*!< USART communication parameters      */
-
-  uint8_t                       *pTxBuffPtr;             /*!< Pointer to USART Tx transfer Buffer */
-
-  uint16_t                      TxXferSize;              /*!< USART Tx Transfer size              */
-
-  __IO uint16_t                 TxXferCount;             /*!< USART Tx Transfer Counter           */
-
-  uint8_t                       *pRxBuffPtr;             /*!< Pointer to USART Rx transfer Buffer */
-
-  uint16_t                      RxXferSize;              /*!< USART Rx Transfer size              */
-
-  __IO uint16_t                 RxXferCount;             /*!< USART Rx Transfer Counter           */
-
-  uint16_t                      Mask;                    /*!< USART Rx RDR register mask          */
-
-  void (*RxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Rx IRQ handler  */
-
-  void (*TxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Tx IRQ handler  */
-
-  DMA_HandleTypeDef             *hdmatx;                 /*!< USART Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef             *hdmarx;                 /*!< USART Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef               Lock;                    /*!< Locking object                      */
-
-  __IO HAL_USART_StateTypeDef   State;                   /*!< USART communication state           */
-
-  __IO uint32_t                 ErrorCode;               /*!< USART Error code                    */
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Tx Half Complete Callback        */
-  void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Tx Complete Callback             */
-  void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Half Complete Callback        */
-  void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Rx Complete Callback             */
-  void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart);          /*!< USART Tx Rx Complete Callback          */
-  void (* ErrorCallback)(struct __USART_HandleTypeDef *husart);             /*!< USART Error Callback                   */
-  void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Abort Complete Callback          */
-
-  void (* MspInitCallback)(struct __USART_HandleTypeDef *husart);           /*!< USART Msp Init callback                */
-  void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Msp DeInit callback              */
-#endif  /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-} USART_HandleTypeDef;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL USART Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_USART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< USART Tx Half Complete Callback ID        */
-  HAL_USART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< USART Tx Complete Callback ID             */
-  HAL_USART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< USART Rx Half Complete Callback ID        */
-  HAL_USART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< USART Rx Complete Callback ID             */
-  HAL_USART_TX_RX_COMPLETE_CB_ID          = 0x04U,    /*!< USART Tx Rx Complete Callback ID          */
-  HAL_USART_ERROR_CB_ID                   = 0x05U,    /*!< USART Error Callback ID                   */
-  HAL_USART_ABORT_COMPLETE_CB_ID          = 0x06U,    /*!< USART Abort Complete Callback ID          */
-
-  HAL_USART_MSPINIT_CB_ID                 = 0x09U,    /*!< USART MspInit callback ID                 */
-  HAL_USART_MSPDEINIT_CB_ID               = 0x0AU     /*!< USART MspDeInit callback ID               */
-
-} HAL_USART_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL USART Callback pointer definition
-  */
-typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< pointer to an USART callback function */
-
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_Exported_Constants USART Exported Constants
-  * @{
-  */
-
-/** @defgroup USART_Error_Definition   USART Error Definition
-  * @{
-  */
-#define HAL_USART_ERROR_NONE             (0x00000000U)    /*!< No error                  */
-#define HAL_USART_ERROR_PE               (0x00000001U)    /*!< Parity error              */
-#define HAL_USART_ERROR_NE               (0x00000002U)    /*!< Noise error               */
-#define HAL_USART_ERROR_FE               (0x00000004U)    /*!< Frame error               */
-#define HAL_USART_ERROR_ORE              (0x00000008U)    /*!< Overrun error             */
-#define HAL_USART_ERROR_DMA              (0x00000010U)    /*!< DMA transfer error        */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U)    /*!< Invalid Callback error    */
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-#define  HAL_USART_ERROR_RTO              (0x00000080U)    /*!< Receiver Timeout error  */
-/**
-  * @}
-  */
-
-/** @defgroup USART_Stop_Bits  USART Number of Stop Bits
-  * @{
-  */
-#define USART_STOPBITS_0_5                   USART_CR2_STOP_0                     /*!< USART frame with 0.5 stop bit  */
-#define USART_STOPBITS_1                     0x00000000U                          /*!< USART frame with 1 stop bit    */
-#define USART_STOPBITS_1_5                  (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
-#define USART_STOPBITS_2                     USART_CR2_STOP_1                     /*!< USART frame with 2 stop bits   */
-/**
-  * @}
-  */
-
-/** @defgroup USART_Parity    USART Parity
-  * @{
-  */
-#define USART_PARITY_NONE                   0x00000000U                      /*!< No parity   */
-#define USART_PARITY_EVEN                   USART_CR1_PCE                    /*!< Even parity */
-#define USART_PARITY_ODD                    (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
-/**
-  * @}
-  */
-
-/** @defgroup USART_Mode   USART Mode
-  * @{
-  */
-#define USART_MODE_RX                       USART_CR1_RE                    /*!< RX mode        */
-#define USART_MODE_TX                       USART_CR1_TE                    /*!< TX mode        */
-#define USART_MODE_TX_RX                    (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
-/**
-  * @}
-  */
-
-/** @defgroup USART_Clock  USART Clock
-  * @{
-  */
-#define USART_CLOCK_DISABLE                 0x00000000U       /*!< USART clock disable */
-#define USART_CLOCK_ENABLE                  USART_CR2_CLKEN   /*!< USART clock enable  */
-/**
-  * @}
-  */
-
-/** @defgroup USART_Clock_Polarity  USART Clock Polarity
-  * @{
-  */
-#define USART_POLARITY_LOW                  0x00000000U      /*!< Driver enable signal is active high */
-#define USART_POLARITY_HIGH                 USART_CR2_CPOL   /*!< Driver enable signal is active low  */
-/**
-  * @}
-  */
-
-/** @defgroup USART_Clock_Phase   USART Clock Phase
-  * @{
-  */
-#define USART_PHASE_1EDGE                   0x00000000U      /*!< USART frame phase on first clock transition  */
-#define USART_PHASE_2EDGE                   USART_CR2_CPHA   /*!< USART frame phase on second clock transition */
-/**
-  * @}
-  */
-
-/** @defgroup USART_Last_Bit  USART Last Bit
-  * @{
-  */
-#define USART_LASTBIT_DISABLE               0x00000000U      /*!< USART frame last data bit clock pulse not output to SCLK pin */
-#define USART_LASTBIT_ENABLE                USART_CR2_LBCL   /*!< USART frame last data bit clock pulse output to SCLK pin     */
-/**
-  * @}
-  */
-
-
-/** @defgroup USART_Request_Parameters  USART Request Parameters
-  * @{
-  */
-#define USART_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
-#define USART_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
-/**
-  * @}
-  */
-
-/** @defgroup USART_Flags      USART Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the ISR register
-  * @{
-  */
-#define USART_FLAG_REACK                    USART_ISR_REACK         /*!< USART receive enable acknowledge flag      */
-#define USART_FLAG_TEACK                    USART_ISR_TEACK         /*!< USART transmit enable acknowledge flag     */
-#define USART_FLAG_BUSY                     USART_ISR_BUSY          /*!< USART busy flag                            */
-#define USART_FLAG_TXE                      USART_ISR_TXE           /*!< USART transmit data register empty         */
-#define USART_FLAG_RTOF                     USART_ISR_RTOF          /*!< USART receiver timeout flag                */
-#define USART_FLAG_TC                       USART_ISR_TC            /*!< USART transmission complete                */
-#define USART_FLAG_RXNE                     USART_ISR_RXNE          /*!< USART read data register not empty         */
-#define USART_FLAG_IDLE                     USART_ISR_IDLE          /*!< USART idle flag                            */
-#define USART_FLAG_ORE                      USART_ISR_ORE           /*!< USART overrun error                        */
-#define USART_FLAG_NE                       USART_ISR_NE            /*!< USART noise error                          */
-#define USART_FLAG_FE                       USART_ISR_FE            /*!< USART frame error                          */
-#define USART_FLAG_PE                       USART_ISR_PE            /*!< USART parity error                         */
-/**
-  * @}
-  */
-
-/** @defgroup USART_Interrupt_definition USART Interrupts Definition
-  *        Elements values convention: 0000ZZZZ0XXYYYYYb
-  *           - YYYYY  : Interrupt source position in the XX register (5bits)
-  *           - XX  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  *           - ZZZZ  : Flag position in the ISR register(4bits)
-  * @{
-  */
-
-#define USART_IT_PE                          0x0028U     /*!< USART parity error interruption                 */
-#define USART_IT_TXE                         0x0727U     /*!< USART transmit data register empty interruption */
-#define USART_IT_TC                          0x0626U     /*!< USART transmission complete interruption        */
-#define USART_IT_RXNE                        0x0525U     /*!< USART read data register not empty interruption */
-#define USART_IT_IDLE                        0x0424U     /*!< USART idle interruption                         */
-#define USART_IT_ERR                         0x0060U     /*!< USART error interruption                        */
-#define USART_IT_ORE                         0x0300U     /*!< USART overrun error interruption                */
-#define USART_IT_NE                          0x0200U     /*!< USART noise error interruption                  */
-#define USART_IT_FE                          0x0100U     /*!< USART frame error interruption                  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
-  * @{
-  */
-#define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag             */
-#define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag            */
-#define USART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise Error detected Clear Flag     */
-#define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag            */
-#define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag       */
-#define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag    */
-#define USART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< USART receiver timeout clear flag  */
-/**
-  * @}
-  */
-
-/** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask
-  * @{
-  */
-#define USART_IT_MASK                             0x001FU     /*!< USART interruptions flags mask */
-#define USART_CR_MASK                             0x00E0U     /*!< USART control register mask */
-#define USART_CR_POS                              5U          /*!< USART control register position */
-#define USART_ISR_MASK                            0x1F00U     /*!< USART ISR register mask         */
-#define USART_ISR_POS                             8U          /*!< USART ISR register position     */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup USART_Exported_Macros USART Exported Macros
-  * @{
-  */
-
-/** @brief Reset USART handle state.
-  * @param  __HANDLE__ USART handle.
-  * @retval None
-  */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  do{                                            \
-                                                        (__HANDLE__)->State = HAL_USART_STATE_RESET; \
-                                                        (__HANDLE__)->MspInitCallback = NULL;        \
-                                                        (__HANDLE__)->MspDeInitCallback = NULL;      \
-                                                      } while(0U)
-#else
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/** @brief  Flush the USART Data registers
-  * @param  __HANDLE__ specifies the USART Handle.
-  */
-#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__)                        \
-  do{                                                                   \
-    SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
-    SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
-  } while(0U)
-
-/** @brief  Check whether the specified USART flag is set or not.
-  * @param  __HANDLE__ specifies the USART Handle
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
-  *            @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
-  *            @arg @ref USART_FLAG_BUSY  Busy flag
-  *            @arg @ref USART_FLAG_TXE   Transmit data register empty flag
-  *            @arg @ref USART_FLAG_TC    Transmission Complete flag
-  *            @arg @ref USART_FLAG_RXNE  Receive data register not empty flag
-  *            @arg @ref USART_FLAG_RTOF  Receiver Timeout flag
-  *            @arg @ref USART_FLAG_IDLE  Idle Line detection flag
-  *            @arg @ref USART_FLAG_ORE   OverRun Error flag
-  *            @arg @ref USART_FLAG_NE    Noise Error flag
-  *            @arg @ref USART_FLAG_FE    Framing Error flag
-  *            @arg @ref USART_FLAG_PE    Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the specified USART pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag
-  *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag
-  *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag
-  *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag
-  *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag
-  *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag
-  *            @arg @ref USART_CLEAR_RTOF     Receiver Timeout clear flag
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief  Clear the USART PE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
-
-/** @brief  Clear the USART FE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
-
-/** @brief  Clear the USART NE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
-
-/** @brief  Clear the USART ORE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
-
-/** @brief  Clear the USART IDLE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
-
-
-
-/** @brief  Enable the specified USART interrupt.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @param  __INTERRUPT__ specifies the USART interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
-  *            @arg @ref USART_IT_TC    Transmission complete interrupt
-  *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
-  *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
-  *            @arg @ref USART_IT_PE    Parity Error interrupt
-  *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
-  (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
-   ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
-   ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
-   ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
-   ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
-
-/** @brief  Disable the specified USART interrupt.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @param  __INTERRUPT__ specifies the USART interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
-  *            @arg @ref USART_IT_TC    Transmission complete interrupt
-  *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
-  *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
-  *            @arg @ref USART_IT_PE    Parity Error interrupt
-  *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
-  (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
-   ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
-   ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
-   ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
-   ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
-
-/** @brief  Check whether the specified USART interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @param  __INTERRUPT__ specifies the USART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
-  *            @arg @ref USART_IT_TC    Transmission complete interrupt
-  *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
-  *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
-  *            @arg @ref USART_IT_ORE   OverRun Error interrupt
-  *            @arg @ref USART_IT_NE    Noise Error interrupt
-  *            @arg @ref USART_IT_FE    Framing Error interrupt
-  *            @arg @ref USART_IT_PE    Parity Error interrupt
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
-                                                         & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
-                                                                      USART_ISR_POS))) != 0U) ? SET : RESET)
-
-/** @brief  Check whether the specified USART interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @param  __INTERRUPT__ specifies the USART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
-  *            @arg @ref USART_IT_TC    Transmission complete interrupt
-  *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
-  *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
-  *            @arg @ref USART_IT_ORE   OverRun Error interrupt
-  *            @arg @ref USART_IT_NE    Noise Error interrupt
-  *            @arg @ref USART_IT_FE    Framing Error interrupt
-  *            @arg @ref USART_IT_PE    Parity Error interrupt
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
-                                                                 (__HANDLE__)->Instance->CR1 : \
-                                                                 (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
-                                                                  (__HANDLE__)->Instance->CR2 : \
-                                                                  (__HANDLE__)->Instance->CR3)) & (0x01U <<\
-                                                                      (((uint16_t)(__INTERRUPT__)) &\
-                                                                       USART_IT_MASK)))  != 0U) ? SET : RESET)
-
-/** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
-  *                       to clear the corresponding interrupt.
-  *          This parameter can be one of the following values:
-  *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag
-  *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag
-  *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag
-  *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag
-  *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag
-  *            @arg @ref USART_CLEAR_RTOF     Receiver timeout clear flag
-  *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-/** @brief  Set a specific USART request flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @param  __REQ__ specifies the request flag to set.
-  *          This parameter can be one of the following values:
-  *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
-  *            @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
-  *
-  * @retval None
-  */
-#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-
-/** @brief  Enable the USART one bit sample method.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @retval None
-  */
-#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief  Disable the USART one bit sample method.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @retval None
-  */
-#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
-
-/** @brief  Enable USART.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @retval None
-  */
-#define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief  Disable USART.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @retval None
-  */
-#define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup USART_Private_Macros   USART Private Macros
-  * @{
-  */
-
-/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
-  * @param  __PCLK__ USART clock.
-  * @param  __BAUD__ Baud rate set by the user.
-  * @retval Division result
-  */
-#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__)   ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
-
-/** @brief  Check USART Baud rate.
-  * @param  __BAUDRATE__ Baudrate specified by the user.
-  *         The maximum Baud Rate is derived from the maximum clock on L0 (i.e. 32 MHz)
-  *         divided by the smallest oversampling used on the USART (i.e. 8)
-  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)  */
-#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 4000000U)
-
-/**
-  * @brief Ensure that USART frame number of stop bits is valid.
-  * @param __STOPBITS__ USART frame number of stop bits.
-  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
-  */
-#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
-                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \
-                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
-                                         ((__STOPBITS__) == USART_STOPBITS_2))
-
-/**
-  * @brief Ensure that USART frame parity is valid.
-  * @param __PARITY__ USART frame parity.
-  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
-  */
-#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
-                                     ((__PARITY__) == USART_PARITY_EVEN) || \
-                                     ((__PARITY__) == USART_PARITY_ODD))
-
-/**
-  * @brief Ensure that USART communication mode is valid.
-  * @param __MODE__ USART communication mode.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
-
-/**
-  * @brief Ensure that USART clock state is valid.
-  * @param __CLOCK__ USART clock state.
-  * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
-  */
-#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
-                                   ((__CLOCK__) == USART_CLOCK_ENABLE))
-
-/**
-  * @brief Ensure that USART frame polarity is valid.
-  * @param __CPOL__ USART frame polarity.
-  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
-  */
-#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
-
-/**
-  * @brief Ensure that USART frame phase is valid.
-  * @param __CPHA__ USART frame phase.
-  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
-  */
-#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
-
-/**
-  * @brief Ensure that USART frame last bit clock pulse setting is valid.
-  * @param __LASTBIT__ USART frame last bit clock pulse setting.
-  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
-  */
-#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
-                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))
-
-/**
-  * @brief Ensure that USART request parameter is valid.
-  * @param __PARAM__ USART request parameter.
-  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
-  */
-#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
-                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
-
-/**
-  * @}
-  */
-
-/* Include USART HAL Extended module */
-#include "stm32l0xx_hal_usart_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_Exported_Functions USART Exported Functions
-  * @{
-  */
-
-/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
-                                             pUSART_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
-                                            uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
-                                               uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
-                                                uint16_t Size);
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
-
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
-void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
-void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
-  * @{
-  */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart_ex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart_ex.h
deleted file mode 100644
index 3a1e189f73..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart_ex.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_usart_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of USART HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_USART_EX_H
-#define STM32L0xx_HAL_USART_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup USARTEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
-  * @{
-  */
-
-/** @defgroup USARTEx_Word_Length USARTEx Word Length
-  * @{
-  */
-#define USART_WORDLENGTH_7B                  (USART_CR1_M1)   /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B                  (0x00000000U)              /*!< 8-bit long USART frame */
-#define USART_WORDLENGTH_9B                  (USART_CR1_M0)   /*!< 9-bit long USART frame */
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
-  * @{
-  */
-
-/** @brief  Report the USART clock source.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @param  __CLOCKSOURCE__ output variable.
-  * @retval the USART clocking source, written in __CLOCKSOURCE__.
-  */
-#if defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx)
-
-#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
-  do {                                                         \
-    if((__HANDLE__)->Instance == USART1)                       \
-    {                                                          \
-      switch(__HAL_RCC_GET_USART1_SOURCE())                    \
-      {                                                        \
-        case RCC_USART1CLKSOURCE_PCLK2:                        \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
-          break;                                               \
-        default:                                               \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                               \
-      }                                                        \
-    }                                                          \
-    else if((__HANDLE__)->Instance == USART2)                  \
-    {                                                          \
-      switch(__HAL_RCC_GET_USART2_SOURCE())                    \
-      {                                                        \
-        case RCC_USART2CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
-          break;                                               \
-        default:                                               \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                               \
-      }                                                        \
-    }                                                          \
-    else                                                       \
-    {                                                          \
-      (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
-    }                                                          \
-  } while(0U)
-
-#elif defined(STM32L071xx) || defined (STM32L081xx) || defined(STM32L072xx) || defined (STM32L082xx) || defined(STM32L073xx) || defined (STM32L083xx)
-
-#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
-  do {                                                         \
-    if((__HANDLE__)->Instance == USART1)                       \
-    {                                                          \
-      switch(__HAL_RCC_GET_USART1_SOURCE())                    \
-      {                                                        \
-        case RCC_USART1CLKSOURCE_PCLK2:                        \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
-          break;                                               \
-        default:                                               \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                               \
-      }                                                        \
-    }                                                          \
-    else if((__HANDLE__)->Instance == USART2)                  \
-    {                                                          \
-      switch(__HAL_RCC_GET_USART2_SOURCE())                    \
-      {                                                        \
-        case RCC_USART2CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
-          break;                                               \
-        default:                                               \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                               \
-      }                                                        \
-    }                                                          \
-    else if((__HANDLE__)->Instance == USART4)                  \
-    {                                                          \
-      (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;             \
-    }                                                          \
-    else if((__HANDLE__)->Instance == USART5)                  \
-    {                                                          \
-      (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;             \
-    }                                                          \
-    else                                                       \
-    {                                                          \
-      (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
-    }                                                          \
-  } while(0U)
-
-#else
-
-#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
-  do {                                                         \
-    if((__HANDLE__)->Instance == USART2)                       \
-    {                                                          \
-      switch(__HAL_RCC_GET_USART2_SOURCE())                    \
-      {                                                        \
-        case RCC_USART2CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
-          break;                                               \
-        default:                                               \
-          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                               \
-      }                                                        \
-    }                                                          \
-    else                                                       \
-    {                                                          \
-      (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
-    }                                                          \
-  } while(0U)
-
-#endif /* STM32L051xx || STM32L052xx || STM32L053xx || STM32L062xx || STM32L063xx */
-
-/** @brief  Compute the USART mask to apply to retrieve the received data
-  *         according to the word length and to the parity bits activation.
-  * @note   If PCE = 1, the parity bit is not included in the data extracted
-  *         by the reception API().
-  *         This masking operation is not carried out in the case of
-  *         DMA transfers.
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
-  */
-#define USART_MASK_COMPUTATION(__HANDLE__)                            \
-  do {                                                                \
-    if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)         \
-    {                                                                 \
-      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x01FFU;                                 \
-      }                                                               \
-      else                                                            \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x00FFU;                                 \
-      }                                                               \
-    }                                                                 \
-    else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)    \
-    {                                                                 \
-      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x00FFU;                                 \
-      }                                                               \
-      else                                                            \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x007FU;                                 \
-      }                                                               \
-    }                                                                 \
-    else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)    \
-    {                                                                 \
-      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x007FU;                                 \
-      }                                                               \
-      else                                                            \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x003FU;                                 \
-      }                                                               \
-    }                                                                 \
-    else                                                              \
-    {                                                                 \
-      (__HANDLE__)->Mask = 0x0000U;                                   \
-    }                                                                 \
-  } while(0U)
-
-/**
-  * @brief Ensure that USART frame length is valid.
-  * @param __LENGTH__ USART frame length.
-  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
-  */
-#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
-                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \
-                                          ((__LENGTH__) == USART_WORDLENGTH_9B))
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USARTEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup USARTEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-
-/**
-  * @}
-  */
-
-/** @addtogroup USARTEx_Exported_Functions_Group2
-  * @{
-  */
-
-/* Peripheral Control functions ***********************************************/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_USART_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_wwdg.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_wwdg.h
deleted file mode 100644
index 9483aafe8a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_wwdg.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_wwdg.h
-  * @author  MCD Application Team
-  * @brief   Header file of WWDG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_HAL_WWDG_H
-#define STM32L0xx_HAL_WWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup WWDG
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Types WWDG Exported Types
-  * @{
-  */
-
-/**
-  * @brief  WWDG Init structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
-                               This parameter can be a value of @ref WWDG_Prescaler */
-
-  uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
-                               This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
-
-  uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
-                               This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
-
-  uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
-                               This parameter can be a value of @ref WWDG_EWI_Mode */
-
-} WWDG_InitTypeDef;
-
-/**
-  * @brief  WWDG handle Structure definition
-  */
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-typedef struct __WWDG_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-{
-  WWDG_TypeDef      *Instance;  /*!< Register base address */
-
-  WWDG_InitTypeDef  Init;       /*!< WWDG required parameters */
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-  void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg);                  /*!< WWDG Early WakeUp Interrupt callback */
-
-  void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg);              /*!< WWDG Msp Init callback */
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-} WWDG_HandleTypeDef;
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL WWDG common Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_WWDG_EWI_CB_ID          = 0x00U,    /*!< WWDG EWI callback ID */
-  HAL_WWDG_MSPINIT_CB_ID      = 0x01U,    /*!< WWDG MspInit callback ID */
-} HAL_WWDG_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL WWDG Callback pointer definition
-  */
-typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer to a WWDG common callback functions */
-
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
-  * @{
-  */
-#define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Flag_definition WWDG Flag definition
-  * @brief WWDG Flag definition
-  * @{
-  */
-#define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Prescaler WWDG Prescaler
-  * @{
-  */
-#define WWDG_PRESCALER_1                    0x00000000u                              /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0                         /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1                         /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8                    (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/8 */
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
-  * @{
-  */
-#define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
-#define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Macros WWDG Private Macros
-  * @{
-  */
-#define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1)  || \
-                                             ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
-                                             ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
-                                             ((__PRESCALER__) == WWDG_PRESCALER_8))
-
-#define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
-
-#define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
-
-#define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
-                                             ((__MODE__) == WWDG_EWI_DISABLE))
-/**
-  * @}
-  */
-
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Enable the WWDG peripheral.
-  * @param  __HANDLE__  WWDG handle
-  * @retval None
-  */
-#define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
-
-/**
-  * @brief  Enable the WWDG early wakeup interrupt.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__  specifies the interrupt to enable.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early wakeup interrupt
-  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
-  * @retval None
-  */
-#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the selected WWDG interrupt has occurred or not.
-  * @param  __HANDLE__  WWDG handle
-  * @param  __INTERRUPT__  specifies the it to check.
-  *        This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
-  * @retval The new state of WWDG_FLAG (SET or RESET).
-  */
-#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
-
-/** @brief  Clear the WWDG interrupt pending bits.
-  *         bits to clear the selected interrupt pending bits.
-  * @param  __HANDLE__  WWDG handle
-  * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
-  */
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified WWDG flag is set or not.
-  * @param  __HANDLE__  WWDG handle
-  * @param  __FLAG__  specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
-  * @retval The new state of WWDG_FLAG (SET or RESET).
-  */
-#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clear the WWDG's pending flags.
-  * @param  __HANDLE__  WWDG handle
-  * @param  __FLAG__  specifies the flag to clear.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
-  * @retval None
-  */
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Check whether the specified WWDG interrupt source is enabled or not.
-  * @param  __HANDLE__  WWDG Handle.
-  * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
-  * @retval state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
-                                                              & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup WWDG_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup WWDG_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
-void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef     HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
-                                                pWWDG_CallbackTypeDef pCallback);
-HAL_StatusTypeDef     HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup WWDG_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
-void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_HAL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h
deleted file mode 100644
index 4b37ebdd1a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h
+++ /dev/null
@@ -1,4074 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_adc.h
-  * @author  MCD Application Team
-  * @brief   Header file of ADC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_ADC_H
-#define __STM32L0xx_LL_ADC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (ADC1)
-
-/** @defgroup ADC_LL ADC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Constants ADC Private Constants
-  * @{
-  */
-
-/* Internal mask for ADC group regular trigger:                               */
-/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
-/* - regular trigger source                                                   */
-/* - regular trigger edge                                                     */
-#define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
-
-/* Mask containing trigger source masks for each of possible                  */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
-#define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0U)) | \
-                                             ((ADC_CFGR1_EXTSEL)                            << (4U * 1U)) | \
-                                             ((ADC_CFGR1_EXTSEL)                            << (4U * 2U)) | \
-                                             ((ADC_CFGR1_EXTSEL)                            << (4U * 3U))  )
-
-/* Mask containing trigger edge masks for each of possible                    */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
-#define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0U)) | \
-                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1U)) | \
-                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2U)) | \
-                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3U))  )
-
-/* Definition of ADC group regular trigger bits information.                  */
-#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */
-#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */
-
-
-
-/* Internal mask for ADC channel:                                             */
-/* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
-/* - channel identifier defined by number                                     */
-/* - channel identifier defined by bitfield                                   */
-/* - channel differentiation between external channels (connected to          */
-/*   GPIO pins) and internal channels (connected to internal paths)           */
-#define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR1_AWDCH)
-#define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_CHSELR_CHSEL)
-#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
-#define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
-/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
-#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
-
-/* Channel differentiation between external and internal channels */
-#define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000U) /* Marker of internal channel */
-#define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH)
-
-/* Definition of channels ID number information to be inserted into           */
-/* channels literals definition.                                              */
-#define ADC_CHANNEL_0_NUMBER               (0x00000000U)
-#define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR1_AWDCH_1                    )
-#define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR1_AWDCH_2                                        )
-#define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR1_AWDCH_2                     | ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1                    )
-#define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR1_AWDCH_3                                                            )
-#define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR1_AWDCH_3                                         | ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR1_AWDCH_3                     | ADC_CFGR1_AWDCH_1                    )
-#define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR1_AWDCH_3                     | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2                                        )
-#define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2                     | ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1                    )
-#define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_16_NUMBER              (ADC_CFGR1_AWDCH_4                                                                                )
-#define ADC_CHANNEL_17_NUMBER              (ADC_CFGR1_AWDCH_4                                                             | ADC_CFGR1_AWDCH_0)
-#define ADC_CHANNEL_18_NUMBER              (ADC_CFGR1_AWDCH_4                                         | ADC_CFGR1_AWDCH_1                    )
-
-/* Definition of channels ID bitfield information to be inserted into         */
-/* channels literals definition.                                              */
-#define ADC_CHANNEL_0_BITFIELD             (ADC_CHSELR_CHSEL0)
-#define ADC_CHANNEL_1_BITFIELD             (ADC_CHSELR_CHSEL1)
-#define ADC_CHANNEL_2_BITFIELD             (ADC_CHSELR_CHSEL2)
-#define ADC_CHANNEL_3_BITFIELD             (ADC_CHSELR_CHSEL3)
-#define ADC_CHANNEL_4_BITFIELD             (ADC_CHSELR_CHSEL4)
-#define ADC_CHANNEL_5_BITFIELD             (ADC_CHSELR_CHSEL5)
-#define ADC_CHANNEL_6_BITFIELD             (ADC_CHSELR_CHSEL6)
-#define ADC_CHANNEL_7_BITFIELD             (ADC_CHSELR_CHSEL7)
-#define ADC_CHANNEL_8_BITFIELD             (ADC_CHSELR_CHSEL8)
-#define ADC_CHANNEL_9_BITFIELD             (ADC_CHSELR_CHSEL9)
-#define ADC_CHANNEL_10_BITFIELD            (ADC_CHSELR_CHSEL10)
-#define ADC_CHANNEL_11_BITFIELD            (ADC_CHSELR_CHSEL11)
-#define ADC_CHANNEL_12_BITFIELD            (ADC_CHSELR_CHSEL12)
-#define ADC_CHANNEL_13_BITFIELD            (ADC_CHSELR_CHSEL13)
-#define ADC_CHANNEL_14_BITFIELD            (ADC_CHSELR_CHSEL14)
-#define ADC_CHANNEL_15_BITFIELD            (ADC_CHSELR_CHSEL15)
-#if  defined(ADC_CCR_VLCDEN)
-#define ADC_CHANNEL_16_BITFIELD            (ADC_CHSELR_CHSEL16)
-#endif
-#define ADC_CHANNEL_17_BITFIELD            (ADC_CHSELR_CHSEL17)
-#define ADC_CHANNEL_18_BITFIELD            (ADC_CHSELR_CHSEL18)
-
-/* Internal mask for ADC analog watchdog:                                     */
-/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
-/* (concatenation of multiple bits used in different analog watchdogs,        */
-/* (feature of several watchdogs not available on all STM32 families)).       */
-/* - analog watchdog 1: monitored channel defined by number,                  */
-/*   selection of ADC group (ADC group regular).                              */
-
-/* Internal register offset for ADC analog watchdog channel configuration */
-#define ADC_AWD_CR1_REGOFFSET              (0x00000000U)
-
-#define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET)
-
-#define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)
-#define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK)
-
-/* Internal register offset for ADC analog watchdog threshold configuration */
-#define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
-#define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET)
-
-
-/* ADC registers bits positions */
-#define ADC_CFGR1_RES_BITOFFSET_POS        (3U)  /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */
-#define ADC_CFGR1_AWDSGL_BITOFFSET_POS     (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */
-#define ADC_TR_HT_BITOFFSET_POS            (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
-#define ADC_CHSELR_CHSEL0_BITOFFSET_POS    (0U)  /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */
-#define ADC_CHSELR_CHSEL1_BITOFFSET_POS    (1U)  /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */
-#define ADC_CHSELR_CHSEL2_BITOFFSET_POS    (2U)  /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */
-#define ADC_CHSELR_CHSEL3_BITOFFSET_POS    (3U)  /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */
-#define ADC_CHSELR_CHSEL4_BITOFFSET_POS    (4U)  /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */
-#define ADC_CHSELR_CHSEL5_BITOFFSET_POS    (5U)  /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */
-#define ADC_CHSELR_CHSEL6_BITOFFSET_POS    (6U)  /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */
-#define ADC_CHSELR_CHSEL7_BITOFFSET_POS    (7U)  /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */
-#define ADC_CHSELR_CHSEL8_BITOFFSET_POS    (8U)  /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */
-#define ADC_CHSELR_CHSEL9_BITOFFSET_POS    (9U)  /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */
-#define ADC_CHSELR_CHSEL10_BITOFFSET_POS   (10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */
-#define ADC_CHSELR_CHSEL11_BITOFFSET_POS   (11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */
-#define ADC_CHSELR_CHSEL12_BITOFFSET_POS   (12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */
-#define ADC_CHSELR_CHSEL13_BITOFFSET_POS   (13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */
-#define ADC_CHSELR_CHSEL14_BITOFFSET_POS   (14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */
-#define ADC_CHSELR_CHSEL15_BITOFFSET_POS   (15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */
-#if  defined(ADC_CCR_VLCDEN)
-#define ADC_CHSELR_CHSEL16_BITOFFSET_POS   (16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */
-#endif
-#define ADC_CHSELR_CHSEL17_BITOFFSET_POS   (17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */
-#define ADC_CHSELR_CHSEL18_BITOFFSET_POS   (18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */
-
-
-/* ADC registers bits groups */
-#define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
-
-
-/* ADC internal channels related definitions */
-/* Internal voltage reference VrefInt */
-#define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FF80078U)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define VREFINT_CAL_VREF                   (3000U)                     /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
-/* Temperature sensor */
-/* Note: On device STM32L011, calibration parameter TS_CAL1 is not available. */
-#if !defined(STM32L011xx)
-#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FF8007AU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L0, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#endif
-#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FF8007EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L0, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#if !defined(STM32L011xx)
-#define TEMPSENSOR_CAL1_TEMP               (30U)                       /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#endif
-#define TEMPSENSOR_CAL2_TEMP               (130U)                      /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL_VREFANALOG          (3000U)                     /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
-
-
-/**
-  * @}
-  */
-
-
-#if  defined(USE_FULL_LL_DRIVER)
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Macros ADC Private Macros
-  * @{
-  */
-
-
-/**
-  * @}
-  */
-
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  Structure definition of some features of ADC common parameters
-  *         and multimode
-  *         (all ADC instances belonging to the same ADC common instance).
-  * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
-  *         is conditioned to ADC instances state (all ADC instances
-  *         sharing the same ADC common instance):
-  *         All ADC instances sharing the same ADC common instance must be
-  *         disabled.
-  */
-typedef struct
-{
-  uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
-                                             This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
-
-} LL_ADC_CommonInitTypeDef;
-
-/**
-  * @brief  Structure definition of some features of ADC instance.
-  * @note   These parameters have an impact on ADC scope: ADC instance.
-  *         Refer to corresponding unitary functions into
-  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
-  * @note   The setting of these parameters by function @ref LL_ADC_Init()
-  *         is conditioned to ADC state:
-  *         ADC instance must be disabled.
-  *         This condition is applied to all ADC features, for efficiency
-  *         and compatibility over all STM32 families. However, the different
-  *         features can be set under different ADC state conditions
-  *         (setting possible with ADC enabled without conversion on going,
-  *         ADC enabled with conversion on going, ...)
-  *         Each feature can be updated afterwards with a unitary function
-  *         and potentially with ADC in a different state than disabled,
-  *         refer to description of each function for setting
-  *         conditioned to ADC state.
-  */
-typedef struct
-{
-  uint32_t Clock;                       /*!< Set ADC instance clock source and prescaler.
-                                             This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
-                                             @note On this STM32 serie, this parameter has some clock ratio constraints:
-                                                   ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
-                                                   (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
-                                             
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
-                                             For more details, refer to description of this function. */
-
-  uint32_t Resolution;                  /*!< Set ADC resolution.
-                                             This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
-
-  uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
-                                             This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
-
-  uint32_t LowPowerMode;                /*!< Set ADC low power mode.
-                                             This parameter can be a value of @ref ADC_LL_EC_LP_MODE
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
-
-} LL_ADC_InitTypeDef;
-
-/**
-  * @brief  Structure definition of some features of ADC group regular.
-  * @note   These parameters have an impact on ADC scope: ADC group regular.
-  *         Refer to corresponding unitary functions into
-  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
-  *         (functions with prefix "REG").
-  * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
-  *         is conditioned to ADC state:
-  *         ADC instance must be disabled.
-  *         This condition is applied to all ADC features, for efficiency
-  *         and compatibility over all STM32 families. However, the different
-  *         features can be set under different ADC state conditions
-  *         (setting possible with ADC enabled without conversion on going,
-  *         ADC enabled with conversion on going, ...)
-  *         Each feature can be updated afterwards with a unitary function
-  *         and potentially with ADC in a different state than disabled,
-  *         refer to description of each function for setting
-  *         conditioned to ADC state.
-  */
-typedef struct
-{
-  uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
-                                             This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
-                                             @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
-                                                   (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
-                                                   In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
-
-  uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
-                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
-                                             @note This parameter has an effect only if group regular sequencer is enabled
-                                                   (several ADC channels enabled in group regular sequencer).
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
-
-  uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
-                                             This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
-                                             Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
-
-  uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
-                                             This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
-
-  uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
-                                             data preserved or overwritten.
-                                             This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
-
-} LL_ADC_REG_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
-  * @{
-  */
-
-/** @defgroup ADC_LL_EC_FLAG ADC flags
-  * @brief    Flags defines which can be used with LL_ADC_ReadReg function
-  * @{
-  */
-#define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
-#define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */
-#define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */
-#define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
-#define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
-#define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD        /*!< ADC flag ADC analog watchdog 1 */
-#define LL_ADC_FLAG_EOCAL                  ADC_ISR_EOCAL      /*!< ADC flag end of calibration */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
-  * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
-  * @{
-  */
-#define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
-#define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */
-#define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */
-#define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
-#define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */
-#define LL_ADC_IT_AWD1                     ADC_IER_AWDIE      /*!< ADC interruption ADC analog watchdog 1 */
-#define LL_ADC_IT_EOCAL                    ADC_IER_EOCALIE    /*!< ADC interruption ADC end of calibration */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
-  * @{
-  */
-/* List of ADC registers intended to be used (most commonly) with             */
-/* DMA transfer.                                                              */
-/* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
-#define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
-  * @{
-  */
-#define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000U)                               /*!< ADC asynchronous clock without prescaler */
-#define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE  ADC common - Clock frequency mode
-  * @{
-  */
-#define LL_ADC_CLOCK_FREQ_MODE_HIGH        (0x00000000U)/*!< ADC clock mode to high frequency. On STM32L0, ADC clock frequency above 2.8MHz.  */
-#define LL_ADC_CLOCK_FREQ_MODE_LOW         (ADC_CCR_LFMEN)        /*!< ADC clock mode to low frequency. On STM32L0, ADC clock frequency below 2.8MHz.  */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
-  * @{
-  */
-/* Note: Other measurement paths to internal channels may be available        */
-/*       (connections to other peripherals).                                  */
-/*       If they are not listed below, they do not require any specific       */
-/*       path enable. In this case, Access to measurement path is done        */
-/*       only by selecting the corresponding ADC internal channel.            */
-#define LL_ADC_PATH_INTERNAL_NONE          (0x00000000U)/*!< ADC measurement pathes all disabled */
-#define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */
-#if defined(ADC_CCR_TSEN)
-#define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */
-#endif
-#if defined(ADC_CCR_VLCDEN)
-#define LL_ADC_PATH_INTERNAL_VLCD          (ADC_CCR_VLCDEN)       /*!< ADC measurement path to internal channel Vlcd */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_CLOCK_SOURCE  ADC instance - Clock source
-  * @{
-  */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CFGR2_CKMODE_1)                                  /*!< ADC synchronous clock derived from AHB clock divided by 4 */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CFGR2_CKMODE_0)                                  /*!< ADC synchronous clock derived from AHB clock divided by 2 */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0)             /*!< ADC synchronous clock derived from AHB clock not divided  */
-#define LL_ADC_CLOCK_ASYNC                 (0x00000000U)                               /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
-  * @{
-  */
-#define LL_ADC_RESOLUTION_12B              (0x00000000U)             /*!< ADC resolution 12 bits */
-#define LL_ADC_RESOLUTION_10B              (                  ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
-#define LL_ADC_RESOLUTION_8B               (ADC_CFGR1_RES_1                  ) /*!< ADC resolution  8 bits */
-#define LL_ADC_RESOLUTION_6B               (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution  6 bits */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
-  * @{
-  */
-#define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR1_ALIGN)      /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
-  * @{
-  */
-#define LL_ADC_LP_MODE_NONE                (0x00000000U)             /*!< No ADC low power mode activated */
-#define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR1_WAIT)                    /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
-#define LL_ADC_LP_AUTOPOWEROFF             (ADC_CFGR1_AUTOFF)                  /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */
-#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF    (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
-  * @{
-  */
-#define LL_ADC_GROUP_REGULAR               (0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
-  * @{
-  */
-#define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
-#define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
-#define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
-#define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
-#define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
-#define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
-#define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
-#define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
-#define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
-#define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
-#define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
-#define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
-#define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
-#define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
-#define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
-#define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
-#define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
-#define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
-#define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
-#define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Temperature sensor. */
-#if defined(ADC_CCR_VLCDEN)
-#define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
-#define LL_ADC_CHANNEL_VLCD                (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Vlcd: Vlcd voltage through a divider ladder of factor 1/4, 1/3 or 1/2 (set by LCD voltage generator biasing),  to have Vlcd always below Vdda. */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
-  * @{
-  */
-#define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000U)                                                                        /*!< ADC group regular conversion trigger internal: SW start. */
-#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM21_CH2      (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM21 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH4       (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM22_TRGO     (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM22 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
-
-/* ADC group regular external trigger TIM2_CC3 available only on              */
-/* STM32L0 devices categories: Cat.1, Cat.2, Cat.5                            */
-#if defined (STM32L011xx) || defined (STM32L021xx) || \
-    defined (STM32L031xx) || defined (STM32L041xx) || \
-    defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
-    defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) || \
-    defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xB)
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#endif
-
-/* ADC group regular external trigger TIM21_TRGO available only on            */
-/* STM32L0 devices categories: Cat.2, Cat.3, Cat.5                            */
-#if defined (STM32L031xx) || defined (STM32L041xx) || \
-    defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || \
-    defined (STM32L062xx) || defined (STM32L063xx) || \
-    defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
-    defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) || \
-    defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xB)
-#define LL_ADC_REG_TRIG_EXT_TIM21_TRGO     (LL_ADC_REG_TRIG_EXT_TIM22_TRGO)
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
-  * @{
-  */
-#define LL_ADC_REG_TRIG_EXT_RISING         (                    ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
-#define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR1_EXTEN_1                    ) /*!< ADC group regular conversion trigger polarity set to falling edge */
-#define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
-* @{
-*/
-#define LL_ADC_REG_CONV_SINGLE             (0x00000000U)           /*!< ADC conversions are performed in single mode: one conversion per trigger */
-#define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR1_CONT)        /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
-  * @{
-  */
-#define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000U)                        /*!< ADC conversions are not transferred by DMA */
-#define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                   ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
-#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
-* @{
-*/
-#define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000U)          /*!< ADC group regular behavior in case of overrun: data preserved */
-#define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR1_OVRMOD)     /*!< ADC group regular behavior in case of overrun: data overwritten */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION  ADC group regular - Sequencer scan direction
-  * @{
-  */
-#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD    (0x00000000U)          /*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
-#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD   (ADC_CFGR1_SCANDIR)    /*!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
-  * @{
-  */
-#define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000U)                                                          /*!< ADC group regular sequencer discontinuous mode disable */
-#define LL_ADC_REG_SEQ_DISCONT_1RANK       (ADC_CFGR1_DISCEN)                                                               /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
-  * @{
-  */
-#define LL_ADC_SAMPLINGTIME_1CYCLE_5       (0x00000000U)                                         /*!< Sampling time 1.5 ADC clock cycle */
-#define LL_ADC_SAMPLINGTIME_3CYCLES_5      (ADC_SMPR_SMP_0)                                      /*!< Sampling time 3.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_7CYCLES_5      (ADC_SMPR_SMP_1)                                      /*!< Sampling time 7.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_12CYCLES_5     (ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)                     /*!< Sampling time 12.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_19CYCLES_5     (ADC_SMPR_SMP_2)                                      /*!< Sampling time 19.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_39CYCLES_5     (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)                     /*!< Sampling time 39.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_79CYCLES_5     (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)                     /*!< Sampling time 79.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_160CYCLES_5    (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)    /*!< Sampling time 160.5 ADC clock cycles */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
-  * @{
-  */
-#define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
-  * @{
-  */
-#define LL_ADC_AWD_DISABLE                 (0x00000000U)                                                                              /*!< ADC analog watchdog monitoring disabled */
-#define LL_ADC_AWD_ALL_CHANNELS_REG        (                                                    ADC_CFGR1_AWDEN                   )   /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
-#define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
-#define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
-#if defined(ADC_CCR_VLCDEN)
-#define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
-#define LL_ADC_AWD_CH_VLCD_REG             ((LL_ADC_CHANNEL_VLCD       & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
-  * @{
-  */
-#define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR_HT            )     /*!< ADC analog watchdog threshold high */
-#define LL_ADC_AWD_THRESHOLD_LOW           (            ADC_TR_LT)     /*!< ADC analog watchdog threshold low */
-#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR_HT | ADC_TR_LT)     /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
-  * @{
-  */
-#define LL_ADC_OVS_DISABLE                 (0x00000000U)                               /*!< ADC oversampling disabled. */
-#define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                          ADC_CFGR2_OVSE)  /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
-  * @{
-  */
-#define LL_ADC_OVS_REG_CONT                (0x00000000U)          /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
-#define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TOVS)       /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
-  * @{
-  */
-#define LL_ADC_OVS_RATIO_2                 (0x00000000U)                                            /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_4                 (                                      ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_8                 (                   ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_16                (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2                                      ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2                    | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift
-  * @{
-  */
-#define LL_ADC_OVS_SHIFT_NONE              (0x00000000U)                                                     /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
-  * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,
-  *         not timeout values.
-  *         For details on delays values, refer to descriptions in source code
-  *         above each literal definition.
-  * @{
-  */
-  
-/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
-/*       not timeout values.                                                  */
-/*       Timeout values for ADC operations are dependent to device clock      */
-/*       configuration (system clock versus ADC clock),                       */
-/*       and therefore must be defined in user application.                   */
-/*       Indications for estimation of ADC timeout delays, for this           */
-/*       STM32 serie:                                                         */
-/*       - ADC calibration time: maximum delay is 83/fADC.                    */
-/*         (refer to device datasheet, parameter "tCAL")                      */
-/*       - ADC enable time: maximum delay is 1 conversion cycle.              */
-/*         (refer to device datasheet, parameter "tSTAB")                     */
-/*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
-/*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
-/*         cycles                                                             */
-/*       - ADC conversion time: duration depending on ADC clock and ADC       */
-/*         configuration.                                                     */
-/*         (refer to device reference manual, section "Timing")               */
-
-/* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
-/* Delay set to maximum value (refer to device datasheet,                     */
-/* parameter "tUP_LDO").                                                      */
-#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US (10U)              /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
-
-/* Delay for internal voltage reference stabilization time.                   */
-/* Delay set to maximum value (refer to device datasheet,                     */
-/* parameter "TADC_BUF").                                                     */
-/* Unit: us                                                                   */
-#define LL_ADC_DELAY_VREFINT_STAB_US       (10U)              /*!< Delay for internal voltage reference stabilization time */
-
-/* Delay for temperature sensor stabilization time.                           */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "tSTART").                                                       */
-/* Unit: us                                                                   */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US    (10U)              /*!< Delay for temperature sensor stabilization time */
-
-/* Delay required between ADC end of calibration and ADC enable.              */
-/* Note: On this STM32 serie, a minimum number of ADC clock cycles            */
-/*       are required between ADC end of calibration and ADC enable.          */
-/*       Wait time can be computed in user application by waiting for the     */
-/*       equivalent number of CPU cycles, by taking into account              */
-/*       ratio of CPU clock versus ADC clock prescalers.                      */
-/* Unit: ADC clock cycles.                                                    */
-#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES (2U)             /*!< Delay required between ADC end of calibration and ADC enable */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
-  * @{
-  */
-
-/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in ADC register
-  * @param  __INSTANCE__ ADC Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in ADC register
-  * @param  __INSTANCE__ ADC Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to get ADC channel number in decimal format
-  *         from literals LL_ADC_CHANNEL_x.
-  * @note   Example:
-  *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
-  *           will return decimal number "4".
-  * @note   The input can be a value from functions where a channel
-  *         number is returned, either defined with number
-  *         or with bitfield (only one bit must be set).
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0
-  *         @arg @ref LL_ADC_CHANNEL_1
-  *         @arg @ref LL_ADC_CHANNEL_2
-  *         @arg @ref LL_ADC_CHANNEL_3
-  *         @arg @ref LL_ADC_CHANNEL_4
-  *         @arg @ref LL_ADC_CHANNEL_5
-  *         @arg @ref LL_ADC_CHANNEL_6
-  *         @arg @ref LL_ADC_CHANNEL_7
-  *         @arg @ref LL_ADC_CHANNEL_8
-  *         @arg @ref LL_ADC_CHANNEL_9
-  *         @arg @ref LL_ADC_CHANNEL_10
-  *         @arg @ref LL_ADC_CHANNEL_11
-  *         @arg @ref LL_ADC_CHANNEL_12
-  *         @arg @ref LL_ADC_CHANNEL_13
-  *         @arg @ref LL_ADC_CHANNEL_14
-  *         @arg @ref LL_ADC_CHANNEL_15
-  *         @arg @ref LL_ADC_CHANNEL_16         (1)
-  *         @arg @ref LL_ADC_CHANNEL_17
-  *         @arg @ref LL_ADC_CHANNEL_18
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
-  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
-  *         
-  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
-  * @retval Value between Min_Data=0 and Max_Data=18
-  */
-#if defined(ADC_CCR_VLCDEN)
-#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                                               \
-  ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U)                                                         \
-    ? (                                                                                                           \
-       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS                        \
-      )                                                                                                           \
-      :                                                                                                           \
-      (                                                                                                           \
-       (((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) :                                        \
-        (                                                                                                         \
-         (((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) :                                      \
-          (                                                                                                       \
-           (((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) :                                    \
-            (                                                                                                     \
-             (((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) :                                  \
-              (                                                                                                   \
-               (((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) :                                \
-                (                                                                                                 \
-                 (((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) :                              \
-                  (                                                                                               \
-                   (((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) :                            \
-                    (                                                                                             \
-                     (((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) :                          \
-                      (                                                                                           \
-                       (((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) :                        \
-                        (                                                                                         \
-                         (((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) :                      \
-                          (                                                                                       \
-                           (((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) :                 \
-                            (                                                                                     \
-                             (((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) :               \
-                              (                                                                                   \
-                               (((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) :             \
-                                (                                                                                 \
-                                 (((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13U) :           \
-                                  (                                                                               \
-                                   (((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? (14U) :         \
-                                    (                                                                             \
-                                     (((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? (15U) :       \
-                                      (                                                                           \
-                                       (((__CHANNEL__) & ADC_CHSELR_CHSEL16) == ADC_CHSELR_CHSEL16) ? (16U) :     \
-                                        (                                                                         \
-                                         (((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL17) ? (17U) :   \
-                                          (                                                                       \
-                                           (((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSEL18) ? (18U) : \
-                                            (0U)                                                                   \
-                                          )                                                                       \
-                                        )                                                                         \
-                                      )                                                                           \
-                                    )                                                                             \
-                                  )                                                                               \
-                                )                                                                                 \
-                              )                                                                                   \
-                            )                                                                                     \
-                          )                                                                                       \
-                        )                                                                                         \
-                      )                                                                                           \
-                    )                                                                                             \
-                  )                                                                                               \
-                )                                                                                                 \
-              )                                                                                                   \
-            )                                                                                                     \
-          )                                                                                                       \
-        )                                                                                                         \
-      )                                                                                                           \
-  )
-#else
-#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                                               \
-  ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U)                                                         \
-    ? (                                                                                                           \
-       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS                        \
-      )                                                                                                           \
-      :                                                                                                           \
-      (                                                                                                           \
-       (((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) :                                        \
-        (                                                                                                         \
-         (((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) :                                      \
-          (                                                                                                       \
-           (((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) :                                    \
-            (                                                                                                     \
-             (((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) :                                  \
-              (                                                                                                   \
-               (((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) :                                \
-                (                                                                                                 \
-                 (((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) :                              \
-                  (                                                                                               \
-                   (((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) :                            \
-                    (                                                                                             \
-                     (((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) :                          \
-                      (                                                                                           \
-                       (((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) :                        \
-                        (                                                                                         \
-                         (((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) :                      \
-                          (                                                                                       \
-                           (((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) :                 \
-                            (                                                                                     \
-                             (((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) :               \
-                              (                                                                                   \
-                               (((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) :             \
-                                (                                                                                 \
-                                 (((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13U) :           \
-                                  (                                                                               \
-                                   (((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? (14U) :         \
-                                    (                                                                             \
-                                     (((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? (15U) :       \
-                                      (                                                                           \
-                                       (((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL17) ? (17U) :     \
-                                        (                                                                         \
-                                         (((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSEL18) ? (18U) :   \
-                                          (0U)                                                                     \
-                                        )                                                                         \
-                                      )                                                                           \
-                                    )                                                                             \
-                                  )                                                                               \
-                                )                                                                                 \
-                              )                                                                                   \
-                            )                                                                                     \
-                          )                                                                                       \
-                        )                                                                                         \
-                      )                                                                                           \
-                    )                                                                                             \
-                  )                                                                                               \
-                )                                                                                                 \
-              )                                                                                                   \
-            )                                                                                                     \
-          )                                                                                                       \
-        )                                                                                                         \
-      )                                                                                                           \
-  )
-#endif
-
-/**
-  * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
-  *         from number in decimal format.
-  * @note   Example:
-  *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
-  *           will return a data equivalent to "LL_ADC_CHANNEL_4".
-  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0
-  *         @arg @ref LL_ADC_CHANNEL_1
-  *         @arg @ref LL_ADC_CHANNEL_2
-  *         @arg @ref LL_ADC_CHANNEL_3
-  *         @arg @ref LL_ADC_CHANNEL_4
-  *         @arg @ref LL_ADC_CHANNEL_5
-  *         @arg @ref LL_ADC_CHANNEL_6
-  *         @arg @ref LL_ADC_CHANNEL_7
-  *         @arg @ref LL_ADC_CHANNEL_8
-  *         @arg @ref LL_ADC_CHANNEL_9
-  *         @arg @ref LL_ADC_CHANNEL_10
-  *         @arg @ref LL_ADC_CHANNEL_11
-  *         @arg @ref LL_ADC_CHANNEL_12
-  *         @arg @ref LL_ADC_CHANNEL_13
-  *         @arg @ref LL_ADC_CHANNEL_14
-  *         @arg @ref LL_ADC_CHANNEL_15
-  *         @arg @ref LL_ADC_CHANNEL_16         (1)
-  *         @arg @ref LL_ADC_CHANNEL_17
-  *         @arg @ref LL_ADC_CHANNEL_18
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT       (2)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR    (2)
-  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)(2)
-  *         
-  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.\n
-  *         (2) For ADC channel read back from ADC register,
-  *             comparison with internal channel parameter to be done
-  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
-  */
-#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
-  (                                                                            \
-   ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) |                 \
-   (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__))                                     \
-  )
-
-/**
-  * @brief  Helper macro to determine whether the selected channel
-  *         corresponds to literal definitions of driver.
-  * @note   The different literal definitions of ADC channels are:
-  *         - ADC internal channel:
-  *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
-  *         - ADC external channel (channel connected to a GPIO pin):
-  *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
-  * @note   The channel parameter must be a value defined from literal
-  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
-  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
-  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
-  *         must not be a value from functions where a channel number is
-  *         returned from ADC registers,
-  *         because internal and external channels share the same channel
-  *         number in ADC registers. The differentiation is made only with
-  *         parameters definitions of driver.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0
-  *         @arg @ref LL_ADC_CHANNEL_1
-  *         @arg @ref LL_ADC_CHANNEL_2
-  *         @arg @ref LL_ADC_CHANNEL_3
-  *         @arg @ref LL_ADC_CHANNEL_4
-  *         @arg @ref LL_ADC_CHANNEL_5
-  *         @arg @ref LL_ADC_CHANNEL_6
-  *         @arg @ref LL_ADC_CHANNEL_7
-  *         @arg @ref LL_ADC_CHANNEL_8
-  *         @arg @ref LL_ADC_CHANNEL_9
-  *         @arg @ref LL_ADC_CHANNEL_10
-  *         @arg @ref LL_ADC_CHANNEL_11
-  *         @arg @ref LL_ADC_CHANNEL_12
-  *         @arg @ref LL_ADC_CHANNEL_13
-  *         @arg @ref LL_ADC_CHANNEL_14
-  *         @arg @ref LL_ADC_CHANNEL_15
-  *         @arg @ref LL_ADC_CHANNEL_16         (1)
-  *         @arg @ref LL_ADC_CHANNEL_17
-  *         @arg @ref LL_ADC_CHANNEL_18
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
-  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
-  *         
-  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
-  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
-  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
-  */
-#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
-  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
-
-/**
-  * @brief  Helper macro to convert a channel defined from parameter
-  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
-  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
-  *         to its equivalent parameter definition of a ADC external channel
-  *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
-  * @note   The channel parameter can be, additionally to a value
-  *         defined from parameter definition of a ADC internal channel
-  *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
-  *         a value defined from parameter definition of
-  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
-  *         or a value from functions where a channel number is returned
-  *         from ADC registers.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0
-  *         @arg @ref LL_ADC_CHANNEL_1
-  *         @arg @ref LL_ADC_CHANNEL_2
-  *         @arg @ref LL_ADC_CHANNEL_3
-  *         @arg @ref LL_ADC_CHANNEL_4
-  *         @arg @ref LL_ADC_CHANNEL_5
-  *         @arg @ref LL_ADC_CHANNEL_6
-  *         @arg @ref LL_ADC_CHANNEL_7
-  *         @arg @ref LL_ADC_CHANNEL_8
-  *         @arg @ref LL_ADC_CHANNEL_9
-  *         @arg @ref LL_ADC_CHANNEL_10
-  *         @arg @ref LL_ADC_CHANNEL_11
-  *         @arg @ref LL_ADC_CHANNEL_12
-  *         @arg @ref LL_ADC_CHANNEL_13
-  *         @arg @ref LL_ADC_CHANNEL_14
-  *         @arg @ref LL_ADC_CHANNEL_15
-  *         @arg @ref LL_ADC_CHANNEL_16         (1)
-  *         @arg @ref LL_ADC_CHANNEL_17
-  *         @arg @ref LL_ADC_CHANNEL_18
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
-  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
-  *         
-  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0
-  *         @arg @ref LL_ADC_CHANNEL_1
-  *         @arg @ref LL_ADC_CHANNEL_2
-  *         @arg @ref LL_ADC_CHANNEL_3
-  *         @arg @ref LL_ADC_CHANNEL_4
-  *         @arg @ref LL_ADC_CHANNEL_5
-  *         @arg @ref LL_ADC_CHANNEL_6
-  *         @arg @ref LL_ADC_CHANNEL_7
-  *         @arg @ref LL_ADC_CHANNEL_8
-  *         @arg @ref LL_ADC_CHANNEL_9
-  *         @arg @ref LL_ADC_CHANNEL_10
-  *         @arg @ref LL_ADC_CHANNEL_11
-  *         @arg @ref LL_ADC_CHANNEL_12
-  *         @arg @ref LL_ADC_CHANNEL_13
-  *         @arg @ref LL_ADC_CHANNEL_14
-  *         @arg @ref LL_ADC_CHANNEL_15
-  *         @arg @ref LL_ADC_CHANNEL_16
-  *         @arg @ref LL_ADC_CHANNEL_17
-  *         @arg @ref LL_ADC_CHANNEL_18
-  */
-#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
-  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
-
-/**
-  * @brief  Helper macro to determine whether the internal channel
-  *         selected is available on the ADC instance selected.
-  * @note   The channel parameter must be a value defined from parameter
-  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
-  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
-  *         must not be a value defined from parameter definition of
-  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
-  *         or a value from functions where a channel number is
-  *         returned from ADC registers,
-  *         because internal and external channels share the same channel
-  *         number in ADC registers. The differentiation is made only with
-  *         parameters definitions of driver.
-  * @param  __ADC_INSTANCE__ ADC instance
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
-  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
-  *         
-  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
-
-  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
-  *         Value "1" if the internal channel selected is available on the ADC instance selected.
-  */
-#if defined(ADC_CCR_VLCDEN)
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
-  (                                                                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VLCD)                                     \
-  )
-#else
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
-  (                                                                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)                               \
-  )
-#endif
-
-/**
-  * @brief  Helper macro to define ADC analog watchdog parameter:
-  *         define a single channel to monitor with analog watchdog
-  *         from sequencer channel and groups definition.
-  * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
-  *         Example:
-  *           LL_ADC_SetAnalogWDMonitChannels(
-  *             ADC1, LL_ADC_AWD1,
-  *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0
-  *         @arg @ref LL_ADC_CHANNEL_1
-  *         @arg @ref LL_ADC_CHANNEL_2
-  *         @arg @ref LL_ADC_CHANNEL_3
-  *         @arg @ref LL_ADC_CHANNEL_4
-  *         @arg @ref LL_ADC_CHANNEL_5
-  *         @arg @ref LL_ADC_CHANNEL_6
-  *         @arg @ref LL_ADC_CHANNEL_7
-  *         @arg @ref LL_ADC_CHANNEL_8
-  *         @arg @ref LL_ADC_CHANNEL_9
-  *         @arg @ref LL_ADC_CHANNEL_10
-  *         @arg @ref LL_ADC_CHANNEL_11
-  *         @arg @ref LL_ADC_CHANNEL_12
-  *         @arg @ref LL_ADC_CHANNEL_13
-  *         @arg @ref LL_ADC_CHANNEL_14
-  *         @arg @ref LL_ADC_CHANNEL_15
-  *         @arg @ref LL_ADC_CHANNEL_16         (1)
-  *         @arg @ref LL_ADC_CHANNEL_17
-  *         @arg @ref LL_ADC_CHANNEL_18
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT       (2)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR    (2)
-  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)(2)
-  *         
-  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.\n
-  *         (2) For ADC channel read back from ADC register,
-  *             comparison with internal channel parameter to be done
-  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
-  * @param  __GROUP__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_GROUP_REGULAR
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_AWD_DISABLE
-  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG
-  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG
-  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
-  *         @arg @ref LL_ADC_AWD_CH_VLCD_REG             (1)
-  *         
-  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
-  */
-#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
-  (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)
-
-/**
-  * @brief  Helper macro to set the value of ADC analog watchdog threshold high
-  *         or low in function of ADC resolution, when ADC resolution is
-  *         different of 12 bits.
-  * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
-  *         or @ref LL_ADC_SetAnalogWDThresholds().
-  *         Example, with a ADC resolution of 8 bits, to set the value of
-  *         analog watchdog threshold high (on 8 bits):
-  *           LL_ADC_SetAnalogWDThresholds
-  *            (< ADCx param >,
-  *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
-  *            );
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-  */
-#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
-  ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
-
-/**
-  * @brief  Helper macro to get the value of ADC analog watchdog threshold high
-  *         or low in function of ADC resolution, when ADC resolution is 
-  *         different of 12 bits.
-  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
-  *         Example, with a ADC resolution of 8 bits, to get the value of
-  *         analog watchdog threshold high (on 8 bits):
-  *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
-  *            (LL_ADC_RESOLUTION_8B,
-  *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
-  *            );
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-  */
-#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
-  ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
-
-/**
-  * @brief  Helper macro to get the ADC analog watchdog threshold high
-  *         or low from raw value containing both thresholds concatenated.
-  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
-  *         Example, to get analog watchdog threshold high from the register raw value:
-  *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
-  * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
-  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
-  * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-  */
-#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
-  (((__AWD_THRESHOLD_TYPE__) == LL_ADC_AWD_THRESHOLD_LOW)                                 \
-    ? (                                                                                   \
-       (__AWD_THRESHOLDS__) & LL_ADC_AWD_THRESHOLD_LOW                                    \
-      )                                                                                   \
-      :                                                                                   \
-      (                                                                                   \
-       ((__AWD_THRESHOLDS__) >> ADC_TR_HT_BITOFFSET_POS) & LL_ADC_AWD_THRESHOLD_LOW       \
-      )                                                                                   \
-  )
-
-/**
-  * @brief  Helper macro to select the ADC common instance
-  *         to which is belonging the selected ADC instance.
-  * @note   ADC common register instance can be used for:
-  *         - Set parameters common to several ADC instances
-  *         - Multimode (for devices with several ADC instances)
-  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
-  * @param  __ADCx__ ADC instance
-  * @retval ADC common register instance
-  */
-#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
-  (ADC1_COMMON)
-
-/**
-  * @brief  Helper macro to check if all ADC instances sharing the same
-  *         ADC common instance are disabled.
-  * @note   This check is required by functions with setting conditioned to
-  *         ADC state:
-  *         All ADC instances of the ADC common group must be disabled.
-  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
-  * @note   On devices with only 1 ADC common instance, parameter of this macro
-  *         is useless and can be ignored (parameter kept for compatibility
-  *         with devices featuring several ADC common instances).
-  * @param  __ADCXY_COMMON__ ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @retval Value "0" if all ADC instances sharing the same ADC common instance
-  *         are disabled.
-  *         Value "1" if at least one ADC instance sharing the same ADC common instance
-  *         is enabled.
-  */
-#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
-  LL_ADC_IsEnabled(ADC1)
-
-/**
-  * @brief  Helper macro to define the ADC conversion data full-scale digital
-  *         value corresponding to the selected ADC resolution.
-  * @note   ADC conversion data full-scale corresponds to voltage range
-  *         determined by analog voltage references Vref+ and Vref-
-  *         (refer to reference manual).
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
-  */
-#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
-  ((0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)))
-
-/**
-  * @brief  Helper macro to convert the ADC conversion data from
-  *         a resolution to another resolution.
-  * @param  __DATA__ ADC conversion data to be converted 
-  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
-  *         This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
-  *         This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval ADC conversion data to the requested resolution
-  */
-#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
-  (((__DATA__)                                                                 \
-    << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)))   \
-   >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))      \
-  )
-
-/**
-  * @brief  Helper macro to calculate the voltage (unit: mVolt)
-  *         corresponding to a ADC conversion data (unit: digital value).
-  * @note   Analog reference voltage (Vref+) must be either known from
-  *         user board environment or can be calculated using ADC measurement
-  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
-  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
-  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
-  *                       (unit: digital value).
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
-  */
-#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
-                                      __ADC_DATA__,\
-                                      __ADC_RESOLUTION__)                      \
-  ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
-   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
-  )
-
-/**
-  * @brief  Helper macro to calculate analog reference voltage (Vref+)
-  *         (unit: mVolt) from ADC conversion data of internal voltage
-  *         reference VrefInt.
-  * @note   Computation is using VrefInt calibration value
-  *         stored in system memory for each device during production.
-  * @note   This voltage depends on user board environment: voltage level
-  *         connected to pin Vref+.
-  *         On devices with small package, the pin Vref+ is not present
-  *         and internally bonded to pin Vdda.
-  * @note   On this STM32 serie, calibration data of internal voltage reference
-  *         VrefInt corresponds to a resolution of 12 bits,
-  *         this is the recommended ADC resolution to convert voltage of
-  *         internal voltage reference VrefInt.
-  *         Otherwise, this macro performs the processing to scale
-  *         ADC conversion data to 12 bits.
-  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
-  *         of internal voltage reference VrefInt (unit: digital value).
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval Analog reference voltage (unit: mV)
-  */
-#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
-                                         __ADC_RESOLUTION__)                   \
-  (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
-    / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \
-                                       (__ADC_RESOLUTION__),                   \
-                                       LL_ADC_RESOLUTION_12B)                  \
-  )
-
-/* Note: On device STM32L011, calibration parameter TS_CAL1 is not available. */
-/*       Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/
-/*       Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().        */
-/* Note: On device STM32L010xx, temperature sensor is not available.          */
-/*       Therefore, helper macro related to temperature sensor are            */
-/*       not available.                                                       */
-#if !defined(STM32L011xx) && !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4)
-/**
-  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
-  *         from ADC conversion data of internal temperature sensor.
-  * @note   Computation is using temperature sensor calibration values
-  *         stored in system memory for each device during production.
-  * @note   Calculation formula:
-  *           Temperature = ((TS_ADC_DATA - TS_CAL1)
-  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
-  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
-  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
-  *                Avg_Slope = (TS_CAL2 - TS_CAL1)
-  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
-  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
-  *                            TEMP_DEGC_CAL1 (calibrated in factory)
-  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
-  *                            TEMP_DEGC_CAL2 (calibrated in factory)
-  *         Caution: Calculation relevancy under reserve that calibration
-  *                  parameters are correct (address and data).
-  *                  To calculate temperature using temperature sensor
-  *                  datasheet typical values (generic values less, therefore
-  *                  less accurate than calibrated values),
-  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
-  * @note   As calculation input, the analog reference voltage (Vref+) must be
-  *         defined as it impacts the ADC LSB equivalent voltage.
-  * @note   Analog reference voltage (Vref+) must be either known from
-  *         user board environment or can be calculated using ADC measurement
-  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
-  * @note   On this STM32 serie, calibration data of temperature sensor
-  *         corresponds to a resolution of 12 bits,
-  *         this is the recommended ADC resolution to convert voltage of
-  *         temperature sensor.
-  *         Otherwise, this macro performs the processing to scale
-  *         ADC conversion data to 12 bits.
-  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
-  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
-  *                                 temperature sensor (unit: digital value).
-  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
-  *                                 sensor voltage has been measured.
-  *         This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval Temperature (unit: degree Celsius)
-  */
-#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
-                                  __TEMPSENSOR_ADC_DATA__,\
-                                  __ADC_RESOLUTION__)                              \
-  (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
-                                                    (__ADC_RESOLUTION__),          \
-                                                    LL_ADC_RESOLUTION_12B)         \
-                   * (__VREFANALOG_VOLTAGE__))                                     \
-                  / TEMPSENSOR_CAL_VREFANALOG)                                     \
-        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
-     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
-    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
-   ) + TEMPSENSOR_CAL1_TEMP                                                        \
-  )
-#endif
-
-/* Note: On device STM32L010xx, temperature sensor is not available.          */
-/*       Therefore, helper macro related to temperature sensor are            */
-/*       not available.                                                       */
-#if !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4)
-/**
-  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
-  *         from ADC conversion data of internal temperature sensor.
-  * @note   Computation is using temperature sensor typical values
-  *         (refer to device datasheet).
-  * @note   Calculation formula:
-  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
-  *                         / Avg_Slope + CALx_TEMP
-  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
-  *                                   (unit: digital value)
-  *                Avg_Slope        = temperature sensor slope
-  *                                   (unit: uV/Degree Celsius)
-  *                TS_TYP_CALx_VOLT = temperature sensor digital value at
-  *                                   temperature CALx_TEMP (unit: mV)
-  *         Caution: Calculation relevancy under reserve the temperature sensor
-  *                  of the current device has characteristics in line with
-  *                  datasheet typical values.
-  *                  If temperature sensor calibration values are available on
-  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
-  *                  temperature calculation will be more accurate using
-  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
-  * @note   As calculation input, the analog reference voltage (Vref+) must be
-  *         defined as it impacts the ADC LSB equivalent voltage.
-  * @note   Analog reference voltage (Vref+) must be either known from
-  *         user board environment or can be calculated using ADC measurement
-  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
-  * @note   ADC measurement data must correspond to a resolution of 12bits
-  *         (full scale digital value 4095). If not the case, the data must be
-  *         preliminarily rescaled to an equivalent resolution of 12 bits.
-  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
-  *                                       On STM32L0, refer to device datasheet parameter "Avg_Slope".
-  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
-  *                                       On STM32L0, refer to device datasheet parameter "V130" (corresponding to TS_CAL2).
-  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
-  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
-  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
-  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
-  *         This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval Temperature (unit: degree Celsius)
-  */
-#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
-                                             __TEMPSENSOR_TYP_CALX_V__,\
-                                             __TEMPSENSOR_CALX_TEMP__,\
-                                             __VREFANALOG_VOLTAGE__,\
-                                             __TEMPSENSOR_ADC_DATA__,\
-                                             __ADC_RESOLUTION__)               \
-  ((( (                                                                        \
-       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
-                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
-                 * 1000)                                                       \
-       -                                                                       \
-       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
-                 * 1000)                                                       \
-      )                                                                        \
-    ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
-   ) + (__TEMPSENSOR_CALX_TEMP__)                                              \
-  )
-#endif
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
-  * @{
-  */
-
-/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
-  * @{
-  */
-/* Note: LL ADC functions to set DMA transfer are located into sections of    */
-/*       configuration of ADC instance, groups and multimode (if available):  */
-/*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
-
-/**
-  * @brief  Function to help to configure DMA transfer from ADC: retrieve the
-  *         ADC register address from ADC instance and a list of ADC registers
-  *         intended to be used (most commonly) with DMA transfer.
-  * @note   These ADC registers are data registers:
-  *         when ADC conversion data is available in ADC data registers,
-  *         ADC generates a DMA transfer request.
-  * @note   This macro is intended to be used with LL DMA driver, refer to
-  *         function "LL_DMA_ConfigAddresses()".
-  *         Example:
-  *           LL_DMA_ConfigAddresses(DMA1,
-  *                                  LL_DMA_CHANNEL_1,
-  *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
-  *                                  (uint32_t)&< array or variable >,
-  *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
-  * @note   For devices with several ADC: in multimode, some devices
-  *         use a different data register outside of ADC instance scope
-  *         (common data register). This macro manages this register difference,
-  *         only ADC instance has to be set as parameter.
-  * @rmtoll DR       DATA           LL_ADC_DMA_GetRegAddr
-  * @param  ADCx ADC instance
-  * @param  Register This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
-  * @retval ADC register address
-  */
-__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
-{
-  /* Prevent unused argument compilation warning */
-  (void)Register;
-
-  /* Retrieve address of register DR */
-  return (uint32_t)&(ADCx->DR);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
-  * @{
-  */
-
-/**
-  * @brief  Set parameter common to several ADC: Clock source and prescaler.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         All ADC instances of the ADC common group must be disabled.
-  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
-  *         ADC instance or by using helper macro helper macro
-  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
-  * @rmtoll CCR      PRESC          LL_ADC_SetCommonClock
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @param  CommonClock This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1   (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2   (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4   (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6   (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8   (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10  (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12  (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16  (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32  (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64  (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
-  *
-  *         (1) ADC common clock asynchronous prescaler is applied to 
-  *             each ADC instance if the corresponding ADC instance clock  
-  *             is set to clock source asynchronous.
-  *             (refer to function @ref LL_ADC_SetClock() ).
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
-{
-  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
-}
-
-/**
-  * @brief  Get parameter common to several ADC: Clock source and prescaler.
-  * @rmtoll CCR      PRESC          LL_ADC_GetCommonClock
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1   (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2   (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4   (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6   (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8   (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10  (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12  (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16  (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32  (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64  (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
-  *
-  *         (1) ADC common clock asynchronous prescaler is applied to 
-  *             each ADC instance if the corresponding ADC instance clock  
-  *             is set to clock source asynchronous.
-  *             (refer to function @ref LL_ADC_SetClock() ).
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
-{
-  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
-}
-
-/**
-  * @brief  Set parameter common to several ADC: Clock low frequency mode.
-  *         Refer to reference manual for alignments formats
-  *         dependencies to ADC resolutions.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CCR      LFMEN          LL_ADC_SetCommonFrequencyMode
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @param  CommonFrequencyMode This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH
-  *         @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonFrequencyMode)
-{
-  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_LFMEN, CommonFrequencyMode);
-}
-
-/**
-  * @brief  Get parameter common to several ADC: Clock low frequency mode.
-  *         Refer to reference manual for alignments formats
-  *         dependencies to ADC resolutions.
-  * @rmtoll CCR      LFMEN          LL_ADC_GetCommonFrequencyMode
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH
-  *         @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON)
-{
-  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_LFMEN));
-}
-
-/**
-  * @brief  Set parameter common to several ADC: measurement path to internal
-  *         channels (VrefInt, temperature sensor, ...).
-  * @note   One or several values can be selected.
-  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
-  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
-  * @note   Stabilization time of measurement path to internal channel:
-  *         After enabling internal paths, before starting ADC conversion,
-  *         a delay is required for internal voltage reference and
-  *         temperature sensor stabilization time.
-  *         Refer to device datasheet.
-  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
-  *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
-  * @note   ADC internal channel sampling time constraint:
-  *         For ADC conversion of internal channels,
-  *         a sampling time minimum value is required.
-  *         Refer to device datasheet.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         All ADC instances of the ADC common group must be disabled.
-  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
-  *         ADC instance or by using helper macro helper macro
-  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
-  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
-  *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n
-  *         CCR      VLCDEN         LL_ADC_SetCommonPathInternalCh
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @param  PathInternal This parameter can be a combination of the following values:
-  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
-  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
-  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR (2)
-  *         @arg @ref LL_ADC_PATH_INTERNAL_VLCD (1)
-  *
-  *         (1) value not defined in all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
-  *         (2) value not defined in all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx, STM32L04xxx, STM32L03xxx, STM32L02xxx.
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
-{
-#if defined (ADC_CCR_VLCDEN) && defined (ADC_CCR_TSEN)
-  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VLCDEN, PathInternal);
-#elif defined (ADC_CCR_TSEN)
-  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
-#else
-  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN, PathInternal);
-#endif
-}
-
-/**
-  * @brief  Get parameter common to several ADC: measurement path to internal
-  *         channels (VrefInt, temperature sensor, ...).
-  * @note   One or several values can be selected.
-  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
-  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
-  * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
-  *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n
-  *         CCR      VLCDEN         LL_ADC_GetCommonPathInternalCh
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @retval Returned value can be a combination of the following values:
-  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
-  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
-  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR (2)
-  *         @arg @ref LL_ADC_PATH_INTERNAL_VLCD (1)
-  *
-  *         (1) value not defined in all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
-  *         (2) value not defined in all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx, STM32L04xxx, STM32L03xxx, STM32L02xxx.
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
-{
-#if defined (ADC_CCR_VLCDEN) && defined (ADC_CCR_TSEN)
-  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VLCDEN));
-#elif defined (ADC_CCR_TSEN)
-  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
-#else
-  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN));
-#endif
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
-  * @{
-  */
-
-/**
-  * @brief  Set ADC instance clock source and prescaler.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled.
-  * @rmtoll CFGR2    CKMODE         LL_ADC_SetClock
-  * @param  ADCx ADC instance
-  * @param  ClockSource This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
-  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
-  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC (1)
-  *         
-  *         (1) Asynchronous clock prescaler can be configured using
-  *             function @ref LL_ADC_SetCommonClock().\n
-  *         (2) Caution: This parameter has some clock ratio constraints:
-  *             This configuration must be enabled only if PCLK has a 50%
-  *             duty clock cycle (APB prescaler configured inside the RCC
-  *             must be bypassed and the system clock must by 50% duty
-  *             cycle).
-  *             Refer to reference manual.
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
-{
-  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
-}
-
-/**
-  * @brief  Get ADC instance clock source and prescaler.
-  * @rmtoll CFGR2    CKMODE         LL_ADC_GetClock
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
-  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
-  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
-  *         @arg @ref LL_ADC_CLOCK_ASYNC (1)
-  *         
-  *         (1) Asynchronous clock prescaler can be retrieved using
-  *             function @ref LL_ADC_GetCommonClock().\n
-  *         (2) Caution: This parameter has some clock ratio constraints:
-  *             This configuration must be enabled only if PCLK has a 50%
-  *             duty clock cycle (APB prescaler configured inside the RCC
-  *             must be bypassed and the system clock must by 50% duty
-  *             cycle).
-  *             Refer to reference manual.
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
-}
-
-/**
-  * @brief  Set ADC calibration factor in the mode single-ended
-  *         or differential (for devices with differential mode available).
-  * @note   This function is intended to set calibration parameters
-  *         without having to perform a new calibration using
-  *         @ref LL_ADC_StartCalibration().
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be enabled, without calibration on going, without conversion
-  *         on going on group regular.
-  * @rmtoll CALFACT  CALFACT        LL_ADC_SetCalibrationFactor
-  * @param  ADCx ADC instance
-  * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
-{
-  MODIFY_REG(ADCx->CALFACT,
-             ADC_CALFACT_CALFACT,
-             CalibrationFactor);
-}
-
-/**
-  * @brief  Get ADC calibration factor in the mode single-ended
-  *         or differential (for devices with differential mode available).
-  * @note   Calibration factors are set by hardware after performing
-  *         a calibration run using function @ref LL_ADC_StartCalibration().
-  * @rmtoll CALFACT  CALFACT        LL_ADC_GetCalibrationFactor
-  * @param  ADCx ADC instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x7F
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
-}
-
-/**
-  * @brief  Set ADC resolution.
-  *         Refer to reference manual for alignments formats
-  *         dependencies to ADC resolutions.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR1    RES            LL_ADC_SetResolution
-  * @param  ADCx ADC instance
-  * @param  Resolution This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
-{
-  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
-}
-
-/**
-  * @brief  Get ADC resolution.
-  *         Refer to reference manual for alignments formats
-  *         dependencies to ADC resolutions.
-  * @rmtoll CFGR1    RES            LL_ADC_GetResolution
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
-}
-
-/**
-  * @brief  Set ADC conversion data alignment.
-  * @note   Refer to reference manual for alignments formats
-  *         dependencies to ADC resolutions.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR1    ALIGN          LL_ADC_SetDataAlignment
-  * @param  ADCx ADC instance
-  * @param  DataAlignment This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
-  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
-{
-  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
-}
-
-/**
-  * @brief  Get ADC conversion data alignment.
-  * @note   Refer to reference manual for alignments formats
-  *         dependencies to ADC resolutions.
-  * @rmtoll CFGR1    ALIGN          LL_ADC_GetDataAlignment
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
-  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
-}
-
-/**
-  * @brief  Set ADC low power mode.
-  * @note   Description of ADC low power modes:
-  *         - ADC low power mode "auto wait": Dynamic low power mode,
-  *           ADC conversions occurrences are limited to the minimum necessary
-  *           in order to reduce power consumption.
-  *           New ADC conversion starts only when the previous
-  *           unitary conversion data (for ADC group regular)
-  *           has been retrieved by user software.
-  *           In the meantime, ADC remains idle: does not performs any
-  *           other conversion.
-  *           This mode allows to automatically adapt the ADC conversions
-  *           triggers to the speed of the software that reads the data.
-  *           Moreover, this avoids risk of overrun for low frequency
-  *           applications.
-  *           How to use this low power mode:
-  *           - Do not use with interruption or DMA since these modes
-  *             have to clear immediately the EOC flag to free the
-  *             IRQ vector sequencer.
-  *           - Do use with polling: 1. Start conversion,
-  *             2. Later on, when conversion data is needed: poll for end of
-  *             conversion  to ensure that conversion is completed and
-  *             retrieve ADC conversion data. This will trig another
-  *             ADC conversion start.
-  *         - ADC low power mode "auto power-off" (feature available on
-  *           this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
-  *           the ADC automatically powers-off after a conversion and
-  *           automatically wakes up when a new conversion is triggered
-  *           (with startup time between trigger and start of sampling).
-  *           This feature can be combined with low power mode "auto wait".
-  * @note   With ADC low power mode "auto wait", the ADC conversion data read
-  *         is corresponding to previous ADC conversion start, independently
-  *         of delay during which ADC was idle.
-  *         Therefore, the ADC conversion data may be outdated: does not
-  *         correspond to the current voltage level on the selected
-  *         ADC channel.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR1    WAIT           LL_ADC_SetLowPowerMode\n
-  *         CFGR1    AUTOFF         LL_ADC_SetLowPowerMode
-  * @param  ADCx ADC instance
-  * @param  LowPowerMode This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_LP_MODE_NONE
-  *         @arg @ref LL_ADC_LP_AUTOWAIT
-  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
-{
-  MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
-}
-
-/**
-  * @brief  Get ADC low power mode:
-  * @note   Description of ADC low power modes:
-  *         - ADC low power mode "auto wait": Dynamic low power mode,
-  *           ADC conversions occurrences are limited to the minimum necessary
-  *           in order to reduce power consumption.
-  *           New ADC conversion starts only when the previous
-  *           unitary conversion data (for ADC group regular)
-  *           has been retrieved by user software.
-  *           In the meantime, ADC remains idle: does not performs any
-  *           other conversion.
-  *           This mode allows to automatically adapt the ADC conversions
-  *           triggers to the speed of the software that reads the data.
-  *           Moreover, this avoids risk of overrun for low frequency
-  *           applications.
-  *           How to use this low power mode:
-  *           - Do not use with interruption or DMA since these modes
-  *             have to clear immediately the EOC flag to free the
-  *             IRQ vector sequencer.
-  *           - Do use with polling: 1. Start conversion,
-  *             2. Later on, when conversion data is needed: poll for end of
-  *             conversion  to ensure that conversion is completed and
-  *             retrieve ADC conversion data. This will trig another
-  *             ADC conversion start.
-  *         - ADC low power mode "auto power-off" (feature available on
-  *           this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
-  *           the ADC automatically powers-off after a conversion and
-  *           automatically wakes up when a new conversion is triggered
-  *           (with startup time between trigger and start of sampling).
-  *           This feature can be combined with low power mode "auto wait".
-  * @note   With ADC low power mode "auto wait", the ADC conversion data read
-  *         is corresponding to previous ADC conversion start, independently
-  *         of delay during which ADC was idle.
-  *         Therefore, the ADC conversion data may be outdated: does not
-  *         correspond to the current voltage level on the selected
-  *         ADC channel.
-  * @rmtoll CFGR1    WAIT           LL_ADC_GetLowPowerMode\n
-  *         CFGR1    AUTOFF         LL_ADC_GetLowPowerMode
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_LP_MODE_NONE
-  *         @arg @ref LL_ADC_LP_AUTOWAIT
-  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
-}
-
-/**
-  * @brief  Set sampling time common to a group of channels.
-  * @note   Unit: ADC clock cycles.
-  * @note   On this STM32 serie, sampling time scope is on ADC instance:
-  *         Sampling time common to all channels.
-  *         (on some other STM32 families, sampling time is channel wise)
-  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
-  *         converted:
-  *         sampling time constraints must be respected (sampling time can be
-  *         adjusted in function of ADC clock frequency and sampling time
-  *         setting).
-  *         Refer to device datasheet for timings values (parameters TS_vrefint,
-  *         TS_temp, ...).
-  * @note   Conversion time is the addition of sampling time and processing time.
-  *         On this STM32 serie, ADC processing time is:
-  *         - 12.5 ADC clock cycles at ADC resolution 12 bits
-  *         - 10.5 ADC clock cycles at ADC resolution 10 bits
-  *         - 8.5 ADC clock cycles at ADC resolution 8 bits
-  *         - 6.5 ADC clock cycles at ADC resolution 6 bits
-  * @note   In case of ADC conversion of internal channel (VrefInt,
-  *         temperature sensor, ...), a sampling time minimum value
-  *         is required.
-  *         Refer to device datasheet.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll SMPR     SMP            LL_ADC_SetSamplingTimeCommonChannels
-  * @param  ADCx ADC instance
-  * @param  SamplingTime This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTime)
-{
-  MODIFY_REG(ADCx->SMPR, ADC_SMPR_SMP, SamplingTime);
-}
-
-/**
-  * @brief  Get sampling time common to a group of channels.
-  * @note   Unit: ADC clock cycles.
-  * @note   On this STM32 serie, sampling time scope is on ADC instance:
-  *         Sampling time common to all channels.
-  *         (on some other STM32 families, sampling time is channel wise)
-  * @note   Conversion time is the addition of sampling time and processing time.
-  *         Refer to reference manual for ADC processing time of
-  *         this STM32 serie.
-  * @rmtoll SMPR     SMP            LL_ADC_GetSamplingTimeCommonChannels
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
-  *         @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->SMPR, ADC_SMPR_SMP));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
-  * @{
-  */
-
-/**
-  * @brief  Set ADC group regular conversion trigger source:
-  *         internal (SW start) or from external peripheral (timer event,
-  *         external interrupt line).
-  * @note   On this STM32 serie, setting trigger source to external trigger
-  *         also set trigger polarity to rising edge 
-  *         (default setting for compatibility with some ADC on other
-  *         STM32 families having this setting set by HW default value).
-  *         In case of need to modify trigger edge, use
-  *         function @ref LL_ADC_REG_SetTriggerEdge().
-  * @note   Availability of parameters of trigger sources from timer 
-  *         depends on timers availability on the selected device.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR1    EXTSEL         LL_ADC_REG_SetTriggerSource\n
-  *         CFGR1    EXTEN          LL_ADC_REG_SetTriggerSource
-  * @param  ADCx ADC instance
-  * @param  TriggerSource This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM21_CH2
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM22_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (*)
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
-{
-  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
-}
-
-/**
-  * @brief  Get ADC group regular conversion trigger source:
-  *         internal (SW start) or from external peripheral (timer event,
-  *         external interrupt line).
-  * @note   To determine whether group regular trigger source is
-  *         internal (SW start) or external, without detail
-  *         of which peripheral is selected as external trigger,
-  *         (equivalent to 
-  *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
-  *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
-  * @note   Availability of parameters of trigger sources from timer 
-  *         depends on timers availability on the selected device.
-  * @rmtoll CFGR1    EXTSEL         LL_ADC_REG_GetTriggerSource\n
-  *         CFGR1    EXTEN          LL_ADC_REG_GetTriggerSource
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM21_CH2
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM22_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (*)
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
-  *
-  *         (*) value not defined in all devices
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
-{
-  uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
-  
-  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
-  /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}.                           */
-  uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
-  
-  /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL       */
-  /* to match with triggers literals definition.                              */
-  return ((TriggerSource
-           & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
-          | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
-         );
-}
-
-/**
-  * @brief  Get ADC group regular conversion trigger source internal (SW start)
-            or external.
-  * @note   In case of group regular trigger source set to external trigger,
-  *         to determine which peripheral is selected as external trigger,
-  *         use function @ref LL_ADC_REG_GetTriggerSource().
-  * @rmtoll CFGR1    EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
-  * @param  ADCx ADC instance
-  * @retval Value "0" if trigger source external trigger
-  *         Value "1" if trigger source SW start.
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN));
-}
-
-/**
-  * @brief  Set ADC group regular conversion trigger polarity.
-  * @note   Applicable only for trigger source set to external trigger.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR1    EXTEN          LL_ADC_REG_SetTriggerEdge
-  * @param  ADCx ADC instance
-  * @param  ExternalTriggerEdge This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
-{
-  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
-}
-
-/**
-  * @brief  Get ADC group regular conversion trigger polarity.
-  * @note   Applicable only for trigger source set to external trigger.
-  * @rmtoll CFGR1    EXTEN          LL_ADC_REG_GetTriggerEdge
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
-}
-
-
-/**
-  * @brief  Set ADC group regular sequencer scan direction.
-  * @note   On some other STM32 families, this setting is not available and
-  *         the default scan direction is forward.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR1    SCANDIR        LL_ADC_REG_SetSequencerScanDirection
-  * @param  ADCx ADC instance
-  * @param  ScanDirection This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
-{
-  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
-}
-
-/**
-  * @brief  Get ADC group regular sequencer scan direction.
-  * @note   On some other STM32 families, this setting is not available and
-  *         the default scan direction is forward.
-  * @rmtoll CFGR1    SCANDIR        LL_ADC_REG_GetSequencerScanDirection
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
-}
-
-/**
-  * @brief  Set ADC group regular sequencer discontinuous mode:
-  *         sequence subdivided and scan conversions interrupted every selected
-  *         number of ranks.
-  * @note   It is not possible to enable both ADC group regular 
-  *         continuous mode and sequencer discontinuous mode.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR1    DISCEN         LL_ADC_REG_SetSequencerDiscont\n
-  * @param  ADCx ADC instance
-  * @param  SeqDiscont This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
-{
-  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
-}
-
-/**
-  * @brief  Get ADC group regular sequencer discontinuous mode:
-  *         sequence subdivided and scan conversions interrupted every selected
-  *         number of ranks.
-  * @rmtoll CFGR1    DISCEN         LL_ADC_REG_GetSequencerDiscont\n
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
-}
-
-/**
-  * @brief  Set ADC group regular sequence: channel on rank corresponding to
-  *         channel number.
-  * @note   This function performs:
-  *         - Channels ordering into each rank of scan sequence:
-  *           rank of each channel is fixed by channel HW number
-  *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
-  *         - Set channels selected by overwriting the current sequencer
-  *           configuration.
-  * @note   On this STM32 serie, ADC group regular sequencer is
-  *         not fully configurable: sequencer length and each rank
-  *         affectation to a channel are fixed by channel HW number.
-  * @note   Depending on devices and packages, some channels may not be available.
-  *         Refer to device datasheet for channels availability.
-  * @note   On this STM32 serie, to measure internal channels (VrefInt,
-  *         TempSensor, ...), measurement paths to internal channels must be
-  *         enabled separately.
-  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @note   One or several values can be selected.
-  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
-  * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChannels\n
-  *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChannels
-  * @param  ADCx ADC instance
-  * @param  Channel This parameter can be a combination of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0
-  *         @arg @ref LL_ADC_CHANNEL_1
-  *         @arg @ref LL_ADC_CHANNEL_2
-  *         @arg @ref LL_ADC_CHANNEL_3
-  *         @arg @ref LL_ADC_CHANNEL_4
-  *         @arg @ref LL_ADC_CHANNEL_5
-  *         @arg @ref LL_ADC_CHANNEL_6
-  *         @arg @ref LL_ADC_CHANNEL_7
-  *         @arg @ref LL_ADC_CHANNEL_8
-  *         @arg @ref LL_ADC_CHANNEL_9
-  *         @arg @ref LL_ADC_CHANNEL_10
-  *         @arg @ref LL_ADC_CHANNEL_11
-  *         @arg @ref LL_ADC_CHANNEL_12
-  *         @arg @ref LL_ADC_CHANNEL_13
-  *         @arg @ref LL_ADC_CHANNEL_14
-  *         @arg @ref LL_ADC_CHANNEL_15
-  *         @arg @ref LL_ADC_CHANNEL_16         (1)
-  *         @arg @ref LL_ADC_CHANNEL_17
-  *         @arg @ref LL_ADC_CHANNEL_18
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
-  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
-  *         
-  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
-{
-  /* Parameter "Channel" is used with masks because containing                */
-  /* other bits reserved for other purpose.                                   */
-  WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
-}
-
-/**
-  * @brief  Add channel to ADC group regular sequence: channel on rank corresponding to
-  *         channel number.
-  * @note   This function performs:
-  *         - Channels ordering into each rank of scan sequence:
-  *           rank of each channel is fixed by channel HW number
-  *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
-  *         - Set channels selected by adding them to the current sequencer
-  *           configuration.
-  * @note   On this STM32 serie, ADC group regular sequencer is
-  *         not fully configurable: sequencer length and each rank
-  *         affectation to a channel are fixed by channel HW number.
-  * @note   Depending on devices and packages, some channels may not be available.
-  *         Refer to device datasheet for channels availability.
-  * @note   On this STM32 serie, to measure internal channels (VrefInt,
-  *         TempSensor, ...), measurement paths to internal channels must be
-  *         enabled separately.
-  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @note   One or several values can be selected.
-  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
-  * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChAdd\n
-  *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChAdd
-  * @param  ADCx ADC instance
-  * @param  Channel This parameter can be a combination of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0
-  *         @arg @ref LL_ADC_CHANNEL_1
-  *         @arg @ref LL_ADC_CHANNEL_2
-  *         @arg @ref LL_ADC_CHANNEL_3
-  *         @arg @ref LL_ADC_CHANNEL_4
-  *         @arg @ref LL_ADC_CHANNEL_5
-  *         @arg @ref LL_ADC_CHANNEL_6
-  *         @arg @ref LL_ADC_CHANNEL_7
-  *         @arg @ref LL_ADC_CHANNEL_8
-  *         @arg @ref LL_ADC_CHANNEL_9
-  *         @arg @ref LL_ADC_CHANNEL_10
-  *         @arg @ref LL_ADC_CHANNEL_11
-  *         @arg @ref LL_ADC_CHANNEL_12
-  *         @arg @ref LL_ADC_CHANNEL_13
-  *         @arg @ref LL_ADC_CHANNEL_14
-  *         @arg @ref LL_ADC_CHANNEL_15
-  *         @arg @ref LL_ADC_CHANNEL_16         (1)
-  *         @arg @ref LL_ADC_CHANNEL_17
-  *         @arg @ref LL_ADC_CHANNEL_18
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
-  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
-  *         
-  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
-{
-  /* Parameter "Channel" is used with masks because containing                */
-  /* other bits reserved for other purpose.                                   */
-  SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
-}
-
-/**
-  * @brief  Remove channel to ADC group regular sequence: channel on rank corresponding to
-  *         channel number.
-  * @note   This function performs:
-  *         - Channels ordering into each rank of scan sequence:
-  *           rank of each channel is fixed by channel HW number
-  *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
-  *         - Set channels selected by removing them to the current sequencer
-  *           configuration.
-  * @note   On this STM32 serie, ADC group regular sequencer is
-  *         not fully configurable: sequencer length and each rank
-  *         affectation to a channel are fixed by channel HW number.
-  * @note   Depending on devices and packages, some channels may not be available.
-  *         Refer to device datasheet for channels availability.
-  * @note   On this STM32 serie, to measure internal channels (VrefInt,
-  *         TempSensor, ...), measurement paths to internal channels must be
-  *         enabled separately.
-  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @note   One or several values can be selected.
-  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
-  * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChRem\n
-  *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChRem
-  * @param  ADCx ADC instance
-  * @param  Channel This parameter can be a combination of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0
-  *         @arg @ref LL_ADC_CHANNEL_1
-  *         @arg @ref LL_ADC_CHANNEL_2
-  *         @arg @ref LL_ADC_CHANNEL_3
-  *         @arg @ref LL_ADC_CHANNEL_4
-  *         @arg @ref LL_ADC_CHANNEL_5
-  *         @arg @ref LL_ADC_CHANNEL_6
-  *         @arg @ref LL_ADC_CHANNEL_7
-  *         @arg @ref LL_ADC_CHANNEL_8
-  *         @arg @ref LL_ADC_CHANNEL_9
-  *         @arg @ref LL_ADC_CHANNEL_10
-  *         @arg @ref LL_ADC_CHANNEL_11
-  *         @arg @ref LL_ADC_CHANNEL_12
-  *         @arg @ref LL_ADC_CHANNEL_13
-  *         @arg @ref LL_ADC_CHANNEL_14
-  *         @arg @ref LL_ADC_CHANNEL_15
-  *         @arg @ref LL_ADC_CHANNEL_16         (1)
-  *         @arg @ref LL_ADC_CHANNEL_17
-  *         @arg @ref LL_ADC_CHANNEL_18
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
-  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
-  *         
-  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
-{
-  /* Parameter "Channel" is used with masks because containing                */
-  /* other bits reserved for other purpose.                                   */
-  CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
-}
-
-/**
-  * @brief  Get ADC group regular sequence: channel on rank corresponding to
-  *         channel number.
-  * @note   This function performs:
-  *         - Channels order reading into each rank of scan sequence:
-  *           rank of each channel is fixed by channel HW number
-  *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
-  * @note   On this STM32 serie, ADC group regular sequencer is
-  *         not fully configurable: sequencer length and each rank
-  *         affectation to a channel are fixed by channel HW number.
-  * @note   Depending on devices and packages, some channels may not be available.
-  *         Refer to device datasheet for channels availability.
-  * @note   On this STM32 serie, to measure internal channels (VrefInt,
-  *         TempSensor, ...), measurement paths to internal channels must be
-  *         enabled separately.
-  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @note   One or several values can be retrieved.
-  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
-  * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL1         LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL2         LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL3         LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL4         LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL5         LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL6         LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL7         LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL8         LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL9         LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL10        LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL11        LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL12        LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL13        LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL14        LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL15        LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL16        LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL17        LL_ADC_REG_GetSequencerChannels\n
-  *         CHSELR   CHSEL18        LL_ADC_REG_GetSequencerChannels
-  * @param  ADCx ADC instance
-  * @retval Returned value can be a combination of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0
-  *         @arg @ref LL_ADC_CHANNEL_1
-  *         @arg @ref LL_ADC_CHANNEL_2
-  *         @arg @ref LL_ADC_CHANNEL_3
-  *         @arg @ref LL_ADC_CHANNEL_4
-  *         @arg @ref LL_ADC_CHANNEL_5
-  *         @arg @ref LL_ADC_CHANNEL_6
-  *         @arg @ref LL_ADC_CHANNEL_7
-  *         @arg @ref LL_ADC_CHANNEL_8
-  *         @arg @ref LL_ADC_CHANNEL_9
-  *         @arg @ref LL_ADC_CHANNEL_10
-  *         @arg @ref LL_ADC_CHANNEL_11
-  *         @arg @ref LL_ADC_CHANNEL_12
-  *         @arg @ref LL_ADC_CHANNEL_13
-  *         @arg @ref LL_ADC_CHANNEL_14
-  *         @arg @ref LL_ADC_CHANNEL_15
-  *         @arg @ref LL_ADC_CHANNEL_16         (1)
-  *         @arg @ref LL_ADC_CHANNEL_17
-  *         @arg @ref LL_ADC_CHANNEL_18
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
-  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
-  *         
-  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
-{
-  uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
-  
-  return (   (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
-#if defined(ADC_CCR_VLCDEN)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
-#endif
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
-           | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
-         );
-}
-/**
-  * @brief  Set ADC continuous conversion mode on ADC group regular.
-  * @note   Description of ADC continuous conversion mode:
-  *         - single mode: one conversion per trigger
-  *         - continuous mode: after the first trigger, following
-  *           conversions launched successively automatically.
-  * @note   It is not possible to enable both ADC group regular 
-  *         continuous mode and sequencer discontinuous mode.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR1    CONT           LL_ADC_REG_SetContinuousMode
-  * @param  ADCx ADC instance
-  * @param  Continuous This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_CONV_SINGLE
-  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
-{
-  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
-}
-
-/**
-  * @brief  Get ADC continuous conversion mode on ADC group regular.
-  * @note   Description of ADC continuous conversion mode:
-  *         - single mode: one conversion per trigger
-  *         - continuous mode: after the first trigger, following
-  *           conversions launched successively automatically.
-  * @rmtoll CFGR1    CONT           LL_ADC_REG_GetContinuousMode
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_CONV_SINGLE
-  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
-}
-
-/**
-  * @brief  Set ADC group regular conversion data transfer: no transfer or
-  *         transfer by DMA, and DMA requests mode.
-  * @note   If transfer by DMA selected, specifies the DMA requests
-  *         mode:
-  *         - Limited mode (One shot mode): DMA transfer requests are stopped
-  *           when number of DMA data transfers (number of
-  *           ADC conversions) is reached.
-  *           This ADC mode is intended to be used with DMA mode non-circular.
-  *         - Unlimited mode: DMA transfer requests are unlimited,
-  *           whatever number of DMA data transfers (number of
-  *           ADC conversions).
-  *           This ADC mode is intended to be used with DMA mode circular.
-  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
-  *         mode non-circular:
-  *         when DMA transfers size will be reached, DMA will stop transfers of
-  *         ADC conversions data ADC will raise an overrun error
-  *        (overrun flag and interruption if enabled).
-  * @note   To configure DMA source address (peripheral address),
-  *         use function @ref LL_ADC_DMA_GetRegAddr().
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR1    DMAEN          LL_ADC_REG_SetDMATransfer\n
-  *         CFGR1    DMACFG         LL_ADC_REG_SetDMATransfer
-  * @param  ADCx ADC instance
-  * @param  DMATransfer This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
-  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
-  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
-{
-  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
-}
-
-/**
-  * @brief  Get ADC group regular conversion data transfer: no transfer or
-  *         transfer by DMA, and DMA requests mode.
-  * @note   If transfer by DMA selected, specifies the DMA requests
-  *         mode:
-  *         - Limited mode (One shot mode): DMA transfer requests are stopped
-  *           when number of DMA data transfers (number of
-  *           ADC conversions) is reached.
-  *           This ADC mode is intended to be used with DMA mode non-circular.
-  *         - Unlimited mode: DMA transfer requests are unlimited,
-  *           whatever number of DMA data transfers (number of
-  *           ADC conversions).
-  *           This ADC mode is intended to be used with DMA mode circular.
-  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
-  *         mode non-circular:
-  *         when DMA transfers size will be reached, DMA will stop transfers of
-  *         ADC conversions data ADC will raise an overrun error
-  *         (overrun flag and interruption if enabled).
-  * @note   To configure DMA source address (peripheral address),
-  *         use function @ref LL_ADC_DMA_GetRegAddr().
-  * @rmtoll CFGR1    DMAEN          LL_ADC_REG_GetDMATransfer\n
-  *         CFGR1    DMACFG         LL_ADC_REG_GetDMATransfer
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
-  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
-  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
-}
-
-/**
-  * @brief  Set ADC group regular behavior in case of overrun:
-  *         data preserved or overwritten.
-  * @note   Compatibility with devices without feature overrun:
-  *         other devices without this feature have a behavior
-  *         equivalent to data overwritten.
-  *         The default setting of overrun is data preserved.
-  *         Therefore, for compatibility with all devices, parameter
-  *         overrun should be set to data overwritten.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR1    OVRMOD         LL_ADC_REG_SetOverrun
-  * @param  ADCx ADC instance
-  * @param  Overrun This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
-  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
-{
-  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
-}
-
-/**
-  * @brief  Get ADC group regular behavior in case of overrun:
-  *         data preserved or overwritten.
-  * @rmtoll CFGR1    OVRMOD         LL_ADC_REG_GetOverrun
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
-  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
-  * @{
-  */
-
-/**
-  * @brief  Set ADC analog watchdog monitored channels:
-  *         a single channel or all channels,
-  *         on ADC group regular.
-  * @note   Once monitored channels are selected, analog watchdog
-  *         is enabled.
-  * @note   In case of need to define a single channel to monitor
-  *         with analog watchdog from sequencer channel definition,
-  *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
-  * @note   On this STM32 serie, there is only 1 kind of analog watchdog
-  *         instance:
-  *         - AWD standard (instance AWD1):
-  *           - channels monitored: can monitor 1 channel or all channels.
-  *           - groups monitored: ADC group regular.
-  *           - resolution: resolution is not limited (corresponds to
-  *             ADC resolution configured).
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR1    AWDCH          LL_ADC_SetAnalogWDMonitChannels\n
-  *         CFGR1    AWDSGL         LL_ADC_SetAnalogWDMonitChannels\n
-  *         CFGR1    AWDEN          LL_ADC_SetAnalogWDMonitChannels
-  * @param  ADCx ADC instance
-  * @param  AWDChannelGroup This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_AWD_DISABLE
-  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG
-  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG
-  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
-  *         @arg @ref LL_ADC_AWD_CH_VLCD_REG             (1)
-  *         
-  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
-{
-  MODIFY_REG(ADCx->CFGR1,
-             (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN),
-             (AWDChannelGroup & ADC_AWD_CR_ALL_CHANNEL_MASK));
-}
-
-/**
-  * @brief  Get ADC analog watchdog monitored channel.
-  * @note   Usage of the returned channel number:
-  *         - To reinject this channel into another function LL_ADC_xxx:
-  *           the returned channel number is only partly formatted on definition
-  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
-  *           with parts of literals LL_ADC_CHANNEL_x or using
-  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
-  *           Then the selected literal LL_ADC_CHANNEL_x can be used
-  *           as parameter for another function.
-  *         - To get the channel number in decimal format:
-  *           process the returned value with the helper macro
-  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
-  *           Applicable only when the analog watchdog is set to monitor
-  *           one channel.
-  * @note   On this STM32 serie, there is only 1 kind of analog watchdog
-  *         instance:
-  *         - AWD standard (instance AWD1):
-  *           - channels monitored: can monitor 1 channel or all channels.
-  *           - groups monitored: ADC group regular.
-  *           - resolution: resolution is not limited (corresponds to
-  *             ADC resolution configured).
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR1    AWDCH          LL_ADC_GetAnalogWDMonitChannels\n
-  *         CFGR1    AWDSGL         LL_ADC_GetAnalogWDMonitChannels\n
-  *         CFGR1    AWDEN          LL_ADC_GetAnalogWDMonitChannels
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_AWD_DISABLE
-  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG 
-  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
-  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
-{
-  uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN));
-  
-  /* Note: Set variable according to channel definition including channel ID  */
-  /*       with bitfield.                                                     */
-  uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BITOFFSET_POS);
-  uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS));
-  
-  return (AWDChannelGroup | (AWDChannelBitField * AWDChannelSingle));
-}
-
-/**
-  * @brief  Set ADC analog watchdog thresholds value of both thresholds
-  *         high and low.
-  * @note   If value of only one threshold high or low must be set,
-  *         use function @ref LL_ADC_SetAnalogWDThresholds().
-  * @note   In case of ADC resolution different of 12 bits,
-  *         analog watchdog thresholds data require a specific shift.
-  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
-  * @note   On this STM32 serie, there is only 1 kind of analog watchdog
-  *         instance:
-  *         - AWD standard (instance AWD1):
-  *           - channels monitored: can monitor 1 channel or all channels.
-  *           - groups monitored: ADC group regular.
-  *           - resolution: resolution is not limited (corresponds to
-  *             ADC resolution configured).
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll TR       HT             LL_ADC_ConfigAnalogWDThresholds\n
-  *         TR       LT             LL_ADC_ConfigAnalogWDThresholds
-  * @param  ADCx ADC instance
-  * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
-{
-  MODIFY_REG(ADCx->TR,
-             ADC_TR_HT | ADC_TR_LT,
-             (AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) | AWDThresholdLowValue);
-}
-
-/**
-  * @brief  Set ADC analog watchdog threshold value of threshold
-  *         high or low.
-  * @note   If values of both thresholds high or low must be set,
-  *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
-  * @note   In case of ADC resolution different of 12 bits,
-  *         analog watchdog thresholds data require a specific shift.
-  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
-  * @note   On this STM32 serie, there is only 1 kind of analog watchdog
-  *         instance:
-  *         - AWD standard (instance AWD1):
-  *           - channels monitored: can monitor 1 channel or all channels.
-  *           - groups monitored: ADC group regular.
-  *           - resolution: resolution is not limited (corresponds to
-  *             ADC resolution configured).
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll TR       HT             LL_ADC_SetAnalogWDThresholds\n
-  *         TR       LT             LL_ADC_SetAnalogWDThresholds
-  * @param  ADCx ADC instance
-  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
-  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
-  * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
-{
-  /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010"          */
-  /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold   */
-  /* high is selected, then data is shifted to LSB. Else(threshold low),      */
-  /* data is not shifted.                                                     */
-  MODIFY_REG(ADCx->TR,
-             AWDThresholdsHighLow,
-             AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & ((uint32_t)0x00000010U)));
-}
-
-/**
-  * @brief  Get ADC analog watchdog threshold value of threshold high,
-  *         threshold low or raw data with ADC thresholds high and low
-  *         concatenated.
-  * @note   If raw data with ADC thresholds high and low is retrieved,
-  *         the data of each threshold high or low can be isolated
-  *         using helper macro:
-  *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
-  * @note   In case of ADC resolution different of 12 bits,
-  *         analog watchdog thresholds data require a specific shift.
-  *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
-  * @rmtoll TR       HT             LL_ADC_GetAnalogWDThresholds\n
-  *         TR       LT             LL_ADC_GetAnalogWDThresholds
-  * @param  ADCx ADC instance
-  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
-  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
-  *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-*/
-__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
-{
-  /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010"          */
-  /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold   */
-  /* high is selected, then data is shifted to LSB. Else(threshold low or     */
-  /* both thresholds), data is not shifted.                                   */
-  return (uint32_t)(READ_BIT(ADCx->TR,
-                             (AWDThresholdsHighLow | ADC_TR_LT))
-                    >> ((~AWDThresholdsHighLow) & (0x00000010U))
-                   );
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
-  * @{
-  */
-
-/**
-  * @brief  Set ADC oversampling scope.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR2    OVSE           LL_ADC_SetOverSamplingScope
-  * @param  ADCx ADC instance
-  * @param  OvsScope This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_OVS_DISABLE
-  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
-{
-  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
-}
-
-/**
-  * @brief  Get ADC oversampling scope.
-  * @rmtoll CFGR2    OVSE           LL_ADC_GetOverSamplingScope
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_OVS_DISABLE
-  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
-}
-
-/**
-  * @brief  Set ADC oversampling discontinuous mode (triggered mode)
-  *         on the selected ADC group.
-  * @note   Number of oversampled conversions are done either in:
-  *         - continuous mode (all conversions of oversampling ratio
-  *           are done from 1 trigger)
-  *         - discontinuous mode (each conversion of oversampling ratio
-  *           needs a trigger)
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR2    TOVS           LL_ADC_SetOverSamplingDiscont
-  * @param  ADCx ADC instance
-  * @param  OverSamplingDiscont This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_OVS_REG_CONT
-  *         @arg @ref LL_ADC_OVS_REG_DISCONT
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
-{
-  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
-}
-
-/**
-  * @brief  Get ADC oversampling discontinuous mode (triggered mode)
-  *         on the selected ADC group.
-  * @note   Number of oversampled conversions are done either in:
-  *         - continuous mode (all conversions of oversampling ratio
-  *           are done from 1 trigger)
-  *         - discontinuous mode (each conversion of oversampling ratio
-  *           needs a trigger)
-  * @rmtoll CFGR2    TOVS           LL_ADC_GetOverSamplingDiscont
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_OVS_REG_CONT
-  *         @arg @ref LL_ADC_OVS_REG_DISCONT
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
-}
-
-/**
-  * @brief  Set ADC oversampling
-  * @note   This function set the 2 items of oversampling configuration:
-  *         - ratio
-  *         - shift
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
-  *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
-  * @param  ADCx ADC instance
-  * @param  Ratio This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_OVS_RATIO_2
-  *         @arg @ref LL_ADC_OVS_RATIO_4
-  *         @arg @ref LL_ADC_OVS_RATIO_8
-  *         @arg @ref LL_ADC_OVS_RATIO_16
-  *         @arg @ref LL_ADC_OVS_RATIO_32
-  *         @arg @ref LL_ADC_OVS_RATIO_64
-  *         @arg @ref LL_ADC_OVS_RATIO_128
-  *         @arg @ref LL_ADC_OVS_RATIO_256
-  * @param  Shift This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
-{
-  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
-}
-
-/**
-  * @brief  Get ADC oversampling ratio
-  * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
-  * @param  ADCx ADC instance
-  * @retval Ratio This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_OVS_RATIO_2
-  *         @arg @ref LL_ADC_OVS_RATIO_4
-  *         @arg @ref LL_ADC_OVS_RATIO_8
-  *         @arg @ref LL_ADC_OVS_RATIO_16
-  *         @arg @ref LL_ADC_OVS_RATIO_32
-  *         @arg @ref LL_ADC_OVS_RATIO_64
-  *         @arg @ref LL_ADC_OVS_RATIO_128
-  *         @arg @ref LL_ADC_OVS_RATIO_256
-*/
-__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
-}
-
-/**
-  * @brief  Get ADC oversampling shift
-  * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
-  * @param  ADCx ADC instance
-  * @retval Shift This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
-  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
-*/
-__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
-  * @{
-  */
-
-/**
-  * @brief  Enable ADC instance internal voltage regulator.
-  * @note   On this STM32 serie, there are three possibilities to enable
-  *         the voltage regulator:
-  *         - by enabling it manually
-  *           using function @ref LL_ADC_EnableInternalRegulator().
-  *         - by launching a calibration
-  *           using function @ref LL_ADC_StartCalibration().
-  *         - by enabling the ADC
-  *           using function @ref LL_ADC_Enable().
-  * @note   On this STM32 serie, after ADC internal voltage regulator enable,
-  *         a delay for ADC internal voltage regulator stabilization
-  *         is required before performing a ADC calibration or ADC enable.
-  *         Refer to device datasheet, parameter "tUP_LDO".
-  *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be ADC disabled.
-  * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
-{
-  /* Note: Write register with some additional bits forced to state reset     */
-  /*       instead of modifying only the selected bit for this function,      */
-  /*       to not interfere with bits with HW property "rs".                  */
-  MODIFY_REG(ADCx->CR,
-             ADC_CR_BITS_PROPERTY_RS,
-             ADC_CR_ADVREGEN);
-}
-
-/**
-  * @brief  Disable ADC internal voltage regulator.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be ADC disabled.
-  * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
-}
-
-/**
-  * @brief  Get the selected ADC instance internal voltage regulator state.
-  * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
-  * @param  ADCx ADC instance
-  * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN));
-}
-
-/**
-  * @brief  Enable the selected ADC instance.
-  * @note   On this STM32 serie, after ADC enable, a delay for 
-  *         ADC internal analog stabilization is required before performing a
-  *         ADC conversion start.
-  *         Refer to device datasheet, parameter tSTAB.
-  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
-  *         is enabled and when conversion clock is active.
-  *         (not only core clock: this ADC has a dual clock domain)
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
-  * @rmtoll CR       ADEN           LL_ADC_Enable
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
-{
-  /* Note: Write register with some additional bits forced to state reset     */
-  /*       instead of modifying only the selected bit for this function,      */
-  /*       to not interfere with bits with HW property "rs".                  */
-  MODIFY_REG(ADCx->CR,
-             ADC_CR_BITS_PROPERTY_RS,
-             ADC_CR_ADEN);
-}
-
-/**
-  * @brief  Disable the selected ADC instance.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be not disabled. Must be enabled without conversion on going
-  *         on group regular.
-  * @rmtoll CR       ADDIS          LL_ADC_Disable
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
-{
-  /* Note: Write register with some additional bits forced to state reset     */
-  /*       instead of modifying only the selected bit for this function,      */
-  /*       to not interfere with bits with HW property "rs".                  */
-  MODIFY_REG(ADCx->CR,
-             ADC_CR_BITS_PROPERTY_RS,
-             ADC_CR_ADDIS);
-}
-
-/**
-  * @brief  Get the selected ADC instance enable state.
-  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
-  *         is enabled and when conversion clock is active.
-  *         (not only core clock: this ADC has a dual clock domain)
-  * @rmtoll CR       ADEN           LL_ADC_IsEnabled
-  * @param  ADCx ADC instance
-  * @retval 0: ADC is disabled, 1: ADC is enabled.
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
-}
-
-/**
-  * @brief  Get the selected ADC instance disable state.
-  * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
-  * @param  ADCx ADC instance
-  * @retval 0: no ADC disable command on going.
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
-}
-
-/**
-  * @brief  Start ADC calibration in the mode single-ended
-  *         or differential (for devices with differential mode available).
-  * @note   On this STM32 serie, a minimum number of ADC clock cycles
-  *         are required between ADC end of calibration and ADC enable.
-  *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
-  * @note   In case of usage of ADC with DMA transfer:
-  *         On this STM32 serie, ADC DMA transfer request should be disabled
-  *         during calibration:
-  *         Calibration factor is available in data register
-  *         and also transfered by DMA.
-  *         To not insert ADC calibration factor among ADC conversion data
-  *         in array variable, DMA transfer must be disabled during
-  *         calibration.
-  *         (DMA transfer setting backup and disable before calibration,
-  *         DMA transfer setting restore after calibration.
-  *         Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
-  *         @ref LL_ADC_REG_SetDMATransfer() ).
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be ADC disabled.
-  * @rmtoll CR       ADCAL          LL_ADC_StartCalibration
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
-{
-  /* Note: Write register with some additional bits forced to state reset     */
-  /*       instead of modifying only the selected bit for this function,      */
-  /*       to not interfere with bits with HW property "rs".                  */
-  MODIFY_REG(ADCx->CR,
-             ADC_CR_BITS_PROPERTY_RS,
-             ADC_CR_ADCAL);
-}
-
-/**
-  * @brief  Get ADC calibration state.
-  * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
-  * @param  ADCx ADC instance
-  * @retval 0: calibration complete, 1: calibration in progress.
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
-  * @{
-  */
-
-/**
-  * @brief  Start ADC group regular conversion.
-  * @note   On this STM32 serie, this function is relevant for both 
-  *         internal trigger (SW start) and external trigger:
-  *         - If ADC trigger has been set to software start, ADC conversion
-  *           starts immediately.
-  *         - If ADC trigger has been set to external trigger, ADC conversion
-  *           will start at next trigger event (on the selected trigger edge)
-  *           following the ADC start conversion command.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be enabled without conversion on going on group regular,
-  *         without conversion stop command on going on group regular,
-  *         without ADC disable command on going.
-  * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
-{
-  /* Note: Write register with some additional bits forced to state reset     */
-  /*       instead of modifying only the selected bit for this function,      */
-  /*       to not interfere with bits with HW property "rs".                  */
-  MODIFY_REG(ADCx->CR,
-             ADC_CR_BITS_PROPERTY_RS,
-             ADC_CR_ADSTART);
-}
-
-/**
-  * @brief  Stop ADC group regular conversion.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be enabled with conversion on going on group regular,
-  *         without ADC disable command on going.
-  * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
-{
-  /* Note: Write register with some additional bits forced to state reset     */
-  /*       instead of modifying only the selected bit for this function,      */
-  /*       to not interfere with bits with HW property "rs".                  */
-  MODIFY_REG(ADCx->CR,
-             ADC_CR_BITS_PROPERTY_RS,
-             ADC_CR_ADSTP);
-}
-
-/**
-  * @brief  Get ADC group regular conversion state.
-  * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
-  * @param  ADCx ADC instance
-  * @retval 0: no conversion is on going on ADC group regular.
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
-}
-
-/**
-  * @brief  Get ADC group regular command of conversion stop state
-  * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
-  * @param  ADCx ADC instance
-  * @retval 0: no command of conversion stop is on going on ADC group regular.
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
-}
-
-/**
-  * @brief  Get ADC group regular conversion data, range fit for
-  *         all ADC configurations: all ADC resolutions and
-  *         all oversampling increased data width (for devices
-  *         with feature oversampling).
-  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData32
-  * @param  ADCx ADC instance
-  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
-}
-
-/**
-  * @brief  Get ADC group regular conversion data, range fit for
-  *         ADC resolution 12 bits.
-  * @note   For devices with feature oversampling: Oversampling
-  *         can increase data width, function for extended range
-  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
-  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData12
-  * @param  ADCx ADC instance
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
-{
-  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
-}
-
-/**
-  * @brief  Get ADC group regular conversion data, range fit for
-  *         ADC resolution 10 bits.
-  * @note   For devices with feature oversampling: Oversampling
-  *         can increase data width, function for extended range
-  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
-  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData10
-  * @param  ADCx ADC instance
-  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
-  */
-__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
-{
-  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
-}
-
-/**
-  * @brief  Get ADC group regular conversion data, range fit for
-  *         ADC resolution 8 bits.
-  * @note   For devices with feature oversampling: Oversampling
-  *         can increase data width, function for extended range
-  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
-  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData8
-  * @param  ADCx ADC instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
-{
-  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
-}
-
-/**
-  * @brief  Get ADC group regular conversion data, range fit for
-  *         ADC resolution 6 bits.
-  * @note   For devices with feature oversampling: Oversampling
-  *         can increase data width, function for extended range
-  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
-  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData6
-  * @param  ADCx ADC instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
-  */
-__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
-{
-  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
-  * @{
-  */
-
-/**
-  * @brief  Get flag ADC ready.
-  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
-  *         is enabled and when conversion clock is active.
-  *         (not only core clock: this ADC has a dual clock domain)
-  * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
-}
-
-/**
-  * @brief  Get flag ADC group regular end of unitary conversion.
-  * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
-}
-
-/**
-  * @brief  Get flag ADC group regular end of sequence conversions.
-  * @rmtoll ISR      EOSEQ          LL_ADC_IsActiveFlag_EOS
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
-}
-
-/**
-  * @brief  Get flag ADC group regular overrun.
-  * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
-}
-
-/**
-  * @brief  Get flag ADC group regular end of sampling phase.
-  * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
-}
-
-/**
-  * @brief  Get flag ADC analog watchdog 1 flag
-  * @rmtoll ISR      AWD            LL_ADC_IsActiveFlag_AWD1
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
-}
-
-/**
-  * @brief  Get flag ADC end of calibration.
-  * @rmtoll ISR      EOCAL          LL_ADC_IsActiveFlag_EOCAL
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL));
-}
-
-/**
-  * @brief  Clear flag ADC ready.
-  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
-  *         is enabled and when conversion clock is active.
-  *         (not only core clock: this ADC has a dual clock domain)
-  * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
-{
-  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
-}
-
-/**
-  * @brief  Clear flag ADC group regular end of unitary conversion.
-  * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
-{
-  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
-}
-
-/**
-  * @brief  Clear flag ADC group regular end of sequence conversions.
-  * @rmtoll ISR      EOSEQ          LL_ADC_ClearFlag_EOS
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
-{
-  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
-}
-
-/**
-  * @brief  Clear flag ADC group regular overrun.
-  * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
-{
-  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
-}
-
-/**
-  * @brief  Clear flag ADC group regular end of sampling phase.
-  * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
-{
-  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
-}
-
-/**
-  * @brief  Clear flag ADC analog watchdog 1.
-  * @rmtoll ISR      AWD            LL_ADC_ClearFlag_AWD1
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
-{
-  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
-}
-
-/**
-  * @brief  Clear flag ADC end of calibration.
-  * @rmtoll ISR      EOCAL          LL_ADC_ClearFlag_EOCAL
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
-{
-  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_IT_Management ADC IT management
-  * @{
-  */
-
-/**
-  * @brief  Enable ADC ready.
-  * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
-}
-
-/**
-  * @brief  Enable interruption ADC group regular end of unitary conversion.
-  * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
-}
-
-/**
-  * @brief  Enable interruption ADC group regular end of sequence conversions.
-  * @rmtoll IER      EOSEQIE        LL_ADC_EnableIT_EOS
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
-}
-
-/**
-  * @brief  Enable ADC group regular interruption overrun.
-  * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
-}
-
-/**
-  * @brief  Enable interruption ADC group regular end of sampling.
-  * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
-}
-
-/**
-  * @brief  Enable interruption ADC analog watchdog 1.
-  * @rmtoll IER      AWDIE          LL_ADC_EnableIT_AWD1
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
-}
-
-/**
-  * @brief  Enable interruption ADC end of calibration.
-  * @rmtoll IER      EOCALIE        LL_ADC_EnableIT_EOCAL
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
-}
-
-/**
-  * @brief  Disable interruption ADC ready.
-  * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
-}
-
-/**
-  * @brief  Disable interruption ADC group regular end of unitary conversion.
-  * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
-}
-
-/**
-  * @brief  Disable interruption ADC group regular end of sequence conversions.
-  * @rmtoll IER      EOSEQIE        LL_ADC_DisableIT_EOS
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
-}
-
-/**
-  * @brief  Disable interruption ADC group regular overrun.
-  * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
-}
-
-/**
-  * @brief  Disable interruption ADC group regular end of sampling.
-  * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
-}
-
-/**
-  * @brief  Disable interruption ADC analog watchdog 1.
-  * @rmtoll IER      AWDIE          LL_ADC_DisableIT_AWD1
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
-}
-
-/**
-  * @brief  Disable interruption ADC end of calibration.
-  * @rmtoll IER      EOCALIE        LL_ADC_DisableIT_EOCAL
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
-}
-
-/**
-  * @brief  Get state of interruption ADC ready
-  *         (0: interrupt disabled, 1: interrupt enabled).
-  * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
-}
-
-/**
-  * @brief  Get state of interruption ADC group regular end of unitary conversion
-  *         (0: interrupt disabled, 1: interrupt enabled).
-  * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
-}
-
-/**
-  * @brief  Get state of interruption ADC group regular end of sequence conversions
-  *         (0: interrupt disabled, 1: interrupt enabled).
-  * @rmtoll IER      EOSEQIE        LL_ADC_IsEnabledIT_EOS
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
-}
-
-/**
-  * @brief  Get state of interruption ADC group regular overrun
-  *         (0: interrupt disabled, 1: interrupt enabled).
-  * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
-}
-
-/**
-  * @brief  Get state of interruption ADC group regular end of sampling
-  *         (0: interrupt disabled, 1: interrupt enabled).
-  * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
-}
-
-/**
-  * @brief  Get state of interruption ADC analog watchdog 1
-  *         (0: interrupt disabled, 1: interrupt enabled).
-  * @rmtoll IER      AWDIE          LL_ADC_IsEnabledIT_AWD1
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
-}
-
-/**
-  * @brief  Get state of interruption ADC end of calibration
-  *         (0: interrupt disabled, 1: interrupt enabled).
-  * @rmtoll IER      EOCALIE        LL_ADC_IsEnabledIT_EOCAL
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL));
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization of some features of ADC common parameters and multimode */
-ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
-ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
-void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
-
-/* De-initialization of ADC instance */
-ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
-
-/* Initialization of some features of ADC instance */
-ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
-void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
-
-/* Initialization of some features of ADC instance and ADC group regular */
-ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
-void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* ADC1 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_ADC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
deleted file mode 100644
index aac198d92b..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
+++ /dev/null
@@ -1,1171 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_bus.h
-  * @author  MCD Application Team
-  * @brief   Header file of BUS LL module.
-
-  @verbatim
-                      ##### RCC Limitations #####
-  ==============================================================================
-    [..]
-      A delay between an RCC peripheral clock enable and the effective peripheral
-      enabling should be taken into account in order to manage the peripheral read/write
-      from/to registers.
-      (+) This delay depends on the peripheral mapping.
-        (++) AHB & APB peripherals, 1 dummy read is necessary
-
-    [..]
-      Workarounds:
-      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
-          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_BUS_H
-#define __STM32L0xx_LL_BUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @defgroup BUS_LL BUS
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
-  * @{
-  */
-
-/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
-  * @{
-  */
-#define LL_AHB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
-#define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHBENR_DMA1EN      /*!< DMA1 clock enable */
-#define LL_AHB1_GRP1_PERIPH_MIF            RCC_AHBENR_MIFEN       /*!< MIF clock enable */
-#define LL_AHB1_GRP1_PERIPH_SRAM           RCC_AHBSMENR_SRAMSMEN  /*!< Sleep Mode SRAM clock enable */
-#define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHBENR_CRCEN       /*!< CRC clock enable */
-#if defined(TSC)
-#define LL_AHB1_GRP1_PERIPH_TSC            RCC_AHBENR_TSCEN       /*!< TSC clock enable */
-#endif /*TSC*/
-#if defined(RNG)
-#define LL_AHB1_GRP1_PERIPH_RNG            RCC_AHBENR_RNGEN       /*!< RNG clock enable */
-#endif /*RNG*/
-#if defined(AES)
-#define LL_AHB1_GRP1_PERIPH_CRYP           RCC_AHBENR_CRYPEN      /*!< CRYP clock enable */
-#endif /*AES*/
-/**
-  * @}
-  */
-
-
-/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
-  * @{
-  */
-#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
-#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN     /*!< TIM2 clock enable */
-#if defined(TIM3)
-#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN     /*!< TIM3 clock enable */
-#endif
-#if defined(TIM6)
-#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN     /*!< TIM6 clock enable */
-#endif
-#if defined(TIM7)
-#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN     /*!< TIM7 clock enable */
-#endif
-#if defined(LCD)
-#define LL_APB1_GRP1_PERIPH_LCD            RCC_APB1ENR_LCDEN      /*!< LCD clock enable */
-#endif /*LCD*/
-#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN     /*!< WWDG clock enable */
-#if defined(SPI2)
-#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN     /*!< SPI2 clock enable */
-#endif
-#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN   /*!< USART2 clock enable */
-#define LL_APB1_GRP1_PERIPH_LPUART1        RCC_APB1ENR_LPUART1EN  /*!< LPUART1 clock enable */
-#if defined(USART4)
-#define LL_APB1_GRP1_PERIPH_USART4         RCC_APB1ENR_USART4EN   /*!< USART4 clock enable */
-#endif
-#if defined(USART5)
-#define LL_APB1_GRP1_PERIPH_USART5         RCC_APB1ENR_USART5EN   /*!< USART5 clock enable */
-#endif
-#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN     /*!< I2C1 clock enable */
-#if defined(I2C2)
-#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN     /*!< I2C2 clock enable */
-#endif
-#if defined(USB)
-#define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR_USBEN      /*!< USB clock enable */
-#endif /*USB*/
-#if defined(CRS)
-#define LL_APB1_GRP1_PERIPH_CRS            RCC_APB1ENR_CRSEN      /*!< CRS clock enable */
-#endif /*CRS*/
-#define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN      /*!< PWR clock enable */
-#if defined(DAC)
-#define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN      /*!< DAC clock enable */
-#endif
-#if defined(I2C3)
-#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN     /*!< I2C3 clock enable */
-#endif
-#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN   /*!< LPTIM1 clock enable */
-/**
-  * @}
-  */
-
-
-
-
-/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
-  * @{
-  */
-#define LL_APB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
-#define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APB2ENR_SYSCFGEN  /*!< SYSCFG clock enable */
-#define LL_APB2_GRP1_PERIPH_TIM21          RCC_APB2ENR_TIM21EN   /*!< TIM21 clock enable */
-#if defined(TIM22)
-#define LL_APB2_GRP1_PERIPH_TIM22          RCC_APB2ENR_TIM22EN   /*!< TIM22 clock enable */
-#endif
-#define LL_APB2_GRP1_PERIPH_FW             RCC_APB2ENR_FWEN      /*!< FireWall clock enable */
-#define LL_APB2_GRP1_PERIPH_ADC1           RCC_APB2ENR_ADC1EN    /*!< ADC1 clock enable */
-#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN    /*!< SPI1 clock enable */
-#if defined(USART1)
-#define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN  /*!< USART1 clock enable */
-#endif
-#define LL_APB2_GRP1_PERIPH_DBGMCU         RCC_APB2ENR_DBGMCUEN  /*!< DBGMCU clock enable */
-
-/**
-  * @}
-  */
-
-
-
-/** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH  IOP GRP1 PERIPH
-  * @{
-  */
-#define LL_IOP_GRP1_PERIPH_ALL             0xFFFFFFFFU
-#define LL_IOP_GRP1_PERIPH_GPIOA           RCC_IOPENR_GPIOAEN    /*!< GPIO port A control */
-#define LL_IOP_GRP1_PERIPH_GPIOB           RCC_IOPENR_GPIOBEN    /*!< GPIO port B control */
-#define LL_IOP_GRP1_PERIPH_GPIOC           RCC_IOPENR_GPIOCEN    /*!< GPIO port C control */
-#if defined(GPIOD)
-#define LL_IOP_GRP1_PERIPH_GPIOD           RCC_IOPENR_GPIODEN    /*!< GPIO port D control */
-#endif /*GPIOD*/
-#if defined(GPIOE)
-#define LL_IOP_GRP1_PERIPH_GPIOE           RCC_IOPENR_GPIOEEN    /*!< GPIO port H control */
-#endif /*GPIOE*/
-#if defined(GPIOH)
-#define LL_IOP_GRP1_PERIPH_GPIOH           RCC_IOPENR_GPIOHEN    /*!< GPIO port H control */
-#endif /*GPIOH*/
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
-  * @{
-  */
-
-/** @defgroup BUS_LL_EF_AHB1 AHB1
-  * @{
-  */
-
-/**
-  * @brief  Enable AHB1 peripherals clock.
-  * @rmtoll AHBENR      DMAEN        LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR      MIFEN        LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR      CRCEN        LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR      TSCEN        LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR      RNGEN        LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR      CRYPEN       LL_AHB1_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHBENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if AHB1 peripheral clock is enabled or not
-  * @rmtoll AHBENR      DMAEN        LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR      MIFEN        LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR      CRCEN        LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR      TSCEN        LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR      RNGEN        LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR      CRYPEN       LL_AHB1_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Disable AHB1 peripherals clock.
-  * @rmtoll AHBENR      DMAEN        LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR      MIFEN        LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR      CRCEN        LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR      TSCEN        LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR      RNGEN        LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR      CRYPEN       LL_AHB1_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHBENR, Periphs);
-}
-
-/**
-  * @brief  Force AHB1 peripherals reset.
-  * @rmtoll AHBRSTR      DMARST        LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      MIFRST        LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      CRCRST        LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      TSCRST        LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      RNGRST        LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      CRYPRST       LL_AHB1_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->AHBRSTR, Periphs);
-}
-
-/**
-  * @brief  Release AHB1 peripherals reset.
-  * @rmtoll AHBRSTR      DMARST        LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      MIFRST        LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      CRCRST        LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      TSCRST        LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      RNGRST        LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      CRYPRST       LL_AHB1_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHBRSTR, Periphs);
-}
-
-/**
-  * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHBSMENR     DMASMEN       LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBSMENR     MIFSMEN       LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBSMENR     SRAMSMEN      LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBSMENR     CRCSMEN       LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBSMENR     TSCSMEN       LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBSMENR     RNGSMEN       LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBSMENR     CRYPSMEN      LL_AHB1_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHBSMENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHBSMENR     DMASMEN       LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBSMENR     MIFSMEN       LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBSMENR     SRAMSMEN      LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBSMENR     CRCSMEN       LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBSMENR     TSCSMEN       LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBSMENR     RNGSMEN       LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBSMENR     CRYPSMEN      LL_AHB1_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHBSMENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_APB1 APB1
-  * @{
-  */
-
-/**
-  * @brief  Enable APB1 peripherals clock.
-  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     LCDEN         LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     LPUART1EN     LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     USART4EN      LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     USART5EN      LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     USBEN         LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     CRSEN         LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB1ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB1 peripheral clock is enabled or not
-  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     LCDEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     LPUART1EN     LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     USART4EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     USART5EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     USBEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     CRSEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->APB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Disable APB1 peripherals clock.
-  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     LCDEN         LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     LPUART1EN     LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     USART4EN      LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     USART5EN      LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     USBEN         LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     CRSEN         LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1ENR, Periphs);
-}
-
-/**
-  * @brief  Force APB1 peripherals reset.
-  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     LCDRST         LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     LPUART1RST     LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     USART4RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     USART5RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     USBRST         LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     CRSRST         LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
-  * @brief  Release APB1 peripherals reset.
-  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     LCDRST         LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     LPUART1RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     USART4RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     USART5RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     USBRST         LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     CRSRST         LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1SMENR    TIM2SMEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    TIM3SMEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    TIM6SMEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    TIM7SMEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    LCDSMEN       LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    WWDGSMEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    SPI2SMEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    USART2SMEN    LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    LPUART1SMEN   LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    USART4SMEN    LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    USART5SMEN    LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    I2C1SMEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    I2C2SMEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    USBSMEN       LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    CRSSMEN       LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    PWRSMEN       LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    DACSMEN       LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    I2C3SMEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1SMENR    LPTIM1SMEN    LL_APB1_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB1SMENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1SMENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1SMENR    TIM2SMEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    TIM3SMEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    TIM6SMEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    TIM7SMEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    LCDSMEN       LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    WWDGSMEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    SPI2SMEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    USART2SMEN    LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    LPUART1SMEN   LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    USART4SMEN    LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    USART5SMEN    LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    I2C1SMEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    I2C2SMEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    USBSMEN       LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    CRSSMEN       LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    PWRSMEN       LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    DACSMEN       LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    I2C3SMEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1SMENR    LPTIM1SMEN    LL_APB1_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1SMENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_APB2 APB2
-  * @{
-  */
-
-/**
-  * @brief  Enable APB2 peripherals clock.
-  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM21EN       LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM22EN       LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      FWEN          LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      ADCEN         LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      DBGEN         LL_APB2_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_FW
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB2ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB2 peripheral clock is enabled or not
-  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM21EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM22EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      FWEN          LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      ADCEN         LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      DBGEN         LL_APB2_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_FW
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Disable APB2 peripherals clock.
-  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM21EN       LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM22EN       LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      FWEN          LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      ADCEN         LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      DBGEN         LL_APB2_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_FW
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB2ENR, Periphs);
-}
-
-/**
-  * @brief  Force APB2 peripherals reset.
-  * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM21RST      LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM22RST      LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     ADCRST        LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     DBGRST        LL_APB2_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
-  * @brief  Release APB2 peripherals reset.
-  * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM21RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM22RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     ADCRST        LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     DBGRST        LL_APB2_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB2SMENR    SYSCFGSMEN    LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2SMENR    TIM21SMEN     LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2SMENR    TIM22SMEN     LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2SMENR    ADCSMEN       LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2SMENR    DBGSMEN       LL_APB2_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB2SMENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB2SMENR    SYSCFGSMEN    LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2SMENR    TIM21SMEN     LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2SMENR    TIM22SMEN     LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2SMENR    ADCSMEN       LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2SMENR    DBGSMEN       LL_APB2_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB2SMENR, Periphs);
-}
-
-/**
-  * @}
-  */
-/** @defgroup BUS_LL_EF_IOP IOP
-  * @{
-  */
-
-/**
-  * @brief  Enable IOP peripherals clock.
-  * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_EnableClock\n
-  *         IOPENR       GPIOBEN       LL_IOP_GRP1_EnableClock\n
-  *         IOPENR       GPIOCEN       LL_IOP_GRP1_EnableClock\n
-  *         IOPENR       GPIODEN       LL_IOP_GRP1_EnableClock\n
-  *         IOPENR       GPIOEEN       LL_IOP_GRP1_EnableClock\n
-  *         IOPENR       GPIOHEN       LL_IOP_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->IOPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->IOPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if IOP peripheral clock is enabled or not
-  * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_IsEnabledClock\n
-  *         IOPENR       GPIOBEN       LL_IOP_GRP1_IsEnabledClock\n
-  *         IOPENR       GPIOCEN       LL_IOP_GRP1_IsEnabledClock\n
-  *         IOPENR       GPIODEN       LL_IOP_GRP1_IsEnabledClock\n
-  *         IOPENR       GPIOEEN       LL_IOP_GRP1_IsEnabledClock\n
-  *         IOPENR       GPIOHEN       LL_IOP_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->IOPENR, Periphs) == (Periphs)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Disable IOP peripherals clock.
-  * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_DisableClock\n
-  *         IOPENR       GPIOBEN       LL_IOP_GRP1_DisableClock\n
-  *         IOPENR       GPIOCEN       LL_IOP_GRP1_DisableClock\n
-  *         IOPENR       GPIODEN       LL_IOP_GRP1_DisableClock\n
-  *         IOPENR       GPIOEEN       LL_IOP_GRP1_DisableClock\n
-  *         IOPENR       GPIOHEN       LL_IOP_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->IOPENR, Periphs);
-}
-
-/**
-  * @brief  Disable IOP peripherals clock.
-  * @rmtoll IOPRSTR      GPIOASMEN     LL_IOP_GRP1_ForceReset\n
-  *         IOPRSTR      GPIOBSMEN     LL_IOP_GRP1_ForceReset\n
-  *         IOPRSTR      GPIOCSMEN     LL_IOP_GRP1_ForceReset\n
-  *         IOPRSTR      GPIODSMEN     LL_IOP_GRP1_ForceReset\n
-  *         IOPRSTR      GPIOESMEN     LL_IOP_GRP1_ForceReset\n
-  *         IOPRSTR      GPIOHSMEN     LL_IOP_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_ALL
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->IOPRSTR, Periphs);
-}
-
-/**
-  * @brief  Release IOP peripherals reset.
-  * @rmtoll IOPRSTR      GPIOASMEN     LL_IOP_GRP1_ReleaseReset\n
-  *         IOPRSTR      GPIOBSMEN     LL_IOP_GRP1_ReleaseReset\n
-  *         IOPRSTR      GPIOCSMEN     LL_IOP_GRP1_ReleaseReset\n
-  *         IOPRSTR      GPIODSMEN     LL_IOP_GRP1_ReleaseReset\n
-  *         IOPRSTR      GPIOESMEN     LL_IOP_GRP1_ReleaseReset\n
-  *         IOPRSTR      GPIOHSMEN     LL_IOP_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_ALL
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->IOPRSTR, Periphs);
-}
-
-/**
-  * @brief  Enable IOP peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll IOPSMENR     GPIOARST      LL_IOP_GRP1_EnableClockSleep\n
-  *         IOPSMENR     GPIOBRST      LL_IOP_GRP1_EnableClockSleep\n
-  *         IOPSMENR     GPIOCRST      LL_IOP_GRP1_EnableClockSleep\n
-  *         IOPSMENR     GPIODRST      LL_IOP_GRP1_EnableClockSleep\n
-  *         IOPSMENR     GPIOERST      LL_IOP_GRP1_EnableClockSleep\n
-  *         IOPSMENR     GPIOHRST      LL_IOP_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_IOP_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->IOPSMENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable IOP peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll IOPSMENR     GPIOARST      LL_IOP_GRP1_DisableClockSleep\n
-  *         IOPSMENR     GPIOBRST      LL_IOP_GRP1_DisableClockSleep\n
-  *         IOPSMENR     GPIOCRST      LL_IOP_GRP1_DisableClockSleep\n
-  *         IOPSMENR     GPIODRST      LL_IOP_GRP1_DisableClockSleep\n
-  *         IOPSMENR     GPIOERST      LL_IOP_GRP1_DisableClockSleep\n
-  *         IOPSMENR     GPIOHRST      LL_IOP_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_IOP_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->IOPSMENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(RCC) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_BUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h
deleted file mode 100644
index c30ea8912e..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h
+++ /dev/null
@@ -1,705 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_comp.h
-  * @author  MCD Application Team
-  * @brief   Header file of COMP LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_COMP_H
-#define __STM32L0xx_LL_COMP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (COMP1) || defined (COMP2)
-
-/** @defgroup COMP_LL COMP
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup COMP_LL_Private_Constants COMP Private Constants
-  * @{
-  */
-
-/* COMP registers bits positions */
-#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) /* Value equivalent to POSITION_VAL(COMP_CSR_COMP1VALUE) */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  Structure definition of some features of COMP instance.
-  */
-typedef struct
-{
-  uint32_t PowerMode;                   /*!< Set comparator operating mode to adjust power and speed.
-                                             This parameter can be a value of @ref COMP_LL_EC_POWERMODE
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
-
-  uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
-                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
-
-  uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
-                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
-
-  uint32_t OutputPolarity;              /*!< Set comparator output polarity.
-                                             This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
-
-} LL_COMP_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
-  * @{
-  */
-
-/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
-  * @{
-  */
-#define LL_COMP_WINDOWMODE_DISABLE                 (0x00000000U)           /*!< Window mode disable: Comparators 1 and 2 are independent */
-#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_COMP1WM)      /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
-  * @{
-  */
-#define LL_COMP_POWERMODE_ULTRALOWPOWER   (0x00000000U)               /*!< COMP power mode to low speed (specific to COMP instance: COMP2) */
-#define LL_COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_COMP2SPEED)       /*!< COMP power mode to fast speed (specific to COMP instance: COMP2) */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
-  * @{
-  */
-#define LL_COMP_INPUT_PLUS_IO1          (0x00000000U)                                      /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA3 for COMP2) */
-#define LL_COMP_INPUT_PLUS_IO2          (COMP_CSR_COMP2INPSEL_0)                           /*!< Comparator input plus connected to IO2 (pin PB4 for COMP2) (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_PLUS_IO3          (COMP_CSR_COMP2INPSEL_1)                           /*!< Comparator input plus connected to IO3 (pin PA5 for COMP2) (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_PLUS_IO4          (COMP_CSR_COMP2INPSEL_0 | COMP_CSR_COMP2INPSEL_1)  /*!< Comparator input plus connected to IO4 (pin PB6 for COMP2) (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_PLUS_IO5          (COMP_CSR_COMP2INPSEL_2)                           /*!< Comparator input plus connected to IO5 (pin PB7 for COMP2) (specific to COMP instance: COMP2) */
-#if defined (STM32L011xx) || defined (STM32L021xx)
-#define LL_COMP_INPUT_PLUS_IO6          (COMP_CSR_COMP2INPSEL_2 | COMP_CSR_COMP2INPSEL_0)  /*!< Comparator input plus connected to IO6 (pin PA7 for COMP2) (specific to COMP instance: COMP2) (Available only on devices STM32L0 category 1) */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
-  * @{
-  */
-#define LL_COMP_INPUT_MINUS_1_4VREFINT  (COMP_CSR_COMP2INNSEL_2                                                  ) /*!< Comparator input minus connected to 1/4 VrefInt (specifity of COMP2 related to path to enable via SYSCFG: refer to comment in function @ref LL_COMP_SetInputMinus() ) (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_MINUS_1_2VREFINT  (COMP_CSR_COMP2INNSEL_2 |                          COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt (specifity of COMP2 related to path to enable via SYSCFG: refer to comment in function @ref LL_COMP_SetInputMinus() ) (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_MINUS_3_4VREFINT  (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_1                         ) /*!< Comparator input minus connected to 3/4 VrefInt (specifity of COMP2 related to path to enable via SYSCFG: refer to comment in function @ref LL_COMP_SetInputMinus() ) (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_MINUS_VREFINT     (0x00000000U)                                                    /*!< Comparator input minus connected to VrefInt (specifity of COMP2 related to path to enable via SYSCFG: refer to comment in function @ref LL_COMP_SetInputMinus() ) */
-#define LL_COMP_INPUT_MINUS_DAC1_CH1    (                         COMP_CSR_COMP2INNSEL_1                         ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)  */
-#define LL_COMP_INPUT_MINUS_DAC1_CH2    (                         COMP_CSR_COMP2INNSEL_1 | COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)  */
-#define LL_COMP_INPUT_MINUS_IO1         (                                                  COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2) */
-#define LL_COMP_INPUT_MINUS_IO2         (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_1 | COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to IO2 (pin PB3 for COMP2) (specific to COMP instance: COMP2) */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_OUTPUT_SELECTION_LPTIM Comparator output - Output selection specific to LPTIM peripheral
-  * @{
-  */
-#define LL_COMP_OUTPUT_LPTIM1_IN1_COMP1         (COMP_CSR_COMP1LPTIM1IN1)                                                   /*!< COMP output connected to TIM2 input capture 4 */
-#define LL_COMP_OUTPUT_LPTIM1_IN1_COMP2         (COMP_CSR_COMP2LPTIM1IN1)                                                   /*!< COMP output connected to TIM2 input capture 4 */
-#define LL_COMP_OUTPUT_LPTIM1_IN2_COMP2         (COMP_CSR_COMP2LPTIM1IN2)                                                   /*!< COMP output connected to TIM2 input capture 4 */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
-  * @{
-  */
-#define LL_COMP_OUTPUTPOL_NONINVERTED   (0x00000000U)            /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
-#define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CSR_COMP1POLARITY) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
-  * @{
-  */
-#define LL_COMP_OUTPUT_LEVEL_LOW        (0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
-#define LL_COMP_OUTPUT_LEVEL_HIGH       (0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
-  * @note   Only COMP IP HW delays are defined in COMP LL driver driver,
-  *         not timeout values.
-  *         For details on delays values, refer to descriptions in source code
-  *         above each literal definition.
-  * @{
-  */
-
-/* Delay for comparator startup time.                                         */
-/* Note: Delay required to reach propagation delay specification.             */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "tSTART").                                                       */
-/* Unit: us                                                                   */
-#define LL_COMP_DELAY_STARTUP_US          (25U)  /*!< Delay for COMP startup time */
-
-/* Delay for comparator voltage scaler stabilization time                     */
-/* (voltage from VrefInt, delay based on VrefInt startup time).               */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "TVREFINT").                                                     */
-/* Unit: us                                                                   */
-#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US (3000U)  /*!< Delay for COMP voltage scaler stabilization time */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
-  * @{
-  */
-/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
-  * @{
-  */
-
-/**
-  * @brief  Write a value in COMP register
-  * @param  __INSTANCE__ comparator instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in COMP register
-  * @param  __INSTANCE__ comparator instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to select the COMP common instance
-  *         to which is belonging the selected COMP instance.
-  * @note   COMP common register instance can be used to
-  *         set parameters common to several COMP instances.
-  *         Refer to functions having argument "COMPxy_COMMON" as parameter.
-  * @param  __COMPx__ COMP instance
-  * @retval COMP common instance or value "0" if there is no COMP common instance.
-  */
-#define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
-  (COMP12_COMMON)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
-  * @{
-  */
-
-/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
-  * @{
-  */
-
-/**
-  * @brief  Set window mode of a pair of comparators instances
-  *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
-  * @rmtoll COMP1_CSR COMP1WM       LL_COMP_SetCommonWindowMode
-  * @param  COMPxy_COMMON Comparator common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
-  * @param  WindowMode This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
-  *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
-{
-  MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_COMP1WM, WindowMode);
-}
-
-/**
-  * @brief  Get window mode of a pair of comparators instances
-  *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
-  * @rmtoll COMP1_CSR COMP1WM       LL_COMP_GetCommonWindowMode
-  * @param  COMPxy_COMMON Comparator common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
-  *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-  */
-__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
-{
-  return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_COMP1WM));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
-  * @{
-  */
-
-/**
-  * @brief  Set comparator instance operating mode to adjust power and speed.
-  * @rmtoll COMP2_CSR COMP2SPEED    LL_COMP_SetPowerMode
-  * @param  COMPx Comparator instance
-  * @param  PowerMode This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED   (1)
-  *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1)
-  *         
-  *         (1) Available only on COMP instance: COMP2.
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
-{
-  MODIFY_REG(COMPx->CSR, COMP_CSR_COMP2SPEED, PowerMode);
-}
-
-/**
-  * @brief  Get comparator instance operating mode to adjust power and speed.
-  * @note  Available only on COMP instance: COMP2.
-  * @rmtoll COMP2_CSR COMP2SPEED    LL_COMP_GetPowerMode\n
-  * @param  COMPx Comparator instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED   (1)
-  *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1)
-  *         
-  *         (1) Available only on COMP instance: COMP2.
-  */
-__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
-{
-  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMP2SPEED));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
-  * @{
-  */
-
-/**
-  * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).
-  * @note   This function shall only be used for COMP2.
-  *         For setting COMP1 input it is recommended to use LL_COMP_SetInputMinus()
-  *         Plus (non-inverting) input is not configurable on COMP1.
-  *         Using this function for COMP1 will corrupt COMP1WM register
-  * @note   On this STM32 serie, specificity if using COMP instance COMP2
-  *         with COMP input based on VrefInt (VrefInt or subdivision
-  *         of VrefInt): scaler bridge is based on VrefInt and requires
-  *         to enable path from VrefInt (refer to literal
-  *         SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP).
-  * @rmtoll COMP2_CSR COMP2INNSEL   LL_COMP_ConfigInputs\n
-  *         COMP2_CSR COMP2INPSEL   LL_COMP_ConfigInputs
-  * @param  COMPx Comparator instance
-  * @param  InputMinus This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
-  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
-  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
-  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
-  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
-  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
-  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
-  *         @arg @ref LL_COMP_INPUT_MINUS_IO2
-  * @param  InputPlus This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO1 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO2 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO4 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO5 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO6 (1)(2)
-  *
-  *         (1) Available only on COMP instance: COMP2.
-  *         (2) Available only on devices STM32L0 category 1.
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
-{
-  MODIFY_REG(COMPx->CSR,
-             COMP_CSR_COMP2INNSEL | COMP_CSR_COMP2INPSEL,
-             InputMinus | InputPlus);
-}
-
-/**
-  * @brief  Set comparator input plus (non-inverting).
-  * @note   Only COMP2 allows to set the input plus (non-inverting).
-  *         For COMP1 it is always PA1 IO, except when Windows Mode is selected.
-  * @rmtoll COMP2_CSR COMP2INPSEL    LL_COMP_SetInputPlus
-  * @param  COMPx Comparator instance
-  * @param  InputPlus This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO1 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO2 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO4 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO5 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO6 (1)(2)
-  *
-  *         (1) Available only on COMP instance: COMP2.
-  *         (2) Available only on devices STM32L0 category 1.
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
-{
-  MODIFY_REG(COMPx->CSR, COMP_CSR_COMP2INPSEL, InputPlus);
-}
-
-/**
-  * @brief  Get comparator input plus (non-inverting).
-  * @note   Only COMP2 allows to set the input plus (non-inverting).
-  *         For COMP1 it is always PA1 IO, except when Windows Mode is selected.
-  * @rmtoll COMP2_CSR COMP2INPSEL    LL_COMP_GetInputPlus
-  * @param  COMPx Comparator instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO1 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO2 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO4 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO5 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO6 (1)(2)
-  *
-  *         (1) Available only on COMP instance: COMP2.
-  *         (2) Available only on devices STM32L0 category 1.
-  */
-__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
-{
-  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMP2INPSEL));
-}
-
-/**
-  * @brief  Set comparator input minus (inverting).
-  * @note   In case of comparator input selected to be connected to IO:
-  *         GPIO pins are specific to each comparator instance.
-  *         Refer to description of parameters or to reference manual.
-  * @note   On this STM32 serie, specificity if using COMP instance COMP2
-  *         with COMP input based on VrefInt (VrefInt or subdivision
-  *         of VrefInt): scaler bridge is based on VrefInt and requires
-  *         to enable path from VrefInt (refer to literal
-  *         SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP).
-  * @rmtoll COMP1_CSR COMP1INNSEL    LL_COMP_SetInputMinus\n
-  *         COMP2_CSR COMP2INNSEL    LL_COMP_SetInputMinus
-  * @param  COMPx Comparator instance
-  * @param  InputMinus This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
-  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
-  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
-  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
-  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT (*)
-  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT (*)
-  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT (*)
-  *         @arg @ref LL_COMP_INPUT_MINUS_IO2        (*)
-  *         
-  *         (*) Available only on COMP instance: COMP2.
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
-{
-  MODIFY_REG(COMPx->CSR, COMP_CSR_COMP2INNSEL, InputMinus);
-}
-
-/**
-  * @brief  Get comparator input minus (inverting).
-  * @note   In case of comparator input selected to be connected to IO:
-  *         GPIO pins are specific to each comparator instance.
-  *         Refer to description of parameters or to reference manual.
-  * @rmtoll COMP1_CSR COMP1INNSEL   LL_COMP_GetInputMinus\n
-  *         COMP2_CSR COMP2INNSEL   LL_COMP_GetInputMinus
-  * @param  COMPx Comparator instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
-  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
-  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
-  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
-  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT (*)
-  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT (*)
-  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT (*)
-  *         @arg @ref LL_COMP_INPUT_MINUS_IO2        (*)
-  *         
-  *         (*) Available only on COMP instance: COMP2.
-  */
-__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
-{
-  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMP2INNSEL));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
-  * @{
-  */
-
-/**
-  * @brief  Set comparator output LPTIM.
-  * @rmtoll COMP1_CSR COMP1LPTIMIN1 LL_COMP_SetOutputLPTIM\n
-  *         COMP2_CSR COMP2LPTIMIN1 LL_COMP_SetOutputLPTIM\n
-  *         COMP2_CSR COMP2LPTIMIN2 LL_COMP_SetOutputLPTIM
-  * @param  COMPx Comparator instance
-  * @param  OutputLptim This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_OUTPUT_LPTIM1_IN1_COMP1 (*)
-  *         @arg @ref LL_COMP_OUTPUT_LPTIM1_IN1_COMP2 (**)
-  *         @arg @ref LL_COMP_OUTPUT_LPTIM1_IN2_COMP2 (**)
-  *         
-  *         (*)  Available only on COMP instance: COMP1.\n
-  *         (**) Available only on COMP instance: COMP2.
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_SetOutputLPTIM(COMP_TypeDef *COMPx, uint32_t OutputLptim)
-{
-  MODIFY_REG(COMPx->CSR, (COMP_CSR_COMP1LPTIM1IN1 | COMP_CSR_COMP2LPTIM1IN1 | COMP_CSR_COMP2LPTIM1IN2), OutputLptim);
-}
-
-/**
-  * @brief  Get comparator output LPTIM.
-  * @rmtoll COMP1_CSR COMP1LPTIMIN1 LL_COMP_GetOutputLPTIM\n
-  *         COMP2_CSR COMP2LPTIMIN1 LL_COMP_GetOutputLPTIM\n
-  *         COMP2_CSR COMP2LPTIMIN2 LL_COMP_GetOutputLPTIM
-  * @param  COMPx Comparator instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_OUTPUT_LPTIM1_IN1_COMP1 (*)
-  *         @arg @ref LL_COMP_OUTPUT_LPTIM1_IN1_COMP2 (**)
-  *         @arg @ref LL_COMP_OUTPUT_LPTIM1_IN2_COMP2 (**)
-  *         
-  *         (*)  Available only on COMP instance: COMP1.\n
-  *         (**) Available only on COMP instance: COMP2.
-  */
-__STATIC_INLINE uint32_t LL_COMP_GetOutputLPTIM(COMP_TypeDef *COMPx)
-{
-  return (uint32_t)(READ_BIT(COMPx->CSR, (COMP_CSR_COMP1LPTIM1IN1 | COMP_CSR_COMP2LPTIM1IN1 | COMP_CSR_COMP2LPTIM1IN2)));
-}
-
-/**
-  * @brief  Set comparator instance output polarity.
-  * @rmtoll COMP     COMP1POLARITY  LL_COMP_SetOutputPolarity
-  * @param  COMPx Comparator instance
-  * @param  OutputPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
-  *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
-{
-  MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxPOLARITY, OutputPolarity);
-}
-
-/**
-  * @brief  Get comparator instance output polarity.
-  * @rmtoll COMP     COMP1POLARITY  LL_COMP_GetOutputPolarity
-  * @param  COMPx Comparator instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
-  *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
-  */
-__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
-{
-  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxPOLARITY));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
-  * @{
-  */
-
-/**
-  * @brief  Enable comparator instance.
-  * @note   After enable from off state, comparator requires a delay
-  *         to reach reach propagation delay specification.
-  *         Refer to device datasheet, parameter "tSTART".
-  * @rmtoll COMP1_CSR COMP1EN       LL_COMP_Enable\n
-  *         COMP2_CSR COMP2EN       LL_COMP_Enable
-  * @param  COMPx Comparator instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
-{
-  SET_BIT(COMPx->CSR, COMP_CSR_COMPxEN);
-}
-
-/**
-  * @brief  Disable comparator instance.
-  * @rmtoll COMP1_CSR COMP1EN       LL_COMP_Disable\n
-  *         COMP2_CSR COMP2EN       LL_COMP_Disable
-  * @param  COMPx Comparator instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
-{
-  CLEAR_BIT(COMPx->CSR, COMP_CSR_COMPxEN);
-}
-
-/**
-  * @brief  Get comparator enable state
-  *         (0: COMP is disabled, 1: COMP is enabled)
-  * @rmtoll COMP1_CSR COMP1EN        LL_COMP_IsEnabled\n
-  *         COMP2_CSR COMP2EN        LL_COMP_IsEnabled
-  * @param  COMPx Comparator instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
-{
-  return (READ_BIT(COMPx->CSR, COMP_CSR_COMPxEN) == (COMP_CSR_COMPxEN));
-}
-
-/**
-  * @brief  Lock comparator instance.
-  * @note   Once locked, comparator configuration can be accessed in read-only.
-  * @note   The only way to unlock the comparator is a device hardware reset.
-  * @rmtoll COMP1_CSR COMP1LOCK     LL_COMP_Lock\n
-  *         COMP2_CSR COMP2LOCK     LL_COMP_Lock
-  * @param  COMPx Comparator instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
-{
-  SET_BIT(COMPx->CSR, COMP_CSR_COMPxLOCK);
-}
-
-/**
-  * @brief  Get comparator lock state
-  *         (0: COMP is unlocked, 1: COMP is locked).
-  * @note   Once locked, comparator configuration can be accessed in read-only.
-  * @note   The only way to unlock the comparator is a device hardware reset.
-  * @rmtoll COMP1_CSR COMP1LOCK     LL_COMP_IsLocked\n
-  *         COMP2_CSR COMP2LOCK     LL_COMP_IsLocked
-  * @param  COMPx Comparator instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
-{
-  return (READ_BIT(COMPx->CSR, COMP_CSR_COMPxLOCK) == (COMP_CSR_COMPxLOCK));
-}
-
-/**
-  * @brief  Read comparator instance output level.
-  * @note   The comparator output level depends on the selected polarity
-  *         (Refer to function @ref LL_COMP_SetOutputPolarity()).
-  *         If the comparator polarity is not inverted:
-  *          - Comparator output is low when the input plus
-  *            is at a lower voltage than the input minus
-  *          - Comparator output is high when the input plus
-  *            is at a higher voltage than the input minus
-  *         If the comparator polarity is inverted:
-  *          - Comparator output is high when the input plus
-  *            is at a lower voltage than the input minus
-  *          - Comparator output is low when the input plus
-  *            is at a higher voltage than the input minus
-  * @rmtoll COMP1_CSR COMP1VALUE    LL_COMP_ReadOutputLevel\n
-  *         COMP2_CSR COMP2VALUE    LL_COMP_ReadOutputLevel
-  * @param  COMPx Comparator instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
-  *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
-  */
-__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
-{
-  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxOUTVALUE)
-                    >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
-ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
-void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* COMP1 || COMP2 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_COMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h
deleted file mode 100644
index 4cb6f3b9f3..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h
+++ /dev/null
@@ -1,590 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_cortex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CORTEX LL module.
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL CORTEX driver contains a set of generic APIs that can be
-    used by user:
-      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
-          functions
-      (+) Low power mode configuration (SCB register of Cortex-MCU)
-      (+) MPU API to configure and enable regions
-      (+) API to access to MCU info (CPUID register)
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_CORTEX_H
-#define __STM32L0xx_LL_CORTEX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX_LL CORTEX
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-
-/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
-  * @{
-  */
-#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     (0x00000000U)                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
-#define LL_SYSTICK_CLKSOURCE_HCLK          (SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
-/**
-  * @}
-  */
-
-#if __MPU_PRESENT
-
-/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
-  * @{
-  */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     (0x00000000U)                            /*!< Disable NMI and privileged SW access */
-#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
-#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
-  * @{
-  */
-#define LL_MPU_REGION_NUMBER0              (0x00U) /*!< REGION Number 0 */
-#define LL_MPU_REGION_NUMBER1              (0x01U) /*!< REGION Number 1 */
-#define LL_MPU_REGION_NUMBER2              (0x02U) /*!< REGION Number 2 */
-#define LL_MPU_REGION_NUMBER3              (0x03U) /*!< REGION Number 3 */
-#define LL_MPU_REGION_NUMBER4              (0x04U) /*!< REGION Number 4 */
-#define LL_MPU_REGION_NUMBER5              (0x05U) /*!< REGION Number 5 */
-#define LL_MPU_REGION_NUMBER6              (0x06U) /*!< REGION Number 6 */
-#define LL_MPU_REGION_NUMBER7              (0x07U) /*!< REGION Number 7 */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
-  * @{
-  */
-#define LL_MPU_REGION_SIZE_32B             ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64B             ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128B            ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256B            ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512B            ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1KB             ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2KB             ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4KB             ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8KB             ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16KB            ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32KB            ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64KB            ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128KB           ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256KB           ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512KB           ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1MB             ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2MB             ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4MB             ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8MB             ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16MB            ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32MB            ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64MB            ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128MB           ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256MB           ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512MB           ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1GB             ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2GB             ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4GB             ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
-  * @{
-  */
-#define LL_MPU_REGION_NO_ACCESS            ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/
-#define LL_MPU_REGION_PRIV_RW              ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/
-#define LL_MPU_REGION_PRIV_RW_URO          ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */
-#define LL_MPU_REGION_FULL_ACCESS          ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */
-#define LL_MPU_REGION_PRIV_RO              ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/
-#define LL_MPU_REGION_PRIV_RO_URO          ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
-  * @{
-  */
-#define LL_MPU_TEX_LEVEL0                  ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */
-#define LL_MPU_TEX_LEVEL1                  ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */
-#define LL_MPU_TEX_LEVEL2                  ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */
-#define LL_MPU_TEX_LEVEL4                  ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
-  * @{
-  */
-#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   (0x00U) /*!< Instruction fetches enabled */
-#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
-#define LL_MPU_ACCESS_NOT_SHAREABLE        (0x00U) /*!< Not Shareable memory attribute */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
-#define LL_MPU_ACCESS_NOT_CACHEABLE        (0x00U) /*!< Not Cacheable memory attribute */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
-#define LL_MPU_ACCESS_NOT_BUFFERABLE       (0x00U) /*!< Not Bufferable memory attribute */
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-
-/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
-  * @{
-  */
-
-/**
-  * @brief  This function checks if the Systick counter flag is active or not.
-  * @note   It can be used in timeout function on application side.
-  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
-{
-  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
-}
-
-/**
-  * @brief  Configures the SysTick clock source
-  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
-{
-  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
-  {
-    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-  }
-  else
-  {
-    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-  }
-}
-
-/**
-  * @brief  Get the SysTick clock source
-  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
-{
-  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-}
-
-/**
-  * @brief  Enable SysTick exception request
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
-{
-  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief  Disable SysTick exception request
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
-{
-  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
-{
-  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
-  * @{
-  */
-
-/**
-  * @brief  Processor uses sleep as its low power mode
-  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableSleep(void)
-{
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
-  * @brief  Processor uses deep sleep as its low power mode
-  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
-{
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
-  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
-  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
-  *         empty main application.
-  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
-{
-  /* Set SLEEPONEXIT bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief  Do not sleep when returning to Thread mode.
-  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
-{
-  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
-  *         processor.
-  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
-{
-  /* Set SEVEONPEND bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
-  *         excluded
-  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
-{
-  /* Clear SEVEONPEND bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
-  * @{
-  */
-
-/**
-  * @brief  Get Implementer code
-  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
-  * @retval Value should be equal to 0x41 for ARM
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
-}
-
-/**
-  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
-  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
-  * @retval Value between 0 and 255 (0x0: revision 0)
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
-}
-
-/**
-  * @brief  Get Architecture number 
-  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetArchitecture
-  * @retval Value should be equal to 0xC for Cortex-M0+ devices
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
-}
-
-/**
-  * @brief  Get Part number
-  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
-  * @retval Value should be equal to 0xC60 for Cortex-M0+
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
-}
-
-/**
-  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
-  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
-  * @retval Value between 0 and 255 (0x1: patch 1)
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
-}
-
-/**
-  * @}
-  */
-
-#if __MPU_PRESENT
-/** @defgroup CORTEX_LL_EF_MPU MPU
-  * @{
-  */
-
-/**
-  * @brief  Enable MPU with input options
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
-  * @param  Options This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
-  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
-  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
-  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
-{
-  /* Enable the MPU*/
-  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
-  /* Ensure MPU settings take effects */
-  __DSB();
-  /* Sequence instruction fetches using update settings */
-  __ISB();
-}
-
-/**
-  * @brief  Disable MPU
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_Disable(void)
-{
-  /* Make sure outstanding transfers are done */
-  __DMB();
-  /* Disable MPU*/
-  WRITE_REG(MPU->CTRL, 0U);
-}
-
-/**
-  * @brief  Check if MPU is enabled or not
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
-{
-  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
-}
-
-/**
-  * @brief  Enable a MPU region
-  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Enable the MPU region */
-  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
-  * @brief  Configure and enable a region
-  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
-  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
-  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
-  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
-  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
-  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  * @param  Address Value of region base address
-  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
-  * @param  Attributes This parameter can be a combination of the following values:
-  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
-  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
-  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
-  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
-  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
-  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
-  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
-  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
-  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
-  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
-  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
-  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
-  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Set base address */
-  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
-  /* Configure MPU */
-  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
-}
-
-/**
-  * @brief  Disable a region
-  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
-  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Disable the MPU region */
-  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
-  * @}
-  */
-
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_CORTEX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h
deleted file mode 100644
index a16c910a83..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h
+++ /dev/null
@@ -1,464 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_crc.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_LL_CRC_H
-#define STM32L0xx_LL_CRC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined(CRC)
-
-/** @defgroup CRC_LL CRC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
-  * @{
-  */
-
-/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
-  * @{
-  */
-#define LL_CRC_POLYLENGTH_32B              0x00000000U                              /*!< 32 bits Polynomial size */
-#define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */
-#define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */
-#define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
-  * @{
-  */
-#define LL_CRC_INDATA_REVERSE_NONE         0x00000000U                              /*!< Input Data bit order not affected */
-#define LL_CRC_INDATA_REVERSE_BYTE         CRC_CR_REV_IN_0                          /*!< Input Data bit reversal done by byte */
-#define LL_CRC_INDATA_REVERSE_HALFWORD     CRC_CR_REV_IN_1                          /*!< Input Data bit reversal done by half-word */
-#define LL_CRC_INDATA_REVERSE_WORD         (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)      /*!< Input Data bit reversal done by word */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
-  * @{
-  */
-#define LL_CRC_OUTDATA_REVERSE_NONE        0x00000000U                               /*!< Output Data bit order not affected */
-#define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT                            /*!< Output Data bit reversal done by bit */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_LL_EC_Default_Polynomial_Value    Default CRC generating polynomial value
-  * @brief    Normal representation of this polynomial value is
-  *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
-  * @{
-  */
-#define LL_CRC_DEFAULT_CRC32_POLY          0x04C11DB7U                               /*!< Default CRC generating polynomial value */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value
-  * @{
-  */
-#define LL_CRC_DEFAULT_CRC_INITVALUE       0xFFFFFFFFU                               /*!< Default CRC computation initialization value */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
-  * @{
-  */
-
-/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in CRC register
-  * @param  __INSTANCE__ CRC Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
-
-/**
-  * @brief  Read a value in CRC register
-  * @param  __INSTANCE__ CRC Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
-  * @{
-  */
-
-/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  Reset the CRC calculation unit.
-  * @note   If Programmable Initial CRC value feature
-  *         is available, also set the Data Register to the value stored in the
-  *         CRC_INIT register, otherwise, reset Data Register to its default value.
-  * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
-  * @param  CRCx CRC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
-{
-  SET_BIT(CRCx->CR, CRC_CR_RESET);
-}
-
-/**
-  * @brief  Configure size of the polynomial.
-  * @rmtoll CR           POLYSIZE      LL_CRC_SetPolynomialSize
-  * @param  CRCx CRC Instance
-  * @param  PolySize This parameter can be one of the following values:
-  *         @arg @ref LL_CRC_POLYLENGTH_32B
-  *         @arg @ref LL_CRC_POLYLENGTH_16B
-  *         @arg @ref LL_CRC_POLYLENGTH_8B
-  *         @arg @ref LL_CRC_POLYLENGTH_7B
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
-{
-  MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
-}
-
-/**
-  * @brief  Return size of the polynomial.
-  * @rmtoll CR           POLYSIZE      LL_CRC_GetPolynomialSize
-  * @param  CRCx CRC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_CRC_POLYLENGTH_32B
-  *         @arg @ref LL_CRC_POLYLENGTH_16B
-  *         @arg @ref LL_CRC_POLYLENGTH_8B
-  *         @arg @ref LL_CRC_POLYLENGTH_7B
-  */
-__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
-{
-  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
-}
-
-/**
-  * @brief  Configure the reversal of the bit order of the input data
-  * @rmtoll CR           REV_IN        LL_CRC_SetInputDataReverseMode
-  * @param  CRCx CRC Instance
-  * @param  ReverseMode This parameter can be one of the following values:
-  *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
-  *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
-  *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
-  *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
-{
-  MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
-}
-
-/**
-  * @brief  Return type of reversal for input data bit order
-  * @rmtoll CR           REV_IN        LL_CRC_GetInputDataReverseMode
-  * @param  CRCx CRC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
-  *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
-  *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
-  *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
-  */
-__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
-{
-  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
-}
-
-/**
-  * @brief  Configure the reversal of the bit order of the Output data
-  * @rmtoll CR           REV_OUT       LL_CRC_SetOutputDataReverseMode
-  * @param  CRCx CRC Instance
-  * @param  ReverseMode This parameter can be one of the following values:
-  *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
-  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
-{
-  MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
-}
-
-/**
-  * @brief  Configure the reversal of the bit order of the Output data
-  * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode
-  * @param  CRCx CRC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
-  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
-  */
-__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
-{
-  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
-}
-
-/**
-  * @brief  Initialize the Programmable initial CRC value.
-  * @note   If the CRC size is less than 32 bits, the least significant bits
-  *         are used to write the correct value
-  * @note   LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
-  * @rmtoll INIT         INIT          LL_CRC_SetInitialData
-  * @param  CRCx CRC Instance
-  * @param  InitCrc Value to be programmed in Programmable initial CRC value register
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
-{
-  WRITE_REG(CRCx->INIT, InitCrc);
-}
-
-/**
-  * @brief  Return current Initial CRC value.
-  * @note   If the CRC size is less than 32 bits, the least significant bits
-  *         are used to read the correct value
-  * @rmtoll INIT         INIT          LL_CRC_GetInitialData
-  * @param  CRCx CRC Instance
-  * @retval Value programmed in Programmable initial CRC value register
-  */
-__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
-{
-  return (uint32_t)(READ_REG(CRCx->INIT));
-}
-
-/**
-  * @brief  Initialize the Programmable polynomial value
-  *         (coefficients of the polynomial to be used for CRC calculation).
-  * @note   LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
-  * @note   Please check Reference Manual and existing Errata Sheets,
-  *         regarding possible limitations for Polynomial values usage.
-  *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
-  * @rmtoll POL          POL           LL_CRC_SetPolynomialCoef
-  * @param  CRCx CRC Instance
-  * @param  PolynomCoef Value to be programmed in Programmable Polynomial value register
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
-{
-  WRITE_REG(CRCx->POL, PolynomCoef);
-}
-
-/**
-  * @brief  Return current Programmable polynomial value
-  * @note   Please check Reference Manual and existing Errata Sheets,
-  *         regarding possible limitations for Polynomial values usage.
-  *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
-  * @rmtoll POL          POL           LL_CRC_GetPolynomialCoef
-  * @param  CRCx CRC Instance
-  * @retval Value programmed in Programmable Polynomial value register
-  */
-__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
-{
-  return (uint32_t)(READ_REG(CRCx->POL));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Write given 32-bit data to the CRC calculator
-  * @rmtoll DR           DR            LL_CRC_FeedData32
-  * @param  CRCx CRC Instance
-  * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
-{
-  WRITE_REG(CRCx->DR, InData);
-}
-
-/**
-  * @brief  Write given 16-bit data to the CRC calculator
-  * @rmtoll DR           DR            LL_CRC_FeedData16
-  * @param  CRCx CRC Instance
-  * @param  InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
-{
-  __IO uint16_t *pReg;
-
-  pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR);                             /* Derogation MisraC2012 R.11.5 */
-  *pReg = InData;
-}
-
-/**
-  * @brief  Write given 8-bit data to the CRC calculator
-  * @rmtoll DR           DR            LL_CRC_FeedData8
-  * @param  CRCx CRC Instance
-  * @param  InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
-{
-  *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
-}
-
-/**
-  * @brief  Return current CRC calculation result. 32 bits value is returned.
-  * @rmtoll DR           DR            LL_CRC_ReadData32
-  * @param  CRCx CRC Instance
-  * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
-  */
-__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
-{
-  return (uint32_t)(READ_REG(CRCx->DR));
-}
-
-/**
-  * @brief  Return current CRC calculation result. 16 bits value is returned.
-  * @note   This function is expected to be used in a 16 bits CRC polynomial size context.
-  * @rmtoll DR           DR            LL_CRC_ReadData16
-  * @param  CRCx CRC Instance
-  * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
-  */
-__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
-{
-  return (uint16_t)READ_REG(CRCx->DR);
-}
-
-/**
-  * @brief  Return current CRC calculation result. 8 bits value is returned.
-  * @note   This function is expected to be used in a 8 bits CRC polynomial size context.
-  * @rmtoll DR           DR            LL_CRC_ReadData8
-  * @param  CRCx CRC Instance
-  * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
-  */
-__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
-{
-  return (uint8_t)READ_REG(CRCx->DR);
-}
-
-/**
-  * @brief  Return current CRC calculation result. 7 bits value is returned.
-  * @note   This function is expected to be used in a 7 bits CRC polynomial size context.
-  * @rmtoll DR           DR            LL_CRC_ReadData7
-  * @param  CRCx CRC Instance
-  * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
-  */
-__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
-{
-  return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
-}
-
-/**
-  * @brief  Return data stored in the Independent Data(IDR) register.
-  * @note   This register can be used as a temporary storage location for one byte.
-  * @rmtoll IDR          IDR           LL_CRC_Read_IDR
-  * @param  CRCx CRC Instance
-  * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
-  */
-__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
-{
-  return (uint32_t)(READ_REG(CRCx->IDR));
-}
-
-/**
-  * @brief  Store data in the Independent Data(IDR) register.
-  * @note   This register can be used as a temporary storage location for one byte.
-  * @rmtoll IDR          IDR           LL_CRC_Write_IDR
-  * @param  CRCx CRC Instance
-  * @param  InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
-{
-  *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
-}
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(CRC) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_LL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h
deleted file mode 100644
index 273853d6db..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h
+++ /dev/null
@@ -1,798 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_crs.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRS LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_CRS_H
-#define __STM32L0xx_LL_CRS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined(CRS)
-
-/** @defgroup CRS_LL CRS
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRS_LL_Private_Constants CRS Private Constants
-  * @{
-  */
-
-/* Defines used for the bit position in the register and perform offsets*/
-#define CRS_POSITION_TRIM        (CRS_CR_TRIM_Pos)     /* bit position in CR reg */
-#define CRS_POSITION_FECAP       (CRS_ISR_FECAP_Pos)   /* bit position in ISR reg */
-#define CRS_POSITION_FELIM       (CRS_CFGR_FELIM_Pos)  /* bit position in CFGR reg */
-
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
-  * @{
-  */
-
-/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_CRS_ReadReg function
-  * @{
-  */
-#define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
-#define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
-#define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
-#define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
-#define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
-#define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
-#define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
-  * @{
-  */
-#define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
-#define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
-#define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
-#define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
-  * @{
-  */
-#define LL_CRS_SYNC_DIV_1                  (0x00U)                         /*!< Synchro Signal not divided (default) */
-#define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
-#define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
-#define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
-#define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
-#define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
-#define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
-#define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
-  * @{
-  */
-#define LL_CRS_SYNC_SOURCE_GPIO            (0x00U)       /*!< Synchro Signal soucre GPIO */
-#define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
-#define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
-  * @{
-  */
-#define LL_CRS_SYNC_POLARITY_RISING        (0x00U)     /*!< Synchro Active on rising edge (default) */
-#define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
-  * @{
-  */
-#define LL_CRS_FREQ_ERROR_DIR_UP             (0x00U)         /*!< Upcounting direction, the actual frequency is above the target */
-#define LL_CRS_FREQ_ERROR_DIR_DOWN           CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
-  * @{
-  */
-/**
-  * @brief Reset value of the RELOAD field
-  * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
-  *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
-  */
-#define LL_CRS_RELOADVALUE_DEFAULT         (0xBB7FU)      
-
-/**
-  * @brief Reset value of Frequency error limit.
-  */
-#define LL_CRS_ERRORLIMIT_DEFAULT          (0x22U)      
-
-/**
-  * @brief Reset value of the HSI48 Calibration field
-  * @note The default value is 32, which corresponds to the middle of the trimming interval. 
-  *       The trimming step is around 67 kHz between two consecutive TRIM steps. 
-  *       A higher TRIM value corresponds to a higher output frequency
-  */
-#define LL_CRS_HSI48CALIBRATION_DEFAULT    (0x20U)      
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
-  * @{
-  */
-
-/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in CRS register
-  * @param  __INSTANCE__ CRS Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in CRS register
-  * @param  __INSTANCE__ CRS Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
-  * @{
-  */
-
-/**
-  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
-  * @note   The RELOAD value should be selected according to the ratio between 
-  *         the target frequency and the frequency of the synchronization source after
-  *         prescaling. It is then decreased by one in order to reach the expected
-  *         synchronization on the zero value. The formula is the following:
-  *              RELOAD = (fTARGET / fSYNC) -1
-  * @param  __FTARGET__ Target frequency (value in Hz)
-  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
-  * @retval Reload value (in Hz)
-  */
-#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
-  * @{
-  */
-
-/** @defgroup CRS_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Enable Frequency error counter
-  * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
-  * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_CEN);
-}
-
-/**
-  * @brief  Disable Frequency error counter
-  * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
-{
-  CLEAR_BIT(CRS->CR, CRS_CR_CEN);
-}
-
-/**
-  * @brief  Check if Frequency error counter is enabled or not
-  * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
-{
-  return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
-}
-
-/**
-  * @brief  Enable Automatic trimming counter
-  * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
-}
-
-/**
-  * @brief  Disable Automatic trimming counter
-  * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
-{
-  CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
-}
-
-/**
-  * @brief  Check if Automatic trimming is enabled or not
-  * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
-{
-  return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
-}
-
-/**
-  * @brief  Set HSI48 oscillator smooth trimming
-  * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
-  * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
-  * @param  Value a number between Min_Data = 0 and Max_Data = 63
-  * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT 
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
-{
-  MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
-}
-
-/**
-  * @brief  Get HSI48 oscillator smooth trimming
-  * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
-  * @retval a number between Min_Data = 0 and Max_Data = 63
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
-{
-  return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
-}
-
-/**
-  * @brief  Set counter reload value
-  * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
-  * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
-  * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT 
-  *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
-{
-  MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
-}
-
-/**
-  * @brief  Get counter reload value
-  * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
-  * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
-{
-  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
-}
-
-/**
-  * @brief  Set frequency error limit
-  * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
-  * @param  Value a number between Min_Data = 0 and Max_Data = 255
-  * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT 
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
-{
-  MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
-}
-
-/**
-  * @brief  Get frequency error limit
-  * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
-  * @retval A number between Min_Data = 0 and Max_Data = 255
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
-{
-  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
-}
-
-/**
-  * @brief  Set division factor for SYNC signal
-  * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
-  * @param  Divider This parameter can be one of the following values:
-  *         @arg @ref LL_CRS_SYNC_DIV_1
-  *         @arg @ref LL_CRS_SYNC_DIV_2
-  *         @arg @ref LL_CRS_SYNC_DIV_4
-  *         @arg @ref LL_CRS_SYNC_DIV_8
-  *         @arg @ref LL_CRS_SYNC_DIV_16
-  *         @arg @ref LL_CRS_SYNC_DIV_32
-  *         @arg @ref LL_CRS_SYNC_DIV_64
-  *         @arg @ref LL_CRS_SYNC_DIV_128
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
-{
-  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
-}
-
-/**
-  * @brief  Get division factor for SYNC signal
-  * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_CRS_SYNC_DIV_1
-  *         @arg @ref LL_CRS_SYNC_DIV_2
-  *         @arg @ref LL_CRS_SYNC_DIV_4
-  *         @arg @ref LL_CRS_SYNC_DIV_8
-  *         @arg @ref LL_CRS_SYNC_DIV_16
-  *         @arg @ref LL_CRS_SYNC_DIV_32
-  *         @arg @ref LL_CRS_SYNC_DIV_64
-  *         @arg @ref LL_CRS_SYNC_DIV_128
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
-{
-  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
-}
-
-/**
-  * @brief  Set SYNC signal source
-  * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
-  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
-  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
-{
-  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
-}
-
-/**
-  * @brief  Get SYNC signal source
-  * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
-  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
-  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
-{
-  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
-}
-
-/**
-  * @brief  Set input polarity for the SYNC signal source
-  * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
-  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
-{
-  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
-}
-
-/**
-  * @brief  Get input polarity for the SYNC signal source
-  * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
-  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
-{
-  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
-}
-
-/**
-  * @brief  Configure CRS for the synchronization
-  * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
-  *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
-  *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
-  *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
-  *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
-  *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
-  * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
-  * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
-  * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
-  * @param  Settings This parameter can be a combination of the following values:
-  *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
-  *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
-  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
-  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
-{
-  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
-  MODIFY_REG(CRS->CFGR, 
-             CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, 
-             ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
-  * @{
-  */
-
-/**
-  * @brief  Generate software SYNC event
-  * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
-}
-
-/**
-  * @brief  Get the frequency error direction latched in the time of the last 
-  * SYNC event
-  * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
-  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
-{
-  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
-}
-
-/**
-  * @brief  Get the frequency error counter value latched in the time of the last SYNC event
-  * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
-  * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
-{
-  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if SYNC event OK signal occurred or not
-  * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
-{
-  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
-}
-
-/**
-  * @brief  Check if SYNC warning signal occurred or not
-  * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
-{
-  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
-}
-
-/**
-  * @brief  Check if Synchronization or trimming error signal occurred or not
-  * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
-{
-  return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
-}
-
-/**
-  * @brief  Check if Expected SYNC signal occurred or not
-  * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
-{
-  return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
-}
-
-/**
-  * @brief  Check if SYNC error signal occurred or not
-  * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
-{
-  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
-}
-
-/**
-  * @brief  Check if SYNC missed error signal occurred or not
-  * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
-{
-  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
-}
-
-/**
-  * @brief  Check if Trimming overflow or underflow occurred or not
-  * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
-{
-  return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
-}
-
-/**
-  * @brief  Clear the SYNC event OK flag
-  * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
-{
-  WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
-}
-
-/**
-  * @brief  Clear the  SYNC warning flag
-  * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
-{
-  WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
-}
-
-/**
-  * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also 
-  * the ERR flag
-  * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
-{
-  WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
-}
-
-/**
-  * @brief  Clear Expected SYNC flag
-  * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
-{
-  WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRS_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable SYNC event OK interrupt
-  * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
-}
-
-/**
-  * @brief  Disable SYNC event OK interrupt
-  * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
-{
-  CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
-}
-
-/**
-  * @brief  Check if SYNC event OK interrupt is enabled or not
-  * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
-{
-  return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
-}
-
-/**
-  * @brief  Enable SYNC warning interrupt
-  * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
-}
-
-/**
-  * @brief  Disable SYNC warning interrupt
-  * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
-{
-  CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
-}
-
-/**
-  * @brief  Check if SYNC warning interrupt is enabled or not
-  * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
-{
-  return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
-}
-
-/**
-  * @brief  Enable Synchronization or trimming error interrupt
-  * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_ERRIE);
-}
-
-/**
-  * @brief  Disable Synchronization or trimming error interrupt
-  * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
-{
-  CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
-}
-
-/**
-  * @brief  Check if Synchronization or trimming error interrupt is enabled or not
-  * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
-{
-  return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
-}
-
-/**
-  * @brief  Enable Expected SYNC interrupt
-  * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
-}
-
-/**
-  * @brief  Disable Expected SYNC interrupt
-  * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
-{
-  CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
-}
-
-/**
-  * @brief  Check if Expected SYNC interrupt is enabled or not
-  * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
-{
-  return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-  
-ErrorStatus LL_CRS_DeInit(void);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(CRS) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_CRS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h
deleted file mode 100644
index e8007ebcc1..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h
+++ /dev/null
@@ -1,1418 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_dac.h
-  * @author  MCD Application Team
-  * @brief   Header file of DAC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_DAC_H
-#define __STM32L0xx_LL_DAC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (DAC1)
-
-/** @defgroup DAC_LL DAC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DAC_LL_Private_Constants DAC Private Constants
-  * @{
-  */
-
-/* Internal masks for DAC channels definition */
-/* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
-/* - channel bits position into register CR                                   */
-/* - channel bits position into register SWTRIG                               */
-/* - channel register offset of data holding register DHRx                    */
-/* - channel register offset of data output register DORx                     */
-#define DAC_CR_CH1_BITOFFSET           0U    /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
-#define DAC_CR_CH2_BITOFFSET           16U   /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
-#define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
-
-#define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
-#define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
-#else
-#define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1)
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-#define DAC_REG_DHR12R1_REGOFFSET      0x00000000U             /* Register DHR12Rx channel 1 taken as reference */
-#define DAC_REG_DHR12L1_REGOFFSET      0x00100000U             /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R1_REGOFFSET       0x02000000U             /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_REG_DHR12R2_REGOFFSET      0x00030000U             /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
-#define DAC_REG_DHR12L2_REGOFFSET      0x00400000U             /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R2_REGOFFSET       0x05000000U             /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#endif /* DAC_CHANNEL2_SUPPORT */
-#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
-#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
-#define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000U
-#define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
-
-#define DAC_REG_DOR1_REGOFFSET         0x00000000U             /* Register DORx channel 1 taken as reference */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_REG_DOR2_REGOFFSET         0x10000000U             /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
-#define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
-#else
-#define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET)
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-#define DAC_REG_REGOFFSET_MASK_POSBIT0             0x0000000FU  /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */
-
-#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS           16U   /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
-#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS           20U   /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS            24U   /* Position of bits register offset of DHR8Rx  channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS              28U   /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
-
-/* DAC registers bits positions */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                16U  /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
-#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                20U  /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
-#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                  8U  /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/* Miscellaneous data */
-#define DAC_DIGITAL_SCALE_12BITS                        4095U  /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
-
-/**
-  * @}
-  */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DAC_LL_Private_Macros DAC Private Macros
-  * @{
-  */
-
-/**
-  * @brief  Driver macro reserved for internal use: set a pointer to
-  *         a register from a register basis from which an offset
-  *         is applied.
-  * @param  __REG__ Register basis from which the offset is applied.
-  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
-  * @retval Pointer to register address
-*/
-#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
- ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
-
-/**
-  * @}
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  Structure definition of some features of DAC instance.
-  */
-typedef struct
-{
-  uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
-                                             This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
-
-  uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
-                                             This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
-
-  uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
-                                             If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
-                                             If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
-                                             @note If waveform automatic generation mode is disabled, this parameter is discarded.
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
-
-  uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
-                                             This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
-
-} LL_DAC_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
-  * @{
-  */
-
-/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
-  * @brief    Flags defines which can be used with LL_DAC_ReadReg function
-  * @{
-  */
-/* DAC channel 1 flags */
-#define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/* DAC channel 2 flags */
-#define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
-#endif /* DAC_CHANNEL2_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_IT DAC interruptions
-  * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
-  * @{
-  */
-#define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
-#endif /* DAC_CHANNEL2_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_CHANNEL DAC channels
-  * @{
-  */
-#define LL_DAC_CHANNEL_1                   (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define LL_DAC_CHANNEL_2                   (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
-#endif /* DAC_CHANNEL2_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
-  * @{
-  */
-#define LL_DAC_TRIG_SOFTWARE               (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM3_CH3           (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM3 CH3 event. */
-#define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM7_TRGO          (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM21_TRGO         (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM21 TRGO. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
-  * @{
-  */
-#define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000U             /*!< DAC channel wave auto generation mode disabled. */
-#define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (DAC_CR_WAVE1_0)        /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
-#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)        /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
-  * @{
-  */
-#define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000U                                                         /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
-  * @{
-  */
-#define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000U                                                         /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
-  * @{
-  */
-#define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000U             /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
-#define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_CR_BOFF1)          /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
-/**
-  * @}
-  */
-
-
-/** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
-  * @{
-  */
-#define LL_DAC_RESOLUTION_12B              0x00000000U             /*!< DAC channel resolution 12 bits */
-#define LL_DAC_RESOLUTION_8B               0x00000002U             /*!< DAC channel resolution 8 bits */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
-  * @{
-  */
-/* List of DAC registers intended to be used (most commonly) with             */
-/* DMA transfer.                                                              */
-/* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
-#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
-#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
-#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS  /*!< DAC channel data holding register 8 bits right aligned */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
-  * @note   Only DAC IP HW delays are defined in DAC LL driver driver,
-  *         not timeout values.
-  *         For details on delays values, refer to descriptions in source code
-  *         above each literal definition.
-  * @{
-  */
-
-/* Delay for DAC channel voltage settling time from DAC channel startup       */
-/* (transition from disable to enable).                                       */
-/* Note: DAC channel startup time depends on board application environment:   */
-/*       impedance connected to DAC channel output.                           */
-/*       The delay below is specified under conditions:                       */
-/*        - voltage maximum transition (lowest to highest value)              */
-/*        - until voltage reaches final value +-1LSB                          */
-/*        - DAC channel output buffer enabled                                 */
-/*        - load impedance of 5kOhm (min), 50pF (max)                         */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "tWAKEUP").                                                      */
-/* Unit: us                                                                   */
-#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             15U  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
-
-/* Delay for DAC channel voltage settling time.                               */
-/* Note: DAC channel startup time depends on board application environment:   */
-/*       impedance connected to DAC channel output.                           */
-/*       The delay below is specified under conditions:                       */
-/*        - voltage maximum transition (lowest to highest value)              */
-/*        - until voltage reaches final value +-1LSB                          */
-/*        - DAC channel output buffer enabled                                 */
-/*        - load impedance of 5kOhm min, 50pF max                             */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "tSETTLING").                                                    */
-/* Unit: us                                                                   */
-#define LL_DAC_DELAY_VOLTAGE_SETTLING_US                    12U  /*!< Delay for DAC channel voltage settling time */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
-  * @{
-  */
-
-/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in DAC register
-  * @param  __INSTANCE__ DAC Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in DAC register
-  * @param  __INSTANCE__ DAC Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to get DAC channel number in decimal format
-  *         from literals LL_DAC_CHANNEL_x.
-  *         Example:
-  *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
-  *            will return decimal number "1".
-  * @note   The input can be a value from functions where a channel
-  *         number is returned.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval 1...2 (value "2" depending on DAC channel 2 availability)
-  */
-#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
-  ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
-
-/**
-  * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
-  *         from number in decimal format.
-  *         Example:
-  *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
-  *           will return a data equivalent to "LL_DAC_CHANNEL_1".
-  * @note  If the input parameter does not correspond to a DAC channel,
-  *        this macro returns value '0'.
-  * @param  __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
-  (((__DECIMAL_NB__) == 1U)                                                     \
-    ? (                                                                        \
-       LL_DAC_CHANNEL_1                                                        \
-      )                                                                        \
-      :                                                                        \
-      (((__DECIMAL_NB__) == 2U)                                                 \
-        ? (                                                                    \
-           LL_DAC_CHANNEL_2                                                    \
-          )                                                                    \
-          :                                                                    \
-          (                                                                    \
-           0                                                                   \
-          )                                                                    \
-      )                                                                        \
-  )
-#else
-#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
-  (((__DECIMAL_NB__) == 1U)                                                     \
-    ? (                                                                        \
-       LL_DAC_CHANNEL_1                                                        \
-      )                                                                        \
-      :                                                                        \
-      (                                                                        \
-       0                                                                       \
-      )                                                                        \
-  )
-#endif  /* DAC_CHANNEL2_SUPPORT */
-
-/**
-  * @brief  Helper macro to define the DAC conversion data full-scale digital
-  *         value corresponding to the selected DAC resolution.
-  * @note   DAC conversion data full-scale corresponds to voltage range
-  *         determined by analog voltage references Vref+ and Vref-
-  *         (refer to reference manual).
-  * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_RESOLUTION_12B
-  *         @arg @ref LL_DAC_RESOLUTION_8B
-  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
-  */
-#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
-  ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
-
-/**
-  * @brief  Helper macro to calculate the DAC conversion data (unit: digital
-  *         value) corresponding to a voltage (unit: mVolt).
-  * @note   This helper macro is intended to provide input data in voltage
-  *         rather than digital value,
-  *         to be used with LL DAC functions such as
-  *         @ref LL_DAC_ConvertData12RightAligned().
-  * @note   Analog reference voltage (Vref+) must be either known from
-  *         user board environment or can be calculated using ADC measurement
-  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
-  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
-  * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
-  *                         (unit: mVolt).
-  * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_RESOLUTION_12B
-  *         @arg @ref LL_DAC_RESOLUTION_8B
-  * @retval DAC conversion data (unit: digital value)
-  */
-#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
-                                      __DAC_VOLTAGE__,\
-                                      __DAC_RESOLUTION__)                      \
-  ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
-   / (__VREFANALOG_VOLTAGE__)                                                  \
-  )
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
-  * @{
-  */
-/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
-  * @{
-  */
-
-/**
-  * @brief  Set the conversion trigger source for the selected DAC channel.
-  * @note   For conversion trigger source to be effective, DAC trigger
-  *         must be enabled using function @ref LL_DAC_EnableTrigger().
-  * @note   To set conversion trigger source, DAC channel must be disabled.
-  *         Otherwise, the setting is discarded.
-  * @note   Availability of parameters of trigger sources from timer
-  *         depends on timers availability on the selected device.
-  * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
-  *         CR       TSEL2          LL_DAC_SetTriggerSource
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @param  TriggerSource This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_TRIG_SOFTWARE
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
-{
-  MODIFY_REG(DACx->CR,
-             DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
-             TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get the conversion trigger source for the selected DAC channel.
-  * @note   For conversion trigger source to be effective, DAC trigger
-  *         must be enabled using function @ref LL_DAC_EnableTrigger().
-  * @note   Availability of parameters of trigger sources from timer
-  *         depends on timers availability on the selected device.
-  * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
-  *         CR       TSEL2          LL_DAC_GetTriggerSource
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DAC_TRIG_SOFTWARE
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
-  */
-__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                   );
-}
-
-/**
-  * @brief  Set the waveform automatic generation mode
-  *         for the selected DAC channel.
-  * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
-  *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @param  WaveAutoGeneration This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
-  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
-  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
-{
-  MODIFY_REG(DACx->CR,
-             DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
-             WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get the waveform automatic generation mode
-  *         for the selected DAC channel.
-  * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
-  *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
-  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
-  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
-  */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                   );
-}
-
-/**
-  * @brief  Set the noise waveform generation for the selected DAC channel:
-  *         Noise mode and parameters LFSR (linear feedback shift register).
-  * @note   For wave generation to be effective, DAC channel
-  *         wave generation mode must be enabled using
-  *         function @ref LL_DAC_SetWaveAutoGeneration().
-  * @note   This setting can be set when the selected DAC channel is disabled
-  *         (otherwise, the setting operation is ignored).
-  * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
-  *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @param  NoiseLFSRMask This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
-{
-  MODIFY_REG(DACx->CR,
-             DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
-             NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Set the noise waveform generation for the selected DAC channel:
-  *         Noise mode and parameters LFSR (linear feedback shift register).
-  * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
-  *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
-  */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                   );
-}
-
-/**
-  * @brief  Set the triangle waveform generation for the selected DAC channel:
-  *         triangle mode and amplitude.
-  * @note   For wave generation to be effective, DAC channel
-  *         wave generation mode must be enabled using
-  *         function @ref LL_DAC_SetWaveAutoGeneration().
-  * @note   This setting can be set when the selected DAC channel is disabled
-  *         (otherwise, the setting operation is ignored).
-  * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
-  *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @param  TriangleAmplitude This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
-{
-  MODIFY_REG(DACx->CR,
-             DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
-             TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Set the triangle waveform generation for the selected DAC channel:
-  *         triangle mode and amplitude.
-  * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
-  *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
-  */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                   );
-}
-
-/**
-  * @brief  Set the output buffer for the selected DAC channel.
-  * @rmtoll CR       BOFF1          LL_DAC_SetOutputBuffer\n
-  *         CR       BOFF2          LL_DAC_SetOutputBuffer
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @param  OutputBuffer This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
-  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
-{
-  MODIFY_REG(DACx->CR,
-             DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
-             OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get the output buffer state for the selected DAC channel.
-  * @rmtoll CR       BOFF1          LL_DAC_GetOutputBuffer\n
-  *         CR       BOFF2          LL_DAC_GetOutputBuffer
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
-  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
-  */
-__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                   );
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EF_DMA_Management DMA Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DAC DMA transfer request of the selected channel.
-  * @note   To configure DMA source address (peripheral address),
-  *         use function @ref LL_DAC_DMA_GetRegAddr().
-  * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
-  *         CR       DMAEN2         LL_DAC_EnableDMAReq
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  SET_BIT(DACx->CR,
-          DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Disable DAC DMA transfer request of the selected channel.
-  * @note   To configure DMA source address (peripheral address),
-  *         use function @ref LL_DAC_DMA_GetRegAddr().
-  * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
-  *         CR       DMAEN2         LL_DAC_DisableDMAReq
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  CLEAR_BIT(DACx->CR,
-            DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get DAC DMA transfer request state of the selected channel.
-  *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
-  * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
-  *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (READ_BIT(DACx->CR,
-                   DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-          == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
-}
-
-/**
-  * @brief  Function to help to configure DMA transfer to DAC: retrieve the
-  *         DAC register address from DAC instance and a list of DAC registers
-  *         intended to be used (most commonly) with DMA transfer.
-  * @note   These DAC registers are data holding registers:
-  *         when DAC conversion is requested, DAC generates a DMA transfer
-  *         request to have data available in DAC data holding registers.
-  * @note   This macro is intended to be used with LL DMA driver, refer to
-  *         function "LL_DMA_ConfigAddresses()".
-  *         Example:
-  *           LL_DMA_ConfigAddresses(DMA1,
-  *                                  LL_DMA_CHANNEL_1,
-  *                                  (uint32_t)&< array or variable >,
-  *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
-  *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
-  * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
-  *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
-  *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
-  *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
-  *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
-  *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @param  Register This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
-  *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
-  *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
-  * @retval DAC register address
-  */
-__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
-{
-  /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
-  /* DAC channel selected.                                                    */
-  return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REGOFFSET_MASK_POSBIT0))));
-}
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
-  * @{
-  */
-
-/**
-  * @brief  Enable DAC selected channel.
-  * @rmtoll CR       EN1            LL_DAC_Enable\n
-  *         CR       EN2            LL_DAC_Enable
-  * @note   After enable from off state, DAC channel requires a delay
-  *         for output voltage to reach accuracy +/- 1 LSB.
-  *         Refer to device datasheet, parameter "tWAKEUP".
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  SET_BIT(DACx->CR,
-          DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Disable DAC selected channel.
-  * @rmtoll CR       EN1            LL_DAC_Disable\n
-  *         CR       EN2            LL_DAC_Disable
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  CLEAR_BIT(DACx->CR,
-            DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get DAC enable state of the selected channel.
-  *         (0: DAC channel is disabled, 1: DAC channel is enabled)
-  * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
-  *         CR       EN2            LL_DAC_IsEnabled
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (READ_BIT(DACx->CR,
-                   DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-          == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
-}
-
-/**
-  * @brief  Enable DAC trigger of the selected channel.
-  * @note   - If DAC trigger is disabled, DAC conversion is performed
-  *           automatically once the data holding register is updated,
-  *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
-  *           @ref LL_DAC_ConvertData12RightAligned(), ...
-  *         - If DAC trigger is enabled, DAC conversion is performed
-  *           only when a hardware of software trigger event is occurring.
-  *           Select trigger source using
-  *           function @ref LL_DAC_SetTriggerSource().
-  * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
-  *         CR       TEN2           LL_DAC_EnableTrigger
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  SET_BIT(DACx->CR,
-          DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Disable DAC trigger of the selected channel.
-  * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
-  *         CR       TEN2           LL_DAC_DisableTrigger
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  CLEAR_BIT(DACx->CR,
-            DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get DAC trigger state of the selected channel.
-  *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
-  * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
-  *         CR       TEN2           LL_DAC_IsTriggerEnabled
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (READ_BIT(DACx->CR,
-                   DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-          == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
-}
-
-/**
-  * @brief  Trig DAC conversion by software for the selected DAC channel.
-  * @note   Preliminarily, DAC trigger must be set to software trigger
-  *         using function @ref LL_DAC_SetTriggerSource()
-  *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
-  *         and DAC trigger must be enabled using
-  *         function @ref LL_DAC_EnableTrigger().
-  * @note   For devices featuring DAC with 2 channels: this function
-  *         can perform a SW start of both DAC channels simultaneously.
-  *         Two channels can be selected as parameter.
-  *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
-  * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
-  *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
-  * @param  DACx DAC instance
-  * @param  DAC_Channel  This parameter can a combination of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  SET_BIT(DACx->SWTRIGR,
-          (DAC_Channel & DAC_SWTR_CHX_MASK));
-}
-
-/**
-  * @brief  Set the data to be loaded in the data holding register
-  *         in format 12 bits left alignment (LSB aligned on bit 0),
-  *         for the selected DAC channel.
-  * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
-  *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
-  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
-  
-  MODIFY_REG(*preg,
-             DAC_DHR12R1_DACC1DHR,
-             Data);
-}
-
-/**
-  * @brief  Set the data to be loaded in the data holding register
-  *         in format 12 bits left alignment (MSB aligned on bit 15),
-  *         for the selected DAC channel.
-  * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
-  *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
-  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
-  
-  MODIFY_REG(*preg,
-             DAC_DHR12L1_DACC1DHR,
-             Data);
-}
-
-/**
-  * @brief  Set the data to be loaded in the data holding register
-  *         in format 8 bits left alignment (LSB aligned on bit 0),
-  *         for the selected DAC channel.
-  * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
-  *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
-  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
-  
-  MODIFY_REG(*preg,
-             DAC_DHR8R1_DACC1DHR,
-             Data);
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
-  * @brief  Set the data to be loaded in the data holding register
-  *         in format 12 bits left alignment (LSB aligned on bit 0),
-  *         for both DAC channels.
-  * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
-  *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
-  * @param  DACx DAC instance
-  * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
-{
-  MODIFY_REG(DACx->DHR12RD,
-             (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
-             ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
-}
-
-/**
-  * @brief  Set the data to be loaded in the data holding register
-  *         in format 12 bits left alignment (MSB aligned on bit 15),
-  *         for both DAC channels.
-  * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
-  *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
-  * @param  DACx DAC instance
-  * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
-{
-  /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
-  /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
-  /*       the 4 LSB must be taken into account for the shift value.          */
-  MODIFY_REG(DACx->DHR12LD,
-             (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
-             ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
-}
-
-/**
-  * @brief  Set the data to be loaded in the data holding register
-  *         in format 8 bits left alignment (LSB aligned on bit 0),
-  *         for both DAC channels.
-  * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
-  *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
-  * @param  DACx DAC instance
-  * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
-  * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
-{
-  MODIFY_REG(DACx->DHR8RD,
-             (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
-             ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
-}
-
-#endif /* DAC_CHANNEL2_SUPPORT */
-/**
-  * @brief  Retrieve output data currently generated for the selected DAC channel.
-  * @note   Whatever alignment and resolution settings
-  *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
-  *         @ref LL_DAC_ConvertData12RightAligned(), ...),
-  *         output data format is 12 bits right aligned (LSB aligned on bit 0).
-  * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
-  *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
-  
-  return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
-  * @{
-  */
-/**
-  * @brief  Get DAC underrun flag for DAC channel 1
-  * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
-  * @param  DACx DAC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
-{
-  return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
-  * @brief  Get DAC underrun flag for DAC channel 2
-  * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
-  * @param  DACx DAC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
-{
-  return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
-  * @brief  Clear DAC underrun flag for DAC channel 1
-  * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
-  * @param  DACx DAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
-{
-  WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
-  * @brief  Clear DAC underrun flag for DAC channel 2
-  * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
-  * @param  DACx DAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
-{
-  WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EF_IT_Management IT management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA underrun interrupt for DAC channel 1
-  * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
-  * @param  DACx DAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
-{
-  SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
-  * @brief  Enable DMA underrun interrupt for DAC channel 2
-  * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
-  * @param  DACx DAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
-{
-  SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
-  * @brief  Disable DMA underrun interrupt for DAC channel 1
-  * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
-  * @param  DACx DAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
-{
-  CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
-  * @brief  Disable DMA underrun interrupt for DAC channel 2
-  * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
-  * @param  DACx DAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
-{
-  CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
-  * @brief  Get DMA underrun interrupt for DAC channel 1
-  * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
-  * @param  DACx DAC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
-{
-  return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
-  * @brief  Get DMA underrun interrupt for DAC channel 2
-  * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
-  * @param  DACx DAC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
-{
-  return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
-ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
-void        LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DAC1 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h
deleted file mode 100644
index 17a7d711fa..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h
+++ /dev/null
@@ -1,2129 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_dma.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMA LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_LL_DMA_H
-#define STM32L0xx_LL_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (DMA1)
-
-/** @defgroup DMA_LL DMA
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Variables DMA Private Variables
-  * @{
-  */
-/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
-static const uint8_t CHANNEL_OFFSET_TAB[] =
-{
-  (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
-#if defined(DMA1_Channel6)
-  (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
-#endif /*DMA1_Channel6*/
-#if defined(DMA1_Channel7)
-  (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
-#endif /*DMA1_Channel7*/
-};
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Constants DMA Private Constants
-  * @{
-  */
-/* Define used to get CSELR register offset */
-#define DMA_CSELR_OFFSET                  (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
-
-/* Defines used for the bit position in the register and perform offsets */
-#define DMA_POSITION_CSELR_CXS            ((Channel-1U)*4U)
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_Private_Macros DMA Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
-  * @{
-  */
-typedef struct
-{
-  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
-                                        or as Source base address in case of memory to memory transfer direction.
-
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
-  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
-                                        or as Destination base address in case of memory to memory transfer direction.
-
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
-  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
-                                        from memory to memory or from peripheral to memory.
-                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
-
-  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
-                                        This parameter can be a value of @ref DMA_LL_EC_MODE
-                                        @note: The circular buffer mode cannot be used if the memory to memory
-                                               data transfer direction is configured on the selected Channel
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
-
-  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
-
-  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
-
-  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
-
-  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
-
-  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
-                                        The data unit is equal to the source buffer configuration set in PeripheralSize
-                                        or MemorySize parameters depending in the transfer direction.
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
-
-  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
-                                        This parameter can be a value of @ref DMA_LL_EC_REQUEST
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
-
-  uint32_t Priority;               /*!< Specifies the channel priority level.
-                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
-
-} LL_DMA_InitTypeDef;
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
-  * @{
-  */
-/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_DMA_WriteReg function
-  * @{
-  */
-#define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
-#define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
-#define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
-#define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
-#define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
-#define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
-#define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
-#define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
-#define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
-#define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
-#if defined(DMA1_Channel6)
-#define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
-#define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
-#endif
-#if defined(DMA1_Channel7)
-#define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
-#define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_DMA_ReadReg function
-  * @{
-  */
-#define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
-#define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
-#define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
-#define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
-#define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
-#define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
-#define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
-#define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
-#define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
-#define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
-#define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
-#define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
-#define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
-#define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
-#define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
-#define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
-#define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
-#define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
-#define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
-#define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
-#if defined(DMA1_Channel6)
-#define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
-#define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
-#define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
-#define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
-#endif
-#if defined(DMA1_Channel7)
-#define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
-#define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
-#define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
-#define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
-  * @{
-  */
-#define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
-#define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
-#define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
-  * @{
-  */
-#define LL_DMA_CHANNEL_1                  0x00000001U /*!< DMA Channel 1 */
-#define LL_DMA_CHANNEL_2                  0x00000002U /*!< DMA Channel 2 */
-#define LL_DMA_CHANNEL_3                  0x00000003U /*!< DMA Channel 3 */
-#define LL_DMA_CHANNEL_4                  0x00000004U /*!< DMA Channel 4 */
-#define LL_DMA_CHANNEL_5                  0x00000005U /*!< DMA Channel 5 */
-#if defined(DMA1_Channel6)
-#define LL_DMA_CHANNEL_6                  0x00000006U /*!< DMA Channel 6 */
-#endif
-#if defined(DMA1_Channel7)
-#define LL_DMA_CHANNEL_7                  0x00000007U /*!< DMA Channel 7 */
-#endif
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_DMA_CHANNEL_ALL                0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
-#endif /*USE_FULL_LL_DRIVER*/
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
-  * @{
-  */
-#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MODE Transfer mode
-  * @{
-  */
-#define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */
-#define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
-  * @{
-  */
-#define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
-#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
-  * @{
-  */
-#define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
-#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
-  * @{
-  */
-#define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */
-#define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
-#define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
-  * @{
-  */
-#define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */
-#define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
-#define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
-  * @{
-  */
-#define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */
-#define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
-#define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
-#define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
-  * @{
-  */
-#define LL_DMA_REQUEST_0                  0x00000000U             /*!< DMA peripheral request 0  */
-#define LL_DMA_REQUEST_1                  0x00000001U             /*!< DMA peripheral request 1  */
-#define LL_DMA_REQUEST_2                  0x00000002U             /*!< DMA peripheral request 2  */
-#define LL_DMA_REQUEST_3                  0x00000003U             /*!< DMA peripheral request 3  */
-#define LL_DMA_REQUEST_4                  0x00000004U             /*!< DMA peripheral request 4  */
-#define LL_DMA_REQUEST_5                  0x00000005U             /*!< DMA peripheral request 5  */
-#define LL_DMA_REQUEST_6                  0x00000006U             /*!< DMA peripheral request 6  */
-#define LL_DMA_REQUEST_7                  0x00000007U             /*!< DMA peripheral request 7  */
-#define LL_DMA_REQUEST_8                  0x00000008U             /*!< DMA peripheral request 8  */
-#define LL_DMA_REQUEST_9                  0x00000009U             /*!< DMA peripheral request 9  */
-#define LL_DMA_REQUEST_10                 0x0000000AU             /*!< DMA peripheral request 10 */
-#define LL_DMA_REQUEST_11                 0x0000000BU             /*!< DMA peripheral request 11 */
-#define LL_DMA_REQUEST_12                 0x0000000CU             /*!< DMA peripheral request 12 */
-#define LL_DMA_REQUEST_13                 0x0000000DU             /*!< DMA peripheral request 13 */
-#define LL_DMA_REQUEST_14                 0x0000000EU             /*!< DMA peripheral request 14 */
-#define LL_DMA_REQUEST_15                 0x0000000FU             /*!< DMA peripheral request 15 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
-  * @{
-  */
-
-/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
-  * @{
-  */
-/**
-  * @brief  Write a value in DMA register
-  * @param  __INSTANCE__ DMA Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in DMA register
-  * @param  __INSTANCE__ DMA Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
-  * @{
-  */
-/**
-  * @brief  Convert DMAx_Channely into DMAx
-  * @param  __CHANNEL_INSTANCE__ DMAx_Channely
-  * @retval DMAx
-  */
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (DMA1)
-
-/**
-  * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
-  * @param  __CHANNEL_INSTANCE__ DMAx_Channely
-  * @retval LL_DMA_CHANNEL_y
-  */
-#if defined (DMA1_Channel6) && defined (DMA1_Channel7)
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#elif defined (DMA1_Channel6)
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- LL_DMA_CHANNEL_6)
-#else
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- LL_DMA_CHANNEL_5)
-#endif /* DMA1_Channel6 && DMA1_Channel7 */
-
-/**
-  * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
-  * @param  __DMA_INSTANCE__ DMAx
-  * @param  __CHANNEL__ LL_DMA_CHANNEL_y
-  * @retval DMAx_Channely
-  */
-#if defined (DMA1_Channel6) && defined (DMA1_Channel7)
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- DMA1_Channel7)
-#elif defined (DMA1_Channel6)
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- DMA1_Channel6)
-#else
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- DMA1_Channel5)
-#endif /* DMA1_Channel6 && DMA1_Channel7 */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_LL_EF_Configuration Configuration
-  * @{
-  */
-/**
-  * @brief  Enable DMA channel.
-  * @rmtoll CCR          EN            LL_DMA_EnableChannel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
-}
-
-/**
-  * @brief  Disable DMA channel.
-  * @rmtoll CCR          EN            LL_DMA_DisableChannel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
-}
-
-/**
-  * @brief  Check if DMA channel is enabled or disabled.
-  * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure all parameters link to DMA transfer.
-  * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
-  *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
-  *         CCR          CIRC          LL_DMA_ConfigTransfer\n
-  *         CCR          PINC          LL_DMA_ConfigTransfer\n
-  *         CCR          MINC          LL_DMA_ConfigTransfer\n
-  *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
-  *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
-  *         CCR          PL            LL_DMA_ConfigTransfer
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
-  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-             DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
-             Configuration);
-}
-
-/**
-  * @brief  Set Data transfer direction (read from peripheral or from memory).
-  * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
-  *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-             DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
-}
-
-/**
-  * @brief  Get Data transfer direction (read from peripheral or from memory).
-  * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
-  *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_DIR | DMA_CCR_MEM2MEM));
-}
-
-/**
-  * @brief  Set DMA mode circular or normal.
-  * @note The circular buffer mode cannot be used if the memory-to-memory
-  * data transfer is configured on the selected Channel.
-  * @rmtoll CCR          CIRC          LL_DMA_SetMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MODE_NORMAL
-  *         @arg @ref LL_DMA_MODE_CIRCULAR
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
-             Mode);
-}
-
-/**
-  * @brief  Get DMA mode circular or normal.
-  * @rmtoll CCR          CIRC          LL_DMA_GetMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MODE_NORMAL
-  *         @arg @ref LL_DMA_MODE_CIRCULAR
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_CIRC));
-}
-
-/**
-  * @brief  Set Peripheral increment mode.
-  * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT
-  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
-             PeriphOrM2MSrcIncMode);
-}
-
-/**
-  * @brief  Get Peripheral increment mode.
-  * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT
-  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_PINC));
-}
-
-/**
-  * @brief  Set Memory increment mode.
-  * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT
-  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
-             MemoryOrM2MDstIncMode);
-}
-
-/**
-  * @brief  Get Memory increment mode.
-  * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT
-  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_MINC));
-}
-
-/**
-  * @brief  Set Peripheral size.
-  * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_PDATAALIGN_WORD
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
-             PeriphOrM2MSrcDataSize);
-}
-
-/**
-  * @brief  Get Peripheral size.
-  * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_PDATAALIGN_WORD
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_PSIZE));
-}
-
-/**
-  * @brief  Set Memory size.
-  * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_MDATAALIGN_WORD
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
-             MemoryOrM2MDstDataSize);
-}
-
-/**
-  * @brief  Get Memory size.
-  * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_MDATAALIGN_WORD
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_MSIZE));
-}
-
-/**
-  * @brief  Set Channel priority level.
-  * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Priority This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PRIORITY_LOW
-  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
-  *         @arg @ref LL_DMA_PRIORITY_HIGH
-  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
-             Priority);
-}
-
-/**
-  * @brief  Get Channel priority level.
-  * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PRIORITY_LOW
-  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
-  *         @arg @ref LL_DMA_PRIORITY_HIGH
-  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_PL));
-}
-
-/**
-  * @brief  Set Number of data to transfer.
-  * @note   This action has no effect if
-  *         channel is enabled.
-  * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
-             DMA_CNDTR_NDT, NbData);
-}
-
-/**
-  * @brief  Get Number of data to transfer.
-  * @note   Once the channel is enabled, the return value indicate the
-  *         remaining bytes to be transmitted.
-  * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
-                   DMA_CNDTR_NDT));
-}
-
-/**
-  * @brief  Configure the Source and Destination addresses.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
-  * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
-  *         CMAR         MA            LL_DMA_ConfigAddresses
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
-                                            uint32_t DstAddress, uint32_t Direction)
-{
-  /* Direction Memory to Periph */
-  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
-  {
-    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
-    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
-  }
-  /* Direction Periph to Memory and Memory to Memory */
-  else
-  {
-    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
-    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
-  }
-}
-
-/**
-  * @brief  Set the Memory address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
-  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
-}
-
-/**
-  * @brief  Set the Peripheral address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
-{
-  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
-}
-
-/**
-  * @brief  Get Memory address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
-}
-
-/**
-  * @brief  Get Peripheral address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
-}
-
-/**
-  * @brief  Set the Memory to Memory Source address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
-  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
-}
-
-/**
-  * @brief  Set the Memory to Memory Destination address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
-  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
-}
-
-/**
-  * @brief  Get the Memory to Memory Source address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
-}
-
-/**
-  * @brief  Get the Memory to Memory Destination address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
-}
-
-/**
-  * @brief  Set DMA request for DMA instance on Channel x.
-  * @note   Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
-  * @rmtoll CSELR        C1S           LL_DMA_SetPeriphRequest\n
-  *         CSELR        C2S           LL_DMA_SetPeriphRequest\n
-  *         CSELR        C3S           LL_DMA_SetPeriphRequest\n
-  *         CSELR        C4S           LL_DMA_SetPeriphRequest\n
-  *         CSELR        C5S           LL_DMA_SetPeriphRequest\n
-  *         CSELR        C6S           LL_DMA_SetPeriphRequest\n
-  *         CSELR        C7S           LL_DMA_SetPeriphRequest
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  PeriphRequest This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_REQUEST_0
-  *         @arg @ref LL_DMA_REQUEST_1
-  *         @arg @ref LL_DMA_REQUEST_2
-  *         @arg @ref LL_DMA_REQUEST_3
-  *         @arg @ref LL_DMA_REQUEST_4
-  *         @arg @ref LL_DMA_REQUEST_5
-  *         @arg @ref LL_DMA_REQUEST_6
-  *         @arg @ref LL_DMA_REQUEST_7
-  *         @arg @ref LL_DMA_REQUEST_8
-  *         @arg @ref LL_DMA_REQUEST_9
-  *         @arg @ref LL_DMA_REQUEST_10
-  *         @arg @ref LL_DMA_REQUEST_11
-  *         @arg @ref LL_DMA_REQUEST_12
-  *         @arg @ref LL_DMA_REQUEST_13
-  *         @arg @ref LL_DMA_REQUEST_14
-  *         @arg @ref LL_DMA_REQUEST_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
-{
-  MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
-             DMA_CSELR_C1S << ((Channel - 1U) * 4U), Request << DMA_POSITION_CSELR_CXS);
-}
-
-/**
-  * @brief  Get DMA request for DMA instance on Channel x.
-  * @rmtoll CSELR        C1S           LL_DMA_GetPeriphRequest\n
-  *         CSELR        C2S           LL_DMA_GetPeriphRequest\n
-  *         CSELR        C3S           LL_DMA_GetPeriphRequest\n
-  *         CSELR        C4S           LL_DMA_GetPeriphRequest\n
-  *         CSELR        C5S           LL_DMA_GetPeriphRequest\n
-  *         CSELR        C6S           LL_DMA_GetPeriphRequest\n
-  *         CSELR        C7S           LL_DMA_GetPeriphRequest
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_REQUEST_0
-  *         @arg @ref LL_DMA_REQUEST_1
-  *         @arg @ref LL_DMA_REQUEST_2
-  *         @arg @ref LL_DMA_REQUEST_3
-  *         @arg @ref LL_DMA_REQUEST_4
-  *         @arg @ref LL_DMA_REQUEST_5
-  *         @arg @ref LL_DMA_REQUEST_6
-  *         @arg @ref LL_DMA_REQUEST_7
-  *         @arg @ref LL_DMA_REQUEST_8
-  *         @arg @ref LL_DMA_REQUEST_9
-  *         @arg @ref LL_DMA_REQUEST_10
-  *         @arg @ref LL_DMA_REQUEST_11
-  *         @arg @ref LL_DMA_REQUEST_12
-  *         @arg @ref LL_DMA_REQUEST_13
-  *         @arg @ref LL_DMA_REQUEST_14
-  *         @arg @ref LL_DMA_REQUEST_15
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
-                   DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Get Channel 1 global interrupt flag.
-  * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 2 global interrupt flag.
-  * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 3 global interrupt flag.
-  * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 4 global interrupt flag.
-  * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 5 global interrupt flag.
-  * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Get Channel 6 global interrupt flag.
-  * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
-}
-#endif
-
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Get Channel 7 global interrupt flag.
-  * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
-}
-#endif
-
-/**
-  * @brief  Get Channel 1 transfer complete flag.
-  * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 2 transfer complete flag.
-  * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 3 transfer complete flag.
-  * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 4 transfer complete flag.
-  * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 5 transfer complete flag.
-  * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Get Channel 6 transfer complete flag.
-  * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
-}
-#endif
-
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Get Channel 7 transfer complete flag.
-  * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
-}
-#endif
-
-/**
-  * @brief  Get Channel 1 half transfer flag.
-  * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 2 half transfer flag.
-  * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 3 half transfer flag.
-  * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 4 half transfer flag.
-  * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 5 half transfer flag.
-  * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Get Channel 6 half transfer flag.
-  * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
-}
-#endif
-
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Get Channel 7 half transfer flag.
-  * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
-}
-#endif
-
-/**
-  * @brief  Get Channel 1 transfer error flag.
-  * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 2 transfer error flag.
-  * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 3 transfer error flag.
-  * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 4 transfer error flag.
-  * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 5 transfer error flag.
-  * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Get Channel 6 transfer error flag.
-  * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
-}
-#endif
-
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Get Channel 7 transfer error flag.
-  * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
-}
-#endif
-
-/**
-  * @brief  Clear Channel 1 global interrupt flag.
-  * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
-}
-
-/**
-  * @brief  Clear Channel 2 global interrupt flag.
-  * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
-}
-
-/**
-  * @brief  Clear Channel 3 global interrupt flag.
-  * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
-}
-
-/**
-  * @brief  Clear Channel 4 global interrupt flag.
-  * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
-}
-
-/**
-  * @brief  Clear Channel 5 global interrupt flag.
-  * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Clear Channel 6 global interrupt flag.
-  * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
-}
-#endif
-
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Clear Channel 7 global interrupt flag.
-  * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
-}
-#endif
-
-/**
-  * @brief  Clear Channel 1  transfer complete flag.
-  * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
-}
-
-/**
-  * @brief  Clear Channel 2  transfer complete flag.
-  * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
-}
-
-/**
-  * @brief  Clear Channel 3  transfer complete flag.
-  * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
-}
-
-/**
-  * @brief  Clear Channel 4  transfer complete flag.
-  * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
-}
-
-/**
-  * @brief  Clear Channel 5  transfer complete flag.
-  * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Clear Channel 6  transfer complete flag.
-  * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
-}
-#endif
-
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Clear Channel 7  transfer complete flag.
-  * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
-}
-#endif
-
-/**
-  * @brief  Clear Channel 1  half transfer flag.
-  * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
-}
-
-/**
-  * @brief  Clear Channel 2  half transfer flag.
-  * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
-}
-
-/**
-  * @brief  Clear Channel 3  half transfer flag.
-  * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
-}
-
-/**
-  * @brief  Clear Channel 4  half transfer flag.
-  * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
-}
-
-/**
-  * @brief  Clear Channel 5  half transfer flag.
-  * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Clear Channel 6  half transfer flag.
-  * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
-}
-#endif
-
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Clear Channel 7  half transfer flag.
-  * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
-}
-#endif
-
-/**
-  * @brief  Clear Channel 1 transfer error flag.
-  * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
-}
-
-/**
-  * @brief  Clear Channel 2 transfer error flag.
-  * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
-}
-
-/**
-  * @brief  Clear Channel 3 transfer error flag.
-  * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
-}
-
-/**
-  * @brief  Clear Channel 4 transfer error flag.
-  * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
-}
-
-/**
-  * @brief  Clear Channel 5 transfer error flag.
-  * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Clear Channel 6 transfer error flag.
-  * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
-}
-#endif
-
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Clear Channel 7 transfer error flag.
-  * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
-}
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EF_IT_Management IT_Management
-  * @{
-  */
-/**
-  * @brief  Enable Transfer complete interrupt.
-  * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
-}
-
-/**
-  * @brief  Enable Half transfer interrupt.
-  * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
-}
-
-/**
-  * @brief  Enable Transfer error interrupt.
-  * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
-}
-
-/**
-  * @brief  Disable Transfer complete interrupt.
-  * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
-}
-
-/**
-  * @brief  Disable Half transfer interrupt.
-  * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
-}
-
-/**
-  * @brief  Disable Transfer error interrupt.
-  * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
-}
-
-/**
-  * @brief  Check if Transfer complete Interrupt is enabled.
-  * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Half transfer Interrupt is enabled.
-  * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Transfer error Interrupt is enabled.
-  * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
-ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DMA1 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_LL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h
deleted file mode 100644
index aff28a1790..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h
+++ /dev/null
@@ -1,1016 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_exti.h
-  * @author  MCD Application Team
-  * @brief   Header file of EXTI LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_EXTI_H
-#define __STM32L0xx_LL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private Macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
-  * @{
-  */
-typedef struct
-{
-
-  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
-                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-
-  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
-                                     This parameter can be set either to ENABLE or DISABLE */
-
-  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
-                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
-
-  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
-                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
-} LL_EXTI_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
-  * @{
-  */
-
-/** @defgroup EXTI_LL_EC_LINE LINE
-  * @{
-  */
-#define LL_EXTI_LINE_0                 EXTI_IMR_IM0           /*!< Extended line 0 */
-#define LL_EXTI_LINE_1                 EXTI_IMR_IM1           /*!< Extended line 1 */
-#define LL_EXTI_LINE_2                 EXTI_IMR_IM2           /*!< Extended line 2 */
-#define LL_EXTI_LINE_3                 EXTI_IMR_IM3           /*!< Extended line 3 */
-#define LL_EXTI_LINE_4                 EXTI_IMR_IM4           /*!< Extended line 4 */
-#define LL_EXTI_LINE_5                 EXTI_IMR_IM5           /*!< Extended line 5 */
-#define LL_EXTI_LINE_6                 EXTI_IMR_IM6           /*!< Extended line 6 */
-#define LL_EXTI_LINE_7                 EXTI_IMR_IM7           /*!< Extended line 7 */
-#define LL_EXTI_LINE_8                 EXTI_IMR_IM8           /*!< Extended line 8 */
-#define LL_EXTI_LINE_9                 EXTI_IMR_IM9           /*!< Extended line 9 */
-#define LL_EXTI_LINE_10                EXTI_IMR_IM10          /*!< Extended line 10 */
-#define LL_EXTI_LINE_11                EXTI_IMR_IM11          /*!< Extended line 11 */
-#define LL_EXTI_LINE_12                EXTI_IMR_IM12          /*!< Extended line 12 */
-#define LL_EXTI_LINE_13                EXTI_IMR_IM13          /*!< Extended line 13 */
-#define LL_EXTI_LINE_14                EXTI_IMR_IM14          /*!< Extended line 14 */
-#define LL_EXTI_LINE_15                EXTI_IMR_IM15          /*!< Extended line 15 */
-#if defined(EXTI_IMR_IM16)
-#define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
-#endif
-#define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
-#if defined(EXTI_IMR_IM18)
-#define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
-#endif
-#define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
-#if defined(EXTI_IMR_IM20)
-#define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
-#endif
-#if defined(EXTI_IMR_IM21)
-#define LL_EXTI_LINE_21                EXTI_IMR_IM21          /*!< Extended line 21 */
-#endif
-#if defined(EXTI_IMR_IM22)
-#define LL_EXTI_LINE_22                EXTI_IMR_IM22          /*!< Extended line 22 */
-#endif
-#define LL_EXTI_LINE_23                EXTI_IMR_IM23          /*!< Extended line 23 */
-#if defined(EXTI_IMR_IM24)
-#define LL_EXTI_LINE_24                EXTI_IMR_IM24          /*!< Extended line 24 */
-#endif
-#if defined(EXTI_IMR_IM25)
-#define LL_EXTI_LINE_25                EXTI_IMR_IM25          /*!< Extended line 25 */
-#endif
-#if defined(EXTI_IMR_IM26)
-#define LL_EXTI_LINE_26                EXTI_IMR_IM26          /*!< Extended line 26 */
-#endif
-#if defined(EXTI_IMR_IM27)
-#define LL_EXTI_LINE_27                EXTI_IMR_IM27          /*!< Extended line 27 */
-#endif
-#if defined(EXTI_IMR_IM28)
-#define LL_EXTI_LINE_28                EXTI_IMR_IM28          /*!< Extended line 28 */
-#endif
-#if defined(EXTI_IMR_IM29)
-#define LL_EXTI_LINE_29                EXTI_IMR_IM29          /*!< Extended line 29 */
-#endif
-#if defined(EXTI_IMR_IM30)
-#define LL_EXTI_LINE_30                EXTI_IMR_IM30          /*!< Extended line 30 */
-#endif
-#if defined(EXTI_IMR_IM31)
-#define LL_EXTI_LINE_31                EXTI_IMR_IM31          /*!< Extended line 31 */
-#endif
-#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
-
-
-#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)          /*!< All Extended line */
-
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_EXTI_LINE_NONE              (0x00000000U)          /*!< None Extended line */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup EXTI_LL_EC_MODE Mode
-  * @{
-  */
-#define LL_EXTI_MODE_IT                 (0x00U) /*!< Interrupt Mode */
-#define LL_EXTI_MODE_EVENT              (0x01U) /*!< Event Mode */
-#define LL_EXTI_MODE_IT_EVENT           (0x02U) /*!< Interrupt & Event Mode */
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
-  * @{
-  */
-#define LL_EXTI_TRIGGER_NONE            (0x00U) /*!< No Trigger Mode */
-#define LL_EXTI_TRIGGER_RISING          (0x01U) /*!< Trigger Rising Mode */
-#define LL_EXTI_TRIGGER_FALLING         (0x02U) /*!< Trigger Falling Mode */
-#define LL_EXTI_TRIGGER_RISING_FALLING  (0x03U) /*!< Trigger Rising & Falling Mode */
-
-/**
-  * @}
-  */
-
-
-#endif /*USE_FULL_LL_DRIVER*/
-
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
-  * @{
-  */
-
-/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in EXTI register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in EXTI register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
- * @{
- */
-/** @defgroup EXTI_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
-  * @note The reset value for the direct or internal lines (see RM)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR         IMx           LL_EXTI_EnableIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->IMR, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
-  * @note The reset value for the direct or internal lines (see RM)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR         IMx           LL_EXTI_DisableIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->IMR, ExtiLine);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
-  * @note The reset value for the direct or internal lines (see RM)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR         IMx           LL_EXTI_IsEnabledIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Event_Management Event_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
-  * @rmtoll EMR         EMx           LL_EXTI_EnableEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->EMR, ExtiLine);
-
-}
-
-
-/**
-  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
-  * @rmtoll EMR         EMx           LL_EXTI_DisableEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->EMR, ExtiLine);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
-  * @rmtoll EMR         EMx           LL_EXTI_IsEnabledEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
-
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR        RTx           LL_EXTI_EnableRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-
-/**
-  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR        RTx           LL_EXTI_DisableRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-
-/**
-  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
-  * @rmtoll RTSR        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll FTSR        FTx           LL_EXTI_EnableFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->FTSR, ExtiLine);
-}
-
-
-/**
-  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a Falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for the same interrupt line.
-  *       In this case, both generate a trigger condition.
-  * @rmtoll FTSR        FTx           LL_EXTI_DisableFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->FTSR, ExtiLine);
-}
-
-
-/**
-  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
-  * @rmtoll FTSR        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
-  * @{
-  */
-
-/**
-  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
-  * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
-  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
-  *       resulting in an interrupt request generation.
-  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
-  *       register (by writing a 1 into the bit)
-  * @rmtoll SWIER       SWIx          LL_EXTI_GenerateSWI_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->SWIER, ExtiLine);
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR          PIFx           LL_EXTI_IsActiveFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
-  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR          PIFx           LL_EXTI_ReadFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
-}
-
-
-/**
-  * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR          PIFx           LL_EXTI_ClearFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->PR, ExtiLine);
-}
-
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-uint32_t LL_EXTI_DeInit(void);
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* EXTI */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_EXTI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h
deleted file mode 100644
index eb22b63e59..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h
+++ /dev/null
@@ -1,945 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_gpio.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_GPIO_H
-#define __STM32L0xx_LL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH)
-
-/** @defgroup GPIO_LL GPIO
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
-  * @{
-  */
-
-/**
-  * @brief LL GPIO Init Structure definition
-  */
-typedef struct
-{
-  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
-                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
-
-  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
-
-  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
-
-  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
-
-  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
-
-  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_AF.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
-} LL_GPIO_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EC_PIN PIN
-  * @{
-  */
-#define LL_GPIO_PIN_0                      GPIO_BSRR_BS_0 /*!< Select pin 0 */
-#define LL_GPIO_PIN_1                      GPIO_BSRR_BS_1 /*!< Select pin 1 */
-#define LL_GPIO_PIN_2                      GPIO_BSRR_BS_2 /*!< Select pin 2 */
-#define LL_GPIO_PIN_3                      GPIO_BSRR_BS_3 /*!< Select pin 3 */
-#define LL_GPIO_PIN_4                      GPIO_BSRR_BS_4 /*!< Select pin 4 */
-#define LL_GPIO_PIN_5                      GPIO_BSRR_BS_5 /*!< Select pin 5 */
-#define LL_GPIO_PIN_6                      GPIO_BSRR_BS_6 /*!< Select pin 6 */
-#define LL_GPIO_PIN_7                      GPIO_BSRR_BS_7 /*!< Select pin 7 */
-#define LL_GPIO_PIN_8                      GPIO_BSRR_BS_8 /*!< Select pin 8 */
-#define LL_GPIO_PIN_9                      GPIO_BSRR_BS_9 /*!< Select pin 9 */
-#define LL_GPIO_PIN_10                     GPIO_BSRR_BS_10 /*!< Select pin 10 */
-#define LL_GPIO_PIN_11                     GPIO_BSRR_BS_11 /*!< Select pin 11 */
-#define LL_GPIO_PIN_12                     GPIO_BSRR_BS_12 /*!< Select pin 12 */
-#define LL_GPIO_PIN_13                     GPIO_BSRR_BS_13 /*!< Select pin 13 */
-#define LL_GPIO_PIN_14                     GPIO_BSRR_BS_14 /*!< Select pin 14 */
-#define LL_GPIO_PIN_15                     GPIO_BSRR_BS_15 /*!< Select pin 15 */
-#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1  | GPIO_BSRR_BS_2  | \
-                                           GPIO_BSRR_BS_3  | GPIO_BSRR_BS_4  | GPIO_BSRR_BS_5  | \
-                                           GPIO_BSRR_BS_6  | GPIO_BSRR_BS_7  | GPIO_BSRR_BS_8  | \
-                                           GPIO_BSRR_BS_9  | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
-                                           GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
-                                           GPIO_BSRR_BS_15) /*!< Select all pins */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_MODE Mode
-  * @{
-  */
-#define LL_GPIO_MODE_INPUT                 (0x00000000U)       /*!< Select input mode */
-#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
-#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
-#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_OUTPUT Output Type
-  * @{
-  */
-#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U)    /*!< Select push-pull as output type */
-#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_SPEED Output Speed
-  * @{
-  */
-#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U)           /*!< Select I/O low output speed    */
-#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDER_OSPEED0_0 /*!< Select I/O medium output speed */
-#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDER_OSPEED0_1 /*!< Select I/O fast output speed   */
-#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDER_OSPEED0   /*!< Select I/O high output speed   */
-/**
-  * @}
-  */
-#define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
-#define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
-#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
-#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
-
-/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
-  * @{
-  */
-#define LL_GPIO_PULL_NO                    (0x00000000U)      /*!< Select I/O no pull */
-#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
-#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_AF Alternate Function
-  * @{
-  */
-#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
-#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
-#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
-#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
-#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
-#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
-#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
-#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in GPIO register
-  * @param  __INSTANCE__ GPIO Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in GPIO register
-  * @param  __INSTANCE__ GPIO Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
-  * @{
-  */
-
-/**
-  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
-  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_MODE_INPUT
-  *         @arg @ref LL_GPIO_MODE_OUTPUT
-  *         @arg @ref LL_GPIO_MODE_ALTERNATE
-  *         @arg @ref LL_GPIO_MODE_ANALOG
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
-{
-  MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
-}
-
-/**
-  * @brief  Return gpio mode for a dedicated pin on dedicated port.
-  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_MODE_INPUT
-  *         @arg @ref LL_GPIO_MODE_OUTPUT
-  *         @arg @ref LL_GPIO_MODE_ALTERNATE
-  *         @arg @ref LL_GPIO_MODE_ANALOG
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin));
-}
-
-/**
-  * @brief  Configure gpio output type for several pins on dedicated port.
-  * @note   Output type as to be set when gpio pin is in output or
-  *         alternate modes. Possible type are Push-pull or Open-drain.
-  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @param  OutputType This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
-  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
-{
-  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
-}
-
-/**
-  * @brief  Return gpio output type for several pins on dedicated port.
-  * @note   Output type as to be set when gpio pin is in output or
-  *         alternate modes. Possible type are Push-pull or Open-drain.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
-  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
-}
-
-/**
-  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
-  * @note   I/O speed can be Low, Medium, Fast or High speed.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @note   Refer to datasheet for frequency specifications and the power
-  *         supply and load conditions for each speed.
-  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Speed This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
-  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
-  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
-  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
-{
-  MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDER_OSPEED0), ((Pin * Pin) * Speed));
-}
-
-/**
-  * @brief  Return gpio speed for a dedicated pin on dedicated port.
-  * @note   I/O speed can be Low, Medium, Fast or High speed.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @note   Refer to datasheet for frequency specifications and the power
-  *         supply and load conditions for each speed.
-  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
-  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
-  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
-  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDER_OSPEED0)) / (Pin * Pin));
-}
-
-/**
-  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Pull This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PULL_NO
-  *         @arg @ref LL_GPIO_PULL_UP
-  *         @arg @ref LL_GPIO_PULL_DOWN
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
-{
-  MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
-}
-
-/**
-  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_PULL_NO
-  *         @arg @ref LL_GPIO_PULL_UP
-  *         @arg @ref LL_GPIO_PULL_DOWN
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin));
-}
-
-/**
-  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
-  * @note   Possible values are from AF0 to AF7 depending on target.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  * @param  Alternate This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
-  MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
-             ((((Pin * Pin) * Pin) * Pin) * Alternate));
-}
-
-/**
-  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
-  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
-                             ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
-}
-
-/**
-  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
-  * @note   Possible values are from AF0 to AF7 depending on target.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Alternate This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
-  MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
-             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
-}
-
-/**
-  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
-  * @note   Possible values are from AF0 to AF7 depending on target.
-  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
-                             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
-                                 (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
-}
-
-
-/**
-  * @brief  Lock configuration of several pins for a dedicated port.
-  * @note   When the lock sequence has been applied on a port bit, the
-  *         value of this port bit can no longer be modified until the
-  *         next reset.
-  * @note   Each lock bit freezes a specific configuration register
-  *         (control and alternate function registers).
-  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  __IO uint32_t temp;
-  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
-  WRITE_REG(GPIOx->LCKR, PinMask);
-  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
-  /* Read LCKK register. This read is mandatory to complete key lock sequence */
-  temp = READ_REG(GPIOx->LCKR);
-  (void) temp;
-}
-
-/**
-  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
-  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
-}
-
-/**
-  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
-  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
-  * @param  GPIOx GPIO Port
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
-{
-  return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EF_Data_Access Data Access
-  * @{
-  */
-
-/**
-  * @brief  Return full input data register value for a dedicated port.
-  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
-  * @param  GPIOx GPIO Port
-  * @retval Input data register value of port
-  */
-__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
-{
-  return (uint32_t)(READ_REG(GPIOx->IDR));
-}
-
-/**
-  * @brief  Return if input data level for several pins of dedicated port is high or low.
-  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
-}
-
-/**
-  * @brief  Write output data register for the port.
-  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
-  * @param  GPIOx GPIO Port
-  * @param  PortValue Level value for each pin of the port
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
-{
-  WRITE_REG(GPIOx->ODR, PortValue);
-}
-
-/**
-  * @brief  Return full output data register value for a dedicated port.
-  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
-  * @param  GPIOx GPIO Port
-  * @retval Output data register value of port
-  */
-__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
-{
-  return (uint32_t)(READ_REG(GPIOx->ODR));
-}
-
-/**
-  * @brief  Return if input data level for several pins of dedicated port is high or low.
-  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
-}
-
-/**
-  * @brief  Set several pins to high level on dedicated gpio port.
-  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  WRITE_REG(GPIOx->BSRR, PinMask);
-}
-
-/**
-  * @brief  Set several pins to low level on dedicated gpio port.
-  * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  WRITE_REG(GPIOx->BRR, PinMask);
-}
-
-/**
-  * @brief  Toggle data value for several pin of dedicated port.
-  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  uint32_t odr = READ_REG(GPIOx->ODR);
-  WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
-void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH) */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h
deleted file mode 100644
index 5659f3412d..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h
+++ /dev/null
@@ -1,2275 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_i2c.h
-  * @author  MCD Application Team
-  * @brief   Header file of I2C LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_LL_I2C_H
-#define STM32L0xx_LL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (I2C1) || defined (I2C2) || defined (I2C3)
-
-/** @defgroup I2C_LL I2C
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_LL_Private_Constants I2C Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_Private_Macros I2C Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
-  * @{
-  */
-typedef struct
-{
-  uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
-                                     This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetMode(). */
-
-  uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
-                                     This parameter must be set by referring to the STM32CubeMX Tool and
-                                     the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetTiming(). */
-
-  uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
-                                     This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
-
-                                     This feature can be modified afterwards using unitary functions
-                                     @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
-
-  uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
-                                     This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetDigitalFilter(). */
-
-  uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
-                                     This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetOwnAddress1(). */
-
-  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
-                                     match code or next received byte.
-                                     This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_AcknowledgeNextData(). */
-
-  uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
-                                     This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetOwnAddress1(). */
-} LL_I2C_InitTypeDef;
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_I2C_WriteReg function
-  * @{
-  */
-#define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
-#define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
-#define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
-#define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
-#define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
-#define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
-#define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
-#define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
-#define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_I2C_ReadReg function
-  * @{
-  */
-#define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
-#define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
-#define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
-#define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
-#define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
-#define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
-#define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
-#define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
-#define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
-#define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
-#define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
-#define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
-#define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
-#define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
-#define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
-  * @{
-  */
-#define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
-#define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
-#define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
-#define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
-#define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
-#define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
-#define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
-  * @{
-  */
-#define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                 */
-#define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge           */
-#define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode
-                                                                         (Default address not acknowledge)        */
-#define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
-  * @{
-  */
-#define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
-#define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
-  * @{
-  */
-#define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
-#define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
-  * @{
-  */
-#define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
-#define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
-  * @{
-  */
-#define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                 */
-#define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.   */
-#define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done.
-                                                                         All Address2 are acknowledged.        */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
-  * @{
-  */
-#define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
-#define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
-  * @{
-  */
-#define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
-#define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
-  * @{
-  */
-#define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
-#define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_MODE Transfer End Mode
-  * @{
-  */
-#define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD           /*!< Enable I2C Reload mode.     */
-#define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND          /*!< Enable I2C Automatic end mode
-                                                                          with no HW PEC comparison.  */
-#define LL_I2C_MODE_SOFTEND                 0x00000000U              /*!< Enable I2C Software end mode
-                                                                          with no HW PEC comparison.  */
-#define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD       /*!< Enable SMBUS Automatic end mode
-                                                                          with HW PEC comparison.     */
-#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND      /*!< Enable SMBUS Automatic end mode
-                                                                          with HW PEC comparison.     */
-#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND      /*!< Enable SMBUS Software end mode
-                                                                          with HW PEC comparison.     */
-#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
-/*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
-#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
-/*!< Enable SMBUS Software end mode with HW PEC comparison.    */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
-  * @{
-  */
-#define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U
-/*!< Don't Generate Stop and Start condition. */
-#define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)
-/*!< Generate Stop condition (Size should be set to 0).      */
-#define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-/*!< Generate Start for read request. */
-#define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)
-/*!< Generate Start for write request. */
-#define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-/*!< Generate Restart for read request, slave 7Bit address.  */
-#define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)
-/*!< Generate Restart for write request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | \
-                                                       I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
-/*!< Generate Restart for read request, slave 10Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
-/*!< Generate Restart for write request, slave 10Bit address.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
-  * @{
-  */
-#define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master,
-                                                                          slave enters receiver mode.  */
-#define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master,
-                                                                          slave enters transmitter mode.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
-  * @{
-  */
-#define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for
-                                                                          transmission */
-#define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for
-                                                                          reception */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
-  * @{
-  */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect
-                                                                          SCL low level timeout.              */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect
-                                                                          both SCL and SDA high level timeout.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
-  * @{
-  */
-#define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                 /*!< TimeoutA enable bit          */
-#define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                   /*!< TimeoutB (extended clock)
-                                                                                       enable bit                   */
-#define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
-                                                       I2C_TIMEOUTR_TEXTEN)       /*!< TimeoutA and TimeoutB
-(extended clock) enable bits */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
-  * @{
-  */
-
-/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in I2C register
-  * @param  __INSTANCE__ I2C Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in I2C register
-  * @param  __INSTANCE__ I2C Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
-  * @{
-  */
-/**
-  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
-  * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
-  * @param  __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
-                           (tscldel = (SCLDEL+1)xtpresc)
-  * @param  __HOLD_TIME__  This parameter must be a value between Min_Data=0 and Max_Data=0xF.
-                           (tsdadel = SDADELxtpresc)
-  * @param  __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
-                            (tsclh = (SCLH+1)xtpresc)
-  * @param  __SCLL_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF.
-                            (tscll = (SCLL+1)xtpresc)
-  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
-  */
-#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
-  ((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
-   (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
-   (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
-   (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
-   (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
-  * @{
-  */
-
-/** @defgroup I2C_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Enable I2C peripheral (PE = 1).
-  * @rmtoll CR1          PE            LL_I2C_Enable
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
-  * @brief  Disable I2C peripheral (PE = 0).
-  * @note   When PE = 0, the I2C SCL and SDA lines are released.
-  *         Internal state machines and status bits are put back to their reset value.
-  *         When cleared, PE must be kept low for at least 3 APB clock cycles.
-  * @rmtoll CR1          PE            LL_I2C_Disable
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
-  * @brief  Check if the I2C peripheral is enabled or disabled.
-  * @rmtoll CR1          PE            LL_I2C_IsEnabled
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure Noise Filters (Analog and Digital).
-  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
-  *         The filters can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
-  *         CR1          DNF           LL_I2C_ConfigFilters
-  * @param  I2Cx I2C Instance.
-  * @param  AnalogFilter This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
-  *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
-  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
-                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
-  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
-  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
-{
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
-}
-
-/**
-  * @brief  Configure Digital Noise Filter.
-  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
-  *         This filter can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
-  * @param  I2Cx I2C Instance.
-  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
-                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
-  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
-  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
-{
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
-}
-
-/**
-  * @brief  Get the current Digital Noise Filter configuration.
-  * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
-}
-
-/**
-  * @brief  Enable Analog Noise Filter.
-  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
-}
-
-/**
-  * @brief  Disable Analog Noise Filter.
-  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
-}
-
-/**
-  * @brief  Check if Analog Noise Filter is enabled or disabled.
-  * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA transmission requests.
-  * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
-}
-
-/**
-  * @brief  Disable DMA transmission requests.
-  * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
-}
-
-/**
-  * @brief  Check if DMA transmission requests are enabled or disabled.
-  * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA reception requests.
-  * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
-}
-
-/**
-  * @brief  Disable DMA reception requests.
-  * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
-}
-
-/**
-  * @brief  Check if DMA reception requests are enabled or disabled.
-  * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the data register address used for DMA transfer
-  * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
-  *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
-  * @param  I2Cx I2C Instance
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
-  *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
-{
-  uint32_t data_reg_addr;
-
-  if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
-  {
-    /* return address of TXDR register */
-    data_reg_addr = (uint32_t) &(I2Cx->TXDR);
-  }
-  else
-  {
-    /* return address of RXDR register */
-    data_reg_addr = (uint32_t) &(I2Cx->RXDR);
-  }
-
-  return data_reg_addr;
-}
-
-/**
-  * @brief  Enable Clock stretching.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
-  * @brief  Disable Clock stretching.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
-  * @brief  Check if Clock stretching is enabled or disabled.
-  * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable hardware byte control in slave mode.
-  * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
-}
-
-/**
-  * @brief  Disable hardware byte control in slave mode.
-  * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
-}
-
-/**
-  * @brief  Check if hardware byte control in slave mode is enabled or disabled.
-  * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Wakeup from STOP.
-  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
-  *         WakeUpFromStop feature is supported by the I2Cx Instance.
-  * @note   This bit can only be programmed when Digital Filter is disabled.
-  * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
-}
-
-/**
-  * @brief  Disable Wakeup from STOP.
-  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
-  *         WakeUpFromStop feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
-}
-
-/**
-  * @brief  Check if Wakeup from STOP is enabled or disabled.
-  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
-  *         WakeUpFromStop feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable General Call.
-  * @note   When enabled the Address 0x00 is ACKed.
-  * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
-}
-
-/**
-  * @brief  Disable General Call.
-  * @note   When disabled the Address 0x00 is NACKed.
-  * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
-}
-
-/**
-  * @brief  Check if General Call is enabled or disabled.
-  * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
-  * @note   Changing this bit is not allowed, when the START bit is set.
-  * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
-  * @param  I2Cx I2C Instance.
-  * @param  AddressingMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
-  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
-}
-
-/**
-  * @brief  Get the Master addressing mode.
-  * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
-  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
-}
-
-/**
-  * @brief  Set the Own Address1.
-  * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
-  *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
-  * @param  OwnAddrSize This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
-  *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
-{
-  MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
-}
-
-/**
-  * @brief  Enable acknowledge on Own Address1 match address.
-  * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
-}
-
-/**
-  * @brief  Disable acknowledge on Own Address1 match address.
-  * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
-}
-
-/**
-  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
-  * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the 7bits Own Address2.
-  * @note   This action has no effect if own address2 is enabled.
-  * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
-  *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
-  * @param  OwnAddrMask This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
-{
-  MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
-}
-
-/**
-  * @brief  Enable acknowledge on Own Address2 match address.
-  * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
-}
-
-/**
-  * @brief  Disable  acknowledge on Own Address2 match address.
-  * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
-}
-
-/**
-  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
-  * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
-  * @param  I2Cx I2C Instance.
-  * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
-  * @note   This parameter is computed with the STM32CubeMX Tool.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
-{
-  WRITE_REG(I2Cx->TIMINGR, Timing);
-}
-
-/**
-  * @brief  Get the Timing Prescaler setting.
-  * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
-}
-
-/**
-  * @brief  Get the SCL low period setting.
-  * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
-}
-
-/**
-  * @brief  Get the SCL high period setting.
-  * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
-}
-
-/**
-  * @brief  Get the SDA hold time.
-  * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
-}
-
-/**
-  * @brief  Get the SDA setup time.
-  * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
-}
-
-/**
-  * @brief  Configure peripheral mode.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
-  *         CR1          SMBDEN        LL_I2C_SetMode
-  * @param  I2Cx I2C Instance.
-  * @param  PeripheralMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_MODE_I2C
-  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
-{
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
-}
-
-/**
-  * @brief  Get peripheral mode.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
-  *         CR1          SMBDEN        LL_I2C_GetMode
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_MODE_I2C
-  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
-}
-
-/**
-  * @brief  Enable SMBus alert (Host or Device mode)
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   SMBus Device mode:
-  *         - SMBus Alert pin is drived low and
-  *           Alert Response Address Header acknowledge is enabled.
-  *         SMBus Host mode:
-  *         - SMBus Alert pin management is supported.
-  * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
-}
-
-/**
-  * @brief  Disable SMBus alert (Host or Device mode)
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   SMBus Device mode:
-  *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
-  *           Alert Response Address Header acknowledge is disabled.
-  *         SMBus Host mode:
-  *         - SMBus Alert pin management is not supported.
-  * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
-}
-
-/**
-  * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable SMBus Packet Error Calculation (PEC).
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
-}
-
-/**
-  * @brief  Disable SMBus Packet Error Calculation (PEC).
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
-}
-
-/**
-  * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the SMBus Clock Timeout.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
-  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
-  *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
-  *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
-  * @param  I2Cx I2C Instance.
-  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
-  * @param  TimeoutAMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
-  * @param  TimeoutB
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
-                                               uint32_t TimeoutB)
-{
-  MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
-             TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
-}
-
-/**
-  * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   These bits can only be programmed when TimeoutA is disabled.
-  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
-  * @param  I2Cx I2C Instance.
-  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
-{
-  WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
-}
-
-/**
-  * @brief  Get the SMBus Clock TimeoutA setting.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
-}
-
-/**
-  * @brief  Set the SMBus Clock TimeoutA mode.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   This bit can only be programmed when TimeoutA is disabled.
-  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
-  * @param  I2Cx I2C Instance.
-  * @param  TimeoutAMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
-{
-  WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
-}
-
-/**
-  * @brief  Get the SMBus Clock TimeoutA mode.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
-}
-
-/**
-  * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   These bits can only be programmed when TimeoutB is disabled.
-  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
-  * @param  I2Cx I2C Instance.
-  * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
-{
-  WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
-}
-
-/**
-  * @brief  Get the SMBus Extended Cumulative Clock TimeoutB setting.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
-}
-
-/**
-  * @brief  Enable the SMBus Clock Timeout.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
-  *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
-  * @param  I2Cx I2C Instance.
-  * @param  ClockTimeout This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
-  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
-{
-  SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
-}
-
-/**
-  * @brief  Disable the SMBus Clock Timeout.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
-  *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
-  * @param  I2Cx I2C Instance.
-  * @param  ClockTimeout This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
-  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
-{
-  CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
-}
-
-/**
-  * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
-  *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
-  * @param  I2Cx I2C Instance.
-  * @param  ClockTimeout This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
-  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
-{
-  return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
-           (ClockTimeout)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable TXIS interrupt.
-  * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
-}
-
-/**
-  * @brief  Disable TXIS interrupt.
-  * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
-}
-
-/**
-  * @brief  Check if the TXIS Interrupt is enabled or disabled.
-  * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable RXNE interrupt.
-  * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
-}
-
-/**
-  * @brief  Disable RXNE interrupt.
-  * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
-}
-
-/**
-  * @brief  Check if the RXNE Interrupt is enabled or disabled.
-  * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Address match interrupt (slave mode only).
-  * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
-}
-
-/**
-  * @brief  Disable Address match interrupt (slave mode only).
-  * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
-}
-
-/**
-  * @brief  Check if Address match interrupt is enabled or disabled.
-  * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Not acknowledge received interrupt.
-  * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
-}
-
-/**
-  * @brief  Disable Not acknowledge received interrupt.
-  * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
-}
-
-/**
-  * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
-  * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable STOP detection interrupt.
-  * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
-}
-
-/**
-  * @brief  Disable STOP detection interrupt.
-  * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
-}
-
-/**
-  * @brief  Check if STOP detection interrupt is enabled or disabled.
-  * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Transfer Complete interrupt.
-  * @note   Any of these events will generate interrupt :
-  *         Transfer Complete (TC)
-  *         Transfer Complete Reload (TCR)
-  * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
-}
-
-/**
-  * @brief  Disable Transfer Complete interrupt.
-  * @note   Any of these events will generate interrupt :
-  *         Transfer Complete (TC)
-  *         Transfer Complete Reload (TCR)
-  * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
-}
-
-/**
-  * @brief  Check if Transfer Complete interrupt is enabled or disabled.
-  * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Error interrupts.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   Any of these errors will generate interrupt :
-  *         Arbitration Loss (ARLO)
-  *         Bus Error detection (BERR)
-  *         Overrun/Underrun (OVR)
-  *         SMBus Timeout detection (TIMEOUT)
-  *         SMBus PEC error detection (PECERR)
-  *         SMBus Alert pin event detection (ALERT)
-  * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
-}
-
-/**
-  * @brief  Disable Error interrupts.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   Any of these errors will generate interrupt :
-  *         Arbitration Loss (ARLO)
-  *         Bus Error detection (BERR)
-  *         Overrun/Underrun (OVR)
-  *         SMBus Timeout detection (TIMEOUT)
-  *         SMBus PEC error detection (PECERR)
-  *         SMBus Alert pin event detection (ALERT)
-  * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
-}
-
-/**
-  * @brief  Check if Error interrupts are enabled or disabled.
-  * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
-  * @{
-  */
-
-/**
-  * @brief  Indicate the status of Transmit data register empty flag.
-  * @note   RESET: When next data is written in Transmit data register.
-  *         SET: When Transmit data register is empty.
-  * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Transmit interrupt flag.
-  * @note   RESET: When next data is written in Transmit data register.
-  *         SET: When Transmit data register is empty.
-  * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Receive data register not empty flag.
-  * @note   RESET: When Receive data register is read.
-  *         SET: When the received data is copied in Receive data register.
-  * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Address matched flag (slave mode).
-  * @note   RESET: Clear default value.
-  *         SET: When the received slave address matched with one of the enabled slave address.
-  * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Not Acknowledge received flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a NACK is received after a byte transmission.
-  * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Stop detection flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a Stop condition is detected.
-  * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Transfer complete flag (master mode).
-  * @note   RESET: Clear default value.
-  *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
-  * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Transfer complete flag (master mode).
-  * @note   RESET: Clear default value.
-  *         SET: When RELOAD=1 and NBYTES date have been transferred.
-  * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Bus error flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a misplaced Start or Stop condition is detected.
-  * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Arbitration lost flag.
-  * @note   RESET: Clear default value.
-  *         SET: When arbitration lost.
-  * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
-  * @note   RESET: Clear default value.
-  *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
-  * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of SMBus PEC error flag in reception.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   RESET: Clear default value.
-  *         SET: When the received PEC does not match with the PEC register content.
-  * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of SMBus Timeout detection flag.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   RESET: Clear default value.
-  *         SET: When a timeout or extended clock timeout occurs.
-  * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of SMBus alert flag.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   RESET: Clear default value.
-  *         SET: When SMBus host configuration, SMBus alert enabled and
-  *              a falling edge event occurs on SMBA pin.
-  * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Bus Busy flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a Start condition is detected.
-  * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear Address Matched flag.
-  * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
-}
-
-/**
-  * @brief  Clear Not Acknowledge flag.
-  * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
-}
-
-/**
-  * @brief  Clear Stop detection flag.
-  * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
-}
-
-/**
-  * @brief  Clear Transmit data register empty flag (TXE).
-  * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
-  * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
-{
-  WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
-}
-
-/**
-  * @brief  Clear Bus error flag.
-  * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
-}
-
-/**
-  * @brief  Clear Arbitration lost flag.
-  * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
-}
-
-/**
-  * @brief  Clear Overrun/Underrun flag.
-  * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
-}
-
-/**
-  * @brief  Clear SMBus PEC error flag.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
-}
-
-/**
-  * @brief  Clear SMBus Timeout detection flag.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
-}
-
-/**
-  * @brief  Clear SMBus Alert flag.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable automatic STOP condition generation (master mode).
-  * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
-  *         This bit has no effect in slave mode or when RELOAD bit is set.
-  * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
-}
-
-/**
-  * @brief  Disable automatic STOP condition generation (master mode).
-  * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
-  * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
-}
-
-/**
-  * @brief  Check if automatic STOP condition is enabled or disabled.
-  * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable reload mode (master mode).
-  * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
-  * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
-}
-
-/**
-  * @brief  Disable reload mode (master mode).
-  * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
-  * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
-}
-
-/**
-  * @brief  Check if reload mode is enabled or disabled.
-  * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the number of bytes for transfer.
-  * @note   Changing these bits when START bit is set is not allowed.
-  * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
-  * @param  I2Cx I2C Instance.
-  * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
-}
-
-/**
-  * @brief  Get the number of bytes configured for transfer.
-  * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
-}
-
-/**
-  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
-            or next received byte.
-  * @note   Usage in Slave mode only.
-  * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
-  * @param  I2Cx I2C Instance.
-  * @param  TypeAcknowledge This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ACK
-  *         @arg @ref LL_I2C_NACK
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
-}
-
-/**
-  * @brief  Generate a START or RESTART condition
-  * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
-  *         This action has no effect when RELOAD is set.
-  * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_START);
-}
-
-/**
-  * @brief  Generate a STOP condition after the current byte transfer (master mode).
-  * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
-}
-
-/**
-  * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
-  * @note   The master sends the complete 10bit slave address read sequence :
-  *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
-            in Read direction.
-  * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
-}
-
-/**
-  * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
-  * @note   The master only sends the first 7 bits of 10bit address in Read direction.
-  * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
-}
-
-/**
-  * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
-  * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the transfer direction (master mode).
-  * @note   Changing these bits when START bit is set is not allowed.
-  * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
-  * @param  I2Cx I2C Instance.
-  * @param  TransferRequest This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_REQUEST_WRITE
-  *         @arg @ref LL_I2C_REQUEST_READ
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
-}
-
-/**
-  * @brief  Get the transfer direction requested (master mode).
-  * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_REQUEST_WRITE
-  *         @arg @ref LL_I2C_REQUEST_READ
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
-}
-
-/**
-  * @brief  Configure the slave address for transfer (master mode).
-  * @note   Changing these bits when START bit is set is not allowed.
-  * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
-  * @param  I2Cx I2C Instance.
-  * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
-}
-
-/**
-  * @brief  Get the slave address programmed for transfer.
-  * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0x3F
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
-}
-
-/**
-  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
-  * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
-  *         CR2          ADD10         LL_I2C_HandleTransfer\n
-  *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
-  *         CR2          START         LL_I2C_HandleTransfer\n
-  *         CR2          STOP          LL_I2C_HandleTransfer\n
-  *         CR2          RELOAD        LL_I2C_HandleTransfer\n
-  *         CR2          NBYTES        LL_I2C_HandleTransfer\n
-  *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
-  *         CR2          HEAD10R       LL_I2C_HandleTransfer
-  * @param  I2Cx I2C Instance.
-  * @param  SlaveAddr Specifies the slave address to be programmed.
-  * @param  SlaveAddrSize This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
-  *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
-  * @param  TransferSize Specifies the number of bytes to be programmed.
-  *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
-  * @param  EndMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_MODE_RELOAD
-  *         @arg @ref LL_I2C_MODE_AUTOEND
-  *         @arg @ref LL_I2C_MODE_SOFTEND
-  *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
-  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
-  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
-  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
-  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
-  * @param  Request This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
-  *         @arg @ref LL_I2C_GENERATE_STOP
-  *         @arg @ref LL_I2C_GENERATE_START_READ
-  *         @arg @ref LL_I2C_GENERATE_START_WRITE
-  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
-  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
-  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
-  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
-                                           uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
-             (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
-             I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
-             I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
-             SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
-}
-
-/**
-  * @brief  Indicate the value of transfer direction (slave mode).
-  * @note   RESET: Write transfer, Slave enters in receiver mode.
-  *         SET: Read transfer, Slave enters in transmitter mode.
-  * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_DIRECTION_WRITE
-  *         @arg @ref LL_I2C_DIRECTION_READ
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
-}
-
-/**
-  * @brief  Return the slave matched address.
-  * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
-}
-
-/**
-  * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
-            or an Address Matched is received.
-  *         This bit has no effect when RELOAD bit is set.
-  *         This bit has no effect in device mode when SBC bit is not set.
-  * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
-}
-
-/**
-  * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the SMBus Packet Error byte calculated.
-  * @note   The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
-}
-
-/**
-  * @brief  Read Receive Data register.
-  * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
-{
-  return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
-}
-
-/**
-  * @brief  Write in Transmit Data Register .
-  * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
-  * @param  I2Cx I2C Instance.
-  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
-{
-  WRITE_REG(I2Cx->TXDR, Data);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
-void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
-
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* I2C1 || I2C2 || I2C3 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_LL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_iwdg.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_iwdg.h
deleted file mode 100644
index b41930e040..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_iwdg.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_iwdg.h
-  * @author  MCD Application Team
-  * @brief   Header file of IWDG LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_LL_IWDG_H
-#define STM32L0xx_LL_IWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined(IWDG)
-
-/** @defgroup IWDG_LL IWDG
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
-  * @{
-  */
-#define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
-#define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
-#define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
-#define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
-  * @{
-  */
-#define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
-#define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
-#define LL_IWDG_SR_WVU                     IWDG_SR_WVU                           /*!< Watchdog counter window value update */
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
-  * @{
-  */
-#define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */
-#define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
-#define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
-#define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */
-#define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */
-#define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */
-#define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
-  * @{
-  */
-
-/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in IWDG register
-  * @param  __INSTANCE__ IWDG Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in IWDG register
-  * @param  __INSTANCE__ IWDG Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
-  * @{
-  */
-/** @defgroup IWDG_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Start the Independent Watchdog
-  * @note   Except if the hardware watchdog option is selected
-  * @rmtoll KR           KEY           LL_IWDG_Enable
-  * @param  IWDGx IWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
-{
-  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
-}
-
-/**
-  * @brief  Reloads IWDG counter with value defined in the reload register
-  * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
-  * @param  IWDGx IWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
-{
-  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
-}
-
-/**
-  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
-  * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
-  * @param  IWDGx IWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
-{
-  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
-}
-
-/**
-  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
-  * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
-  * @param  IWDGx IWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
-{
-  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
-}
-
-/**
-  * @brief  Select the prescaler of the IWDG
-  * @rmtoll PR           PR            LL_IWDG_SetPrescaler
-  * @param  IWDGx IWDG Instance
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_IWDG_PRESCALER_4
-  *         @arg @ref LL_IWDG_PRESCALER_8
-  *         @arg @ref LL_IWDG_PRESCALER_16
-  *         @arg @ref LL_IWDG_PRESCALER_32
-  *         @arg @ref LL_IWDG_PRESCALER_64
-  *         @arg @ref LL_IWDG_PRESCALER_128
-  *         @arg @ref LL_IWDG_PRESCALER_256
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
-{
-  WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
-}
-
-/**
-  * @brief  Get the selected prescaler of the IWDG
-  * @rmtoll PR           PR            LL_IWDG_GetPrescaler
-  * @param  IWDGx IWDG Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_IWDG_PRESCALER_4
-  *         @arg @ref LL_IWDG_PRESCALER_8
-  *         @arg @ref LL_IWDG_PRESCALER_16
-  *         @arg @ref LL_IWDG_PRESCALER_32
-  *         @arg @ref LL_IWDG_PRESCALER_64
-  *         @arg @ref LL_IWDG_PRESCALER_128
-  *         @arg @ref LL_IWDG_PRESCALER_256
-  */
-__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
-{
-  return (READ_REG(IWDGx->PR));
-}
-
-/**
-  * @brief  Specify the IWDG down-counter reload value
-  * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
-  * @param  IWDGx IWDG Instance
-  * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
-{
-  WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
-}
-
-/**
-  * @brief  Get the specified IWDG down-counter reload value
-  * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
-  * @param  IWDGx IWDG Instance
-  * @retval Value between Min_Data=0 and Max_Data=0x0FFF
-  */
-__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
-{
-  return (READ_REG(IWDGx->RLR));
-}
-
-/**
-  * @brief  Specify high limit of the window value to be compared to the down-counter.
-  * @rmtoll WINR         WIN           LL_IWDG_SetWindow
-  * @param  IWDGx IWDG Instance
-  * @param  Window Value between Min_Data=0 and Max_Data=0x0FFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
-{
-  WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
-}
-
-/**
-  * @brief  Get the high limit of the window value specified.
-  * @rmtoll WINR         WIN           LL_IWDG_GetWindow
-  * @param  IWDGx IWDG Instance
-  * @retval Value between Min_Data=0 and Max_Data=0x0FFF
-  */
-__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
-{
-  return (READ_REG(IWDGx->WINR));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if flag Prescaler Value Update is set or not
-  * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
-  * @param  IWDGx IWDG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
-{
-  return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if flag Reload Value Update is set or not
-  * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
-  * @param  IWDGx IWDG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
-{
-  return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if flag Window Value Update is set or not
-  * @rmtoll SR           WVU           LL_IWDG_IsActiveFlag_WVU
-  * @param  IWDGx IWDG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
-{
-  return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if all flags Prescaler, Reload & Window Value Update are reset or not
-  * @rmtoll SR           PVU           LL_IWDG_IsReady\n
-  *         SR           RVU           LL_IWDG_IsReady\n
-  *         SR           WVU           LL_IWDG_IsReady
-  * @param  IWDGx IWDG Instance
-  * @retval State of bits (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
-{
-  return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* IWDG */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_LL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h
deleted file mode 100644
index c831f50fe1..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h
+++ /dev/null
@@ -1,1370 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_lptim.h
-  * @author  MCD Application Team
-  * @brief   Header file of LPTIM LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_LL_LPTIM_H
-#define STM32L0xx_LL_LPTIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (LPTIM1)
-
-/** @defgroup LPTIM_LL LPTIM
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  LPTIM Init structure definition
-  */
-typedef struct
-{
-  uint32_t ClockSource;    /*!< Specifies the source of the clock used by the LPTIM instance.
-                                This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
-
-                                This feature can be modified afterwards using unitary
-                                function @ref LL_LPTIM_SetClockSource().*/
-
-  uint32_t Prescaler;      /*!< Specifies the prescaler division ratio.
-                                This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
-
-                                This feature can be modified afterwards using using unitary
-                                function @ref LL_LPTIM_SetPrescaler().*/
-
-  uint32_t Waveform;       /*!< Specifies the waveform shape.
-                                This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
-
-                                This feature can be modified afterwards using unitary
-                                function @ref LL_LPTIM_ConfigOutput().*/
-
-  uint32_t Polarity;       /*!< Specifies waveform polarity.
-                                This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
-
-                                This feature can be modified afterwards using unitary
-                                function @ref LL_LPTIM_ConfigOutput().*/
-} LL_LPTIM_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
-  * @{
-  */
-
-/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_LPTIM_ReadReg function
-  * @{
-  */
-#define LL_LPTIM_ISR_CMPM                     LPTIM_ISR_CMPM     /*!< Compare match */
-#define LL_LPTIM_ISR_CMPOK                    LPTIM_ISR_CMPOK    /*!< Compare register update OK */
-#define LL_LPTIM_ISR_ARRM                     LPTIM_ISR_ARRM     /*!< Autoreload match */
-#define LL_LPTIM_ISR_EXTTRIG                  LPTIM_ISR_EXTTRIG  /*!< External trigger edge event */
-#define LL_LPTIM_ISR_ARROK                    LPTIM_ISR_ARROK    /*!< Autoreload register update OK */
-#define LL_LPTIM_ISR_UP                       LPTIM_ISR_UP       /*!< Counter direction change down to up */
-#define LL_LPTIM_ISR_DOWN                     LPTIM_ISR_DOWN     /*!< Counter direction change up to down */
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_LPTIM_ReadReg and  LL_LPTIM_WriteReg functions
-  * @{
-  */
-#define LL_LPTIM_IER_CMPMIE                   LPTIM_IER_CMPMIE     /*!< Compare match */
-#define LL_LPTIM_IER_CMPOKIE                  LPTIM_IER_CMPOKIE    /*!< Compare register update OK */
-#define LL_LPTIM_IER_ARRMIE                   LPTIM_IER_ARRMIE     /*!< Autoreload match */
-#define LL_LPTIM_IER_EXTTRIGIE                LPTIM_IER_EXTTRIGIE  /*!< External trigger edge event */
-#define LL_LPTIM_IER_ARROKIE                  LPTIM_IER_ARROKIE    /*!< Autoreload register update OK */
-#define LL_LPTIM_IER_UPIE                     LPTIM_IER_UPIE       /*!< Counter direction change down to up */
-#define LL_LPTIM_IER_DOWNIE                   LPTIM_IER_DOWNIE     /*!< Counter direction change up to down */
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
-  * @{
-  */
-#define LL_LPTIM_OPERATING_MODE_CONTINUOUS    LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
-#define LL_LPTIM_OPERATING_MODE_ONESHOT       LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
-  * @{
-  */
-#define LL_LPTIM_UPDATE_MODE_IMMEDIATE        0x00000000U        /*!<Preload is disabled: registers are updated after each APB bus write access*/
-#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD      LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
-  * @{
-  */
-#define LL_LPTIM_COUNTER_MODE_INTERNAL        0x00000000U          /*!<The counter is incremented following each internal clock pulse*/
-#define LL_LPTIM_COUNTER_MODE_EXTERNAL        LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
-  * @{
-  */
-#define LL_LPTIM_OUTPUT_WAVEFORM_PWM          0x00000000U     /*!<LPTIM  generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
-#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE      LPTIM_CFGR_WAVE /*!<LPTIM  generates a Set Once waveform*/
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
-  * @{
-  */
-#define LL_LPTIM_OUTPUT_POLARITY_REGULAR      0x00000000U             /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
-#define LL_LPTIM_OUTPUT_POLARITY_INVERSE      LPTIM_CFGR_WAVPOL       /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
-  * @{
-  */
-#define LL_LPTIM_PRESCALER_DIV1               0x00000000U                               /*!<Prescaler division factor is set to 1*/
-#define LL_LPTIM_PRESCALER_DIV2               LPTIM_CFGR_PRESC_0                        /*!<Prescaler division factor is set to 2*/
-#define LL_LPTIM_PRESCALER_DIV4               LPTIM_CFGR_PRESC_1                        /*!<Prescaler division factor is set to 4*/
-#define LL_LPTIM_PRESCALER_DIV8               (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
-#define LL_LPTIM_PRESCALER_DIV16              LPTIM_CFGR_PRESC_2                        /*!<Prescaler division factor is set to 16*/
-#define LL_LPTIM_PRESCALER_DIV32              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
-#define LL_LPTIM_PRESCALER_DIV64              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
-#define LL_LPTIM_PRESCALER_DIV128             LPTIM_CFGR_PRESC                          /*!<Prescaler division factor is set to 128*/
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
-  * @{
-  */
-#define LL_LPTIM_TRIG_SOURCE_GPIO             0x00000000U                                                          /*!<External input trigger is connected to TIMx_ETR input*/
-#define LL_LPTIM_TRIG_SOURCE_RTCALARMA        LPTIM_CFGR_TRIGSEL_0                                                 /*!<External input trigger is connected to RTC Alarm A*/
-#define LL_LPTIM_TRIG_SOURCE_RTCALARMB        LPTIM_CFGR_TRIGSEL_1                                                 /*!<External input trigger is connected to RTC Alarm B*/
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1         (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 1*/
-#endif /* RTC_TAMPER1_SUPPORT */
-#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2         LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to RTC Tamper 2*/
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3         (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 3*/
-#endif /* RTC_TAMPER3_SUPPORT */
-#define LL_LPTIM_TRIG_SOURCE_COMP1            (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)                        /*!<External input trigger is connected to COMP1 output*/
-#define LL_LPTIM_TRIG_SOURCE_COMP2            LPTIM_CFGR_TRIGSEL                                                   /*!<External input trigger is connected to COMP2 output*/
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
-  * @{
-  */
-#define LL_LPTIM_TRIG_FILTER_NONE             0x00000000U         /*!<Any trigger active level change is considered as a valid trigger*/
-#define LL_LPTIM_TRIG_FILTER_2                LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
-#define LL_LPTIM_TRIG_FILTER_4                LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
-#define LL_LPTIM_TRIG_FILTER_8                LPTIM_CFGR_TRGFLT   /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
-  * @{
-  */
-#define LL_LPTIM_TRIG_POLARITY_RISING         LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
-#define LL_LPTIM_TRIG_POLARITY_FALLING        LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
-#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN   /*!<LPTIM counter starts when a rising or a falling edge is detected*/
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
-  * @{
-  */
-#define LL_LPTIM_CLK_SOURCE_INTERNAL          0x00000000U      /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
-#define LL_LPTIM_CLK_SOURCE_EXTERNAL          LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
-  * @{
-  */
-#define LL_LPTIM_CLK_FILTER_NONE              0x00000000U        /*!<Any external clock signal level change is considered as a valid transition*/
-#define LL_LPTIM_CLK_FILTER_2                 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
-#define LL_LPTIM_CLK_FILTER_4                 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
-#define LL_LPTIM_CLK_FILTER_8                 LPTIM_CFGR_CKFLT   /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
-  * @{
-  */
-#define LL_LPTIM_CLK_POLARITY_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
-#define LL_LPTIM_CLK_POLARITY_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
-#define LL_LPTIM_CLK_POLARITY_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
-  * @{
-  */
-#define LL_LPTIM_ENCODER_MODE_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
-#define LL_LPTIM_ENCODER_MODE_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
-#define LL_LPTIM_ENCODER_MODE_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
-  * @{
-  */
-
-/** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in LPTIM register
-  * @param  __INSTANCE__ LPTIM Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in LPTIM register
-  * @param  __INSTANCE__ LPTIM Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
-  * @{
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
-  * @{
-  */
-
-ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
-void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
-ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
-void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
-  * @{
-  */
-
-/**
-  * @brief  Enable the LPTIM instance
-  * @note After setting the ENABLE bit, a delay of two counter clock is needed
-  *       before the LPTIM instance is actually enabled.
-  * @rmtoll CR           ENABLE        LL_LPTIM_Enable
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
-}
-
-/**
-  * @brief  Indicates whether the LPTIM instance is enabled.
-  * @rmtoll CR           ENABLE        LL_LPTIM_IsEnabled
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Starts the LPTIM counter in the desired mode.
-  * @note LPTIM instance must be enabled before starting the counter.
-  * @note It is possible to change on the fly from One Shot mode to
-  *       Continuous mode.
-  * @rmtoll CR           CNTSTRT       LL_LPTIM_StartCounter\n
-  *         CR           SNGSTRT       LL_LPTIM_StartCounter
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  OperatingMode This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
-  *         @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
-{
-  MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
-}
-
-/**
-  * @brief  Set the LPTIM registers update mode (enable/disable register preload)
-  * @note This function must be called when the LPTIM instance is disabled.
-  * @rmtoll CFGR         PRELOAD       LL_LPTIM_SetUpdateMode
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  UpdateMode This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
-  *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
-{
-  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
-}
-
-/**
-  * @brief  Get the LPTIM registers update mode
-  * @rmtoll CFGR         PRELOAD       LL_LPTIM_GetUpdateMode
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
-  *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
-}
-
-/**
-  * @brief  Set the auto reload value
-  * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
-  * @note After a write to the LPTIMx_ARR register a new write operation to the
-  *       same register can only be performed when the previous write operation
-  *       is completed. Any successive write before  the ARROK flag is set, will
-  *       lead to unpredictable results.
-  * @note autoreload value be strictly greater than the compare value.
-  * @rmtoll ARR          ARR           LL_LPTIM_SetAutoReload
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
-{
-  MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
-}
-
-/**
-  * @brief  Get actual auto reload value
-  * @rmtoll ARR          ARR           LL_LPTIM_GetAutoReload
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
-}
-
-/**
-  * @brief  Set the compare value
-  * @note After a write to the LPTIMx_CMP register a new write operation to the
-  *       same register can only be performed when the previous write operation
-  *       is completed. Any successive write before the CMPOK flag is set, will
-  *       lead to unpredictable results.
-  * @rmtoll CMP          CMP           LL_LPTIM_SetCompare
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
-{
-  MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
-}
-
-/**
-  * @brief  Get actual compare value
-  * @rmtoll CMP          CMP           LL_LPTIM_GetCompare
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
-}
-
-/**
-  * @brief  Get actual counter value
-  * @note When the LPTIM instance is running with an asynchronous clock, reading
-  *       the LPTIMx_CNT register may return unreliable values. So in this case
-  *       it is necessary to perform two consecutive read accesses and verify
-  *       that the two returned values are identical.
-  * @rmtoll CNT          CNT           LL_LPTIM_GetCounter
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Counter value
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
-}
-
-/**
-  * @brief  Set the counter mode (selection of the LPTIM counter clock source).
-  * @note The counter mode can be set only when the LPTIM instance is disabled.
-  * @rmtoll CFGR         COUNTMODE     LL_LPTIM_SetCounterMode
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  CounterMode This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
-  *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
-{
-  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
-}
-
-/**
-  * @brief  Get the counter mode
-  * @rmtoll CFGR         COUNTMODE     LL_LPTIM_GetCounterMode
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
-  *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
-}
-
-/**
-  * @brief  Configure the LPTIM instance output (LPTIMx_OUT)
-  * @note This function must be called when the LPTIM instance is disabled.
-  * @note Regarding the LPTIM output polarity the change takes effect
-  *       immediately, so the output default value will change immediately after
-  *       the polarity is re-configured, even before the timer is enabled.
-  * @rmtoll CFGR         WAVE          LL_LPTIM_ConfigOutput\n
-  *         CFGR         WAVPOL        LL_LPTIM_ConfigOutput
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  Waveform This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
-  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
-  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
-{
-  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
-}
-
-/**
-  * @brief  Set  waveform shape
-  * @rmtoll CFGR         WAVE          LL_LPTIM_SetWaveform
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  Waveform This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
-  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
-{
-  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
-}
-
-/**
-  * @brief  Get actual waveform shape
-  * @rmtoll CFGR         WAVE          LL_LPTIM_GetWaveform
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
-  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
-}
-
-/**
-  * @brief  Set  output polarity
-  * @rmtoll CFGR         WAVPOL        LL_LPTIM_SetPolarity
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
-  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
-{
-  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
-}
-
-/**
-  * @brief  Get actual output polarity
-  * @rmtoll CFGR         WAVPOL        LL_LPTIM_GetPolarity
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
-  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
-}
-
-/**
-  * @brief  Set actual prescaler division ratio.
-  * @note This function must be called when the LPTIM instance is disabled.
-  * @note When the LPTIM is configured to be clocked by an internal clock source
-  *       and the LPTIM counter is configured to be updated by active edges
-  *       detected on the LPTIM external Input1, the internal clock provided to
-  *       the LPTIM must be not be prescaled.
-  * @rmtoll CFGR         PRESC         LL_LPTIM_SetPrescaler
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV1
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV2
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV4
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV8
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV16
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV32
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV64
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV128
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
-{
-  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
-}
-
-/**
-  * @brief  Get actual prescaler division ratio.
-  * @rmtoll CFGR         PRESC         LL_LPTIM_GetPrescaler
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV1
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV2
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV4
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV8
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV16
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV32
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV64
-  *         @arg @ref LL_LPTIM_PRESCALER_DIV128
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
-  * @{
-  */
-
-/**
-  * @brief  Enable the timeout function
-  * @note This function must be called when the LPTIM instance is disabled.
-  * @note The first trigger event will start the timer, any successive trigger
-  *       event will reset the counter and the timer will restart.
-  * @note The timeout value corresponds to the compare value; if no trigger
-  *       occurs within the expected time frame, the MCU is waked-up by the
-  *       compare match event.
-  * @rmtoll CFGR         TIMOUT        LL_LPTIM_EnableTimeout
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
-}
-
-/**
-  * @brief  Disable the timeout function
-  * @note This function must be called when the LPTIM instance is disabled.
-  * @note A trigger event arriving when the timer is already started will be
-  *       ignored.
-  * @rmtoll CFGR         TIMOUT        LL_LPTIM_DisableTimeout
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
-{
-  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
-}
-
-/**
-  * @brief  Indicate whether the timeout function is enabled.
-  * @rmtoll CFGR         TIMOUT        LL_LPTIM_IsEnabledTimeout
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Start the LPTIM counter
-  * @note This function must be called when the LPTIM instance is disabled.
-  * @rmtoll CFGR         TRIGEN        LL_LPTIM_TrigSw
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
-{
-  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
-}
-
-/**
-  * @brief  Configure the external trigger used as a trigger event for the LPTIM.
-  * @note This function must be called when the LPTIM instance is disabled.
-  * @note An internal clock source must be present when a digital filter is
-  *       required for the trigger.
-  * @rmtoll CFGR         TRIGSEL       LL_LPTIM_ConfigTrigger\n
-  *         CFGR         TRGFLT        LL_LPTIM_ConfigTrigger\n
-  *         CFGR         TRIGEN        LL_LPTIM_ConfigTrigger
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
-  *
-  *         (*)  Value not defined in all devices. \n
-  *
-  * @param  Filter This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
-  *         @arg @ref LL_LPTIM_TRIG_FILTER_2
-  *         @arg @ref LL_LPTIM_TRIG_FILTER_4
-  *         @arg @ref LL_LPTIM_TRIG_FILTER_8
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
-  *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
-  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
-{
-  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
-}
-
-/**
-  * @brief  Get actual external trigger source.
-  * @rmtoll CFGR         TRIGSEL       LL_LPTIM_GetTriggerSource
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
-  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
-  *
-  *         (*)  Value not defined in all devices. \n
-  *
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
-}
-
-/**
-  * @brief  Get actual external trigger filter.
-  * @rmtoll CFGR         TRGFLT        LL_LPTIM_GetTriggerFilter
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
-  *         @arg @ref LL_LPTIM_TRIG_FILTER_2
-  *         @arg @ref LL_LPTIM_TRIG_FILTER_4
-  *         @arg @ref LL_LPTIM_TRIG_FILTER_8
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
-}
-
-/**
-  * @brief  Get actual external trigger polarity.
-  * @rmtoll CFGR         TRIGEN        LL_LPTIM_GetTriggerPolarity
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
-  *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
-  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
-  * @{
-  */
-
-/**
-  * @brief  Set the source of the clock used by the LPTIM instance.
-  * @note This function must be called when the LPTIM instance is disabled.
-  * @rmtoll CFGR         CKSEL         LL_LPTIM_SetClockSource
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  ClockSource This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
-  *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
-{
-  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
-}
-
-/**
-  * @brief  Get actual LPTIM instance clock source.
-  * @rmtoll CFGR         CKSEL         LL_LPTIM_GetClockSource
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
-  *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
-}
-
-/**
-  * @brief  Configure the active edge or edges used by the counter when
-            the LPTIM is clocked by an external clock source.
-  * @note This function must be called when the LPTIM instance is disabled.
-  * @note When both external clock signal edges are considered active ones,
-  *       the LPTIM must also be clocked by an internal clock source with a
-  *       frequency equal to at least four times the external clock frequency.
-  * @note An internal clock source must be present when a digital filter is
-  *       required for external clock.
-  * @rmtoll CFGR         CKFLT         LL_LPTIM_ConfigClock\n
-  *         CFGR         CKPOL         LL_LPTIM_ConfigClock
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  ClockFilter This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
-  *         @arg @ref LL_LPTIM_CLK_FILTER_2
-  *         @arg @ref LL_LPTIM_CLK_FILTER_4
-  *         @arg @ref LL_LPTIM_CLK_FILTER_8
-  * @param  ClockPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
-  *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
-  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
-{
-  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
-}
-
-/**
-  * @brief  Get actual clock polarity
-  * @rmtoll CFGR         CKPOL         LL_LPTIM_GetClockPolarity
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
-  *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
-  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
-}
-
-/**
-  * @brief  Get actual clock digital filter
-  * @rmtoll CFGR         CKFLT         LL_LPTIM_GetClockFilter
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
-  *         @arg @ref LL_LPTIM_CLK_FILTER_2
-  *         @arg @ref LL_LPTIM_CLK_FILTER_4
-  *         @arg @ref LL_LPTIM_CLK_FILTER_8
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
-  * @{
-  */
-
-/**
-  * @brief  Configure the encoder mode.
-  * @note This function must be called when the LPTIM instance is disabled.
-  * @rmtoll CFGR         CKPOL         LL_LPTIM_SetEncoderMode
-  * @param  LPTIMx Low-Power Timer instance
-  * @param  EncoderMode This parameter can be one of the following values:
-  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
-  *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
-  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
-{
-  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
-}
-
-/**
-  * @brief  Get actual encoder mode.
-  * @rmtoll CFGR         CKPOL         LL_LPTIM_GetEncoderMode
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
-  *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
-  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
-{
-  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
-}
-
-/**
-  * @brief  Enable the encoder mode
-  * @note This function must be called when the LPTIM instance is disabled.
-  * @note In this mode the LPTIM instance must be clocked by an internal clock
-  *       source. Also, the prescaler division ratio must be equal to 1.
-  * @note LPTIM instance must be configured in continuous mode prior enabling
-  *       the encoder mode.
-  * @rmtoll CFGR         ENC           LL_LPTIM_EnableEncoderMode
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
-}
-
-/**
-  * @brief  Disable the encoder mode
-  * @note This function must be called when the LPTIM instance is disabled.
-  * @rmtoll CFGR         ENC           LL_LPTIM_DisableEncoderMode
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
-{
-  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
-}
-
-/**
-  * @brief  Indicates whether the LPTIM operates in encoder mode.
-  * @rmtoll CFGR         ENC           LL_LPTIM_IsEnabledEncoderMode
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Clear the compare match flag (CMPMCF)
-  * @rmtoll ICR          CMPMCF        LL_LPTIM_ClearFLAG_CMPM
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
-}
-
-/**
-  * @brief  Inform application whether a compare match interrupt has occurred.
-  * @rmtoll ISR          CMPM          LL_LPTIM_IsActiveFlag_CMPM
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Clear the autoreload match flag (ARRMCF)
-  * @rmtoll ICR          ARRMCF        LL_LPTIM_ClearFLAG_ARRM
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
-}
-
-/**
-  * @brief  Inform application whether a autoreload match interrupt has occurred.
-  * @rmtoll ISR          ARRM          LL_LPTIM_IsActiveFlag_ARRM
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Clear the external trigger valid edge flag(EXTTRIGCF).
-  * @rmtoll ICR          EXTTRIGCF     LL_LPTIM_ClearFlag_EXTTRIG
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
-}
-
-/**
-  * @brief  Inform application whether a valid edge on the selected external trigger input has occurred.
-  * @rmtoll ISR          EXTTRIG       LL_LPTIM_IsActiveFlag_EXTTRIG
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Clear the compare register update interrupt flag (CMPOKCF).
-  * @rmtoll ICR          CMPOKCF       LL_LPTIM_ClearFlag_CMPOK
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
-}
-
-/**
-  * @brief  Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
-            completed. If so, a new one can be initiated.
-  * @rmtoll ISR          CMPOK         LL_LPTIM_IsActiveFlag_CMPOK
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Clear the autoreload register update interrupt flag (ARROKCF).
-  * @rmtoll ICR          ARROKCF       LL_LPTIM_ClearFlag_ARROK
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
-}
-
-/**
-  * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
-            completed. If so, a new one can be initiated.
-  * @rmtoll ISR          ARROK         LL_LPTIM_IsActiveFlag_ARROK
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Clear the counter direction change to up interrupt flag (UPCF).
-  * @rmtoll ICR          UPCF          LL_LPTIM_ClearFlag_UP
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
-}
-
-/**
-  * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
-            operates in encoder mode).
-  * @rmtoll ISR          UP            LL_LPTIM_IsActiveFlag_UP
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Clear the counter direction change to down interrupt flag (DOWNCF).
-  * @rmtoll ICR          DOWNCF        LL_LPTIM_ClearFlag_DOWN
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
-}
-
-/**
-  * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
-            operates in encoder mode).
-  * @rmtoll ISR          DOWN          LL_LPTIM_IsActiveFlag_DOWN
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
-  * @{
-  */
-
-/**
-  * @brief  Enable compare match interrupt (CMPMIE).
-  * @rmtoll IER          CMPMIE        LL_LPTIM_EnableIT_CMPM
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
-}
-
-/**
-  * @brief  Disable compare match interrupt (CMPMIE).
-  * @rmtoll IER          CMPMIE        LL_LPTIM_DisableIT_CMPM
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
-{
-  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
-}
-
-/**
-  * @brief  Indicates whether the compare match interrupt (CMPMIE) is enabled.
-  * @rmtoll IER          CMPMIE        LL_LPTIM_IsEnabledIT_CMPM
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Enable autoreload match interrupt (ARRMIE).
-  * @rmtoll IER          ARRMIE        LL_LPTIM_EnableIT_ARRM
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
-}
-
-/**
-  * @brief  Disable autoreload match interrupt (ARRMIE).
-  * @rmtoll IER          ARRMIE        LL_LPTIM_DisableIT_ARRM
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
-{
-  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
-}
-
-/**
-  * @brief  Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
-  * @rmtoll IER          ARRMIE        LL_LPTIM_IsEnabledIT_ARRM
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Enable external trigger valid edge interrupt (EXTTRIGIE).
-  * @rmtoll IER          EXTTRIGIE     LL_LPTIM_EnableIT_EXTTRIG
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
-}
-
-/**
-  * @brief  Disable external trigger valid edge interrupt (EXTTRIGIE).
-  * @rmtoll IER          EXTTRIGIE     LL_LPTIM_DisableIT_EXTTRIG
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
-{
-  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
-}
-
-/**
-  * @brief  Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
-  * @rmtoll IER          EXTTRIGIE     LL_LPTIM_IsEnabledIT_EXTTRIG
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Enable compare register write completed interrupt (CMPOKIE).
-  * @rmtoll IER          CMPOKIE       LL_LPTIM_EnableIT_CMPOK
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
-}
-
-/**
-  * @brief  Disable compare register write completed interrupt (CMPOKIE).
-  * @rmtoll IER          CMPOKIE       LL_LPTIM_DisableIT_CMPOK
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
-{
-  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
-}
-
-/**
-  * @brief  Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
-  * @rmtoll IER          CMPOKIE       LL_LPTIM_IsEnabledIT_CMPOK
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Enable autoreload register write completed interrupt (ARROKIE).
-  * @rmtoll IER         ARROKIE       LL_LPTIM_EnableIT_ARROK
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
-}
-
-/**
-  * @brief  Disable autoreload register write completed interrupt (ARROKIE).
-  * @rmtoll IER         ARROKIE       LL_LPTIM_DisableIT_ARROK
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
-{
-  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
-}
-
-/**
-  * @brief  Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
-  * @rmtoll IER         ARROKIE       LL_LPTIM_IsEnabledIT_ARROK
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit(1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Enable direction change to up interrupt (UPIE).
-  * @rmtoll IER         UPIE          LL_LPTIM_EnableIT_UP
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
-}
-
-/**
-  * @brief  Disable direction change to up interrupt (UPIE).
-  * @rmtoll IER         UPIE          LL_LPTIM_DisableIT_UP
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
-{
-  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
-}
-
-/**
-  * @brief  Indicates whether the direction change to up interrupt (UPIE) is enabled.
-  * @rmtoll IER         UPIE          LL_LPTIM_IsEnabledIT_UP
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit(1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
-{
-  return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
-}
-
-/**
-  * @brief  Enable direction change to down interrupt (DOWNIE).
-  * @rmtoll IER         DOWNIE        LL_LPTIM_EnableIT_DOWN
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
-{
-  SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
-}
-
-/**
-  * @brief  Disable direction change to down interrupt (DOWNIE).
-  * @rmtoll IER         DOWNIE        LL_LPTIM_DisableIT_DOWN
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
-{
-  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
-}
-
-/**
-  * @brief  Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
-  * @rmtoll IER         DOWNIE        LL_LPTIM_IsEnabledIT_DOWN
-  * @param  LPTIMx Low-Power Timer instance
-  * @retval State of bit(1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
-{
-  return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* LPTIM1 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_LL_LPTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h
deleted file mode 100644
index c75a44cb47..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h
+++ /dev/null
@@ -1,2205 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_lpuart.h
-  * @author  MCD Application Team
-  * @brief   Header file of LPUART LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_LL_LPUART_H
-#define STM32L0xx_LL_LPUART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (LPUART1)
-
-/** @defgroup LPUART_LL LPUART
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
-  * @{
-  */
-/* Defines used in Baud Rate related macros and corresponding register setting computation */
-#define LPUART_LPUARTDIV_FREQ_MUL     256U
-#define LPUART_BRR_MASK               0x000FFFFFU
-#define LPUART_BRR_MIN_VALUE          0x00000300U
-/**
-  * @}
-  */
-
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
-  * @{
-  */
-
-/**
-  * @brief LL LPUART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetBaudRate().*/
-
-  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetDataWidth().*/
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetStopBitsLength().*/
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref LPUART_LL_EC_PARITY.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetParity().*/
-
-  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetTransferDirection().*/
-
-  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
-                                           This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_LPUART_SetHWFlowCtrl().*/
-
-} LL_LPUART_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
-  * @{
-  */
-
-/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
-  * @{
-  */
-#define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error clear flag */
-#define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error clear flag */
-#define LL_LPUART_ICR_NCF                  USART_ICR_NCF                 /*!< Noise error detected clear flag */
-#define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error clear flag */
-#define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected clear flag */
-#define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete clear flag */
-#define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS clear flag */
-#define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match clear flag */
-#define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
-  * @{
-  */
-#define LL_LPUART_ISR_PE               USART_ISR_PE         /*!< Parity error flag */
-#define LL_LPUART_ISR_FE               USART_ISR_FE         /*!< Framing error flag */
-#define LL_LPUART_ISR_NE               USART_ISR_NE         /*!< Noise detected flag */
-#define LL_LPUART_ISR_ORE              USART_ISR_ORE        /*!< Overrun error flag */
-#define LL_LPUART_ISR_IDLE             USART_ISR_IDLE       /*!< Idle line detected flag */
-#define LL_LPUART_ISR_RXNE             USART_ISR_RXNE       /*!< Read data register not empty flag */
-#define LL_LPUART_ISR_TC               USART_ISR_TC         /*!< Transmission complete flag */
-#define LL_LPUART_ISR_TXE              USART_ISR_TXE        /*!< Transmit data register empty flag */
-#define LL_LPUART_ISR_CTSIF            USART_ISR_CTSIF      /*!< CTS interrupt flag */
-#define LL_LPUART_ISR_CTS              USART_ISR_CTS        /*!< CTS flag */
-#define LL_LPUART_ISR_BUSY             USART_ISR_BUSY       /*!< Busy flag */
-#define LL_LPUART_ISR_CMF              USART_ISR_CMF        /*!< Character match flag */
-#define LL_LPUART_ISR_SBKF             USART_ISR_SBKF       /*!< Send break flag */
-#define LL_LPUART_ISR_RWU              USART_ISR_RWU        /*!< Receiver wakeup from Mute mode flag */
-#define LL_LPUART_ISR_WUF              USART_ISR_WUF        /*!< Wakeup from Stop mode flag */
-#define LL_LPUART_ISR_TEACK            USART_ISR_TEACK      /*!< Transmit enable acknowledge flag */
-#define LL_LPUART_ISR_REACK            USART_ISR_REACK      /*!< Receive enable acknowledge flag */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
-  * @{
-  */
-#define LL_LPUART_CR1_IDLEIE         USART_CR1_IDLEIE         /*!< IDLE interrupt enable */
-#define LL_LPUART_CR1_RXNEIE         USART_CR1_RXNEIE         /*!< Read data register not empty interrupt enable */
-#define LL_LPUART_CR1_TCIE           USART_CR1_TCIE           /*!< Transmission complete interrupt enable */
-#define LL_LPUART_CR1_TXEIE          USART_CR1_TXEIE          /*!< Transmit data register empty interrupt enable */
-#define LL_LPUART_CR1_PEIE           USART_CR1_PEIE           /*!< Parity error */
-#define LL_LPUART_CR1_CMIE           USART_CR1_CMIE           /*!< Character match interrupt enable */
-#define LL_LPUART_CR3_EIE            USART_CR3_EIE            /*!< Error interrupt enable */
-#define LL_LPUART_CR3_CTSIE          USART_CR3_CTSIE          /*!< CTS interrupt enable */
-#define LL_LPUART_CR3_WUFIE          USART_CR3_WUFIE          /*!< Wakeup from Stop mode interrupt enable */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_DIRECTION Direction
-  * @{
-  */
-#define LL_LPUART_DIRECTION_NONE  0x00000000U                  /*!< Transmitter and Receiver are disabled           */
-#define LL_LPUART_DIRECTION_RX    USART_CR1_RE                 /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_LPUART_DIRECTION_TX    USART_CR1_TE                 /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled            */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_PARITY Parity Control
-  * @{
-  */
-#define LL_LPUART_PARITY_NONE 0x00000000U                    /*!< Parity control disabled                            */
-#define LL_LPUART_PARITY_EVEN USART_CR1_PCE                  /*!< Parity control enabled and Even Parity is selected */
-#define LL_LPUART_PARITY_ODD  (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected  */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
-  * @{
-  */
-#define LL_LPUART_WAKEUP_IDLELINE    0x00000000U    /*!<  LPUART wake up from Mute mode on Idle Line    */
-#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!<  LPUART wake up from Mute mode on Address Mark */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
-  * @{
-  */
-#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
-#define LL_LPUART_DATAWIDTH_8B 0x00000000U  /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
-  * @{
-  */
-#define LL_LPUART_STOPBITS_1         0x00000000U             /*!< 1 stop bit */
-#define LL_LPUART_STOPBITS_2         USART_CR2_STOP_1        /*!< 2 stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
-  * @{
-  */
-#define LL_LPUART_TXRX_STANDARD      0x00000000U        /*!< TX/RX pins are used as defined in standard pinout */
-#define LL_LPUART_TXRX_SWAPPED       (USART_CR2_SWAP)   /*!< TX and RX pins functions are swapped.             */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
-  * @{
-  */
-#define LL_LPUART_RXPIN_LEVEL_STANDARD   0x00000000U       /*!< RX pin signal works using the standard logic levels */
-#define LL_LPUART_RXPIN_LEVEL_INVERTED   (USART_CR2_RXINV) /*!< RX pin signal values are inverted.                  */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
-  * @{
-  */
-#define LL_LPUART_TXPIN_LEVEL_STANDARD  0x00000000U       /*!< TX pin signal works using the standard logic levels */
-#define LL_LPUART_TXPIN_LEVEL_INVERTED  (USART_CR2_TXINV) /*!< TX pin signal values are inverted.                  */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
-  * @{
-  */
-#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U       /*!< Logical data from the data register are send/received
-                                                               in positive/direct logic. (1=H, 0=L)                  */
-#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
-                                                               in negative/inverse logic. (1=L, 0=H).
-                                                               The parity bit is also inverted.                      */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_BITORDER Bit Order
-  * @{
-  */
-#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U        /*!< data is transmitted/received with data bit 0 first,
-                                                            following the start bit */
-#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
-                                                            following the start bit */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
-  * @{
-  */
-#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U     /*!< 4-bit address detection method selected */
-#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
-  * @{
-  */
-#define LL_LPUART_HWCONTROL_NONE    0x00000000U                       /*!< CTS and RTS hardware flow control disabled */
-#define LL_LPUART_HWCONTROL_RTS     USART_CR3_RTSE                    /*!< RTS output enabled, data is only requested
-                                                                           when there is space in the receive buffer  */
-#define LL_LPUART_HWCONTROL_CTS     USART_CR3_CTSE                    /*!< CTS mode enabled, data is only transmitted
-                                                                           when the nCTS input is asserted (tied to 0)*/
-#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
-  * @{
-  */
-#define LL_LPUART_WAKEUP_ON_ADDRESS   0x00000000U                          /*!< Wake up active on address match */
-#define LL_LPUART_WAKEUP_ON_STARTBIT  USART_CR3_WUS_1                      /*!< Wake up active on Start bit detection */
-#define LL_LPUART_WAKEUP_ON_RXNE      (USART_CR3_WUS_0 | USART_CR3_WUS_1)  /*!< Wake up active on RXNE */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
-  * @{
-  */
-#define LL_LPUART_DE_POLARITY_HIGH         0x00000000U    /*!< DE signal is active high */
-#define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP  /*!< DE signal is active low */
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
-  * @{
-  */
-#define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U    /*!< Get address of data register used for transmission */
-#define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U    /*!< Get address of data register used for reception */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
-  * @{
-  */
-
-/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in LPUART register
-  * @param  __INSTANCE__ LPUART Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in LPUART register
-  * @param  __INSTANCE__ LPUART Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
-  * @{
-  */
-
-/**
-  * @brief  Compute LPUARTDIV value according to Peripheral Clock and
-  *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
-  * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
-  * @param  __BAUDRATE__ Baud Rate value to achieve
-  * @retval LPUARTDIV value to be used for BRR register filling
-  */
-#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (uint32_t)(((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__))\
-                                                                & LPUART_BRR_MASK)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
-  * @{
-  */
-
-/** @defgroup LPUART_LL_EF_Configuration Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  LPUART Enable
-  * @rmtoll CR1          UE            LL_LPUART_Enable
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  LPUART Disable
-  * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
-  *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
-  *         flags, in the LPUARTx_ISR are set to their default values.
-  * @note   In order to go into low-power mode without generating errors on the line,
-  *         the TE bit must be reset before and the software must wait
-  *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
-  *         The DMA requests are also reset when UE = 0 so the DMA channel must
-  *         be disabled before resetting the UE bit.
-  * @rmtoll CR1          UE            LL_LPUART_Disable
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  Indicate if LPUART is enabled
-  * @rmtoll CR1          UE            LL_LPUART_IsEnabled
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
-}
-
-
-/**
-  * @brief  LPUART enabled in STOP Mode
-  * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
-  *         LPUART clock selection is HSI or LSE in RCC.
-  * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
-}
-
-/**
-  * @brief  LPUART disabled in STOP Mode
-  * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
-  * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
-}
-
-/**
-  * @brief  Indicate if LPUART is enabled in STOP Mode
-  *         (able to wake up MCU from Stop mode or not)
-  * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  LPUART Clock enabled in STOP Mode
-  * @note   When this function is called, LPUART Clock is enabled while in STOP mode
-  * @rmtoll CR3          UCESM         LL_LPUART_EnableClockInStopMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableClockInStopMode(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_UCESM);
-}
-
-/**
-  * @brief  LPUART clock disabled in STOP Mode
-  * @note   When this function is called, LPUART Clock is disabled while in STOP mode
-  * @rmtoll CR3          UCESM         LL_LPUART_DisableClockInStopMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableClockInStopMode(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_UCESM);
-}
-
-/**
-  * @brief  Indicate if LPUART clock is enabled in STOP Mode
-  * @rmtoll CR3          UCESM         LL_LPUART_IsClockEnabledInStopMode
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsClockEnabledInStopMode(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
-  * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Receiver Disable
-  * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Transmitter Enable
-  * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Transmitter Disable
-  * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Configure simultaneously enabled/disabled states
-  *         of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
-  *         CR1          TE            LL_LPUART_SetTransferDirection
-  * @param  LPUARTx LPUART Instance
-  * @param  TransferDirection This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_DIRECTION_NONE
-  *         @arg @ref LL_LPUART_DIRECTION_RX
-  *         @arg @ref LL_LPUART_DIRECTION_TX
-  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
-{
-  ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
-}
-
-/**
-  * @brief  Return enabled/disabled states of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
-  *         CR1          TE            LL_LPUART_GetTransferDirection
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_DIRECTION_NONE
-  *         @arg @ref LL_LPUART_DIRECTION_RX
-  *         @arg @ref LL_LPUART_DIRECTION_TX
-  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
-}
-
-/**
-  * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
-  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
-  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
-  *         (depending on data width) and parity is checked on the received data.
-  * @rmtoll CR1          PS            LL_LPUART_SetParity\n
-  *         CR1          PCE           LL_LPUART_SetParity
-  * @param  LPUARTx LPUART Instance
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_PARITY_NONE
-  *         @arg @ref LL_LPUART_PARITY_EVEN
-  *         @arg @ref LL_LPUART_PARITY_ODD
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
-{
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
-}
-
-/**
-  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
-  * @rmtoll CR1          PS            LL_LPUART_GetParity\n
-  *         CR1          PCE           LL_LPUART_GetParity
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_PARITY_NONE
-  *         @arg @ref LL_LPUART_PARITY_EVEN
-  *         @arg @ref LL_LPUART_PARITY_ODD
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
-}
-
-/**
-  * @brief  Set Receiver Wake Up method from Mute mode.
-  * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
-  * @param  LPUARTx LPUART Instance
-  * @param  Method This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
-  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
-{
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
-}
-
-/**
-  * @brief  Return Receiver Wake Up method from Mute mode
-  * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
-  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
-}
-
-/**
-  * @brief  Set Word length (nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M             LL_LPUART_SetDataWidth
-  * @param  LPUARTx LPUART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_DATAWIDTH_7B
-  *         @arg @ref LL_LPUART_DATAWIDTH_8B
-  *         @arg @ref LL_LPUART_DATAWIDTH_9B
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
-{
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
-}
-
-/**
-  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M             LL_LPUART_GetDataWidth
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_DATAWIDTH_7B
-  *         @arg @ref LL_LPUART_DATAWIDTH_8B
-  *         @arg @ref LL_LPUART_DATAWIDTH_9B
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
-}
-
-/**
-  * @brief  Allow switch between Mute Mode and Active mode
-  * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
-}
-
-/**
-  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
-  * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
-}
-
-/**
-  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
-  * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
-}
-
-
-/**
-  * @brief  Set the length of the stop bits
-  * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
-  * @param  LPUARTx LPUART Instance
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_STOPBITS_1
-  *         @arg @ref LL_LPUART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Retrieve the length of the stop bits
-  * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_STOPBITS_1
-  *         @arg @ref LL_LPUART_STOPBITS_2
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
-}
-
-/**
-  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
-  *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
-  *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
-  * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
-  *         CR1          PCE           LL_LPUART_ConfigCharacter\n
-  *         CR1          M             LL_LPUART_ConfigCharacter\n
-  *         CR2          STOP          LL_LPUART_ConfigCharacter
-  * @param  LPUARTx LPUART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_DATAWIDTH_7B
-  *         @arg @ref LL_LPUART_DATAWIDTH_8B
-  *         @arg @ref LL_LPUART_DATAWIDTH_9B
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_PARITY_NONE
-  *         @arg @ref LL_LPUART_PARITY_EVEN
-  *         @arg @ref LL_LPUART_PARITY_ODD
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_STOPBITS_1
-  *         @arg @ref LL_LPUART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
-                                               uint32_t StopBits)
-{
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Configure TX/RX pins swapping setting.
-  * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
-  * @param  LPUARTx LPUART Instance
-  * @param  SwapConfig This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_TXRX_STANDARD
-  *         @arg @ref LL_LPUART_TXRX_SWAPPED
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
-}
-
-/**
-  * @brief  Retrieve TX/RX pins swapping configuration.
-  * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_TXRX_STANDARD
-  *         @arg @ref LL_LPUART_TXRX_SWAPPED
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
-}
-
-/**
-  * @brief  Configure RX pin active level logic
-  * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
-  * @param  LPUARTx LPUART Instance
-  * @param  PinInvMethod This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
-}
-
-/**
-  * @brief  Retrieve RX pin active level logic configuration
-  * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
-}
-
-/**
-  * @brief  Configure TX pin active level logic
-  * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
-  * @param  LPUARTx LPUART Instance
-  * @param  PinInvMethod This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
-}
-
-/**
-  * @brief  Retrieve TX pin active level logic configuration
-  * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
-}
-
-/**
-  * @brief  Configure Binary data logic.
-  *
-  * @note   Allow to define how Logical data from the data register are send/received :
-  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
-  * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
-  * @param  LPUARTx LPUART Instance
-  * @param  DataLogic This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
-  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
-}
-
-/**
-  * @brief  Retrieve Binary data configuration
-  * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
-  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
-}
-
-/**
-  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
-  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
-  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
-  * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
-  * @param  LPUARTx LPUART Instance
-  * @param  BitOrder This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
-  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
-}
-
-/**
-  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
-  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
-  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
-  * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
-  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
-}
-
-/**
-  * @brief  Set Address of the LPUART node.
-  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
-  *         for wake up with address mark detection.
-  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
-  *         (b7-b4 should be set to 0)
-  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
-  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
-  *         for wake up with 7-bit address mark detection.
-  *         The MSB of the character sent by the transmitter should be equal to 1.
-  *         It may also be used for character detection during normal reception,
-  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
-  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
-  *         value and CMF flag is set on match)
-  * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
-  *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
-  * @param  LPUARTx LPUART Instance
-  * @param  AddressLen This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
-  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
-  * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
-{
-  MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
-             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
-}
-
-/**
-  * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
-  * @note   If 4-bit Address Detection is selected in ADDM7,
-  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
-  *         If 7-bit Address Detection is selected in ADDM7,
-  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
-  * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
-  * @param  LPUARTx LPUART Instance
-  * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
-}
-
-/**
-  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
-  * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
-  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
-}
-
-/**
-  * @brief  Enable RTS HW Flow Control
-  * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Disable RTS HW Flow Control
-  * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Enable CTS HW Flow Control
-  * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Disable CTS HW Flow Control
-  * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Configure HW Flow Control mode (both CTS and RTS)
-  * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
-  *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
-  * @param  LPUARTx LPUART Instance
-  * @param  HardwareFlowControl This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_HWCONTROL_NONE
-  *         @arg @ref LL_LPUART_HWCONTROL_RTS
-  *         @arg @ref LL_LPUART_HWCONTROL_CTS
-  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
-{
-  MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
-}
-
-/**
-  * @brief  Return HW Flow Control configuration (both CTS and RTS)
-  * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
-  *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_HWCONTROL_NONE
-  *         @arg @ref LL_LPUART_HWCONTROL_RTS
-  *         @arg @ref LL_LPUART_HWCONTROL_CTS
-  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
-}
-
-/**
-  * @brief  Enable Overrun detection
-  * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
-  * @brief  Disable Overrun detection
-  * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
-  * @brief  Indicate if Overrun detection is enabled
-  * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
-  * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
-  * @param  LPUARTx LPUART Instance
-  * @param  Type This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
-  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
-  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
-{
-  MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
-}
-
-/**
-  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
-  * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
-  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
-  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
-}
-
-/**
-  * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
-  *
-  * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
-  *         according to used Peripheral Clock and expected Baud Rate values
-  * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
-  *         (Baud rate value != 0).
-  * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
-  *         a care should be taken when generating high baud rates using high PeriphClk
-  *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
-  * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
-  * @param  LPUARTx LPUART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  BaudRate Baud Rate
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
-{
-  if (BaudRate != 0U)
-  {
-    LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
-  }
-}
-
-/**
-  * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
-  *         (full BRR content), and to used Peripheral Clock values
-  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
-  * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
-  * @param  LPUARTx LPUART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @retval Baud Rate
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk)
-{
-  uint32_t lpuartdiv;
-  uint32_t brrresult;
-
-  lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
-
-  if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
-  {
-    brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
-  }
-  else
-  {
-    brrresult = 0x0UL;
-  }
-
-  return (brrresult);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
-  * @{
-  */
-
-/**
-  * @brief  Enable Single Wire Half-Duplex mode
-  * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Disable Single Wire Half-Duplex mode
-  * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
-  * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
-  * @{
-  */
-
-/**
-  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
-  * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
-  * @param  LPUARTx LPUART Instance
-  * @param  Time Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
-{
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
-}
-
-/**
-  * @brief  Return DEDT (Driver Enable De-Assertion Time)
-  * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
-  * @param  LPUARTx LPUART Instance
-  * @retval Time value expressed on 5 bits ([4:0] bits) : c
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
-}
-
-/**
-  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
-  * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
-  * @param  LPUARTx LPUART Instance
-  * @param  Time Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
-{
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
-}
-
-/**
-  * @brief  Return DEAT (Driver Enable Assertion Time)
-  * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
-  * @param  LPUARTx LPUART Instance
-  * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
-}
-
-/**
-  * @brief  Enable Driver Enable (DE) Mode
-  * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
-}
-
-/**
-  * @brief  Disable Driver Enable (DE) Mode
-  * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
-}
-
-/**
-  * @brief  Indicate if Driver Enable (DE) Mode is enabled
-  * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Select Driver Enable Polarity
-  * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
-  * @param  LPUARTx LPUART Instance
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
-  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
-{
-  MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
-}
-
-/**
-  * @brief  Return Driver Enable Polarity
-  * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
-  * @param  LPUARTx LPUART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
-  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
-  */
-__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
-{
-  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if the LPUART Parity Error Flag is set or not
-  * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Framing Error Flag is set or not
-  * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Noise error detected Flag is set or not
-  * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART OverRun Error Flag is set or not
-  * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART IDLE line detected Flag is set or not
-  * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Read Data Register Not Empty Flag is set or not
-  * @rmtoll ISR          RXNE          LL_LPUART_IsActiveFlag_RXNE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Transmission Complete Flag is set or not
-  * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Transmit Data Register Empty Flag is set or not
-  * @rmtoll ISR          TXE           LL_LPUART_IsActiveFlag_TXE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART CTS interrupt Flag is set or not
-  * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART CTS Flag is set or not
-  * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Busy Flag is set or not
-  * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Character Match Flag is set or not
-  * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Send Break Flag is set or not
-  * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
-  * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
-  * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
-  * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
-  * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
-}
-
-
-/**
-  * @brief  Clear Parity Error Flag
-  * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
-}
-
-/**
-  * @brief  Clear Framing Error Flag
-  * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
-}
-
-/**
-  * @brief  Clear Noise detected Flag
-  * @rmtoll ICR          NCF           LL_LPUART_ClearFlag_NE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_NCF);
-}
-
-/**
-  * @brief  Clear OverRun Error Flag
-  * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
-}
-
-/**
-  * @brief  Clear IDLE line detected Flag
-  * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
-}
-
-
-/**
-  * @brief  Clear Transmission Complete Flag
-  * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
-}
-
-/**
-  * @brief  Clear CTS Interrupt Flag
-  * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
-}
-
-/**
-  * @brief  Clear Character Match Flag
-  * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
-}
-
-/**
-  * @brief  Clear Wake Up from stop mode Flag
-  * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
-}
-
-
-/**
-  * @brief  Enable RX Not Empty Interrupt
-  * @rmtoll CR1          RXNEIE        LL_LPUART_EnableIT_RXNE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
-  * @brief  Enable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
-}
-
-
-/**
-  * @brief  Enable TX Empty Interrupt
-  * @rmtoll CR1          TXEIE         LL_LPUART_EnableIT_TXE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
-  * @brief  Enable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Enable Character Match Interrupt
-  * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
-}
-
-
-/**
-  * @brief  Enable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
-  *         - 0: Interrupt is inhibited
-  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
-  * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Enable CTS Interrupt
-  * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Enable Wake Up from Stop Mode Interrupt
-  * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
-}
-
-
-/**
-  * @brief  Disable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
-}
-
-
-/**
-  * @brief  Disable RX Not Empty Interrupt
-  * @rmtoll CR1          RXNEIE        LL_LPUART_DisableIT_RXNE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
-  * @brief  Disable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
-}
-
-
-/**
-  * @brief  Disable TX Empty Interrupt
-  * @rmtoll CR1          TXEIE         LL_LPUART_DisableIT_TXE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
-  * @brief  Disable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Disable Character Match Interrupt
-  * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
-}
-
-
-/**
-  * @brief  Disable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
-  *         - 0: Interrupt is inhibited
-  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
-  * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Disable CTS Interrupt
-  * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Disable Wake Up from Stop Mode Interrupt
-  * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
-}
-
-
-/**
-  * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
-  * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
-}
-
-
-/**
-  * @brief  Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
-  * @rmtoll CR1          RXNEIE        LL_LPUART_IsEnabledIT_RXNE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
-  * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
-}
-
-
-/**
-  * @brief  Check if the LPUART TX Empty Interrupt is enabled or disabled.
-  * @rmtoll CR1          TXEIE         LL_LPUART_IsEnabledIT_TXE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
-  * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
-  * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
-}
-
-
-/**
-  * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
-  * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
-  * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
-  * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Disable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for reception
-  * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Disable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
-{
-  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for transmission
-  * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Disabling on Reception Error
-  * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
-  * @brief  Disable DMA Disabling on Reception Error
-  * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
-{
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
-  * @brief  Indicate if DMA Disabling on Reception Error is disabled
-  * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
-  * @param  LPUARTx LPUART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
-{
-  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the LPUART data register address used for DMA transfer
-  * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
-  * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
-  * @param  LPUARTx LPUART Instance
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
-  *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
-{
-  uint32_t data_reg_addr;
-
-  if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
-  {
-    /* return address of TDR register */
-    data_reg_addr = (uint32_t) &(LPUARTx->TDR);
-  }
-  else
-  {
-    /* return address of RDR register */
-    data_reg_addr = (uint32_t) &(LPUARTx->RDR);
-  }
-
-  return data_reg_addr;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
-  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
-  * @param  LPUARTx LPUART Instance
-  * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
-{
-  return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
-}
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
-  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
-  * @param  LPUARTx LPUART Instance
-  * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
-  */
-__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
-{
-  return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
-  * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
-  * @param  LPUARTx LPUART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
-{
-  LPUARTx->TDR = Value;
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
-  * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
-  * @param  LPUARTx LPUART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
-{
-  LPUARTx->TDR = Value & 0x1FFUL;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_LL_EF_Execution Execution
-  * @{
-  */
-
-/**
-  * @brief  Request Break sending
-  * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
-}
-
-/**
-  * @brief  Put LPUART in mute mode and set the RWU flag
-  * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
-}
-
-/**
-  * @brief  Request a Receive Data flush
-  * @note   Allows to discard the received data without reading them, and avoid an overrun
-  *         condition.
-  * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
-{
-  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
-ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
-void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* LPUART1 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_LL_LPUART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h
deleted file mode 100644
index 56fc1b4481..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h
+++ /dev/null
@@ -1,746 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_pwr.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_PWR_H
-#define __STM32L0xx_LL_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
-  * @{
-  */
-
-/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
-  * @{
-  */
-#define LL_PWR_CR_CSBF                     PWR_CR_CSBF            /*!< Clear standby flag */
-#define LL_PWR_CR_CWUF                     PWR_CR_CWUF            /*!< Clear wakeup flag */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
-  * @{
-  */
-#define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */
-#define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */
-#if defined(PWR_PVD_SUPPORT)
-#define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */
-#endif /* PWR_PVD_SUPPORT */
-#if defined(PWR_CSR_VREFINTRDYF)
-#define LL_PWR_CSR_VREFINTRDYF             PWR_CSR_VREFINTRDYF    /*!< VREFINT ready flag */
-#endif /* PWR_CSR_VREFINTRDYF */
-#define LL_PWR_CSR_VOS                     PWR_CSR_VOSF           /*!< Voltage scaling select flag */
-#define LL_PWR_CSR_REGLPF                  PWR_CSR_REGLPF         /*!< Regulator low power flag */
-#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */
-#define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */
-#if defined(PWR_CSR_EWUP3)
-#define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */
-#endif /* PWR_CSR_EWUP3 */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
-  * @{
-  */
-#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS_0)                   /*!< 1.8V (range 1) */
-#define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR_VOS_1)                   /*!< 1.5V (range 2) */
-#define LL_PWR_REGU_VOLTAGE_SCALE3         (PWR_CR_VOS_0 | PWR_CR_VOS_1)    /*!< 1.2V (range 3) */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
-  * @{
-  */
-#define LL_PWR_MODE_STOP                      0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
-#define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_REGU_MODE_LP_MODES  Regulator Mode In Low Power Modes
-  * @{
-  */
-#define LL_PWR_REGU_LPMODES_MAIN           0x00000000U        /*!< Voltage regulator in main mode during deepsleep/sleep/low-power run mode */
-#define LL_PWR_REGU_LPMODES_LOW_POWER      (PWR_CR_LPSDSR)    /*!< Voltage regulator in low-power mode during deepsleep/sleep/low-power run mode */
-/**
-  * @}
-  */
-#if defined(PWR_CR_LPDS)
-/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
- * @{
- */
-#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage regulator in main mode during deepsleep mode when PWR_CR_LPSDSR = 0 */
-#define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage regulator in low-power mode during deepsleep mode when PWR_CR_LPSDSR = 0 */
-/**
-  * @}
-  */
-#endif /* PWR_CR_LPDS */
-
-#if defined(PWR_PVD_SUPPORT)
-/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
-  * @{
-  */
-#define LL_PWR_PVDLEVEL_0                  (PWR_CR_PLS_LEV0)      /*!< Voltage threshold detected by PVD 1.9 V */
-#define LL_PWR_PVDLEVEL_1                  (PWR_CR_PLS_LEV1)      /*!< Voltage threshold detected by PVD 2.1 V */
-#define LL_PWR_PVDLEVEL_2                  (PWR_CR_PLS_LEV2)      /*!< Voltage threshold detected by PVD 2.3 V */
-#define LL_PWR_PVDLEVEL_3                  (PWR_CR_PLS_LEV3)      /*!< Voltage threshold detected by PVD 2.5 V */
-#define LL_PWR_PVDLEVEL_4                  (PWR_CR_PLS_LEV4)      /*!< Voltage threshold detected by PVD 2.7 V */
-#define LL_PWR_PVDLEVEL_5                  (PWR_CR_PLS_LEV5)      /*!< Voltage threshold detected by PVD 2.9 V */
-#define LL_PWR_PVDLEVEL_6                  (PWR_CR_PLS_LEV6)      /*!< Voltage threshold detected by PVD 3.1 V */
-#define LL_PWR_PVDLEVEL_7                  (PWR_CR_PLS_LEV7)      /*!< External input analog voltage   (Compare internally to VREFINT) */
-/**
-  * @}
-  */
-#endif /* PWR_PVD_SUPPORT */
-/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
-  * @{
-  */
-#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */
-#define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC13 */
-#if defined(PWR_CSR_EWUP3)
-#define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PE6 or PA2 according to device */
-#endif /* PWR_CSR_EWUP3 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
-  * @{
-  */
-
-/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in PWR register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in PWR register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @defgroup PWR_LL_EF_Configuration Configuration
-  * @{
-  */
-/**
-  * @brief  Switch the regulator from main mode to low-power mode
-  * @rmtoll CR    LPRUN       LL_PWR_EnableLowPowerRunMode
-  * @note   Remind to set the regulator to low power before enabling
-  *         LowPower run mode (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER).
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_LPRUN);
-}
-
-/**
-  * @brief  Switch the regulator from low-power mode to main mode
-  * @rmtoll CR    LPRUN       LL_PWR_DisableLowPowerRunMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);
-}
-
-/**
-  * @brief  Check if the regulator is in low-power mode
-  * @rmtoll CR    LPRUN       LL_PWR_IsEnabledLowPowerRunMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_LPRUN) == (PWR_CR_LPRUN));
-}
-
-/**
-  * @brief  Set voltage regulator to low-power and switch from 
-  *         run main mode to run low-power mode.
-  * @rmtoll CR    LPSDSR       LL_PWR_EnterLowPowerRunMode\n
-  *         CR    LPRUN        LL_PWR_EnterLowPowerRunMode
-  * @note   This "high level" function is introduced to provide functional
-  *         compatibility with other families. Notice that the two registers
-  *         have to be written sequentially, so this function is not atomic.
-  *         To assure atomicity you can call separately the following functions:
-  *         - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_LOW_POWER);
-  *         - @ref LL_PWR_EnableLowPowerRunMode();
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_LOW_POWER) */
-  SET_BIT(PWR->CR, PWR_CR_LPRUN);  /* => LL_PWR_EnableLowPowerRunMode() */
-}
-
-/**
-  * @brief  Set voltage regulator to main and switch from 
-  *         run main mode to low-power mode.
-  * @rmtoll CR    LPSDSR       LL_PWR_ExitLowPowerRunMode\n
-  *         CR    LPRUN        LL_PWR_ExitLowPowerRunMode
-  * @note   This "high level" function is introduced to provide functional   
-  *         compatibility with other families. Notice that the two registers 
-  *         have to be written sequentially, so this function is not atomic.
-  *         To assure atomicity you can call separately the following functions:
-  *         - @ref LL_PWR_DisableLowPowerRunMode();
-  *         - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_MAIN);
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);   /* => LL_PWR_DisableLowPowerRunMode() */
-  CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR);  /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_MAIN) */
-}
-/**
-  * @brief  Set the main internal regulator output voltage
-  * @rmtoll CR    VOS       LL_PWR_SetRegulVoltageScaling
-  * @param  VoltageScaling This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
-}
-
-/**
-  * @brief  Get the main internal regulator output voltage
-  * @rmtoll CR    VOS       LL_PWR_GetRegulVoltageScaling
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
-}
-
-/**
-  * @brief  Enable access to the backup domain
-  * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
-  * @brief  Disable access to the backup domain
-  * @rmtoll CR    DBP       LL_PWR_DisableBkUpAccess
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
-  * @brief  Check if the backup domain is enabled
-  * @rmtoll CR    DBP       LL_PWR_IsEnabledBkUpAccess
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
-}
-
-/**
-  * @brief  Set voltage regulator mode during low power modes
-  * @rmtoll CR    LPSDSR       LL_PWR_SetRegulModeLP
-  * @param  RegulMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_LPMODES_MAIN
-  *         @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetRegulModeLP(uint32_t RegulMode)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_LPSDSR, RegulMode);
-}
-
-/**
-  * @brief  Get voltage regulator mode during low power modes
-  * @rmtoll CR    LPSDSR       LL_PWR_GetRegulModeLP
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_LPMODES_MAIN
-  *         @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulModeLP(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPSDSR));
-}
-
-#if defined(PWR_CR_LPDS)
-/**
-  * @brief  Set voltage regulator mode during deep sleep mode
-  * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
-  * @param  RegulMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
-  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
-}
-
-/**
-  * @brief  Get voltage regulator mode during deep sleep mode
-  * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
-  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
-}
-#endif /* PWR_CR_LPDS */
-
-/**
-  * @brief  Set power down mode when CPU enters deepsleep
-  * @rmtoll CR    PDDS         LL_PWR_SetPowerMode
-  * @param  PDMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_MODE_STOP
-  *         @arg @ref LL_PWR_MODE_STANDBY
-  * @note   Set the regulator to low power (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER)  
-  *         before setting MODE_STOP. If the regulator remains in "main mode",   
-  *         it consumes more power without providing any additional feature. 
-  *         In MODE_STANDBY the regulator is automatically off.
-  * @note   It is forbidden to configure both EN_VREFINT=1 and ULP=1 if the device is
-  *         in Stop mode or in Sleep/Low-power sleep mode. If the device is not in 
-  *         low-power mode, VREFINT is always enabled whatever the state of EN_VREFINT and ULP
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_PDDS, PDMode);
-}
-
-/**
-  * @brief  Get power down mode when CPU enters deepsleep
-  * @rmtoll CR    PDDS         LL_PWR_GetPowerMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_MODE_STOP
-  *         @arg @ref LL_PWR_MODE_STANDBY
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PDDS));
-}
-
-#if defined(PWR_PVD_SUPPORT)
-/**
-  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
-  * @rmtoll CR    PLS       LL_PWR_SetPVDLevel
-  * @param  PVDLevel This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_PVDLEVEL_0
-  *         @arg @ref LL_PWR_PVDLEVEL_1
-  *         @arg @ref LL_PWR_PVDLEVEL_2
-  *         @arg @ref LL_PWR_PVDLEVEL_3
-  *         @arg @ref LL_PWR_PVDLEVEL_4
-  *         @arg @ref LL_PWR_PVDLEVEL_5
-  *         @arg @ref LL_PWR_PVDLEVEL_6
-  *         @arg @ref LL_PWR_PVDLEVEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
-}
-
-/**
-  * @brief  Get the voltage threshold detection
-  * @rmtoll CR    PLS       LL_PWR_GetPVDLevel
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_PVDLEVEL_0
-  *         @arg @ref LL_PWR_PVDLEVEL_1
-  *         @arg @ref LL_PWR_PVDLEVEL_2
-  *         @arg @ref LL_PWR_PVDLEVEL_3
-  *         @arg @ref LL_PWR_PVDLEVEL_4
-  *         @arg @ref LL_PWR_PVDLEVEL_5
-  *         @arg @ref LL_PWR_PVDLEVEL_6
-  *         @arg @ref LL_PWR_PVDLEVEL_7
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
-}
-
-/**
-  * @brief  Enable Power Voltage Detector
-  * @rmtoll CR    PVDE       LL_PWR_EnablePVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnablePVD(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
-  * @brief  Disable Power Voltage Detector
-  * @rmtoll CR    PVDE       LL_PWR_DisablePVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisablePVD(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
-  * @brief  Check if Power Voltage Detector is enabled
-  * @rmtoll CR    PVDE       LL_PWR_IsEnabledPVD
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
-}
-#endif /* PWR_PVD_SUPPORT */
-
-/**
-  * @brief  Enable the WakeUp PINx functionality
-  * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\n
-  * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
-  * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *
-  *         (*) not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
-{
-  SET_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
-  * @brief  Disable the WakeUp PINx functionality
-  * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\n
-  * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
-  * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *
-  *         (*) not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
-{
-  CLEAR_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
-  * @brief  Check if the WakeUp PINx functionality is enabled
-  * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
-  * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
-  * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *
-  *         (*) not available on all devices
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
-{
-  return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
-}
-
-/**
-  * @brief  Enable ultra low-power mode by enabling VREFINT switch off in low-power modes
-  * @rmtoll CR    ULP       LL_PWR_EnableUltraLowPower
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableUltraLowPower(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_ULP);
-}
-
-/**
-  * @brief  Disable ultra low-power mode by disabling VREFINT switch off in low-power modes
-  * @rmtoll CR    ULP       LL_PWR_DisableUltraLowPower
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableUltraLowPower(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_ULP);
-}
-
-/**
-  * @brief  Check if ultra low-power mode is enabled by checking if VREFINT switch off in low-power modes is enabled
-  * @rmtoll CR    ULP       LL_PWR_IsEnabledUltraLowPower
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPower(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_ULP) == (PWR_CR_ULP));
-}
-
-/**
-  * @brief  Enable fast wakeup by ignoring VREFINT startup time when exiting from low-power mode
-  * @rmtoll CR    FWU       LL_PWR_EnableFastWakeUp
-  * @note   Works in conjunction with ultra low power mode.
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableFastWakeUp(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_FWU);
-}
-
-/**
-  * @brief  Disable fast wakeup by waiting VREFINT startup time when exiting from low-power mode
-  * @rmtoll CR    FWU       LL_PWR_DisableFastWakeUp
-  * @note   Works in conjunction with ultra low power mode.
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableFastWakeUp(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_FWU);
-}
-
-/**
-  * @brief  Check if fast wakeup is enabled by checking if VREFINT startup time when exiting from low-power mode is ignored
-  * @rmtoll CR    FWU       LL_PWR_IsEnabledFastWakeUp
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledFastWakeUp(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_FWU) == (PWR_CR_FWU));
-}
-
-/**
-  * @brief  Enable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode
-  * @rmtoll CR    DS_EE_KOFF       LL_PWR_EnableNVMKeptOff
-  * @note   When enabled, after entering low-power mode (Stop or Standby only), if RUN_PD of FLASH_ACR register
-  *         is also set, the Flash memory will not be woken up when exiting from deepsleep mode.
-  *         When enabled, the EEPROM will not be woken up when exiting from low-power mode (if the bit RUN_PD is set)
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableNVMKeptOff(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_DSEEKOFF);
-}
-
-/**
-  * @brief  Disable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode
-  * @rmtoll CR    DS_EE_KOFF       LL_PWR_DisableNVMKeptOff
-  * @note   When disabled, Flash memory is woken up when exiting from deepsleep mode even if the bit RUN_PD is set
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableNVMKeptOff(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF);
-}
-
-/**
-  * @brief  Check if non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode is enabled
-  * @rmtoll CR    DS_EE_KOFF       LL_PWR_IsEnabledNVMKeptOff
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledNVMKeptOff(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_DSEEKOFF) == (PWR_CR_DSEEKOFF));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Get Wake-up Flag
-  * @rmtoll CSR   WUF       LL_PWR_IsActiveFlag_WU
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
-}
-
-/**
-  * @brief  Get Standby Flag
-  * @rmtoll CSR   SBF       LL_PWR_IsActiveFlag_SB
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
-}
-
-#if defined(PWR_PVD_SUPPORT)
-/**
-  * @brief  Indicate whether VDD voltage is below the selected PVD threshold
-  * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
-}
-#endif /* PWR_PVD_SUPPORT */
-
-#if defined(PWR_CSR_VREFINTRDYF)
-/**
-  * @brief  Get Internal Reference VrefInt Flag
-  * @rmtoll CSR   VREFINTRDYF       LL_PWR_IsActiveFlag_VREFINTRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
-}
-#endif /* PWR_CSR_VREFINTRDYF */
-/**
-  * @brief  Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
-  * @rmtoll CSR   VOSF       LL_PWR_IsActiveFlag_VOS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
-{
-  return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
-}
-/**
-  * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
-  * @rmtoll CSR   REGLPF       LL_PWR_IsActiveFlag_REGLPF
-  * @note Take care, return value "0" means the regulator is ready.  Return value "1" means the output voltage range is still changing.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_REGLPF) == (PWR_CSR_REGLPF));
-}
-/**
-  * @brief  Clear Standby Flag
-  * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_CSBF);
-}
-
-/**
-  * @brief  Clear Wake-up Flags
-  * @rmtoll CR   CWUF       LL_PWR_ClearFlag_WU
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_CWUF);
-}
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup PWR_LL_EF_Init De-initialization function
-  * @{
-  */
-ErrorStatus LL_PWR_DeInit(void);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(PWR) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h
deleted file mode 100644
index d352dd752d..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h
+++ /dev/null
@@ -1,2497 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_rcc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_RCC_H
-#define __STM32L0xx_LL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_LL_Private_Variables RCC Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCC_LL_Private_Constants RCC Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Private_Macros RCC Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Exported_Types RCC Exported Types
-  * @{
-  */
-
-/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
-  * @{
-  */
-
-/**
-  * @brief  RCC Clocks Frequency Structure
-  */
-typedef struct
-{
-  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
-  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
-  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
-  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
-} LL_RCC_ClocksTypeDef;
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
-  * @brief    Defines used to adapt values of different oscillators
-  * @note     These values could be modified in the user environment according to
-  *           HW set-up.
-  * @{
-  */
-#if !defined  (HSE_VALUE)
-#define HSE_VALUE    (8000000U)  /*!< Value of the HSE oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-#define HSI_VALUE    (16000000U) /*!< Value of the HSI oscillator in Hz */
-#endif /* HSI_VALUE */
-
-#if !defined  (LSE_VALUE)
-#define LSE_VALUE    (32768U)    /*!< Value of the LSE oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSI_VALUE)
-#define LSI_VALUE    (37000U)    /*!< Value of the LSI oscillator in Hz */
-#endif /* LSI_VALUE */
-#if defined(RCC_HSI48_SUPPORT)
-
-#if !defined  (HSI48_VALUE)
-#define HSI48_VALUE  (48000000U) /*!< Value of the HSI48 oscillator in Hz */
-#endif /* HSI48_VALUE */
-#endif /* RCC_HSI48_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_RCC_WriteReg function
-  * @{
-  */
-#define LL_RCC_CICR_LSIRDYC                RCC_CICR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
-#define LL_RCC_CICR_LSERDYC                RCC_CICR_LSERDYC     /*!< LSE Ready Interrupt Clear */
-#define LL_RCC_CICR_HSIRDYC                RCC_CICR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
-#define LL_RCC_CICR_HSERDYC                RCC_CICR_HSERDYC     /*!< HSE Ready Interrupt Clear */
-#define LL_RCC_CICR_PLLRDYC                RCC_CICR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
-#define LL_RCC_CICR_MSIRDYC                RCC_CICR_MSIRDYC     /*!< MSI Ready Interrupt Clear */
-#if defined(RCC_HSI48_SUPPORT)
-#define LL_RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC  /*!< HSI48 Ready Interrupt Clear */
-#endif /* RCC_HSI48_SUPPORT */
-#define LL_RCC_CICR_LSECSSC                RCC_CICR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */
-#define LL_RCC_CICR_CSSC                   RCC_CICR_CSSC        /*!< Clock Security System Interrupt Clear */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_RCC_ReadReg function
-  * @{
-  */
-#define LL_RCC_CIFR_LSIRDYF                RCC_CIFR_LSIRDYF     /*!< LSI Ready Interrupt flag */
-#define LL_RCC_CIFR_LSERDYF                RCC_CIFR_LSERDYF     /*!< LSE Ready Interrupt flag */
-#define LL_RCC_CIFR_HSIRDYF                RCC_CIFR_HSIRDYF     /*!< HSI Ready Interrupt flag */
-#define LL_RCC_CIFR_HSERDYF                RCC_CIFR_HSERDYF     /*!< HSE Ready Interrupt flag */
-#define LL_RCC_CIFR_PLLRDYF                RCC_CIFR_PLLRDYF     /*!< PLL Ready Interrupt flag */
-#define LL_RCC_CIFR_MSIRDYF                RCC_CIFR_MSIRDYF     /*!< MSI Ready Interrupt flag */
-#if defined(RCC_HSI48_SUPPORT)
-#define LL_RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF  /*!< HSI48 Ready Interrupt flag */
-#endif /* RCC_HSI48_SUPPORT */
-#define LL_RCC_CIFR_LSECSSF                RCC_CIFR_LSECSSF    /*!< LSE Clock Security System Interrupt flag */
-#define LL_RCC_CIFR_CSSF                   RCC_CIFR_CSSF       /*!< Clock Security System Interrupt flag */
-#define LL_RCC_CSR_FWRSTF                 RCC_CSR_FWRSTF          /*!< Firewall reset flag */
-#define LL_RCC_CSR_OBLRSTF                RCC_CSR_OBLRSTF         /*!< OBL reset flag */
-#define LL_RCC_CSR_PINRSTF                RCC_CSR_PINRSTF         /*!< PIN reset flag */
-#define LL_RCC_CSR_PORRSTF                RCC_CSR_PORRSTF         /*!< POR/PDR reset flag */
-#define LL_RCC_CSR_SFTRSTF                RCC_CSR_SFTRSTF         /*!< Software Reset flag */
-#define LL_RCC_CSR_IWDGRSTF               RCC_CSR_IWDGRSTF        /*!< Independent Watchdog reset flag */
-#define LL_RCC_CSR_WWDGRSTF               RCC_CSR_WWDGRSTF        /*!< Window watchdog reset flag */
-#define LL_RCC_CSR_LPWRRSTF               RCC_CSR_LPWRRSTF        /*!< Low-Power reset flag */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
-  * @{
-  */
-#define LL_RCC_CIER_LSIRDYIE               RCC_CIER_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
-#define LL_RCC_CIER_LSERDYIE               RCC_CIER_LSERDYIE      /*!< LSE Ready Interrupt Enable */
-#define LL_RCC_CIER_HSIRDYIE               RCC_CIER_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
-#define LL_RCC_CIER_HSERDYIE               RCC_CIER_HSERDYIE      /*!< HSE Ready Interrupt Enable */
-#define LL_RCC_CIER_PLLRDYIE               RCC_CIER_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
-#define LL_RCC_CIER_MSIRDYIE               RCC_CIER_MSIRDYIE      /*!< MSI Ready Interrupt Enable */
-#if defined(RCC_HSI48_SUPPORT)
-#define LL_RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE   /*!< HSI48 Ready Interrupt Enable */
-#endif /* RCC_HSI48_SUPPORT */
-#define LL_RCC_CIER_LSECSSIE               RCC_CIER_LSECSSIE      /*!< LSE CSS Interrupt Enable */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
-  * @{
-  */
-#define LL_RCC_LSEDRIVE_LOW                (0x00000000U) /*!< Xtal mode lower driving capability */
-#define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_CSR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
-#define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_CSR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
-#define LL_RCC_LSEDRIVE_HIGH               RCC_CSR_LSEDRV   /*!< Xtal mode higher driving capability */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
-  * @{
-  */
-#define LL_RCC_RTC_HSE_DIV_2               0x00000000U          /*!< HSE is divided by 2 for RTC clock  */
-#define LL_RCC_RTC_HSE_DIV_4               RCC_CR_RTCPRE_0      /*!< HSE is divided by 4 for RTC clock  */
-#define LL_RCC_RTC_HSE_DIV_8               RCC_CR_RTCPRE_1      /*!< HSE is divided by 8 for RTC clock  */
-#define LL_RCC_RTC_HSE_DIV_16              RCC_CR_RTCPRE        /*!< HSE is divided by 16 for RTC clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MSIRANGE  MSI clock ranges
-  * @{
-  */
-#define LL_RCC_MSIRANGE_0                  RCC_ICSCR_MSIRANGE_0  /*!< MSI = 65.536 KHz */
-#define LL_RCC_MSIRANGE_1                  RCC_ICSCR_MSIRANGE_1  /*!< MSI = 131.072 KHz*/
-#define LL_RCC_MSIRANGE_2                  RCC_ICSCR_MSIRANGE_2  /*!< MSI = 262.144 KHz */
-#define LL_RCC_MSIRANGE_3                  RCC_ICSCR_MSIRANGE_3  /*!< MSI = 524.288 KHz */
-#define LL_RCC_MSIRANGE_4                  RCC_ICSCR_MSIRANGE_4  /*!< MSI = 1.048 MHz */
-#define LL_RCC_MSIRANGE_5                  RCC_ICSCR_MSIRANGE_5  /*!< MSI = 2.097 MHz */
-#define LL_RCC_MSIRANGE_6                  RCC_ICSCR_MSIRANGE_6  /*!< MSI = 4.194 MHz */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
-  * @{
-  */
-#define LL_RCC_SYS_CLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
-  * @{
-  */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
-  * @{
-  */
-#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
-#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
-#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
-#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
-#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
-#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
-#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
-  * @{
-  */
-#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
-#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
-#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
-#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
-#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
-  * @{
-  */
-#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
-#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
-#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
-#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
-#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK  Wakeup from Stop and CSS backup clock selection
-  * @{
-  */
-#define LL_RCC_STOP_WAKEUPCLOCK_MSI        (0x00000000U) /*!< MSI selection after wake-up from STOP */
-#define LL_RCC_STOP_WAKEUPCLOCK_HSI        RCC_CFGR_STOPWUCK       /*!< HSI selection after wake-up from STOP */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
-  * @{
-  */
-#define LL_RCC_MCO1SOURCE_NOCLOCK          RCC_CFGR_MCOSEL_NOCLOCK      /*!< MCO output disabled, no clock on MCO */
-#define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_SYSCLK       /*!< SYSCLK selection as MCO source */
-#define LL_RCC_MCO1SOURCE_HSI              RCC_CFGR_MCOSEL_HSI          /*!< HSI selection as MCO source */
-#define LL_RCC_MCO1SOURCE_MSI              RCC_CFGR_MCOSEL_MSI          /*!< MSI selection as MCO source */
-#define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_HSE          /*!< HSE selection as MCO source */
-#define LL_RCC_MCO1SOURCE_LSI              RCC_CFGR_MCOSEL_LSI          /*!< LSI selection as MCO source */
-#define LL_RCC_MCO1SOURCE_LSE              RCC_CFGR_MCOSEL_LSE          /*!< LSE selection as MCO source */
-#if defined(RCC_CFGR_MCOSEL_HSI48)
-#define LL_RCC_MCO1SOURCE_HSI48            RCC_CFGR_MCOSEL_HSI48        /*!< HSI48 selection as MCO source */
-#endif /* RCC_CFGR_MCOSEL_HSI48 */
-#define LL_RCC_MCO1SOURCE_PLLCLK           RCC_CFGR_MCOSEL_PLL          /*!< PLLCLK selection as MCO source */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
-  * @{
-  */
-#define LL_RCC_MCO1_DIV_1                  RCC_CFGR_MCOPRE_DIV1  /*!< MCO Clock divided by 1  */
-#define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_DIV2  /*!< MCO Clock divided by 2  */
-#define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_DIV4  /*!< MCO Clock divided by 4  */
-#define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCOPRE_DIV8  /*!< MCO Clock divided by 8  */
-#define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
-  * @{
-  */
-#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U      /*!< No clock enabled for the peripheral            */
-#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU      /*!< Frequency cannot be provided as external clock */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup RCC_LL_EC_USART1_CLKSOURCE  Peripheral USART clock source selection
-  * @{
-  */
-#if defined(RCC_CCIPR_USART1SEL)
-#define LL_RCC_USART1_CLKSOURCE_PCLK2      (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U)             /*!< PCLK2 selected as USART1 clock */
-#define LL_RCC_USART1_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0)   /*!< SYSCLK selected as USART1 clock */
-#define LL_RCC_USART1_CLKSOURCE_HSI        (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1)   /*!< HSI selected as USART1 clock */
-#define LL_RCC_USART1_CLKSOURCE_LSE        (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)     /*!< LSE selected as USART1 clock*/
-#endif /* RCC_CCIPR_USART1SEL */
-#define LL_RCC_USART2_CLKSOURCE_PCLK1      (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U)             /*!< PCLK1 selected as USART2 clock */
-#define LL_RCC_USART2_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0)   /*!< SYSCLK selected as USART2 clock */
-#define LL_RCC_USART2_CLKSOURCE_HSI        (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1)   /*!< HSI selected as USART2 clock */
-#define LL_RCC_USART2_CLKSOURCE_LSE        (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)     /*!< LSE selected as USART2 clock*/
-/**
-  * @}
-  */
-
-
-
-/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE  Peripheral LPUART clock source selection
-  * @{
-  */
-#define LL_RCC_LPUART1_CLKSOURCE_PCLK1     0x00000000U   /*!< PCLK1 selected as LPUART1 clock */
-#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0  /*!< SYSCLK selected as LPUART1 clock */
-#define LL_RCC_LPUART1_CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1  /*!< HSI selected as LPUART1 clock */
-#define LL_RCC_LPUART1_CLKSOURCE_LSE       RCC_CCIPR_LPUART1SEL    /*!< LSE selected as LPUART1 clock*/
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE  Peripheral I2C clock source selection
-  * @{
-  */
-#define LL_RCC_I2C1_CLKSOURCE_PCLK1        (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (0x00000000U >> 4U))           /*!< PCLK1 selected as I2C1 clock */
-#define LL_RCC_I2C1_CLKSOURCE_SYSCLK       (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SEL_0 >> 4U))  /*!< SYSCLK selected as I2C1 clock */
-#define LL_RCC_I2C1_CLKSOURCE_HSI          (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SEL_1 >> 4U))  /*!< HSI selected as I2C1 clock */
-#if defined(RCC_CCIPR_I2C3SEL)
-#define LL_RCC_I2C3_CLKSOURCE_PCLK1        (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (0x00000000U >> 4U))           /*!< PCLK1 selected as I2C3 clock */
-#define LL_RCC_I2C3_CLKSOURCE_SYSCLK       (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SEL_0 >> 4U))  /*!< SYSCLK selected as I2C3 clock */
-#define LL_RCC_I2C3_CLKSOURCE_HSI          (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SEL_1 >> 4U))  /*!< HSI selected as I2C3 clock */
-#endif /*RCC_CCIPR_I2C3SEL*/
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
-  * @{
-  */
-#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1      (0x00000000U)          /*!< PCLK1 selected as LPTIM1 clock */
-#define LL_RCC_LPTIM1_CLKSOURCE_LSI        RCC_CCIPR_LPTIM1SEL_0  /*!< LSI selected as LPTIM1 clock */
-#define LL_RCC_LPTIM1_CLKSOURCE_HSI        RCC_CCIPR_LPTIM1SEL_1  /*!< HSI selected as LPTIM1 clock */
-#define LL_RCC_LPTIM1_CLKSOURCE_LSE        RCC_CCIPR_LPTIM1SEL    /*!< LSE selected as LPTIM1 clock*/
-/**
-  * @}
-  */
-
-#if defined(RCC_CCIPR_HSI48SEL)
-
-#if defined(RNG)
-/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
-  * @{
-  */
-#define LL_RCC_RNG_CLKSOURCE_PLL           (0x00000000U)          /*!< PLL selected as RNG clock */
-#define LL_RCC_RNG_CLKSOURCE_HSI48         RCC_CCIPR_HSI48SEL   /*!< HSI48 selected as RNG clock*/
-/**
-  * @}
-  */
-#endif /* RNG */
-#if defined(USB)
-/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
-  * @{
-  */
-#define LL_RCC_USB_CLKSOURCE_PLL           (0x00000000U)          /*!< PLL selected as USB clock */
-#define LL_RCC_USB_CLKSOURCE_HSI48         RCC_CCIPR_HSI48SEL   /*!< HSI48 selected as USB clock*/
-/**
-  * @}
-  */
-
-#endif /* USB */
-#endif /* RCC_CCIPR_HSI48SEL */
-
-
-/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
-  * @{
-  */
-#if defined(RCC_CCIPR_USART1SEL)
-#define LL_RCC_USART1_CLKSOURCE            RCC_CCIPR_USART1SEL    /*!< USART1 clock source selection bits */
-#endif /* RCC_CCIPR_USART1SEL */
-#define LL_RCC_USART2_CLKSOURCE            RCC_CCIPR_USART2SEL    /*!< USART2 clock source selection bits */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
-  * @{
-  */
-#define LL_RCC_LPUART1_CLKSOURCE           RCC_CCIPR_LPUART1SEL   /*!< LPUART1 clock source selection bits */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
-  * @{
-  */
-#define LL_RCC_I2C1_CLKSOURCE              RCC_CCIPR_I2C1SEL   /*!< I2C1 clock source selection bits */
-#if defined(RCC_CCIPR_I2C3SEL)
-#define LL_RCC_I2C3_CLKSOURCE              RCC_CCIPR_I2C3SEL   /*!< I2C3 clock source selection bits */
-#endif /*RCC_CCIPR_I2C3SEL*/
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
-  * @{
-  */
-#define LL_RCC_LPTIM1_CLKSOURCE            RCC_CCIPR_LPTIM1SEL  /*!< LPTIM1 clock source selection bits */
-/**
-  * @}
-  */
-
-#if defined(RCC_CCIPR_HSI48SEL)
-#if defined(RNG)
-/** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
-  * @{
-  */
-#define LL_RCC_RNG_CLKSOURCE               RCC_CCIPR_HSI48SEL   /*!< HSI48 RC clock source selection bit for RNG*/
-/**
-  * @}
-  */
-#endif /* RNG */
-
-#if defined(USB)
-/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
-  * @{
-  */
-#define LL_RCC_USB_CLKSOURCE               RCC_CCIPR_HSI48SEL  /*!< HSI48 RC clock source selection bit for USB*/
-/**
-  * @}
-  */
-
-#endif /* USB */
-#endif /* RCC_CCIPR_HSI48SEL */
-
-/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
-  * @{
-  */
-#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U         /*!< No clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_CSR_RTCSEL_LSE            /*!< LSE oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_CSR_RTCSEL_LSI            /*!< LSI oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_HSE           RCC_CSR_RTCSEL_HSE            /*!< HSE oscillator clock divided by a programmable prescaler
-                                                                             (selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
-  * @{
-  */
-#define LL_RCC_PLL_MUL_3                   RCC_CFGR_PLLMUL3  /*!< PLL input clock * 3  */
-#define LL_RCC_PLL_MUL_4                   RCC_CFGR_PLLMUL4  /*!< PLL input clock * 4  */
-#define LL_RCC_PLL_MUL_6                   RCC_CFGR_PLLMUL6  /*!< PLL input clock * 6  */
-#define LL_RCC_PLL_MUL_8                   RCC_CFGR_PLLMUL8  /*!< PLL input clock * 8  */
-#define LL_RCC_PLL_MUL_12                  RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */
-#define LL_RCC_PLL_MUL_16                  RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */
-#define LL_RCC_PLL_MUL_24                  RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */
-#define LL_RCC_PLL_MUL_32                  RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */
-#define LL_RCC_PLL_MUL_48                  RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLL_DIV PLL division factor
-  * @{
-  */
-#define LL_RCC_PLL_DIV_2                   RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */
-#define LL_RCC_PLL_DIV_3                   RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */
-#define LL_RCC_PLL_DIV_4                   RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
-  * @{
-  */
-#define LL_RCC_PLLSOURCE_HSI               RCC_CFGR_PLLSRC_HSI                           /*!< HSI clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE               RCC_CFGR_PLLSRC_HSE                           /*!< HSE clock selected as PLL entry clock source */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in RCC register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in RCC register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to calculate the PLLCLK frequency
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,
-  *                                      @ref LL_RCC_PLL_GetMultiplicator (),
-  *                                      @ref LL_RCC_PLL_GetDivider ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
-  * @param  __PLLMUL__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLL_MUL_3
-  *         @arg @ref LL_RCC_PLL_MUL_4
-  *         @arg @ref LL_RCC_PLL_MUL_6
-  *         @arg @ref LL_RCC_PLL_MUL_8
-  *         @arg @ref LL_RCC_PLL_MUL_12
-  *         @arg @ref LL_RCC_PLL_MUL_16
-  *         @arg @ref LL_RCC_PLL_MUL_24
-  *         @arg @ref LL_RCC_PLL_MUL_32
-  *         @arg @ref LL_RCC_PLL_MUL_48
-  * @param  __PLLDIV__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLL_DIV_2
-  *         @arg @ref LL_RCC_PLL_DIV_3
-  *         @arg @ref LL_RCC_PLL_DIV_4
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__,  __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_CFGR_PLLMUL_Pos]) / (((__PLLDIV__) >> RCC_CFGR_PLLDIV_Pos)+1UL))
-
-/**
-  * @brief  Helper macro to calculate the HCLK frequency
-  * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
-  *        ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
-  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
-  * @param  __AHBPRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  * @retval HCLK clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
-
-/**
-  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
-  * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
-  *        ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
-  * @param  __HCLKFREQ__ HCLK frequency
-  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  * @retval PCLK1 clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
-
-/**
-  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
-  * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
-  *        ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
-  * @param  __HCLKFREQ__ HCLK frequency
-  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB2_DIV_1
-  *         @arg @ref LL_RCC_APB2_DIV_2
-  *         @arg @ref LL_RCC_APB2_DIV_4
-  *         @arg @ref LL_RCC_APB2_DIV_8
-  *         @arg @ref LL_RCC_APB2_DIV_16
-  * @retval PCLK2 clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
-
-/**
-  * @brief  Helper macro to calculate the MSI frequency (in Hz)
-  * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange
-  *        ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange())
-  * @param  __MSIRANGE__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MSIRANGE_0
-  *         @arg @ref LL_RCC_MSIRANGE_1
-  *         @arg @ref LL_RCC_MSIRANGE_2
-  *         @arg @ref LL_RCC_MSIRANGE_3
-  *         @arg @ref LL_RCC_MSIRANGE_4
-  *         @arg @ref LL_RCC_MSIRANGE_5
-  *         @arg @ref LL_RCC_MSIRANGE_6
-  * @retval MSI clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) (32768UL * ( 1UL << (((__MSIRANGE__) >> RCC_ICSCR_MSIRANGE_Pos) + 1UL) ))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
-  * @{
-  */
-
-/** @defgroup RCC_LL_EF_HSE HSE
-  * @{
-  */
-
-#if defined(RCC_HSECSS_SUPPORT)
-/**
-  * @brief  Enable the Clock Security System.
-  * @rmtoll CR           CSSHSEON         LL_RCC_HSE_EnableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_CSSON);
-}
-#endif /* RCC_HSECSS_SUPPORT */
-
-/**
-  * @brief  Enable HSE external oscillator (HSE Bypass)
-  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
-  * @brief  Disable HSE external oscillator (HSE Bypass)
-  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
-  * @brief  Enable HSE crystal oscillator (HSE ON)
-  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
-  * @brief  Disable HSE crystal oscillator (HSE ON)
-  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
-  * @brief  Check if HSE oscillator Ready
-  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the RTC prescaler (divider)
-  * @rmtoll CR           RTCPRE        LL_RCC_SetRTC_HSEPrescaler
-  * @param  Div This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div)
-{
-  MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div);
-}
-
-/**
-  * @brief  Get the RTC divider (prescaler)
-  * @rmtoll CR           RTCPRE        LL_RCC_GetRTC_HSEPrescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_HSI HSI
-  * @{
-  */
-
-/**
-  * @brief  Enable HSI oscillator
-  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
-  * @brief  Disable HSI oscillator
-  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
-  * @brief  Check if HSI clock is ready
-  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable HSI even in stop mode
-  * @note HSI oscillator is forced ON even in Stop mode
-  * @rmtoll CR           HSIKERON      LL_RCC_HSI_EnableInStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSIKERON);
-}
-
-/**
-  * @brief  Disable HSI in stop mode
-  * @rmtoll CR           HSIKERON      LL_RCC_HSI_DisableInStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
-}
-
-/**
-  * @brief  Enable HSI Divider (it divides by 4)
-  * @rmtoll CR           HSIDIVEN       LL_RCC_HSI_EnableDivider
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_EnableDivider(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSIDIVEN);
-}
-
-/**
-  * @brief  Disable HSI Divider (it divides by 4)
-  * @rmtoll CR           HSIDIVEN       LL_RCC_HSI_DisableDivider
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_DisableDivider(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSIDIVEN);
-}
-
-
-
-#if defined(RCC_CR_HSIOUTEN)
-/**
-  * @brief  Enable HSI Output
-  * @rmtoll CR           HSIOUTEN       LL_RCC_HSI_EnableOutput
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_EnableOutput(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSIOUTEN);
-}
-
-/**
-  * @brief  Disable HSI Output
-  * @rmtoll CR           HSIOUTEN       LL_RCC_HSI_DisableOutput
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_DisableOutput(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN);
-}
-#endif /* RCC_CR_HSIOUTEN */
-
-/**
-  * @brief  Get HSI Calibration value
-  * @note When HSITRIM is written, HSICAL is updated with the sum of
-  *       HSITRIM and the factory trim value
-  * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
-  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
-{
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
-}
-
-/**
-  * @brief  Set HSI Calibration trimming
-  * @note user-programmable trimming value that is added to the HSICAL
-  * @note Default value is 16, which, when added to the HSICAL value,
-  *       should trim the HSI to 16 MHz +/- 1 %
-  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
-  * @param  Value between Min_Data = 0x00 and Max_Data = 0x1F
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
-{
-  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
-}
-
-/**
-  * @brief  Get HSI Calibration trimming
-  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
-  * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
-{
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
-}
-
-/**
-  * @}
-  */
-
-#if defined(RCC_HSI48_SUPPORT)
-/** @defgroup RCC_LL_EF_HSI48 HSI48
-  * @{
-  */
-
-/**
-  * @brief  Enable HSI48
-  * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
-{
-  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
-}
-
-/**
-  * @brief  Disable HSI48
-  * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
-{
-  CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
-}
-
-/**
-  * @brief  Check if HSI48 oscillator Ready
-  * @rmtoll CRRCR          HSI48RDY      LL_RCC_HSI48_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
-{
-  return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get HSI48 Calibration value
-  * @rmtoll CRRCR          HSI48CAL      LL_RCC_HSI48_GetCalibration
-  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
-}
-
-#if defined(RCC_CRRCR_HSI48DIV6OUTEN)
-/**
-  * @brief  Enable HSI48 Divider (it divides by 6)
-  * @rmtoll CRRCR           HSI48DIV6OUTEN       LL_RCC_HSI48_EnableDivider
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI48_EnableDivider(void)
-{
-  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN);
-}
-
-/**
-  * @brief  Disable HSI48 Divider (it divides by 6)
-  * @rmtoll CRRCR           HSI48DIV6OUTEN       LL_RCC_HSI48_DisableDivider
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI48_DisableDivider(void)
-{
-  CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN);
-}
-
-/**
-  * @brief  Check if HSI48 Divider is enabled (it divides by 6)
-  * @rmtoll CRRCR        HSI48DIV6OUTEN        LL_RCC_HSI48_IsDivided
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI48_IsDivided(void)
-{
-  return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN) == RCC_CRRCR_HSI48DIV6OUTEN) ? 1UL : 0UL);
-}
-
-#endif /*RCC_CRRCR_HSI48DIV6OUTEN*/
-
-/**
-  * @}
-  */
-
-#endif /* RCC_HSI48_SUPPORT */
-
-/** @defgroup RCC_LL_EF_LSE LSE
-  * @{
-  */
-
-/**
-  * @brief  Enable  Low Speed External (LSE) crystal.
-  * @rmtoll CSR         LSEON         LL_RCC_LSE_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_Enable(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_LSEON);
-}
-
-/**
-  * @brief  Disable  Low Speed External (LSE) crystal.
-  * @rmtoll CSR         LSEON         LL_RCC_LSE_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_Disable(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);
-}
-
-/**
-  * @brief  Enable external clock source (LSE bypass).
-  * @rmtoll CSR         LSEBYP        LL_RCC_LSE_EnableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);
-}
-
-/**
-  * @brief  Disable external clock source (LSE bypass).
-  * @rmtoll CSR         LSEBYP        LL_RCC_LSE_DisableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);
-}
-
-/**
-  * @brief  Set LSE oscillator drive capability
-  * @note The oscillator is in Xtal mode when it is not in bypass mode.
-  * @rmtoll CSR         LSEDRV        LL_RCC_LSE_SetDriveCapability
-  * @param  LSEDrive This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LSEDRIVE_LOW
-  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
-  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
-  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
-{
-  MODIFY_REG(RCC->CSR, RCC_CSR_LSEDRV, LSEDrive);
-}
-
-/**
-  * @brief  Get LSE oscillator drive capability
-  * @rmtoll CSR         LSEDRV        LL_RCC_LSE_GetDriveCapability
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_LSEDRIVE_LOW
-  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
-  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
-  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_LSEDRV));
-}
-
-/**
-  * @brief  Enable Clock security system on LSE.
-  * @rmtoll CSR         LSECSSON      LL_RCC_LSE_EnableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_LSECSSON);
-}
-
-/**
-  * @brief  Disable Clock security system on LSE.
-  * @note   Clock security system can be disabled only after a LSE
-  *         failure detection. In that case it MUST be disabled by software.
-  * @rmtoll CSR          LSECSSON      LL_RCC_LSE_DisableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON);
-}
-
-/**
-  * @brief  Check if LSE oscillator Ready
-  * @rmtoll CSR         LSERDY        LL_RCC_LSE_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == RCC_CSR_LSERDY) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if CSS on LSE failure Detection
-  * @rmtoll CSR         LSECSSD       LL_RCC_LSE_IsCSSDetected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == RCC_CSR_LSECSSD) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_LSI LSI
-  * @{
-  */
-
-/**
-  * @brief  Enable LSI Oscillator
-  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSI_Enable(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
-  * @brief  Disable LSI Oscillator
-  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
-  * @brief  Check if LSI is Ready
-  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_MSI MSI
-  * @{
-  */
-
-/**
-  * @brief  Enable MSI oscillator
-  * @rmtoll CR           MSION         LL_RCC_MSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_MSI_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_MSION);
-}
-
-/**
-  * @brief  Disable MSI oscillator
-  * @rmtoll CR           MSION         LL_RCC_MSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_MSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_MSION);
-}
-
-/**
-  * @brief  Check if MSI oscillator Ready
-  * @rmtoll CR           MSIRDY        LL_RCC_MSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
-  * @rmtoll ICSCR           MSIRANGE      LL_RCC_MSI_SetRange
-  * @param  Range This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MSIRANGE_0
-  *         @arg @ref LL_RCC_MSIRANGE_1
-  *         @arg @ref LL_RCC_MSIRANGE_2
-  *         @arg @ref LL_RCC_MSIRANGE_3
-  *         @arg @ref LL_RCC_MSIRANGE_4
-  *         @arg @ref LL_RCC_MSIRANGE_5
-  *         @arg @ref LL_RCC_MSIRANGE_6
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
-{
-  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
-}
-
-/**
-  * @brief  Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
-  * @rmtoll ICSCR           MSIRANGE      LL_RCC_MSI_GetRange
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_MSIRANGE_0
-  *         @arg @ref LL_RCC_MSIRANGE_1
-  *         @arg @ref LL_RCC_MSIRANGE_2
-  *         @arg @ref LL_RCC_MSIRANGE_3
-  *         @arg @ref LL_RCC_MSIRANGE_4
-  *         @arg @ref LL_RCC_MSIRANGE_5
-  *         @arg @ref LL_RCC_MSIRANGE_6
-  */
-__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
-{
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE));
-}
-
-/**
-  * @brief  Get MSI Calibration value
-  * @note When MSITRIM is written, MSICAL is updated with the sum of
-  *       MSITRIM and the factory trim value
-  * @rmtoll ICSCR        MSICAL        LL_RCC_MSI_GetCalibration
-  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
-  */
-__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
-{
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
-}
-
-/**
-  * @brief  Set MSI Calibration trimming
-  * @note user-programmable trimming value that is added to the MSICAL
-  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_SetCalibTrimming
-  * @param  Value between Min_Data = 0x00 and Max_Data = 0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
-{
-  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
-}
-
-/**
-  * @brief  Get MSI Calibration trimming
-  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_GetCalibTrimming
-  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
-  */
-__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
-{
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_System System
-  * @{
-  */
-
-/**
-  * @brief  Configure the system clock source
-  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
-}
-
-/**
-  * @brief  Get the system clock source
-  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
-}
-
-/**
-  * @brief  Set AHB prescaler
-  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
-}
-
-/**
-  * @brief  Set APB1 prescaler
-  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
-}
-
-/**
-  * @brief  Set APB2 prescaler
-  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB2_DIV_1
-  *         @arg @ref LL_RCC_APB2_DIV_2
-  *         @arg @ref LL_RCC_APB2_DIV_4
-  *         @arg @ref LL_RCC_APB2_DIV_8
-  *         @arg @ref LL_RCC_APB2_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
-}
-
-/**
-  * @brief  Get AHB prescaler
-  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
-}
-
-/**
-  * @brief  Get APB1 prescaler
-  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
-}
-
-/**
-  * @brief  Get APB2 prescaler
-  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_APB2_DIV_1
-  *         @arg @ref LL_RCC_APB2_DIV_2
-  *         @arg @ref LL_RCC_APB2_DIV_4
-  *         @arg @ref LL_RCC_APB2_DIV_8
-  *         @arg @ref LL_RCC_APB2_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
-}
-
-/**
-  * @brief  Set Clock After Wake-Up From Stop mode
-  * @rmtoll CFGR         STOPWUCK      LL_RCC_SetClkAfterWakeFromStop
-  * @param  Clock This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
-  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
-}
-
-/**
-  * @brief  Get Clock After Wake-Up From Stop mode
-  * @rmtoll CFGR         STOPWUCK      LL_RCC_GetClkAfterWakeFromStop
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
-  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_MCO MCO
-  * @{
-  */
-
-/**
-  * @brief  Configure MCOx
-  * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
-  *         CFGR         MCOPRE        LL_RCC_ConfigMCO
-  * @param  MCOxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
-  *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
-  *         @arg @ref LL_RCC_MCO1SOURCE_MSI
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
-  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
-  *         @arg @ref LL_RCC_MCO1SOURCE_LSI
-  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  MCOxPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MCO1_DIV_1
-  *         @arg @ref LL_RCC_MCO1_DIV_2
-  *         @arg @ref LL_RCC_MCO1_DIV_4
-  *         @arg @ref LL_RCC_MCO1_DIV_8
-  *         @arg @ref LL_RCC_MCO1_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
-  * @{
-  */
-
-/**
-  * @brief  Configure USARTx clock source
-  * @rmtoll CCIPR        USARTxSEL     LL_RCC_SetUSARTClockSource
-  * @param  USARTxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*)
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*)
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*)
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
-{
-  MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
-}
-
-/**
-  * @brief  Configure LPUART1x clock source
-  * @rmtoll CCIPR        LPUART1SEL    LL_RCC_SetLPUARTClockSource
-  * @param  LPUARTxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
-{
-  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
-}
-
-/**
-  * @brief  Configure I2Cx clock source
-  * @rmtoll CCIPR        I2CxSEL       LL_RCC_SetI2CClockSource
-  * @param  I2CxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*)
-  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
-  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
-{
-  MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4U) & 0x000FF000U), ((I2CxSource << 4U) & 0x000FF000U));
-}
-
-/**
-  * @brief  Configure LPTIMx clock source
-  * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_SetLPTIMClockSource
-  * @param  LPTIMxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
-{
-  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
-}
-
-#if defined(RCC_CCIPR_HSI48SEL)
-#if defined(RNG)
-/**
-  * @brief  Configure RNG clock source
-  * @rmtoll CCIPR        HSI48SEL      LL_RCC_SetRNGClockSource
-  * @param  RNGxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
-{
-  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, RNGxSource);
-}
-#endif /* RNG */
-
-#if defined(USB)
-/**
-  * @brief  Configure USB clock source
-  * @rmtoll CCIPR        HSI48SEL      LL_RCC_SetUSBClockSource
-  * @param  USBxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
-{
-  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, USBxSource);
-}
-#endif /* USB */
-
-#endif /* RCC_CCIPR_HSI48SEL */
-
-/**
-  * @brief  Get USARTx clock source
-  * @rmtoll CCIPR        USARTxSEL     LL_RCC_GetUSARTClockSource
-  * @param  USARTx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE (*)
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*)
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*)
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*)
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
-}
-
-
-
-/**
-  * @brief  Get LPUARTx clock source
-  * @rmtoll CCIPR        LPUART1SEL    LL_RCC_GetLPUARTClockSource
-  * @param  LPUARTx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
-}
-
-/**
-  * @brief  Get I2Cx clock source
-  * @rmtoll CCIPR        I2CxSEL       LL_RCC_GetI2CClockSource
-  * @param  I2Cx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
-  *         @arg @ref LL_RCC_I2C3_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1  (*)
-  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK  (*)
-  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI   (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
-{
-  return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4U) | (I2Cx << 4U));
-}
-
-/**
-  * @brief  Get LPTIMx clock source
-  * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_GetLPTIMClockSource
-  * @param  LPTIMx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx));
-}
-
-#if defined(RCC_CCIPR_HSI48SEL)
-#if defined(RNG)
-/**
-  * @brief  Get RNGx clock source
-  * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetRNGClockSource
-  * @param  RNGx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
-}
-#endif /* RNG */
-
-#if defined(USB)
-/**
-  * @brief  Get USBx clock source
-  * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetUSBClockSource
-  * @param  USBx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
-}
-#endif /* USB */
-
-#endif /* RCC_CCIPR_HSI48SEL */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_RTC RTC
-  * @{
-  */
-
-/**
-  * @brief  Set RTC Clock Source
-  * @note Once the RTC clock source has been selected, it cannot be changed any more unless
-  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
-  *       set). The RTCRST bit can be used to reset them.
-  * @rmtoll CSR         RTCSEL        LL_RCC_SetRTCClockSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source);
-}
-
-/**
-  * @brief  Get RTC Clock Source
-  * @rmtoll CSR         RTCSEL        LL_RCC_GetRTCClockSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL));
-}
-
-/**
-  * @brief  Enable RTC
-  * @rmtoll CSR         RTCEN         LL_RCC_EnableRTC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableRTC(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_RTCEN);
-}
-
-/**
-  * @brief  Disable RTC
-  * @rmtoll CSR         RTCEN         LL_RCC_DisableRTC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableRTC(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN);
-}
-
-/**
-  * @brief  Check if RTC has been enabled or not
-  * @rmtoll CSR         RTCEN         LL_RCC_IsEnabledRTC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == RCC_CSR_RTCEN) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Force the Backup domain reset
-  * @rmtoll CSR         RTCRST         LL_RCC_ForceBackupDomainReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_RTCRST);
-}
-
-/**
-  * @brief  Release the Backup domain reset
-  * @rmtoll CSR         RTCRST         LL_RCC_ReleaseBackupDomainReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_PLL PLL
-  * @{
-  */
-
-/**
-  * @brief  Enable PLL
-  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
-  * @brief  Disable PLL
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
-  * @brief  Check if PLL Ready
-  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure PLL used for SYSCLK Domain
-  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
-  *         CFGR         PLLMUL        LL_RCC_PLL_ConfigDomain_SYS\n
-  *         CFGR         PLLDIV        LL_RCC_PLL_ConfigDomain_SYS
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLMul This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLL_MUL_3
-  *         @arg @ref LL_RCC_PLL_MUL_4
-  *         @arg @ref LL_RCC_PLL_MUL_6
-  *         @arg @ref LL_RCC_PLL_MUL_8
-  *         @arg @ref LL_RCC_PLL_MUL_12
-  *         @arg @ref LL_RCC_PLL_MUL_16
-  *         @arg @ref LL_RCC_PLL_MUL_24
-  *         @arg @ref LL_RCC_PLL_MUL_32
-  *         @arg @ref LL_RCC_PLL_MUL_48
-  * @param  PLLDiv This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLL_DIV_2
-  *         @arg @ref LL_RCC_PLL_DIV_3
-  *         @arg @ref LL_RCC_PLL_DIV_4
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv);
-}
-
-/**
-  * @brief  Configure PLL clock source
-  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_SetMainSource
-  * @param  PLLSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
-}
-
-/**
-  * @brief  Get the oscillator used as PLL clock source.
-  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_GetMainSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
-}
-
-/**
-  * @brief  Get PLL multiplication Factor
-  * @rmtoll CFGR         PLLMUL        LL_RCC_PLL_GetMultiplicator
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLL_MUL_3
-  *         @arg @ref LL_RCC_PLL_MUL_4
-  *         @arg @ref LL_RCC_PLL_MUL_6
-  *         @arg @ref LL_RCC_PLL_MUL_8
-  *         @arg @ref LL_RCC_PLL_MUL_12
-  *         @arg @ref LL_RCC_PLL_MUL_16
-  *         @arg @ref LL_RCC_PLL_MUL_24
-  *         @arg @ref LL_RCC_PLL_MUL_32
-  *         @arg @ref LL_RCC_PLL_MUL_48
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
-}
-
-/**
-  * @brief  Get Division factor for the main PLL and other PLL
-  * @rmtoll CFGR         PLLDIV        LL_RCC_PLL_GetDivider
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLL_DIV_2
-  *         @arg @ref LL_RCC_PLL_DIV_3
-  *         @arg @ref LL_RCC_PLL_DIV_4
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Clear LSI ready interrupt flag
-  * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
-}
-
-/**
-  * @brief  Clear LSE ready interrupt flag
-  * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
-}
-
-/**
-  * @brief  Clear MSI ready interrupt flag
-  * @rmtoll CICR         MSIRDYC       LL_RCC_ClearFlag_MSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
-}
-
-/**
-  * @brief  Clear HSI ready interrupt flag
-  * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
-}
-
-/**
-  * @brief  Clear HSE ready interrupt flag
-  * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
-}
-
-/**
-  * @brief  Clear PLL ready interrupt flag
-  * @rmtoll CICR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
-}
-
-#if defined(RCC_HSI48_SUPPORT)
-/**
-  * @brief  Clear HSI48 ready interrupt flag
-  * @rmtoll CICR          HSI48RDYC     LL_RCC_ClearFlag_HSI48RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
-}
-#endif /* RCC_HSI48_SUPPORT */
-
-#if defined(RCC_HSECSS_SUPPORT)
-/**
-  * @brief  Clear Clock security system interrupt flag
-  * @rmtoll CICR         CSSC          LL_RCC_ClearFlag_HSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_CSSC);
-}
-#endif /* RCC_HSECSS_SUPPORT */
-
-/**
-  * @brief  Clear LSE Clock security system interrupt flag
-  * @rmtoll CICR         LSECSSC       LL_RCC_ClearFlag_LSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
-}
-
-/**
-  * @brief  Check if LSI ready interrupt occurred or not
-  * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if LSE ready interrupt occurred or not
-  * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if MSI ready interrupt occurred or not
-  * @rmtoll CIFR         MSIRDYF       LL_RCC_IsActiveFlag_MSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if HSI ready interrupt occurred or not
-  * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if HSE ready interrupt occurred or not
-  * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if PLL ready interrupt occurred or not
-  * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == RCC_CIFR_PLLRDYF) ? 1UL : 0UL);
-}
-
-#if defined(RCC_HSI48_SUPPORT)
-/**
-  * @brief  Check if HSI48 ready interrupt occurred or not
-  * @rmtoll CIFR          HSI48RDYF     LL_RCC_IsActiveFlag_HSI48RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL);
-}
-#endif /* RCC_HSI48_SUPPORT */
-
-#if defined(RCC_HSECSS_SUPPORT)
-/**
-  * @brief  Check if Clock security system interrupt occurred or not
-  * @rmtoll CIFR         CSSF          LL_RCC_IsActiveFlag_HSECSS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL);
-}
-#endif /* RCC_HSECSS_SUPPORT */
-
-/**
-  * @brief  Check if LSE Clock security system interrupt occurred or not
-  * @rmtoll CIFR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if HSI Divider is enabled (it divides by 4)
-  * @rmtoll CR        HSIDIVF        LL_RCC_IsActiveFlag_HSIDIV
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIDIV(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == RCC_CR_HSIDIVF) ? 1UL : 0UL);
-}
-
-#if defined(RCC_CSR_FWRSTF)
-/**
-  * @brief  Check if RCC flag FW reset is set or not.
-  * @rmtoll CSR          FWRSTF        LL_RCC_IsActiveFlag_FWRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == RCC_CSR_FWRSTF) ? 1UL : 0UL);
-}
-#endif /* RCC_CSR_FWRSTF */
-
-/**
-  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
-  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Low Power reset is set or not.
-  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag is set or not.
-  * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Pin reset is set or not.
-  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag POR/PDR reset is set or not.
-  * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == RCC_CSR_PORRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Software reset is set or not.
-  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Window Watchdog reset is set or not.
-  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set RMVF bit to clear the reset flags.
-  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_IT_Management IT Management
-  * @{
-  */
-
-/**
-  * @brief  Enable LSI ready interrupt
-  * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
-}
-
-/**
-  * @brief  Enable LSE ready interrupt
-  * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
-}
-
-/**
-  * @brief  Enable MSI ready interrupt
-  * @rmtoll CIER         MSIRDYIE      LL_RCC_EnableIT_MSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
-}
-
-/**
-  * @brief  Enable HSI ready interrupt
-  * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
-}
-
-/**
-  * @brief  Enable HSE ready interrupt
-  * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
-}
-
-/**
-  * @brief  Enable PLL ready interrupt
-  * @rmtoll CIER         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
-}
-
-#if defined(RCC_HSI48_SUPPORT)
-/**
-  * @brief  Enable HSI48 ready interrupt
-  * @rmtoll CIER          HSI48RDYIE    LL_RCC_EnableIT_HSI48RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
-}
-#endif /* RCC_HSI48_SUPPORT */
-
-/**
-  * @brief  Enable LSE clock security system interrupt
-  * @rmtoll CIER         LSECSSIE      LL_RCC_EnableIT_LSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
-}
-
-/**
-  * @brief  Disable LSI ready interrupt
-  * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
-}
-
-/**
-  * @brief  Disable LSE ready interrupt
-  * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
-}
-
-/**
-  * @brief  Disable MSI ready interrupt
-  * @rmtoll CIER         MSIRDYIE      LL_RCC_DisableIT_MSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
-}
-
-/**
-  * @brief  Disable HSI ready interrupt
-  * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
-}
-
-/**
-  * @brief  Disable HSE ready interrupt
-  * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
-}
-
-/**
-  * @brief  Disable PLL ready interrupt
-  * @rmtoll CIER         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
-}
-
-#if defined(RCC_HSI48_SUPPORT)
-/**
-  * @brief  Disable HSI48 ready interrupt
-  * @rmtoll CIER          HSI48RDYIE    LL_RCC_DisableIT_HSI48RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
-}
-#endif /* RCC_HSI48_SUPPORT */
-
-/**
-  * @brief  Disable LSE clock security system interrupt
-  * @rmtoll CIER         LSECSSIE      LL_RCC_DisableIT_LSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
-}
-
-/**
-  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if MSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         MSIRDYIE      LL_RCC_IsEnabledIT_MSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if PLL ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == RCC_CIER_PLLRDYIE) ? 1UL : 0UL);
-}
-
-#if defined(RCC_HSI48_SUPPORT)
-/**
-  * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
-  * @rmtoll CIER          HSI48RDYIE    LL_RCC_IsEnabledIT_HSI48RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
-}
-#endif /* RCC_HSI48_SUPPORT */
-
-/**
-  * @brief  Checks if LSECSS interrupt source is enabled or disabled.
-  * @rmtoll CIER         LSECSSIE      LL_RCC_IsEnabledIT_LSECSS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EF_Init De-initialization function
-  * @{
-  */
-ErrorStatus LL_RCC_DeInit(void);
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
-  * @{
-  */
-void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
-uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
-uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
-uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
-uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
-#if defined(USB_OTG_FS) || defined(USB)
-uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
-#endif /* USB_OTG_FS || USB */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* RCC */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h
deleted file mode 100644
index 168993ad99..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_rng.h
-  * @author  MCD Application Team
-  * @brief   Header file of RNG LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_LL_RNG_H
-#define STM32L0xx_LL_RNG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (RNG)
-
-/** @defgroup RNG_LL RNG
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
-  * @{
-  */
-
-
-/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_RNG_ReadReg function
-  * @{
-  */
-#define LL_RNG_SR_DRDY RNG_SR_DRDY    /*!< Register contains valid random data */
-#define LL_RNG_SR_CECS RNG_SR_CECS    /*!< Clock error current status */
-#define LL_RNG_SR_SECS RNG_SR_SECS    /*!< Seed error current status */
-#define LL_RNG_SR_CEIS RNG_SR_CEIS    /*!< Clock error interrupt status */
-#define LL_RNG_SR_SEIS RNG_SR_SEIS    /*!< Seed error interrupt status */
-/**
-  * @}
-  */
-
-/** @defgroup RNG_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_RNG_ReadReg and  LL_RNG_WriteReg macros
-  * @{
-  */
-#define LL_RNG_CR_IE   RNG_CR_IE      /*!< RNG Interrupt enable */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
-  * @{
-  */
-
-/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in RNG register
-  * @param  __INSTANCE__ RNG Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in RNG register
-  * @param  __INSTANCE__ RNG Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
-  * @{
-  */
-/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  Enable Random Number Generation
-  * @rmtoll CR           RNGEN         LL_RNG_Enable
-  * @param  RNGx RNG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
-{
-  SET_BIT(RNGx->CR, RNG_CR_RNGEN);
-}
-
-/**
-  * @brief  Disable Random Number Generation
-  * @rmtoll CR           RNGEN         LL_RNG_Disable
-  * @param  RNGx RNG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
-{
-  CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
-}
-
-/**
-  * @brief  Check if Random Number Generator is enabled
-  * @rmtoll CR           RNGEN         LL_RNG_IsEnabled
-  * @param  RNGx RNG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
-{
-  return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Indicate if the RNG Data ready Flag is set or not
-  * @rmtoll SR           DRDY          LL_RNG_IsActiveFlag_DRDY
-  * @param  RNGx RNG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
-{
-  return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate if the Clock Error Current Status Flag is set or not
-  * @rmtoll SR           CECS          LL_RNG_IsActiveFlag_CECS
-  * @param  RNGx RNG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
-{
-  return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate if the Seed Error Current Status Flag is set or not
-  * @rmtoll SR           SECS          LL_RNG_IsActiveFlag_SECS
-  * @param  RNGx RNG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
-{
-  return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate if the Clock Error Interrupt Status Flag is set or not
-  * @rmtoll SR           CEIS          LL_RNG_IsActiveFlag_CEIS
-  * @param  RNGx RNG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
-{
-  return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate if the Seed Error Interrupt Status Flag is set or not
-  * @rmtoll SR           SEIS          LL_RNG_IsActiveFlag_SEIS
-  * @param  RNGx RNG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
-{
-  return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear Clock Error interrupt Status (CEIS) Flag
-  * @rmtoll SR           CEIS          LL_RNG_ClearFlag_CEIS
-  * @param  RNGx RNG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
-{
-  WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
-}
-
-/**
-  * @brief  Clear Seed Error interrupt Status (SEIS) Flag
-  * @rmtoll SR           SEIS          LL_RNG_ClearFlag_SEIS
-  * @param  RNGx RNG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
-{
-  WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_LL_EF_IT_Management IT Management
-  * @{
-  */
-
-/**
-  * @brief  Enable Random Number Generator Interrupt
-  *         (applies for either Seed error, Clock Error or Data ready interrupts)
-  * @rmtoll CR           IE            LL_RNG_EnableIT
-  * @param  RNGx RNG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
-{
-  SET_BIT(RNGx->CR, RNG_CR_IE);
-}
-
-/**
-  * @brief  Disable Random Number Generator Interrupt
-  *         (applies for either Seed error, Clock Error or Data ready interrupts)
-  * @rmtoll CR           IE            LL_RNG_DisableIT
-  * @param  RNGx RNG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
-{
-  CLEAR_BIT(RNGx->CR, RNG_CR_IE);
-}
-
-/**
-  * @brief  Check if Random Number Generator Interrupt is enabled
-  *         (applies for either Seed error, Clock Error or Data ready interrupts)
-  * @rmtoll CR           IE            LL_RNG_IsEnabledIT
-  * @param  RNGx RNG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
-{
-  return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_LL_EF_Data_Management Data Management
-  * @{
-  */
-
-/**
-  * @brief  Return32-bit Random Number value
-  * @rmtoll DR           RNDATA        LL_RNG_ReadRandData32
-  * @param  RNGx RNG Instance
-  * @retval Generated 32-bit random value
-  */
-__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
-{
-  return (uint32_t)(READ_REG(RNGx->DR));
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* RNG */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_RNG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h
deleted file mode 100644
index 066e51d1c2..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h
+++ /dev/null
@@ -1,3812 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_rtc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RTC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_LL_RTC_H
-#define STM32L0xx_LL_RTC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined(RTC)
-
-/** @defgroup RTC_LL RTC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_LL_Private_Constants RTC Private Constants
-  * @{
-  */
-/* Masks Definition */
-#define RTC_LL_INIT_MASK                 (0xFFFFFFFFU)
-#define RTC_LL_RSF_MASK                  (0xFFFFFF5FU)
-
-/* Write protection defines */
-#define RTC_WRITE_PROTECTION_DISABLE  ((uint8_t)0xFF)
-#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCA)
-#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53)
-
-/* Defines used to combine date & time */
-#define RTC_OFFSET_WEEKDAY            (24U)
-#define RTC_OFFSET_DAY                (16U)
-#define RTC_OFFSET_MONTH              (8U)
-#define RTC_OFFSET_HOUR               (16U)
-#define RTC_OFFSET_MINUTE             (8U)
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_Private_Macros RTC Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  RTC Init structures definition
-  */
-typedef struct
-{
-  uint32_t HourFormat;   /*!< Specifies the RTC Hours Format.
-                              This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
-
-                              This feature can be modified afterwards using unitary function
-                              @ref LL_RTC_SetHourFormat(). */
-
-  uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
-                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
-
-                              This feature can be modified afterwards using unitary function
-                              @ref LL_RTC_SetAsynchPrescaler(). */
-
-  uint32_t SynchPrescaler;  /*!< Specifies the RTC Synchronous Predivider value.
-                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
-
-                              This feature can be modified afterwards using unitary function
-                              @ref LL_RTC_SetSynchPrescaler(). */
-} LL_RTC_InitTypeDef;
-
-/**
-  * @brief  RTC Time structure definition
-  */
-typedef struct
-{
-  uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
-                            This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
-
-                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
-
-  uint8_t Hours;       /*!< Specifies the RTC Time Hours.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
-
-                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
-
-  uint8_t Minutes;     /*!< Specifies the RTC Time Minutes.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 59
-
-                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
-
-  uint8_t Seconds;     /*!< Specifies the RTC Time Seconds.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 59
-
-                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
-} LL_RTC_TimeTypeDef;
-
-/**
-  * @brief  RTC Date structure definition
-  */
-typedef struct
-{
-  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
-                         This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
-
-                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
-
-  uint8_t Month;    /*!< Specifies the RTC Date Month.
-                         This parameter can be a value of @ref RTC_LL_EC_MONTH
-
-                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
-
-  uint8_t Day;      /*!< Specifies the RTC Date Day.
-                         This parameter must be a number between Min_Data = 1 and Max_Data = 31
-
-                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
-
-  uint8_t Year;     /*!< Specifies the RTC Date Year.
-                         This parameter must be a number between Min_Data = 0 and Max_Data = 99
-
-                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
-} LL_RTC_DateTypeDef;
-
-/**
-  * @brief  RTC Alarm structure definition
-  */
-typedef struct
-{
-  LL_RTC_TimeTypeDef AlarmTime;  /*!< Specifies the RTC Alarm Time members. */
-
-  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
-                                      This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
-
-                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
-                                      or @ref LL_RTC_ALMB_SetMask() for ALARM B
-                                 */
-
-  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on day or WeekDay.
-                                      This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
-
-                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
-                                      for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
-                                 */
-
-  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Day/WeekDay.
-                                      If AlarmDateWeekDaySel set to day, this parameter  must be a number between Min_Data = 1 and Max_Data = 31.
-
-                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
-                                      for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
-
-                                      If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
-
-                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
-                                      for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
-                                 */
-} LL_RTC_AlarmTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
-  * @{
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_EC_FORMAT FORMAT
-  * @{
-  */
-#define LL_RTC_FORMAT_BIN                  0x000000000U /*!< Binary data format */
-#define LL_RTC_FORMAT_BCD                  0x000000001U /*!< BCD data format */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
-  * @{
-  */
-#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm A Date is selected */
-#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
-  * @{
-  */
-#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm B Date is selected */
-#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL        /*!< Alarm B WeekDay is selected */
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_RTC_ReadReg function
-  * @{
-  */
-#define LL_RTC_ISR_ITSF                    RTC_ISR_ITSF
-#define LL_RTC_ISR_RECALPF                 RTC_ISR_RECALPF
-#define LL_RTC_ISR_TAMP3F                  RTC_ISR_TAMP3F
-#define LL_RTC_ISR_TAMP2F                  RTC_ISR_TAMP2F
-#define LL_RTC_ISR_TAMP1F                  RTC_ISR_TAMP1F
-#define LL_RTC_ISR_TSOVF                   RTC_ISR_TSOVF
-#define LL_RTC_ISR_TSF                     RTC_ISR_TSF
-#define LL_RTC_ISR_WUTF                    RTC_ISR_WUTF
-#define LL_RTC_ISR_ALRBF                   RTC_ISR_ALRBF
-#define LL_RTC_ISR_ALRAF                   RTC_ISR_ALRAF
-#define LL_RTC_ISR_INITF                   RTC_ISR_INITF
-#define LL_RTC_ISR_RSF                     RTC_ISR_RSF
-#define LL_RTC_ISR_INITS                   RTC_ISR_INITS
-#define LL_RTC_ISR_SHPF                    RTC_ISR_SHPF
-#define LL_RTC_ISR_WUTWF                   RTC_ISR_WUTWF
-#define LL_RTC_ISR_ALRBWF                  RTC_ISR_ALRBWF
-#define LL_RTC_ISR_ALRAWF                  RTC_ISR_ALRAWF
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_RTC_ReadReg and  LL_RTC_WriteReg functions
-  * @{
-  */
-#define LL_RTC_CR_TSIE                     RTC_CR_TSIE
-#define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE
-#define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE
-#define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE
-#define LL_RTC_TAMPCR_TAMP3IE              RTC_TAMPCR_TAMP3IE
-#define LL_RTC_TAMPCR_TAMP2IE              RTC_TAMPCR_TAMP2IE
-#define LL_RTC_TAMPCR_TAMP1IE              RTC_TAMPCR_TAMP1IE
-#define LL_RTC_TAMPCR_TAMPIE               RTC_TAMPCR_TAMPIE
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_WEEKDAY  WEEK DAY
-  * @{
-  */
-#define LL_RTC_WEEKDAY_MONDAY              ((uint8_t)0x01U) /*!< Monday    */
-#define LL_RTC_WEEKDAY_TUESDAY             ((uint8_t)0x02U) /*!< Tuesday   */
-#define LL_RTC_WEEKDAY_WEDNESDAY           ((uint8_t)0x03U) /*!< Wednesday */
-#define LL_RTC_WEEKDAY_THURSDAY            ((uint8_t)0x04U) /*!< Thrusday  */
-#define LL_RTC_WEEKDAY_FRIDAY              ((uint8_t)0x05U) /*!< Friday    */
-#define LL_RTC_WEEKDAY_SATURDAY            ((uint8_t)0x06U) /*!< Saturday  */
-#define LL_RTC_WEEKDAY_SUNDAY              ((uint8_t)0x07U) /*!< Sunday    */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_MONTH  MONTH
-  * @{
-  */
-#define LL_RTC_MONTH_JANUARY               ((uint8_t)0x01U)  /*!< January   */
-#define LL_RTC_MONTH_FEBRUARY              ((uint8_t)0x02U)  /*!< February  */
-#define LL_RTC_MONTH_MARCH                 ((uint8_t)0x03U)  /*!< March     */
-#define LL_RTC_MONTH_APRIL                 ((uint8_t)0x04U)  /*!< April     */
-#define LL_RTC_MONTH_MAY                   ((uint8_t)0x05U)  /*!< May       */
-#define LL_RTC_MONTH_JUNE                  ((uint8_t)0x06U)  /*!< June      */
-#define LL_RTC_MONTH_JULY                  ((uint8_t)0x07U)  /*!< July      */
-#define LL_RTC_MONTH_AUGUST                ((uint8_t)0x08U)  /*!< August    */
-#define LL_RTC_MONTH_SEPTEMBER             ((uint8_t)0x09U)  /*!< September */
-#define LL_RTC_MONTH_OCTOBER               ((uint8_t)0x10U)  /*!< October   */
-#define LL_RTC_MONTH_NOVEMBER              ((uint8_t)0x11U)  /*!< November  */
-#define LL_RTC_MONTH_DECEMBER              ((uint8_t)0x12U)  /*!< December  */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
-  * @{
-  */
-#define LL_RTC_HOURFORMAT_24HOUR           0x00000000U           /*!< 24 hour/day format */
-#define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
-  * @{
-  */
-#define LL_RTC_ALARMOUT_DISABLE            0x00000000U             /*!< Output disabled */
-#define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */
-#define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */
-#define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
-  * @{
-  */
-#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  0x00000000U                          /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
-#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
-  * @{
-  */
-#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     0x00000000U           /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
-#define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
-  * @{
-  */
-#define LL_RTC_TIME_FORMAT_AM_OR_24        0x00000000U           /*!< AM or 24-hour format */
-#define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
-  * @{
-  */
-#define LL_RTC_SHIFT_SECOND_DELAY          0x00000000U           /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
-#define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
-  * @{
-  */
-#define LL_RTC_ALMA_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm A*/
-#define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_SECONDS           RTC_ALRMAR_MSK1         /*!< Seconds do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_ALL               (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
-  * @{
-  */
-#define LL_RTC_ALMA_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
-#define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK
-  * @{
-  */
-#define LL_RTC_ALMB_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm B*/
-#define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4         /*!< Date/day do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3         /*!< Hours do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2         /*!< Minutes do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_SECONDS           RTC_ALRMBR_MSK1         /*!< Seconds do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_ALL               (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT
-  * @{
-  */
-#define LL_RTC_ALMB_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
-#define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
-  * @{
-  */
-#define LL_RTC_TIMESTAMP_EDGE_RISING       0x00000000U           /*!< RTC_TS input rising edge generates a time-stamp event */
-#define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
-  * @{
-  */
-#define LL_RTC_TS_TIME_FORMAT_AM           0x00000000U           /*!< AM or 24-hour format */
-#define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_TAMPER  TAMPER
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER1         RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER2         RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER3         RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER1      RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER2      RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER3      RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-#if defined(RTC_TAMPCR_TAMPPRCH)
-/** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
-  * @{
-  */
-#define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U                             /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
-#define LL_RTC_TAMPER_DURATION_2RTCCLK     RTC_TAMPCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
-#define LL_RTC_TAMPER_DURATION_4RTCCLK     RTC_TAMPCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
-#define LL_RTC_TAMPER_DURATION_8RTCCLK     RTC_TAMPCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
-/**
-  * @}
-  */
-#endif /* RTC_TAMPCR_TAMPPRCH */
-
-#if defined(RTC_TAMPCR_TAMPFLT)
-/** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
-  * @{
-  */
-#define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U                              /*!< Tamper filter is disabled */
-#define LL_RTC_TAMPER_FILTER_2SAMPLE       RTC_TAMPCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
-#define LL_RTC_TAMPER_FILTER_4SAMPLE       RTC_TAMPCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
-#define LL_RTC_TAMPER_FILTER_8SAMPLE       RTC_TAMPCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
-/**
-  * @}
-  */
-#endif /* RTC_TAMPCR_TAMPFLT */
-
-#if defined(RTC_TAMPCR_TAMPFREQ)
-/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
-  * @{
-  */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                                      /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_16384   RTC_TAMPCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_8192    RTC_TAMPCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_2048    RTC_TAMPCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_512     (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_256     RTC_TAMPCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */
-/**
-  * @}
-  */
-#endif /* RTC_TAMPCR_TAMPFREQ */
-
-/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
-  * @{
-  */
-#define LL_RTC_WAKEUPCLOCK_DIV_16          0x00000000U                           /*!< RTC/16 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_DIV_8           RTC_CR_WUCKSEL_0                    /*!< RTC/8 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_DIV_4           RTC_CR_WUCKSEL_1                    /*!< RTC/4 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_CKSPRE          RTC_CR_WUCKSEL_2                    /*!< ck_spre (usually 1 Hz) clock is selected */
-#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT      (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
-/**
-  * @}
-  */
-
-#if defined(RTC_BACKUP_SUPPORT)
-/** @defgroup RTC_LL_EC_BKP  BACKUP
-  * @{
-  */
-#define LL_RTC_BKP_DR0                     (0x00000000U)
-#define LL_RTC_BKP_DR1                     (0x00000001U)
-#define LL_RTC_BKP_DR2                     (0x00000002U)
-#define LL_RTC_BKP_DR3                     (0x00000003U)
-#define LL_RTC_BKP_DR4                     (0x00000004U)
-/**
-  * @}
-  */
-#endif /* RTC_BACKUP_SUPPORT */
-
-/** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
-  * @{
-  */
-#define LL_RTC_CALIB_OUTPUT_NONE           (0x00000000U)                 /*!< Calibration output disabled */
-#define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */
-#define LL_RTC_CALIB_OUTPUT_512HZ          RTC_CR_COE                /*!< Calibration output is 1 Hz */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion
-  * @{
-  */
-#define LL_RTC_CALIB_INSERTPULSE_NONE      (0x00000000U)           /*!< No RTCCLK pulses are added */
-#define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
-  * @{
-  */
-#define LL_RTC_CALIB_PERIOD_32SEC          (0x00000000U)           /*!< Use a 32-second calibration cycle period */
-#define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
-#define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
-  * @{
-  */
-
-/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in RTC register
-  * @param  __INSTANCE__ RTC Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in RTC register
-  * @param  __INSTANCE__ RTC Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EM_Convert Convert helper Macros
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to convert a value from 2 digit decimal format to BCD format
-  * @param  __VALUE__ Byte to be converted
-  * @retval Converted byte
-  */
-#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
-
-/**
-  * @brief  Helper macro to convert a value from BCD format to 2 digit decimal format
-  * @param  __VALUE__ BCD value to be converted
-  * @retval Converted byte
-  */
-#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U ) + ((__VALUE__) & (uint8_t)0x0FU))
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EM_Date Date helper Macros
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to retrieve weekday.
-  * @param  __RTC_DATE__ Date returned by @ref  LL_RTC_DATE_Get function.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  */
-#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
-
-/**
-  * @brief  Helper macro to retrieve Year in BCD format
-  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
-  * @retval Year in BCD format (0x00 . . . 0x99)
-  */
-#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
-
-/**
-  * @brief  Helper macro to retrieve Month in BCD format
-  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_MONTH_JANUARY
-  *         @arg @ref LL_RTC_MONTH_FEBRUARY
-  *         @arg @ref LL_RTC_MONTH_MARCH
-  *         @arg @ref LL_RTC_MONTH_APRIL
-  *         @arg @ref LL_RTC_MONTH_MAY
-  *         @arg @ref LL_RTC_MONTH_JUNE
-  *         @arg @ref LL_RTC_MONTH_JULY
-  *         @arg @ref LL_RTC_MONTH_AUGUST
-  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
-  *         @arg @ref LL_RTC_MONTH_OCTOBER
-  *         @arg @ref LL_RTC_MONTH_NOVEMBER
-  *         @arg @ref LL_RTC_MONTH_DECEMBER
-  */
-#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
-
-/**
-  * @brief  Helper macro to retrieve Day in BCD format
-  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
-  * @retval Day in BCD format (0x01 . . . 0x31)
-  */
-#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EM_Time Time helper Macros
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to retrieve hour in BCD format
-  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
-  * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
-  */
-#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
-
-/**
-  * @brief  Helper macro to retrieve minute in BCD format
-  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
-  * @retval Minutes in BCD format (0x00. . .0x59)
-  */
-#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
-
-/**
-  * @brief  Helper macro to retrieve second in BCD format
-  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
-  * @retval Seconds in  format (0x00. . .0x59)
-  */
-#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
-  * @{
-  */
-
-/** @defgroup RTC_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Set Hours format (24 hour/day or AM/PM hour format)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @rmtoll CR           FMT           LL_RTC_SetHourFormat
-  * @param  RTCx RTC Instance
-  * @param  HourFormat This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
-  *         @arg @ref LL_RTC_HOURFORMAT_AMPM
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
-{
-  MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
-}
-
-/**
-  * @brief  Get Hours format (24 hour/day or AM/PM hour format)
-  * @rmtoll CR           FMT           LL_RTC_GetHourFormat
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
-  *         @arg @ref LL_RTC_HOURFORMAT_AMPM
-  */
-__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
-}
-
-/**
-  * @brief  Select the flag to be routed to RTC_ALARM output
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           OSEL          LL_RTC_SetAlarmOutEvent
-  * @param  RTCx RTC Instance
-  * @param  AlarmOutput This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_ALARMOUT_DISABLE
-  *         @arg @ref LL_RTC_ALARMOUT_ALMA
-  *         @arg @ref LL_RTC_ALARMOUT_ALMB
-  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
-{
-  MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
-}
-
-/**
-  * @brief  Get the flag to be routed to RTC_ALARM output
-  * @rmtoll CR           OSEL          LL_RTC_GetAlarmOutEvent
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_ALARMOUT_DISABLE
-  *         @arg @ref LL_RTC_ALARMOUT_ALMA
-  *         @arg @ref LL_RTC_ALARMOUT_ALMB
-  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
-  */
-__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
-}
-
-/**
-  * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
-  * @note   Used only when RTC_ALARM is mapped on PC13
-  * @rmtoll OR        ALARMOUTTYPE  LL_RTC_SetAlarmOutputType
-  * @param  RTCx RTC Instance
-  * @param  Output This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
-  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
-{
-  MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output);
-}
-
-/**
-  * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
-  * @note   used only when RTC_ALARM is mapped on PC13
-  * @rmtoll OR        ALARMOUTTYPE  LL_RTC_GetAlarmOutputType
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
-  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
-  */
-__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE));
-}
-
-/**
-  * @brief  Enable initialization mode
-  * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
-  *         and prescaler register (RTC_PRER).
-  *         Counters are stopped and start counting from the new value when INIT is reset.
-  * @rmtoll ISR          INIT          LL_RTC_EnableInitMode
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
-{
-  /* Set the Initialization mode */
-  WRITE_REG(RTCx->ISR, RTC_LL_INIT_MASK);
-}
-
-/**
-  * @brief  Disable initialization mode (Free running mode)
-  * @rmtoll ISR          INIT          LL_RTC_DisableInitMode
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
-{
-  /* Exit Initialization mode */
-  WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
-}
-
-/**
-  * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           POL           LL_RTC_SetOutputPolarity
-  * @param  RTCx RTC Instance
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
-  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
-{
-  MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
-}
-
-/**
-  * @brief  Get Output polarity
-  * @rmtoll CR           POL           LL_RTC_GetOutputPolarity
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
-  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
-  */
-__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
-}
-
-/**
-  * @brief  Enable Bypass the shadow registers
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           BYPSHAD       LL_RTC_EnableShadowRegBypass
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
-}
-
-/**
-  * @brief  Disable Bypass the shadow registers
-  * @rmtoll CR           BYPSHAD       LL_RTC_DisableShadowRegBypass
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
-}
-
-/**
-  * @brief  Check if Shadow registers bypass is enabled or not.
-  * @rmtoll CR           BYPSHAD       LL_RTC_IsShadowRegBypassEnabled
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable RTC_REFIN reference clock detection (50 or 60 Hz)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @rmtoll CR           REFCKON       LL_RTC_EnableRefClock
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_REFCKON);
-}
-
-/**
-  * @brief  Disable RTC_REFIN reference clock detection (50 or 60 Hz)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @rmtoll CR           REFCKON       LL_RTC_DisableRefClock
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
-}
-
-/**
-  * @brief  Set Asynchronous prescaler factor
-  * @rmtoll PRER         PREDIV_A      LL_RTC_SetAsynchPrescaler
-  * @param  RTCx RTC Instance
-  * @param  AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
-{
-  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
-}
-
-/**
-  * @brief  Set Synchronous prescaler factor
-  * @rmtoll PRER         PREDIV_S      LL_RTC_SetSynchPrescaler
-  * @param  RTCx RTC Instance
-  * @param  SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
-{
-  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
-}
-
-/**
-  * @brief  Get Asynchronous prescaler factor
-  * @rmtoll PRER         PREDIV_A      LL_RTC_GetAsynchPrescaler
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data = 0 and Max_Data = 0x7F
-  */
-__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
-}
-
-/**
-  * @brief  Get Synchronous prescaler factor
-  * @rmtoll PRER         PREDIV_S      LL_RTC_GetSynchPrescaler
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
-  */
-__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
-}
-
-/**
-  * @brief  Enable the write protection for RTC registers.
-  * @rmtoll WPR          KEY           LL_RTC_EnableWriteProtection
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
-}
-
-/**
-  * @brief  Disable the write protection for RTC registers.
-  * @rmtoll WPR          KEY           LL_RTC_DisableWriteProtection
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
-  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
-}
-
-/**
-  * @brief  Enable RTC_OUT remap
-  * @rmtoll OR           OUT_RMP       LL_RTC_EnableOutRemap
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableOutRemap(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->OR, RTC_OR_OUT_RMP);
-}
-
-/**
-  * @brief  Disable RTC_OUT remap
-  * @rmtoll OR           OUT_RMP       LL_RTC_DisableOutRemap
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_Time Time
-  * @{
-  */
-
-/**
-  * @brief  Set time format (AM/24-hour or PM notation)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @rmtoll TR           PM            LL_RTC_TIME_SetFormat
-  * @param  RTCx RTC Instance
-  * @param  TimeFormat This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
-  *         @arg @ref LL_RTC_TIME_FORMAT_PM
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
-{
-  MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
-}
-
-/**
-  * @brief  Get time format (AM or PM notation)
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
-  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
-  * @rmtoll TR           PM            LL_RTC_TIME_GetFormat
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
-  *         @arg @ref LL_RTC_TIME_FORMAT_PM
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
-}
-
-/**
-  * @brief  Set Hours in BCD format
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
-  * @rmtoll TR           HT            LL_RTC_TIME_SetHour\n
-  *         TR           HU            LL_RTC_TIME_SetHour
-  * @param  RTCx RTC Instance
-  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
-{
-  MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
-             (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
-}
-
-/**
-  * @brief  Get Hours in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
-  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
-  *       Binary format
-  * @rmtoll TR           HT            LL_RTC_TIME_GetHour\n
-  *         TR           HU            LL_RTC_TIME_GetHour
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
-  return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos));
-}
-
-/**
-  * @brief  Set Minutes in BCD format
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
-  * @rmtoll TR           MNT           LL_RTC_TIME_SetMinute\n
-  *         TR           MNU           LL_RTC_TIME_SetMinute
-  * @param  RTCx RTC Instance
-  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
-{
-  MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
-             (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
-}
-
-/**
-  * @brief  Get Minutes in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
-  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
-  *       to Binary format
-  * @rmtoll TR           MNT           LL_RTC_TIME_GetMinute\n
-  *         TR           MNU           LL_RTC_TIME_GetMinute
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
-  return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos));
-}
-
-/**
-  * @brief  Set Seconds in BCD format
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
-  * @rmtoll TR           ST            LL_RTC_TIME_SetSecond\n
-  *         TR           SU            LL_RTC_TIME_SetSecond
-  * @param  RTCx RTC Instance
-  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
-{
-  MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
-             (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
-}
-
-/**
-  * @brief  Get Seconds in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
-  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
-  *       to Binary format
-  * @rmtoll TR           ST            LL_RTC_TIME_GetSecond\n
-  *         TR           SU            LL_RTC_TIME_GetSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
-  return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos));
-}
-
-/**
-  * @brief  Set time (hour, minute and second) in BCD format
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @note TimeFormat and Hours should follow the same format
-  * @rmtoll TR           PM            LL_RTC_TIME_Config\n
-  *         TR           HT            LL_RTC_TIME_Config\n
-  *         TR           HU            LL_RTC_TIME_Config\n
-  *         TR           MNT           LL_RTC_TIME_Config\n
-  *         TR           MNU           LL_RTC_TIME_Config\n
-  *         TR           ST            LL_RTC_TIME_Config\n
-  *         TR           SU            LL_RTC_TIME_Config
-  * @param  RTCx RTC Instance
-  * @param  Format12_24 This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
-  *         @arg @ref LL_RTC_TIME_FORMAT_PM
-  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
-  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
-{
-  uint32_t temp;
-
-  temp = Format12_24                                                                                    | \
-         (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))     | \
-         (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
-         (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
-  MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
-}
-
-/**
-  * @brief  Get time (hour, minute and second) in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
-  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
-  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
-  *       are available to get independently each parameter.
-  * @rmtoll TR           HT            LL_RTC_TIME_Get\n
-  *         TR           HU            LL_RTC_TIME_Get\n
-  *         TR           MNT           LL_RTC_TIME_Get\n
-  *         TR           MNU           LL_RTC_TIME_Get\n
-  *         TR           ST            LL_RTC_TIME_Get\n
-  *         TR           SU            LL_RTC_TIME_Get
-  * @param  RTCx RTC Instance
-  * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
-  return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) |  \
-                    (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
-                    ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
-}
-
-/**
-  * @brief  Memorize whether the daylight saving time change has been performed
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           BKP           LL_RTC_TIME_EnableDayLightStore
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_BKP);
-}
-
-/**
-  * @brief  Disable memorization whether the daylight saving time change has been performed.
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           BKP           LL_RTC_TIME_DisableDayLightStore
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
-}
-
-/**
-  * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
-  * @rmtoll CR           BKP           LL_RTC_TIME_IsDayLightStoreEnabled
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Subtract 1 hour (winter time change)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           SUB1H         LL_RTC_TIME_DecHour
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_SUB1H);
-}
-
-/**
-  * @brief  Add 1 hour (summer time change)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ADD1H         LL_RTC_TIME_IncHour
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_ADD1H);
-}
-
-/**
-  * @brief  Get Sub second value in the synchronous prescaler counter.
-  * @note  You can use both SubSeconds value and SecondFraction (PREDIV_S through
-  *        LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
-  *        SubSeconds value in second fraction ratio with time unit following
-  *        generic formula:
-  *          ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
-  *        This conversion can be performed only if no shift operation is pending
-  *        (ie. SHFP=0) when PREDIV_S >= SS.
-  * @rmtoll SSR          SS            LL_RTC_TIME_GetSubSecond
-  * @param  RTCx RTC Instance
-  * @retval Sub second value (number between 0 and 65535)
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
-}
-
-/**
-  * @brief  Synchronize to a remote clock with a high degree of precision.
-  * @note   This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   When REFCKON is set, firmware must not write to Shift control register.
-  * @rmtoll SHIFTR       ADD1S         LL_RTC_TIME_Synchronize\n
-  *         SHIFTR       SUBFS         LL_RTC_TIME_Synchronize
-  * @param  RTCx RTC Instance
-  * @param  ShiftSecond This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_SHIFT_SECOND_DELAY
-  *         @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
-  * @param  Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
-{
-  WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_Date Date
-  * @{
-  */
-
-/**
-  * @brief  Set Year in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
-  * @rmtoll DR           YT            LL_RTC_DATE_SetYear\n
-  *         DR           YU            LL_RTC_DATE_SetYear
-  * @param  RTCx RTC Instance
-  * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
-{
-  MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
-             (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
-}
-
-/**
-  * @brief  Get Year in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
-  * @rmtoll DR           YT            LL_RTC_DATE_GetYear\n
-  *         DR           YU            LL_RTC_DATE_GetYear
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x99
-  */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
-  return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos));
-}
-
-/**
-  * @brief  Set Week day
-  * @rmtoll DR           WDU           LL_RTC_DATE_SetWeekDay
-  * @param  RTCx RTC Instance
-  * @param  WeekDay This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
-{
-  MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
-}
-
-/**
-  * @brief  Get Week day
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @rmtoll DR           WDU           LL_RTC_DATE_GetWeekDay
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
-}
-
-/**
-  * @brief  Set Month in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
-  * @rmtoll DR           MT            LL_RTC_DATE_SetMonth\n
-  *         DR           MU            LL_RTC_DATE_SetMonth
-  * @param  RTCx RTC Instance
-  * @param  Month This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_MONTH_JANUARY
-  *         @arg @ref LL_RTC_MONTH_FEBRUARY
-  *         @arg @ref LL_RTC_MONTH_MARCH
-  *         @arg @ref LL_RTC_MONTH_APRIL
-  *         @arg @ref LL_RTC_MONTH_MAY
-  *         @arg @ref LL_RTC_MONTH_JUNE
-  *         @arg @ref LL_RTC_MONTH_JULY
-  *         @arg @ref LL_RTC_MONTH_AUGUST
-  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
-  *         @arg @ref LL_RTC_MONTH_OCTOBER
-  *         @arg @ref LL_RTC_MONTH_NOVEMBER
-  *         @arg @ref LL_RTC_MONTH_DECEMBER
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
-{
-  MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
-             (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
-}
-
-/**
-  * @brief  Get Month in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
-  * @rmtoll DR           MT            LL_RTC_DATE_GetMonth\n
-  *         DR           MU            LL_RTC_DATE_GetMonth
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_MONTH_JANUARY
-  *         @arg @ref LL_RTC_MONTH_FEBRUARY
-  *         @arg @ref LL_RTC_MONTH_MARCH
-  *         @arg @ref LL_RTC_MONTH_APRIL
-  *         @arg @ref LL_RTC_MONTH_MAY
-  *         @arg @ref LL_RTC_MONTH_JUNE
-  *         @arg @ref LL_RTC_MONTH_JULY
-  *         @arg @ref LL_RTC_MONTH_AUGUST
-  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
-  *         @arg @ref LL_RTC_MONTH_OCTOBER
-  *         @arg @ref LL_RTC_MONTH_NOVEMBER
-  *         @arg @ref LL_RTC_MONTH_DECEMBER
-  */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
-  return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos));
-}
-
-/**
-  * @brief  Set Day in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
-  * @rmtoll DR           DT            LL_RTC_DATE_SetDay\n
-  *         DR           DU            LL_RTC_DATE_SetDay
-  * @param  RTCx RTC Instance
-  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
-{
-  MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
-             (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
-}
-
-/**
-  * @brief  Get Day in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
-  * @rmtoll DR           DT            LL_RTC_DATE_GetDay\n
-  *         DR           DU            LL_RTC_DATE_GetDay
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x31
-  */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
-  return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos));
-}
-
-/**
-  * @brief  Set date (WeekDay, Day, Month and Year) in BCD format
-  * @rmtoll DR           WDU           LL_RTC_DATE_Config\n
-  *         DR           MT            LL_RTC_DATE_Config\n
-  *         DR           MU            LL_RTC_DATE_Config\n
-  *         DR           DT            LL_RTC_DATE_Config\n
-  *         DR           DU            LL_RTC_DATE_Config\n
-  *         DR           YT            LL_RTC_DATE_Config\n
-  *         DR           YU            LL_RTC_DATE_Config
-  * @param  RTCx RTC Instance
-  * @param  WeekDay This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
-  * @param  Month This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_MONTH_JANUARY
-  *         @arg @ref LL_RTC_MONTH_FEBRUARY
-  *         @arg @ref LL_RTC_MONTH_MARCH
-  *         @arg @ref LL_RTC_MONTH_APRIL
-  *         @arg @ref LL_RTC_MONTH_MAY
-  *         @arg @ref LL_RTC_MONTH_JUNE
-  *         @arg @ref LL_RTC_MONTH_JULY
-  *         @arg @ref LL_RTC_MONTH_AUGUST
-  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
-  *         @arg @ref LL_RTC_MONTH_OCTOBER
-  *         @arg @ref LL_RTC_MONTH_NOVEMBER
-  *         @arg @ref LL_RTC_MONTH_DECEMBER
-  * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
-{
-  uint32_t temp;
-
-  temp = (WeekDay << RTC_DR_WDU_Pos)                                                        | \
-         (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))   | \
-         (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
-         (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
-
-  MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
-}
-
-/**
-  * @brief  Get date (WeekDay, Day, Month and Year) in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
-  * and __LL_RTC_GET_DAY are available to get independently each parameter.
-  * @rmtoll DR           WDU           LL_RTC_DATE_Get\n
-  *         DR           MT            LL_RTC_DATE_Get\n
-  *         DR           MU            LL_RTC_DATE_Get\n
-  *         DR           DT            LL_RTC_DATE_Get\n
-  *         DR           DU            LL_RTC_DATE_Get\n
-  *         DR           YT            LL_RTC_DATE_Get\n
-  *         DR           YU            LL_RTC_DATE_Get
-  * @param  RTCx RTC Instance
-  * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
-  */
-__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
-  return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
-                    (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
-                    (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
-                    ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_ALARMA ALARMA
-  * @{
-  */
-
-/**
-  * @brief  Enable Alarm A
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRAE         LL_RTC_ALMA_Enable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_ALRAE);
-}
-
-/**
-  * @brief  Disable Alarm A
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRAE         LL_RTC_ALMA_Disable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
-}
-
-/**
-  * @brief  Specify the Alarm A masks.
-  * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_SetMask\n
-  *         ALRMAR       MSK3          LL_RTC_ALMA_SetMask\n
-  *         ALRMAR       MSK2          LL_RTC_ALMA_SetMask\n
-  *         ALRMAR       MSK1          LL_RTC_ALMA_SetMask
-  * @param  RTCx RTC Instance
-  * @param  Mask This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_ALMA_MASK_NONE
-  *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
-  *         @arg @ref LL_RTC_ALMA_MASK_HOURS
-  *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
-  *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
-  *         @arg @ref LL_RTC_ALMA_MASK_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
-  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
-}
-
-/**
-  * @brief  Get the Alarm A masks.
-  * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_GetMask\n
-  *         ALRMAR       MSK3          LL_RTC_ALMA_GetMask\n
-  *         ALRMAR       MSK2          LL_RTC_ALMA_GetMask\n
-  *         ALRMAR       MSK1          LL_RTC_ALMA_GetMask
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be can be a combination of the following values:
-  *         @arg @ref LL_RTC_ALMA_MASK_NONE
-  *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
-  *         @arg @ref LL_RTC_ALMA_MASK_HOURS
-  *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
-  *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
-  *         @arg @ref LL_RTC_ALMA_MASK_ALL
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
-}
-
-/**
-  * @brief  Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
-  * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_EnableWeekday
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
-}
-
-/**
-  * @brief  Disable AlarmA Week day selection (DU[3:0] represents the date )
-  * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_DisableWeekday
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
-}
-
-/**
-  * @brief  Set ALARM A Day in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
-  * @rmtoll ALRMAR       DT            LL_RTC_ALMA_SetDay\n
-  *         ALRMAR       DU            LL_RTC_ALMA_SetDay
-  * @param  RTCx RTC Instance
-  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
-{
-  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
-             (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM A Day in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
-  * @rmtoll ALRMAR       DT            LL_RTC_ALMA_GetDay\n
-  *         ALRMAR       DU            LL_RTC_ALMA_GetDay
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x31
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
-  return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos));
-}
-
-/**
-  * @brief  Set ALARM A Weekday
-  * @rmtoll ALRMAR       DU            LL_RTC_ALMA_SetWeekDay
-  * @param  RTCx RTC Instance
-  * @param  WeekDay This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
-{
-  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
-}
-
-/**
-  * @brief  Get ALARM A Weekday
-  * @rmtoll ALRMAR       DU            LL_RTC_ALMA_GetWeekDay
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
-}
-
-/**
-  * @brief  Set Alarm A time format (AM/24-hour or PM notation)
-  * @rmtoll ALRMAR       PM            LL_RTC_ALMA_SetTimeFormat
-  * @param  RTCx RTC Instance
-  * @param  TimeFormat This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
-{
-  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
-}
-
-/**
-  * @brief  Get Alarm A time format (AM or PM notation)
-  * @rmtoll ALRMAR       PM            LL_RTC_ALMA_GetTimeFormat
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
-}
-
-/**
-  * @brief  Set ALARM A Hours in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
-  * @rmtoll ALRMAR       HT            LL_RTC_ALMA_SetHour\n
-  *         ALRMAR       HU            LL_RTC_ALMA_SetHour
-  * @param  RTCx RTC Instance
-  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
-{
-  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
-             (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM A Hours in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
-  * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetHour\n
-  *         ALRMAR       HU            LL_RTC_ALMA_GetHour
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
-  return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos));
-}
-
-/**
-  * @brief  Set ALARM A Minutes in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
-  * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_SetMinute\n
-  *         ALRMAR       MNU           LL_RTC_ALMA_SetMinute
-  * @param  RTCx RTC Instance
-  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
-{
-  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
-             (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM A Minutes in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
-  * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_GetMinute\n
-  *         ALRMAR       MNU           LL_RTC_ALMA_GetMinute
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
-  return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos));
-}
-
-/**
-  * @brief  Set ALARM A Seconds in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
-  * @rmtoll ALRMAR       ST            LL_RTC_ALMA_SetSecond\n
-  *         ALRMAR       SU            LL_RTC_ALMA_SetSecond
-  * @param  RTCx RTC Instance
-  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
-{
-  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
-             (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM A Seconds in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
-  * @rmtoll ALRMAR       ST            LL_RTC_ALMA_GetSecond\n
-  *         ALRMAR       SU            LL_RTC_ALMA_GetSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
-  return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos));
-}
-
-/**
-  * @brief  Set Alarm A Time (hour, minute and second) in BCD format
-  * @rmtoll ALRMAR       PM            LL_RTC_ALMA_ConfigTime\n
-  *         ALRMAR       HT            LL_RTC_ALMA_ConfigTime\n
-  *         ALRMAR       HU            LL_RTC_ALMA_ConfigTime\n
-  *         ALRMAR       MNT           LL_RTC_ALMA_ConfigTime\n
-  *         ALRMAR       MNU           LL_RTC_ALMA_ConfigTime\n
-  *         ALRMAR       ST            LL_RTC_ALMA_ConfigTime\n
-  *         ALRMAR       SU            LL_RTC_ALMA_ConfigTime
-  * @param  RTCx RTC Instance
-  * @param  Format12_24 This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
-  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
-  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
-{
-  uint32_t temp;
-
-  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))    | \
-         (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
-         (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
-
-  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
-}
-
-/**
-  * @brief  Get Alarm B Time (hour, minute and second) in BCD format
-  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
-  * are available to get independently each parameter.
-  * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetTime\n
-  *         ALRMAR       HU            LL_RTC_ALMA_GetTime\n
-  *         ALRMAR       MNT           LL_RTC_ALMA_GetTime\n
-  *         ALRMAR       MNU           LL_RTC_ALMA_GetTime\n
-  *         ALRMAR       ST            LL_RTC_ALMA_GetTime\n
-  *         ALRMAR       SU            LL_RTC_ALMA_GetTime
-  * @param  RTCx RTC Instance
-  * @retval Combination of hours, minutes and seconds.
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
-}
-
-/**
-  * @brief  Set Alarm A Mask the most-significant bits starting at this bit
-  * @note This register can be written only when ALRAE is reset in RTC_CR register,
-  *       or in initialization mode.
-  * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_SetSubSecondMask
-  * @param  RTCx RTC Instance
-  * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
-  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
-}
-
-/**
-  * @brief  Get Alarm A Mask the most-significant bits starting at this bit
-  * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_GetSubSecondMask
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
-}
-
-/**
-  * @brief  Set Alarm A Sub seconds value
-  * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_SetSubSecond
-  * @param  RTCx RTC Instance
-  * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
-{
-  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
-}
-
-/**
-  * @brief  Get Alarm A Sub seconds value
-  * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_GetSubSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_ALARMB ALARMB
-  * @{
-  */
-
-/**
-  * @brief  Enable Alarm B
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRBE         LL_RTC_ALMB_Enable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_ALRBE);
-}
-
-/**
-  * @brief  Disable Alarm B
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRBE         LL_RTC_ALMB_Disable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
-}
-
-/**
-  * @brief  Specify the Alarm B masks.
-  * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_SetMask\n
-  *         ALRMBR       MSK3          LL_RTC_ALMB_SetMask\n
-  *         ALRMBR       MSK2          LL_RTC_ALMB_SetMask\n
-  *         ALRMBR       MSK1          LL_RTC_ALMB_SetMask
-  * @param  RTCx RTC Instance
-  * @param  Mask This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_ALMB_MASK_NONE
-  *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
-  *         @arg @ref LL_RTC_ALMB_MASK_HOURS
-  *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
-  *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
-  *         @arg @ref LL_RTC_ALMB_MASK_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
-  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
-}
-
-/**
-  * @brief  Get the Alarm B masks.
-  * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_GetMask\n
-  *         ALRMBR       MSK3          LL_RTC_ALMB_GetMask\n
-  *         ALRMBR       MSK2          LL_RTC_ALMB_GetMask\n
-  *         ALRMBR       MSK1          LL_RTC_ALMB_GetMask
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be can be a combination of the following values:
-  *         @arg @ref LL_RTC_ALMB_MASK_NONE
-  *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
-  *         @arg @ref LL_RTC_ALMB_MASK_HOURS
-  *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
-  *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
-  *         @arg @ref LL_RTC_ALMB_MASK_ALL
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
-}
-
-/**
-  * @brief  Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
-  * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_EnableWeekday
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
-}
-
-/**
-  * @brief  Disable AlarmB Week day selection (DU[3:0] represents the date )
-  * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_DisableWeekday
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
-}
-
-/**
-  * @brief  Set ALARM B Day in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
-  * @rmtoll ALRMBR       DT            LL_RTC_ALMB_SetDay\n
-  *         ALRMBR       DU            LL_RTC_ALMB_SetDay
-  * @param  RTCx RTC Instance
-  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
-{
-  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
-             (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM B Day in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
-  * @rmtoll ALRMBR       DT            LL_RTC_ALMB_GetDay\n
-  *         ALRMBR       DU            LL_RTC_ALMB_GetDay
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x31
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
-  return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos));
-}
-
-/**
-  * @brief  Set ALARM B Weekday
-  * @rmtoll ALRMBR       DU            LL_RTC_ALMB_SetWeekDay
-  * @param  RTCx RTC Instance
-  * @param  WeekDay This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
-{
-  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
-}
-
-/**
-  * @brief  Get ALARM B Weekday
-  * @rmtoll ALRMBR       DU            LL_RTC_ALMB_GetWeekDay
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
-}
-
-/**
-  * @brief  Set ALARM B time format (AM/24-hour or PM notation)
-  * @rmtoll ALRMBR       PM            LL_RTC_ALMB_SetTimeFormat
-  * @param  RTCx RTC Instance
-  * @param  TimeFormat This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
-{
-  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
-}
-
-/**
-  * @brief  Get ALARM B time format (AM or PM notation)
-  * @rmtoll ALRMBR       PM            LL_RTC_ALMB_GetTimeFormat
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
-}
-
-/**
-  * @brief  Set ALARM B Hours in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
-  * @rmtoll ALRMBR       HT            LL_RTC_ALMB_SetHour\n
-  *         ALRMBR       HU            LL_RTC_ALMB_SetHour
-  * @param  RTCx RTC Instance
-  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
-{
-  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
-             (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM B Hours in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
-  * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetHour\n
-  *         ALRMBR       HU            LL_RTC_ALMB_GetHour
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
-  return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos));
-}
-
-/**
-  * @brief  Set ALARM B Minutes in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
-  * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_SetMinute\n
-  *         ALRMBR       MNU           LL_RTC_ALMB_SetMinute
-  * @param  RTCx RTC Instance
-  * @param  Minutes between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
-{
-  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
-             (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM B Minutes in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
-  * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_GetMinute\n
-  *         ALRMBR       MNU           LL_RTC_ALMB_GetMinute
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
-  return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos));
-}
-
-/**
-  * @brief  Set ALARM B Seconds in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
-  * @rmtoll ALRMBR       ST            LL_RTC_ALMB_SetSecond\n
-  *         ALRMBR       SU            LL_RTC_ALMB_SetSecond
-  * @param  RTCx RTC Instance
-  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
-{
-  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
-             (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM B Seconds in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
-  * @rmtoll ALRMBR       ST            LL_RTC_ALMB_GetSecond\n
-  *         ALRMBR       SU            LL_RTC_ALMB_GetSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
-  return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos));
-}
-
-/**
-  * @brief  Set Alarm B Time (hour, minute and second) in BCD format
-  * @rmtoll ALRMBR       PM            LL_RTC_ALMB_ConfigTime\n
-  *         ALRMBR       HT            LL_RTC_ALMB_ConfigTime\n
-  *         ALRMBR       HU            LL_RTC_ALMB_ConfigTime\n
-  *         ALRMBR       MNT           LL_RTC_ALMB_ConfigTime\n
-  *         ALRMBR       MNU           LL_RTC_ALMB_ConfigTime\n
-  *         ALRMBR       ST            LL_RTC_ALMB_ConfigTime\n
-  *         ALRMBR       SU            LL_RTC_ALMB_ConfigTime
-  * @param  RTCx RTC Instance
-  * @param  Format12_24 This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
-  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
-  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
-{
-  uint32_t temp;
-
-  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))    | \
-         (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
-         (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
-
-  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
-}
-
-/**
-  * @brief  Get Alarm B Time (hour, minute and second) in BCD format
-  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
-  * are available to get independently each parameter.
-  * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetTime\n
-  *         ALRMBR       HU            LL_RTC_ALMB_GetTime\n
-  *         ALRMBR       MNT           LL_RTC_ALMB_GetTime\n
-  *         ALRMBR       MNU           LL_RTC_ALMB_GetTime\n
-  *         ALRMBR       ST            LL_RTC_ALMB_GetTime\n
-  *         ALRMBR       SU            LL_RTC_ALMB_GetTime
-  * @param  RTCx RTC Instance
-  * @retval Combination of hours, minutes and seconds.
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
-}
-
-/**
-  * @brief  Set Alarm B Mask the most-significant bits starting at this bit
-  * @note This register can be written only when ALRBE is reset in RTC_CR register,
-  *       or in initialization mode.
-  * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_SetSubSecondMask
-  * @param  RTCx RTC Instance
-  * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
-  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
-}
-
-/**
-  * @brief  Get Alarm B Mask the most-significant bits starting at this bit
-  * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_GetSubSecondMask
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_ALRMBSSR_MASKSS_Pos);
-}
-
-/**
-  * @brief  Set Alarm B Sub seconds value
-  * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_SetSubSecond
-  * @param  RTCx RTC Instance
-  * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
-{
-  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
-}
-
-/**
-  * @brief  Get Alarm B Sub seconds value
-  * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_GetSubSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_Timestamp Timestamp
-  * @{
-  */
-
-/**
-  * @brief  Enable Timestamp
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           TSE           LL_RTC_TS_Enable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_TSE);
-}
-
-/**
-  * @brief  Disable Timestamp
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           TSE           LL_RTC_TS_Disable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
-}
-
-/**
-  * @brief  Set Time-stamp event active edge
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
-  * @rmtoll CR           TSEDGE        LL_RTC_TS_SetActiveEdge
-  * @param  RTCx RTC Instance
-  * @param  Edge This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
-  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
-{
-  MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
-}
-
-/**
-  * @brief  Get Time-stamp event active edge
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           TSEDGE        LL_RTC_TS_GetActiveEdge
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
-  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
-}
-
-/**
-  * @brief  Get Timestamp AM/PM notation (AM or 24-hour format)
-  * @rmtoll TSTR         PM            LL_RTC_TS_GetTimeFormat
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_TS_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
-}
-
-/**
-  * @brief  Get Timestamp Hours in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
-  * @rmtoll TSTR         HT            LL_RTC_TS_GetHour\n
-  *         TSTR         HU            LL_RTC_TS_GetHour
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
-}
-
-/**
-  * @brief  Get Timestamp Minutes in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
-  * @rmtoll TSTR         MNT           LL_RTC_TS_GetMinute\n
-  *         TSTR         MNU           LL_RTC_TS_GetMinute
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
-}
-
-/**
-  * @brief  Get Timestamp Seconds in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
-  * @rmtoll TSTR         ST            LL_RTC_TS_GetSecond\n
-  *         TSTR         SU            LL_RTC_TS_GetSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
-}
-
-/**
-  * @brief  Get Timestamp time (hour, minute and second) in BCD format
-  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
-  * are available to get independently each parameter.
-  * @rmtoll TSTR         HT            LL_RTC_TS_GetTime\n
-  *         TSTR         HU            LL_RTC_TS_GetTime\n
-  *         TSTR         MNT           LL_RTC_TS_GetTime\n
-  *         TSTR         MNU           LL_RTC_TS_GetTime\n
-  *         TSTR         ST            LL_RTC_TS_GetTime\n
-  *         TSTR         SU            LL_RTC_TS_GetTime
-  * @param  RTCx RTC Instance
-  * @retval Combination of hours, minutes and seconds.
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSTR,
-                             RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
-}
-
-/**
-  * @brief  Get Timestamp Week day
-  * @rmtoll TSDR         WDU           LL_RTC_TS_GetWeekDay
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
-}
-
-/**
-  * @brief  Get Timestamp Month in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
-  * @rmtoll TSDR         MT            LL_RTC_TS_GetMonth\n
-  *         TSDR         MU            LL_RTC_TS_GetMonth
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_MONTH_JANUARY
-  *         @arg @ref LL_RTC_MONTH_FEBRUARY
-  *         @arg @ref LL_RTC_MONTH_MARCH
-  *         @arg @ref LL_RTC_MONTH_APRIL
-  *         @arg @ref LL_RTC_MONTH_MAY
-  *         @arg @ref LL_RTC_MONTH_JUNE
-  *         @arg @ref LL_RTC_MONTH_JULY
-  *         @arg @ref LL_RTC_MONTH_AUGUST
-  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
-  *         @arg @ref LL_RTC_MONTH_OCTOBER
-  *         @arg @ref LL_RTC_MONTH_NOVEMBER
-  *         @arg @ref LL_RTC_MONTH_DECEMBER
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
-}
-
-/**
-  * @brief  Get Timestamp Day in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
-  * @rmtoll TSDR         DT            LL_RTC_TS_GetDay\n
-  *         TSDR         DU            LL_RTC_TS_GetDay
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x31
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
-}
-
-/**
-  * @brief  Get Timestamp date (WeekDay, Day and Month) in BCD format
-  * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
-  * and __LL_RTC_GET_DAY are available to get independently each parameter.
-  * @rmtoll TSDR         WDU           LL_RTC_TS_GetDate\n
-  *         TSDR         MT            LL_RTC_TS_GetDate\n
-  *         TSDR         MU            LL_RTC_TS_GetDate\n
-  *         TSDR         DT            LL_RTC_TS_GetDate\n
-  *         TSDR         DU            LL_RTC_TS_GetDate
-  * @param  RTCx RTC Instance
-  * @retval Combination of Weekday, Day and Month
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
-}
-
-/**
-  * @brief  Get time-stamp sub second value
-  * @rmtoll TSSSR        SS            LL_RTC_TS_GetSubSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
-}
-
-#if defined(RTC_TAMPCR_TAMPTS)
-/**
-  * @brief  Activate timestamp on tamper detection event
-  * @rmtoll TAMPCR       TAMPTS        LL_RTC_TS_EnableOnTamper
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
-}
-
-/**
-  * @brief  Disable timestamp on tamper detection event
-  * @rmtoll TAMPCR       TAMPTS        LL_RTC_TS_DisableOnTamper
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
-}
-#endif /* RTC_TAMPCR_TAMPTS */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_Tamper Tamper
-  * @{
-  */
-
-/**
-  * @brief  Enable RTC_TAMPx input detection
-  * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Enable\n
-  *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Enable\n
-  *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Enable
-  * @param  RTCx RTC Instance
-  * @param  Tamper This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_TAMPER_1
-  *         @arg @ref LL_RTC_TAMPER_2
-  *         @arg @ref LL_RTC_TAMPER_3
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
-  SET_BIT(RTCx->TAMPCR, Tamper);
-}
-
-/**
-  * @brief  Clear RTC_TAMPx input detection
-  * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Disable\n
-  *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Disable\n
-  *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Disable
-  * @param  RTCx RTC Instance
-  * @param  Tamper This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_TAMPER_1
-  *         @arg @ref LL_RTC_TAMPER_2
-  *         @arg @ref LL_RTC_TAMPER_3
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
-  CLEAR_BIT(RTCx->TAMPCR, Tamper);
-}
-
-/**
-  * @brief  Enable Tamper mask flag
-  * @note Associated Tamper IT must not enabled when tamper mask is set.
-  * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_EnableMask\n
-  *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_EnableMask\n
-  *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_EnableMask
-  * @param  RTCx RTC Instance
-  * @param  Mask This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
-  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
-  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
-  SET_BIT(RTCx->TAMPCR, Mask);
-}
-
-/**
-  * @brief  Disable Tamper mask flag
-  * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_DisableMask\n
-  *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_DisableMask\n
-  *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_DisableMask
-  * @param  RTCx RTC Instance
-  * @param  Mask This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
-  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
-  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
-  CLEAR_BIT(RTCx->TAMPCR, Mask);
-}
-
-/**
-  * @brief  Enable backup register erase after Tamper event detection
-  * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_EnableEraseBKP\n
-  *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_EnableEraseBKP\n
-  *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_EnableEraseBKP
-  * @param  RTCx RTC Instance
-  * @param  Tamper This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
-  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
-  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
-  CLEAR_BIT(RTCx->TAMPCR, Tamper);
-}
-
-/**
-  * @brief  Disable backup register erase after Tamper event detection
-  * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_DisableEraseBKP\n
-  *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_DisableEraseBKP\n
-  *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_DisableEraseBKP
-  * @param  RTCx RTC Instance
-  * @param  Tamper This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
-  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
-  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
-  SET_BIT(RTCx->TAMPCR, Tamper);
-}
-
-#if defined(RTC_TAMPCR_TAMPPUDIS)
-/**
-  * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
-  * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
-}
-
-/**
-  * @brief  Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
-  * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
-}
-#endif /* RTC_TAMPCR_TAMPPUDIS */
-
-#if defined(RTC_TAMPCR_TAMPPRCH)
-/**
-  * @brief  Set RTC_TAMPx precharge duration
-  * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
-  * @param  RTCx RTC Instance
-  * @param  Duration This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
-  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
-  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
-  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
-{
-  MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration);
-}
-
-/**
-  * @brief  Get RTC_TAMPx precharge duration
-  * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
-  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
-  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
-  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
-  */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH));
-}
-#endif /* RTC_TAMPCR_TAMPPRCH */
-
-#if defined(RTC_TAMPCR_TAMPFLT)
-/**
-  * @brief  Set RTC_TAMPx filter count
-  * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
-  * @param  RTCx RTC Instance
-  * @param  FilterCount This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
-  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
-  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
-  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
-{
-  MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount);
-}
-
-/**
-  * @brief  Get RTC_TAMPx filter count
-  * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
-  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
-  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
-  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
-  */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT));
-}
-#endif /* RTC_TAMPCR_TAMPFLT */
-
-#if defined(RTC_TAMPCR_TAMPFREQ)
-/**
-  * @brief  Set Tamper sampling frequency
-  * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
-  * @param  RTCx RTC Instance
-  * @param  SamplingFreq This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
-{
-  MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq);
-}
-
-/**
-  * @brief  Get Tamper sampling frequency
-  * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
-  */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ));
-}
-#endif /* RTC_TAMPCR_TAMPFREQ */
-
-/**
-  * @brief  Enable Active level for Tamper input
-  * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel\n
-  *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_EnableActiveLevel\n
-  *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_EnableActiveLevel
-  * @param  RTCx RTC Instance
-  * @param  Tamper This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
-  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
-  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
-  SET_BIT(RTCx->TAMPCR, Tamper);
-}
-
-/**
-  * @brief  Disable Active level for Tamper input
-  * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel\n
-  *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel\n
-  *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_DisableActiveLevel
-  * @param  RTCx RTC Instance
-  * @param  Tamper This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
-  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
-  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
-  CLEAR_BIT(RTCx->TAMPCR, Tamper);
-}
-
-/**
-  * @}
-  */
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/** @defgroup RTC_LL_EF_Wakeup Wakeup
-  * @{
-  */
-
-/**
-  * @brief  Enable Wakeup timer
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Enable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_WUTE);
-}
-
-/**
-  * @brief  Disable Wakeup timer
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Disable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
-}
-
-/**
-  * @brief  Check if Wakeup timer is enabled or not
-  * @rmtoll CR           WUTE          LL_RTC_WAKEUP_IsEnabled
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Select Wakeup clock
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
-  * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_SetClock
-  * @param  RTCx RTC Instance
-  * @param  WakeupClock This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
-{
-  MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
-}
-
-/**
-  * @brief  Get Wakeup clock
-  * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_GetClock
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
-  */
-__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
-}
-
-/**
-  * @brief  Set Wakeup auto-reload value
-  * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
-  * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_SetAutoReload
-  * @param  RTCx RTC Instance
-  * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
-{
-  MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
-}
-
-/**
-  * @brief  Get Wakeup auto-reload value
-  * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_GetAutoReload
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
-}
-
-/**
-  * @}
-  */
-#endif /* RTC_WAKEUP_SUPPORT */
-
-#if defined(RTC_BACKUP_SUPPORT)
-/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
-  * @{
-  */
-
-/**
-  * @brief  Writes a data in a specified RTC Backup data register.
-  * @rmtoll BKPxR        BKP           LL_RTC_BAK_SetRegister
-  * @param  RTCx RTC Instance
-  * @param  BackupRegister This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_BKP_DR0
-  *         @arg @ref LL_RTC_BKP_DR1
-  *         @arg @ref LL_RTC_BKP_DR2
-  *         @arg @ref LL_RTC_BKP_DR3
-  *         @arg @ref LL_RTC_BKP_DR4
-  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
-{
-  uint32_t temp;
-
-  temp = (uint32_t)(&(RTCx->BKP0R));
-  temp += (BackupRegister * 4U);
-
-  /* Write the specified register */
-  *(__IO uint32_t *)temp = (uint32_t)Data;
-}
-
-/**
-  * @brief  Reads data from the specified RTC Backup data Register.
-  * @rmtoll BKPxR        BKP           LL_RTC_BAK_GetRegister
-  * @param  RTCx RTC Instance
-  * @param  BackupRegister This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_BKP_DR0
-  *         @arg @ref LL_RTC_BKP_DR1
-  *         @arg @ref LL_RTC_BKP_DR2
-  *         @arg @ref LL_RTC_BKP_DR3
-  *         @arg @ref LL_RTC_BKP_DR4
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
-{
-  uint32_t temp;
-
-  temp = (uint32_t)(&(RTCx->BKP0R));
-  temp += (BackupRegister * 4U);
-
-  /* Read the specified register */
-  return (*(__IO uint32_t *)temp);
-}
-
-/**
-  * @}
-  */
-#endif /* RTC_BACKUP_SUPPORT */
-
-/** @defgroup RTC_LL_EF_Calibration Calibration
-  * @{
-  */
-
-/**
-  * @brief  Set Calibration output frequency (1 Hz or 512 Hz)
-  * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           COE           LL_RTC_CAL_SetOutputFreq\n
-  *         CR           COSEL         LL_RTC_CAL_SetOutputFreq
-  * @param  RTCx RTC Instance
-  * @param  Frequency This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
-  *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
-  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
-{
-  MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
-}
-
-/**
-  * @brief  Get Calibration output frequency (1 Hz or 512 Hz)
-  * @rmtoll CR           COE           LL_RTC_CAL_GetOutputFreq\n
-  *         CR           COSEL         LL_RTC_CAL_GetOutputFreq
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
-  *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
-  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
-  */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
-}
-
-/**
-  * @brief  Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
-  * @rmtoll CALR         CALP          LL_RTC_CAL_SetPulse
-  * @param  RTCx RTC Instance
-  * @param  Pulse This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
-  *         @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
-{
-  MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
-}
-
-/**
-  * @brief  Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
-  * @rmtoll CALR         CALP          LL_RTC_CAL_IsPulseInserted
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the calibration cycle period
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
-  * @rmtoll CALR         CALW8         LL_RTC_CAL_SetPeriod\n
-  *         CALR         CALW16        LL_RTC_CAL_SetPeriod
-  * @param  RTCx RTC Instance
-  * @param  Period This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
-  *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
-  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
-{
-  MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
-}
-
-/**
-  * @brief  Get the calibration cycle period
-  * @rmtoll CALR         CALW8         LL_RTC_CAL_GetPeriod\n
-  *         CALR         CALW16        LL_RTC_CAL_GetPeriod
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
-  *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
-  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
-  */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
-}
-
-/**
-  * @brief  Set Calibration minus
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
-  * @rmtoll CALR         CALM          LL_RTC_CAL_SetMinus
-  * @param  RTCx RTC Instance
-  * @param  CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
-{
-  MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
-}
-
-/**
-  * @brief  Get Calibration minus
-  * @rmtoll CALR         CALM          LL_RTC_CAL_GetMinus
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
-  */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Get Recalibration pending Flag
-  * @rmtoll ISR          RECALPF       LL_RTC_IsActiveFlag_RECALP
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL);
-}
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
-  * @brief  Get RTC_TAMP3 detection flag
-  * @rmtoll ISR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL);
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-#if defined(RTC_TAMPER2_SUPPORT)
-/**
-  * @brief  Get RTC_TAMP2 detection flag
-  * @rmtoll ISR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL);
-}
-#endif /* RTC_TAMPER2_SUPPORT */
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
-  * @brief  Get RTC_TAMP1 detection flag
-  * @rmtoll ISR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL);
-}
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
-  * @brief  Get Time-stamp overflow flag
-  * @rmtoll ISR          TSOVF         LL_RTC_IsActiveFlag_TSOV
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Time-stamp flag
-  * @rmtoll ISR          TSF           LL_RTC_IsActiveFlag_TS
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL);
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
-  * @brief  Get Wakeup timer flag
-  * @rmtoll ISR          WUTF          LL_RTC_IsActiveFlag_WUT
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL);
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
-  * @brief  Get Alarm B flag
-  * @rmtoll ISR          ALRBF         LL_RTC_IsActiveFlag_ALRB
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Alarm A flag
-  * @rmtoll ISR          ALRAF         LL_RTC_IsActiveFlag_ALRA
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL);
-}
-
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
-  * @brief  Clear RTC_TAMP3 detection flag
-  * @rmtoll ISR          TAMP3F        LL_RTC_ClearFlag_TAMP3
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-#if defined(RTC_TAMPER2_SUPPORT)
-/**
-  * @brief  Clear RTC_TAMP2 detection flag
-  * @rmtoll ISR          TAMP2F        LL_RTC_ClearFlag_TAMP2
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-#endif /* RTC_TAMPER2_SUPPORT */
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
-  * @brief  Clear RTC_TAMP1 detection flag
-  * @rmtoll ISR          TAMP1F        LL_RTC_ClearFlag_TAMP1
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
-  * @brief  Clear Time-stamp overflow flag
-  * @rmtoll ISR          TSOVF         LL_RTC_ClearFlag_TSOV
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
-  * @brief  Clear Time-stamp flag
-  * @rmtoll ISR          TSF           LL_RTC_ClearFlag_TS
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
-  * @brief  Clear Wakeup timer flag
-  * @rmtoll ISR          WUTF          LL_RTC_ClearFlag_WUT
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
-  * @brief  Clear Alarm B flag
-  * @rmtoll ISR          ALRBF         LL_RTC_ClearFlag_ALRB
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
-  * @brief  Clear Alarm A flag
-  * @rmtoll ISR          ALRAF         LL_RTC_ClearFlag_ALRA
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
-  * @brief  Get Initialization flag
-  * @rmtoll ISR          INITF         LL_RTC_IsActiveFlag_INIT
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Registers synchronization flag
-  * @rmtoll ISR          RSF           LL_RTC_IsActiveFlag_RS
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear Registers synchronization flag
-  * @rmtoll ISR          RSF           LL_RTC_ClearFlag_RS
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
-  * @brief  Get Initialization status flag
-  * @rmtoll ISR          INITS         LL_RTC_IsActiveFlag_INITS
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Shift operation pending flag
-  * @rmtoll ISR          SHPF          LL_RTC_IsActiveFlag_SHP
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL);
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
-  * @brief  Get Wakeup timer write flag
-  * @rmtoll ISR          WUTWF         LL_RTC_IsActiveFlag_WUTW
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL);
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
-  * @brief  Get Alarm B write flag
-  * @rmtoll ISR          ALRBWF        LL_RTC_IsActiveFlag_ALRBW
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Alarm A write flag
-  * @rmtoll ISR          ALRAWF        LL_RTC_IsActiveFlag_ALRAW
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable Time-stamp interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           TSIE          LL_RTC_EnableIT_TS
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_TSIE);
-}
-
-/**
-  * @brief  Disable Time-stamp interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           TSIE          LL_RTC_DisableIT_TS
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
-  * @brief  Enable Wakeup timer interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           WUTIE         LL_RTC_EnableIT_WUT
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_WUTIE);
-}
-
-/**
-  * @brief  Disable Wakeup timer interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           WUTIE         LL_RTC_DisableIT_WUT
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
-  * @brief  Enable Alarm B interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRBIE        LL_RTC_EnableIT_ALRB
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
-}
-
-/**
-  * @brief  Disable Alarm B interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRBIE        LL_RTC_DisableIT_ALRB
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
-}
-
-/**
-  * @brief  Enable Alarm A interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRAIE        LL_RTC_EnableIT_ALRA
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
-}
-
-/**
-  * @brief  Disable Alarm A interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRAIE        LL_RTC_DisableIT_ALRA
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
-}
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
-  * @brief  Enable Tamper 3 interrupt
-  * @rmtoll TAMPCR       TAMP3IE       LL_RTC_EnableIT_TAMP3
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
-}
-
-/**
-  * @brief  Disable Tamper 3 interrupt
-  * @rmtoll TAMPCR       TAMP3IE       LL_RTC_DisableIT_TAMP3
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-#if defined(RTC_TAMPER2_SUPPORT)
-/**
-  * @brief  Enable Tamper 2 interrupt
-  * @rmtoll TAMPCR       TAMP2IE       LL_RTC_EnableIT_TAMP2
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
-}
-
-/**
-  * @brief  Disable Tamper 2 interrupt
-  * @rmtoll TAMPCR       TAMP2IE       LL_RTC_DisableIT_TAMP2
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
-}
-#endif /* RTC_TAMPER2_SUPPORT */
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
-  * @brief  Enable Tamper 1 interrupt
-  * @rmtoll TAMPCR       TAMP1IE       LL_RTC_EnableIT_TAMP1
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
-}
-
-/**
-  * @brief  Disable Tamper 1 interrupt
-  * @rmtoll TAMPCR       TAMP1IE       LL_RTC_DisableIT_TAMP1
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
-}
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
-  * @brief  Enable all Tamper Interrupt
-  * @rmtoll TAMPCR       TAMPIE        LL_RTC_EnableIT_TAMP
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
-}
-
-/**
-  * @brief  Disable all Tamper Interrupt
-  * @rmtoll TAMPCR       TAMPIE        LL_RTC_DisableIT_TAMP
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
-}
-
-/**
-  * @brief  Check if  Time-stamp interrupt is enabled or not
-  * @rmtoll CR           TSIE          LL_RTC_IsEnabledIT_TS
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL);
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
-  * @brief  Check if  Wakeup timer interrupt is enabled or not
-  * @rmtoll CR           WUTIE         LL_RTC_IsEnabledIT_WUT
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL);
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
-  * @brief  Check if  Alarm B interrupt is enabled or not
-  * @rmtoll CR           ALRBIE        LL_RTC_IsEnabledIT_ALRB
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if  Alarm A interrupt is enabled or not
-  * @rmtoll CR           ALRAIE        LL_RTC_IsEnabledIT_ALRA
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL);
-}
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
-  * @brief  Check if  Tamper 3 interrupt is enabled or not
-  * @rmtoll TAMPCR       TAMP3IE       LL_RTC_IsEnabledIT_TAMP3
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->TAMPCR,
-                    RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL);
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-#if defined(RTC_TAMPER2_SUPPORT)
-/**
-  * @brief  Check if  Tamper 2 interrupt is enabled or not
-  * @rmtoll TAMPCR       TAMP2IE       LL_RTC_IsEnabledIT_TAMP2
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->TAMPCR,
-                    RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL);
-
-}
-#endif /* RTC_TAMPER2_SUPPORT */
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
-  * @brief  Check if  Tamper 1 interrupt is enabled or not
-  * @rmtoll TAMPCR       TAMP1IE       LL_RTC_IsEnabledIT_TAMP1
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->TAMPCR,
-                    RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL);
-}
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
-  * @brief  Check if all the TAMPER interrupts are enabled or not
-  * @rmtoll TAMPCR       TAMPIE        LL_RTC_IsEnabledIT_TAMP
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->TAMPCR,
-                    RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
-void        LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
-ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
-void        LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
-ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
-void        LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
-ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-void        LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-void        LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(RTC) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_LL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h
deleted file mode 100644
index 6a436734c1..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h
+++ /dev/null
@@ -1,2028 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_spi.h
-  * @author  MCD Application Team
-  * @brief   Header file of SPI LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_LL_SPI_H
-#define STM32L0xx_LL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (SPI1) || defined (SPI2)
-
-/** @defgroup SPI_LL SPI
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  SPI Init structures definition
-  */
-typedef struct
-{
-  uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
-                                         This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
-
-  uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
-                                         This parameter can be a value of @ref SPI_LL_EC_MODE.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
-
-  uint32_t DataWidth;               /*!< Specifies the SPI data width.
-                                         This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
-
-  uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
-                                         This parameter can be a value of @ref SPI_LL_EC_POLARITY.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
-
-  uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
-                                         This parameter can be a value of @ref SPI_LL_EC_PHASE.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
-
-  uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
-                                         This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
-
-  uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
-                                         This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
-                                         @note The communication clock is derived from the master clock. The slave clock does not need to be set.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
-
-  uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                         This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
-
-  uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
-                                         This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
-
-                                         This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
-
-  uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
-                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
-
-} LL_SPI_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
-  * @{
-  */
-
-/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_SPI_ReadReg function
-  * @{
-  */
-#define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
-#define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
-#define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
-#define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
-#define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
-#define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
-#define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
-  * @{
-  */
-#define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
-#define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
-#define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_MODE Operation Mode
-  * @{
-  */
-#define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
-#define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
-  * @{
-  */
-#define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
-#define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_PHASE Clock Phase
-  * @{
-  */
-#define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
-#define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
-  * @{
-  */
-#define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
-#define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
-  * @{
-  */
-#define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
-#define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
-#define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
-#define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
-#define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
-#define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
-#define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
-  * @{
-  */
-#define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
-#define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
-  * @{
-  */
-#define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
-#define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
-#define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
-#define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
-  * @{
-  */
-#define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
-#define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
-#define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
-  * @{
-  */
-#define LL_SPI_DATAWIDTH_8BIT              0x00000000U                       /*!< Data length for SPI transfer:  8 bits */
-#define LL_SPI_DATAWIDTH_16BIT             (SPI_CR1_DFF)                     /*!< Data length for SPI transfer:  16 bits */
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
-  * @{
-  */
-#define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
-#define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
-  * @{
-  */
-
-/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in SPI register
-  * @param  __INSTANCE__ SPI Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in SPI register
-  * @param  __INSTANCE__ SPI Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
-  * @{
-  */
-
-/** @defgroup SPI_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Enable SPI peripheral
-  * @rmtoll CR1          SPE           LL_SPI_Enable
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
-  * @brief  Disable SPI peripheral
-  * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
-  * @rmtoll CR1          SPE           LL_SPI_Disable
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
-  * @brief  Check if SPI peripheral is enabled
-  * @rmtoll CR1          SPE           LL_SPI_IsEnabled
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set SPI operation mode to Master or Slave
-  * @note   This bit should not be changed when communication is ongoing.
-  * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
-  *         CR1          SSI           LL_SPI_SetMode
-  * @param  SPIx SPI Instance
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_MODE_MASTER
-  *         @arg @ref LL_SPI_MODE_SLAVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
-}
-
-/**
-  * @brief  Get SPI operation mode (Master or Slave)
-  * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
-  *         CR1          SSI           LL_SPI_GetMode
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_MODE_MASTER
-  *         @arg @ref LL_SPI_MODE_SLAVE
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
-}
-
-/**
-  * @brief  Set serial protocol used
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR2          FRF           LL_SPI_SetStandard
-  * @param  SPIx SPI Instance
-  * @param  Standard This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
-  *         @arg @ref LL_SPI_PROTOCOL_TI
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
-{
-  MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
-}
-
-/**
-  * @brief  Get serial protocol used
-  * @rmtoll CR2          FRF           LL_SPI_GetStandard
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
-  *         @arg @ref LL_SPI_PROTOCOL_TI
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
-}
-
-/**
-  * @brief  Set clock phase
-  * @note   This bit should not be changed when communication is ongoing.
-  *         This bit is not used in SPI TI mode.
-  * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
-  * @param  SPIx SPI Instance
-  * @param  ClockPhase This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_PHASE_1EDGE
-  *         @arg @ref LL_SPI_PHASE_2EDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
-}
-
-/**
-  * @brief  Get clock phase
-  * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_PHASE_1EDGE
-  *         @arg @ref LL_SPI_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
-}
-
-/**
-  * @brief  Set clock polarity
-  * @note   This bit should not be changed when communication is ongoing.
-  *         This bit is not used in SPI TI mode.
-  * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
-  * @param  SPIx SPI Instance
-  * @param  ClockPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_POLARITY_LOW
-  *         @arg @ref LL_SPI_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
-}
-
-/**
-  * @brief  Get clock polarity
-  * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_POLARITY_LOW
-  *         @arg @ref LL_SPI_POLARITY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
-}
-
-/**
-  * @brief  Set baud rate prescaler
-  * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
-  * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
-  * @param  SPIx SPI Instance
-  * @param  BaudRate This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
-}
-
-/**
-  * @brief  Get baud rate prescaler
-  * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
-}
-
-/**
-  * @brief  Set transfer bit order
-  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
-  * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
-  * @param  SPIx SPI Instance
-  * @param  BitOrder This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_LSB_FIRST
-  *         @arg @ref LL_SPI_MSB_FIRST
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
-}
-
-/**
-  * @brief  Get transfer bit order
-  * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_LSB_FIRST
-  *         @arg @ref LL_SPI_MSB_FIRST
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
-}
-
-/**
-  * @brief  Set transfer direction mode
-  * @note   For Half-Duplex mode, Rx Direction is set by default.
-  *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
-  * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
-  *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
-  *         CR1          BIDIOE        LL_SPI_SetTransferDirection
-  * @param  SPIx SPI Instance
-  * @param  TransferDirection This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_FULL_DUPLEX
-  *         @arg @ref LL_SPI_SIMPLEX_RX
-  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
-  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
-}
-
-/**
-  * @brief  Get transfer direction mode
-  * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
-  *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
-  *         CR1          BIDIOE        LL_SPI_GetTransferDirection
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_FULL_DUPLEX
-  *         @arg @ref LL_SPI_SIMPLEX_RX
-  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
-  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
-}
-
-/**
-  * @brief  Set frame data width
-  * @rmtoll CR1          DFF           LL_SPI_SetDataWidth
-  * @param  SPIx SPI Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
-}
-
-/**
-  * @brief  Get frame data width
-  * @rmtoll CR1          DFF           LL_SPI_GetDataWidth
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_CRC_Management CRC Management
-  * @{
-  */
-
-/**
-  * @brief  Enable CRC
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
-  * @brief  Disable CRC
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
-  * @brief  Check if CRC is enabled
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set CRCNext to transfer CRC on the line
-  * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
-  * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
-}
-
-/**
-  * @brief  Set polynomial for CRC calculation
-  * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
-  * @param  SPIx SPI Instance
-  * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
-{
-  WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
-}
-
-/**
-  * @brief  Get polynomial for CRC calculation
-  * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
-  * @param  SPIx SPI Instance
-  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_REG(SPIx->CRCPR));
-}
-
-/**
-  * @brief  Get Rx CRC
-  * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
-  * @param  SPIx SPI Instance
-  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_REG(SPIx->RXCRCR));
-}
-
-/**
-  * @brief  Get Tx CRC
-  * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
-  * @param  SPIx SPI Instance
-  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_REG(SPIx->TXCRCR));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
-  * @{
-  */
-
-/**
-  * @brief  Set NSS mode
-  * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
-  * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
-  * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
-  * @param  SPIx SPI Instance
-  * @param  NSS This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_NSS_SOFT
-  *         @arg @ref LL_SPI_NSS_HARD_INPUT
-  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
-  MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
-}
-
-/**
-  * @brief  Get NSS mode
-  * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
-  * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_NSS_SOFT
-  *         @arg @ref LL_SPI_NSS_HARD_INPUT
-  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
-{
-  uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
-  uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
-  return (Ssm | Ssoe);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Check if Rx buffer is not empty
-  * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Tx buffer is empty
-  * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get CRC error flag
-  * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get mode fault error flag
-  * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get overrun error flag
-  * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get busy flag
-  * @note   The BSY flag is cleared under any one of the following conditions:
-  * -When the SPI is correctly disabled
-  * -When a fault is detected in Master mode (MODF bit set to 1)
-  * -In Master mode, when it finishes a data transmission and no new data is ready to be
-  * sent
-  * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
-  * each data transfer.
-  * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get frame format error flag
-  * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear CRC error flag
-  * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
-}
-
-/**
-  * @brief  Clear mode fault error flag
-  * @note   Clearing this flag is done by a read access to the SPIx_SR
-  *         register followed by a write access to the SPIx_CR1 register
-  * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
-{
-  __IO uint32_t tmpreg_sr;
-  tmpreg_sr = SPIx->SR;
-  (void) tmpreg_sr;
-  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
-  * @brief  Clear overrun error flag
-  * @note   Clearing this flag is done by a read access to the SPIx_DR
-  *         register followed by a read access to the SPIx_SR register
-  * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = SPIx->DR;
-  (void) tmpreg;
-  tmpreg = SPIx->SR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear frame format error flag
-  * @note   Clearing this flag is done by reading SPIx_SR register
-  * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = SPIx->SR;
-  (void) tmpreg;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
-  * @{
-  */
-
-/**
-  * @brief  Enable error interrupt
-  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
-  * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
-  * @brief  Enable Rx buffer not empty interrupt
-  * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
-  * @brief  Enable Tx buffer empty interrupt
-  * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
-  * @brief  Disable error interrupt
-  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
-  * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
-  * @brief  Disable Rx buffer not empty interrupt
-  * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
-  * @brief  Disable Tx buffer empty interrupt
-  * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
-  * @brief  Check if error interrupt is enabled
-  * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Rx buffer not empty interrupt is enabled
-  * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Tx buffer empty interrupt
-  * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_DMA_Management DMA Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Rx
-  * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
-  * @brief  Disable DMA Rx
-  * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
-  * @brief  Check if DMA Rx is enabled
-  * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Tx
-  * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
-  * @brief  Disable DMA Tx
-  * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
-  * @brief  Check if DMA Tx is enabled
-  * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the data register address used for DMA transfer
-  * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
-  * @param  SPIx SPI Instance
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
-{
-  return (uint32_t) &(SPIx->DR);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_DATA_Management DATA Management
-  * @{
-  */
-
-/**
-  * @brief  Read 8-Bits in the data register
-  * @rmtoll DR           DR            LL_SPI_ReceiveData8
-  * @param  SPIx SPI Instance
-  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
-{
-  return (*((__IO uint8_t *)&SPIx->DR));
-}
-
-/**
-  * @brief  Read 16-Bits in the data register
-  * @rmtoll DR           DR            LL_SPI_ReceiveData16
-  * @param  SPIx SPI Instance
-  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
-{
-  return (uint16_t)(READ_REG(SPIx->DR));
-}
-
-/**
-  * @brief  Write 8-Bits in the data register
-  * @rmtoll DR           DR            LL_SPI_TransmitData8
-  * @param  SPIx SPI Instance
-  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
-{
-#if defined (__GNUC__)
-  __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
-  *spidr = TxData;
-#else
-  *((__IO uint8_t *)&SPIx->DR) = TxData;
-#endif /* __GNUC__ */
-}
-
-/**
-  * @brief  Write 16-Bits in the data register
-  * @rmtoll DR           DR            LL_SPI_TransmitData16
-  * @param  SPIx SPI Instance
-  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
-#if defined (__GNUC__)
-  __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
-  *spidr = TxData;
-#else
-  SPIx->DR = TxData;
-#endif /* __GNUC__ */
-}
-
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
-void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @defgroup I2S_LL I2S
-  * @{
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  I2S Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t Mode;                    /*!< Specifies the I2S operating mode.
-                                         This parameter can be a value of @ref I2S_LL_EC_MODE
-
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
-
-  uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
-                                         This parameter can be a value of @ref I2S_LL_EC_STANDARD
-
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
-
-
-  uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
-                                         This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
-
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
-
-
-  uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
-                                         This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
-
-                                         This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
-
-
-  uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
-                                         This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
-
-                                         Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
-                                         and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
-
-
-  uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
-                                         This parameter can be a value of @ref I2S_LL_EC_POLARITY
-
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
-
-} LL_I2S_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
-  * @{
-  */
-
-/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_I2S_ReadReg function
-  * @{
-  */
-#define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
-#define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
-#define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
-#define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
-#define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
-#define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
-  * @{
-  */
-#define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
-#define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
-#define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
-  * @{
-  */
-#define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel length 16bit */
-#define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel length 32bit */
-#define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel length 32bit */
-#define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel length 32bit */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
-  * @{
-  */
-#define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
-#define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_STANDARD I2s Standard
-  * @{
-  */
-#define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
-#define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
-#define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
-#define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
-#define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_MODE Operation Mode
-  * @{
-  */
-#define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
-#define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
-#define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
-#define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
-  * @{
-  */
-#define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
-#define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
-  * @{
-  */
-#define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
-#define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
-  * @{
-  */
-
-#define LL_I2S_AUDIOFREQ_192K              192000U       /*!< Audio Frequency configuration 192000 Hz       */
-#define LL_I2S_AUDIOFREQ_96K               96000U        /*!< Audio Frequency configuration  96000 Hz       */
-#define LL_I2S_AUDIOFREQ_48K               48000U        /*!< Audio Frequency configuration  48000 Hz       */
-#define LL_I2S_AUDIOFREQ_44K               44100U        /*!< Audio Frequency configuration  44100 Hz       */
-#define LL_I2S_AUDIOFREQ_32K               32000U        /*!< Audio Frequency configuration  32000 Hz       */
-#define LL_I2S_AUDIOFREQ_22K               22050U        /*!< Audio Frequency configuration  22050 Hz       */
-#define LL_I2S_AUDIOFREQ_16K               16000U        /*!< Audio Frequency configuration  16000 Hz       */
-#define LL_I2S_AUDIOFREQ_11K               11025U        /*!< Audio Frequency configuration  11025 Hz       */
-#define LL_I2S_AUDIOFREQ_8K                8000U         /*!< Audio Frequency configuration   8000 Hz       */
-#define LL_I2S_AUDIOFREQ_DEFAULT           2U            /*!< Audio Freq not specified. Register I2SDIV = 2 */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
-  * @{
-  */
-
-/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in I2S register
-  * @param  __INSTANCE__ I2S Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in I2S register
-  * @param  __INSTANCE__ I2S Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
-  * @{
-  */
-
-/** @defgroup I2S_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Select I2S mode and Enable I2S peripheral
-  * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
-  *         I2SCFGR      I2SE          LL_I2S_Enable
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
-  * @brief  Disable I2S peripheral
-  * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
-  * @brief  Check if I2S peripheral is enabled
-  * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set I2S data frame length
-  * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
-  *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
-  * @param  SPIx SPI Instance
-  * @param  DataFormat This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_DATAFORMAT_16B
-  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
-  *         @arg @ref LL_I2S_DATAFORMAT_24B
-  *         @arg @ref LL_I2S_DATAFORMAT_32B
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
-{
-  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
-}
-
-/**
-  * @brief  Get I2S data frame length
-  * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
-  *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_DATAFORMAT_16B
-  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
-  *         @arg @ref LL_I2S_DATAFORMAT_24B
-  *         @arg @ref LL_I2S_DATAFORMAT_32B
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
-}
-
-/**
-  * @brief  Set I2S clock polarity
-  * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
-  * @param  SPIx SPI Instance
-  * @param  ClockPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_POLARITY_LOW
-  *         @arg @ref LL_I2S_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
-  SET_BIT(SPIx->I2SCFGR, ClockPolarity);
-}
-
-/**
-  * @brief  Get I2S clock polarity
-  * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_POLARITY_LOW
-  *         @arg @ref LL_I2S_POLARITY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
-}
-
-/**
-  * @brief  Set I2S standard protocol
-  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
-  *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
-  * @param  SPIx SPI Instance
-  * @param  Standard This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_STANDARD_PHILIPS
-  *         @arg @ref LL_I2S_STANDARD_MSB
-  *         @arg @ref LL_I2S_STANDARD_LSB
-  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
-  *         @arg @ref LL_I2S_STANDARD_PCM_LONG
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
-{
-  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
-}
-
-/**
-  * @brief  Get I2S standard protocol
-  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
-  *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_STANDARD_PHILIPS
-  *         @arg @ref LL_I2S_STANDARD_MSB
-  *         @arg @ref LL_I2S_STANDARD_LSB
-  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
-  *         @arg @ref LL_I2S_STANDARD_PCM_LONG
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
-}
-
-/**
-  * @brief  Set I2S transfer mode
-  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
-  * @param  SPIx SPI Instance
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_MODE_SLAVE_TX
-  *         @arg @ref LL_I2S_MODE_SLAVE_RX
-  *         @arg @ref LL_I2S_MODE_MASTER_TX
-  *         @arg @ref LL_I2S_MODE_MASTER_RX
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
-  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
-}
-
-/**
-  * @brief  Get I2S transfer mode
-  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_MODE_SLAVE_TX
-  *         @arg @ref LL_I2S_MODE_SLAVE_RX
-  *         @arg @ref LL_I2S_MODE_MASTER_TX
-  *         @arg @ref LL_I2S_MODE_MASTER_RX
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
-}
-
-/**
-  * @brief  Set I2S linear prescaler
-  * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
-  * @param  SPIx SPI Instance
-  * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
-{
-  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
-}
-
-/**
-  * @brief  Get I2S linear prescaler
-  * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
-  * @param  SPIx SPI Instance
-  * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
-}
-
-/**
-  * @brief  Set I2S parity prescaler
-  * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
-  * @param  SPIx SPI Instance
-  * @param  PrescalerParity This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
-{
-  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
-}
-
-/**
-  * @brief  Get I2S parity prescaler
-  * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
-}
-
-/**
-  * @brief  Enable the master clock output (Pin MCK)
-  * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
-  * @brief  Disable the master clock output (Pin MCK)
-  * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
-  * @brief  Check if the master clock output (Pin MCK) is enabled
-  * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
-}
-
-#if defined(SPI_I2SCFGR_ASTRTEN)
-/**
-  * @brief  Enable asynchronous start
-  * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_EnableAsyncStart
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
-}
-
-/**
-  * @brief  Disable  asynchronous start
-  * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_DisableAsyncStart
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
-}
-
-/**
-  * @brief  Check if asynchronous start is enabled
-  * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_IsEnabledAsyncStart
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
-}
-#endif /* SPI_I2SCFGR_ASTRTEN */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EF_FLAG FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Check if Rx buffer is not empty
-  * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_RXNE(SPIx);
-}
-
-/**
-  * @brief  Check if Tx buffer is empty
-  * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_TXE(SPIx);
-}
-
-/**
-  * @brief  Get busy flag
-  * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_BSY(SPIx);
-}
-
-/**
-  * @brief  Get overrun error flag
-  * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_OVR(SPIx);
-}
-
-/**
-  * @brief  Get underrun error flag
-  * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get frame format error flag
-  * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_FRE(SPIx);
-}
-
-/**
-  * @brief  Get channel side flag.
-  * @note   0: Channel Left has to be transmitted or has been received\n
-  *         1: Channel Right has to be transmitted or has been received\n
-  *         It has no significance in PCM mode.
-  * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear overrun error flag
-  * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
-  LL_SPI_ClearFlag_OVR(SPIx);
-}
-
-/**
-  * @brief  Clear underrun error flag
-  * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = SPIx->SR;
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Clear frame format error flag
-  * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_ClearFlag_FRE(SPIx);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EF_IT Interrupt Management
-  * @{
-  */
-
-/**
-  * @brief  Enable error IT
-  * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
-  * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableIT_ERR(SPIx);
-}
-
-/**
-  * @brief  Enable Rx buffer not empty IT
-  * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableIT_RXNE(SPIx);
-}
-
-/**
-  * @brief  Enable Tx buffer empty IT
-  * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableIT_TXE(SPIx);
-}
-
-/**
-  * @brief  Disable error IT
-  * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
-  * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableIT_ERR(SPIx);
-}
-
-/**
-  * @brief  Disable Rx buffer not empty IT
-  * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableIT_RXNE(SPIx);
-}
-
-/**
-  * @brief  Disable Tx buffer empty IT
-  * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableIT_TXE(SPIx);
-}
-
-/**
-  * @brief  Check if ERR IT is enabled
-  * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledIT_ERR(SPIx);
-}
-
-/**
-  * @brief  Check if RXNE IT is enabled
-  * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledIT_RXNE(SPIx);
-}
-
-/**
-  * @brief  Check if TXE IT is enabled
-  * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledIT_TXE(SPIx);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EF_DMA DMA Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Rx
-  * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableDMAReq_RX(SPIx);
-}
-
-/**
-  * @brief  Disable DMA Rx
-  * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableDMAReq_RX(SPIx);
-}
-
-/**
-  * @brief  Check if DMA Rx is enabled
-  * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledDMAReq_RX(SPIx);
-}
-
-/**
-  * @brief  Enable DMA Tx
-  * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableDMAReq_TX(SPIx);
-}
-
-/**
-  * @brief  Disable DMA Tx
-  * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableDMAReq_TX(SPIx);
-}
-
-/**
-  * @brief  Check if DMA Tx is enabled
-  * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledDMAReq_TX(SPIx);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EF_DATA DATA Management
-  * @{
-  */
-
-/**
-  * @brief  Read 16-Bits in data register
-  * @rmtoll DR           DR            LL_I2S_ReceiveData16
-  * @param  SPIx SPI Instance
-  * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_ReceiveData16(SPIx);
-}
-
-/**
-  * @brief  Write 16-Bits in data register
-  * @rmtoll DR           DR            LL_I2S_TransmitData16
-  * @param  SPIx SPI Instance
-  * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
-  LL_SPI_TransmitData16(SPIx, TxData);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
-void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
-void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_LL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h
deleted file mode 100644
index 6b273749a4..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h
+++ /dev/null
@@ -1,1089 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_system.h
-  * @author  MCD Application Team
-  * @brief   Header file of SYSTEM LL module.
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL SYSTEM driver contains a set of generic APIs that can be
-    used by user:
-      (+) Some of the FLASH features need to be handled in the SYSTEM file.
-      (+) Access to DBGCMU registers
-      (+) Access to SYSCFG registers
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_SYSTEM_H
-#define __STM32L0xx_LL_SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
-
-/** @defgroup SYSTEM_LL SYSTEM
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
-  * @{
-  */
-
-/**
- * @brief Power-down in Run mode Flash key
- */
-#define FLASH_PDKEY1                  (0x04152637U) /*!< Flash power down key1 */
-#define FLASH_PDKEY2                  (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
-                                                                   to unlock the RUN_PD bit in FLASH_ACR */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
-  * @{
-  */
-
-/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Memory Remap
-* @{
-*/
-#define LL_SYSCFG_REMAP_FLASH              0x00000000U                                           /*!< Main Flash memory mapped at 0x00000000              */
-#define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_CFGR1_MEM_MODE_0                               /*!< System Flash memory mapped at 0x00000000            */
-#define LL_SYSCFG_REMAP_SRAM               (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)   /*!< SRAM mapped at 0x00000000                           */
-
-/**
-  * @}
-  */
-
-#if defined(SYSCFG_CFGR1_UFB)
-/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG Bank Mode
-  * @{
-  */
-#define LL_SYSCFG_BANKMODE_BANK1           0x00000000U               /*!< Flash Bank1 mapped at 0x08000000 (and aliased at 0x00000000),
-                                                                          Flash Bank2 mapped at 0x08018000 (and aliased at 0x00018000),
-                                                                          Data EEPROM Bank1 mapped at 0x08080000 (and aliased at 0x00080000),
-                                                                          Data EEPROM Bank2 mapped at 0x08080C00 (and aliased at 0x00080C00) */
-#define LL_SYSCFG_BANKMODE_BANK2           SYSCFG_CFGR1_UFB          /*!< Flash Bank2 mapped at 0x08000000 (and aliased at 0x00000000),
-                                                                          Flash Bank1 mapped at 0x08018000 (and aliased at 0x00018000),
-                                                                          Data EEPROM Bank2 mapped at 0x08080000 (and aliased at 0x00080000),
-                                                                          Data EEPROM Bank1 mapped at 0x08080C00 (and aliased at 0x00080C00) */
-/**
-  * @}
-  */
-
-#endif /* SYSCFG_CFGR1_UFB */
-
-/** @defgroup SYSTEM_LL_EC_BOOTMODE SYSCFG Boot Mode
-* @{
-*/
-#define LL_SYSCFG_BOOTMODE_FLASH           0x00000000U                                           /*!< Main Flash memory boot mode              */
-#define LL_SYSCFG_BOOTMODE_SYSTEMFLASH     SYSCFG_CFGR1_BOOT_MODE_0                              /*!< System Flash memory boot mode            */
-#define LL_SYSCFG_BOOTMODE_SRAM            (SYSCFG_CFGR1_BOOT_MODE_1 | SYSCFG_CFGR1_BOOT_MODE_0) /*!< SRAM boot mode                           */
-
-/**
-  * @}
-  */
-
-#if defined(SYSCFG_CFGR2_CAPA)
-/** @defgroup SYSTEM_LL_EC_CFGR2 SYSCFG VLCD Rail Connection
-  * @{
-  */
-
-#define LL_SYSCFG_CAPA_VLCD2_PB2           SYSCFG_CFGR2_CAPA_0       /*!< Connect PB2  pin to LCD_VLCD2 rails supply voltage  */
-#define LL_SYSCFG_CAPA_VLCD1_PB12          SYSCFG_CFGR2_CAPA_1       /*!< Connect PB12 pin to LCD_VLCD1 rails supply voltage  */
-#define LL_SYSCFG_CAPA_VLCD3_PB0           SYSCFG_CFGR2_CAPA_2       /*!< Connect PB0  pin to LCD_VLCD3 rails supply voltage  */
-#if defined (SYSCFG_CFGR2_CAPA_3)
-#define LL_SYSCFG_CAPA_VLCD1_PE11          SYSCFG_CFGR2_CAPA_3       /*!< Connect PE11 pin to LCD_VLCD1 rails supply voltage  */
-#endif /* SYSCFG_CFGR2_CAPA_3 */
-#if defined (SYSCFG_CFGR2_CAPA_4)
-#define LL_SYSCFG_CAPA_VLCD3_PE12          SYSCFG_CFGR2_CAPA_4       /*!< Connect PE12 pin to LCD_VLCD3 rails supply voltage  */
-#endif /* SYSCFG_CFGR2_CAPA_4 */
-/**
-  * @}
-  */
-#endif /* SYSCFG_CFGR2_CAPA */
-
-/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
-  * @{
-  */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6     SYSCFG_CFGR2_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7     SYSCFG_CFGR2_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8     SYSCFG_CFGR2_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9     SYSCFG_CFGR2_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1    SYSCFG_CFGR2_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
-#if defined(SYSCFG_CFGR2_I2C2_FMP)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2    SYSCFG_CFGR2_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
-#endif /* SYSCFG_CFGR2_I2C2_FMP */
-#if defined(SYSCFG_CFGR2_I2C3_FMP)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3    SYSCFG_CFGR2_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */
-#endif /* SYSCFG_CFGR2_I2C3_FMP */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_VREFINT_CONTROL SYSCFG VREFINT Control
-  * @{
-  */
-#define LL_SYSCFG_VREFINT_CONNECT_NONE        0x00000000U                       /*!< No pad connected to VREFINT_ADC */
-#define LL_SYSCFG_VREFINT_CONNECT_IO1         SYSCFG_CFGR3_VREF_OUT_0           /*!< PB0 connected to VREFINT_ADC */
-#define LL_SYSCFG_VREFINT_CONNECT_IO2         SYSCFG_CFGR3_VREF_OUT_1           /*!< PB1 connected to VREFINT_ADC */
-#define LL_SYSCFG_VREFINT_CONNECT_IO1_IO2     (SYSCFG_CFGR3_VREF_OUT_0 | SYSCFG_CFGR3_VREF_OUT_1)   /*!< PB0 and PB1 connected to VREFINT_ADC */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI Port
-  * @{
-  */
-#define LL_SYSCFG_EXTI_PORTA               0U              /*!< EXTI PORT A */
-#define LL_SYSCFG_EXTI_PORTB               1U              /*!< EXTI PORT B */
-#define LL_SYSCFG_EXTI_PORTC               2U              /*!< EXTI PORT C */
-#if defined(GPIOD_BASE)
-#define LL_SYSCFG_EXTI_PORTD               3U              /*!< EXTI PORT D */
-#endif /*GPIOD_BASE*/
-#if defined(GPIOE_BASE)
-#define LL_SYSCFG_EXTI_PORTE               4U              /*!< EXTI PORT E */
-#endif /*GPIOE_BASE*/
-#if defined(GPIOH_BASE)
-#define LL_SYSCFG_EXTI_PORTH               5U              /*!< EXTI PORT H */
-#endif /*GPIOH_BASE*/
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI Line
-  * @{
-  */
-#define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0U  << 16U | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE1               (uint32_t)(4U  << 16U | 0U)  /*!< EXTI_POSITION_4  | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE2               (uint32_t)(8U  << 16U | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE3               (uint32_t)(12U << 16U | 0U)  /*!< EXTI_POSITION_12 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0U  << 16U | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE5               (uint32_t)(4U  << 16U | 1U)  /*!< EXTI_POSITION_4  | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE6               (uint32_t)(8U  << 16U | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE7               (uint32_t)(12U << 16U | 1U)  /*!< EXTI_POSITION_12 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0U  << 16U | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE9               (uint32_t)(4U  << 16U | 2U)  /*!< EXTI_POSITION_4  | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE10              (uint32_t)(8U  << 16U | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE11              (uint32_t)(12U << 16U | 2U)  /*!< EXTI_POSITION_12 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0U  << 16U | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE13              (uint32_t)(4U  << 16U | 3U)  /*!< EXTI_POSITION_4  | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE14              (uint32_t)(8U  << 16U | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE15              (uint32_t)(12U << 16U | 3U)  /*!< EXTI_POSITION_12 | EXTICR[3] */
-/**
-  * @}
-  */
-
-
-
-/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
-  * @{
-  */
-#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1_FZ_DBG_TIM2_STOP    /*!< TIM2 counter stopped when core is halted */
-#if defined(TIM3)
-#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1_FZ_DBG_TIM3_STOP    /*!< TIM3 counter stopped when core is halted */
-#endif /*TIM3*/
-#if defined(TIM6)
-#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1_FZ_DBG_TIM6_STOP    /*!< TIM6 counter stopped when core is halted */
-#endif /*TIM6*/
-#if defined(TIM7)
-#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1_FZ_DBG_TIM7_STOP    /*!< TIM7 counter stopped when core is halted */
-#endif /*TIM7*/
-#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1_FZ_DBG_RTC_STOP     /*!< RTC Calendar frozen when core is halted */
-#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1_FZ_DBG_WWDG_STOP    /*!< Debug Window Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1_FZ_DBG_IWDG_STOP    /*!< Debug Independent Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1_FZ_DBG_I2C1_STOP    /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#if defined(I2C2)
-#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1_FZ_DBG_I2C2_STOP    /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#endif /*I2C2*/
-#if defined(I2C3)
-#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1_FZ_DBG_I2C3_STOP    /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
-#endif /*I2C3*/
-#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1_FZ_DBG_LPTIMER_STOP /*!< LPTIM1 counter stopped when core is halted */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
-  * @{
-  */
-#if defined(TIM22)
-#define LL_DBGMCU_APB2_GRP1_TIM22_STOP     DBGMCU_APB2_FZ_DBG_TIM22_STOP /*!< TIM22 counter stopped when core is halted */
-#endif /*TIM22*/
-#define LL_DBGMCU_APB2_GRP1_TIM21_STOP     DBGMCU_APB2_FZ_DBG_TIM21_STOP /*!< TIM21 counter stopped when core is halted */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
-  * @{
-  */
-#define LL_FLASH_LATENCY_0                 (0x00000000U)           /*!< FLASH Zero Latency cycle */
-#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY       /*!< FLASH One Latency cycle */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
-  * @{
-  */
-
-/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
-  * @{
-  */
-
-/**
-  * @brief  Set memory mapping at address 0x00000000
-  * @rmtoll SYSCFG_CFGR1 MEM_MODE      LL_SYSCFG_SetRemapMemory
-  * @param  Memory This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_REMAP_FLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SRAM
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
-{
-  MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
-}
-
-/**
-  * @brief  Get memory mapping at address 0x00000000
-  * @rmtoll SYSCFG_CFGR1 MEM_MODE      LL_SYSCFG_GetRemapMemory
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_REMAP_FLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SRAM
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
-}
-
-#if defined(SYSCFG_CFGR1_UFB)
-/**
-  * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
-  * @rmtoll SYSCFG_CFGR1 UFB           LL_SYSCFG_SetFlashBankMode
-  * @param  Bank This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
-  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
-{
-  MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_UFB, Bank);
-}
-
-/**
-  * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
-  * @rmtoll SYSCFG_CFGR1 UFB           LL_SYSCFG_GetFlashBankMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
-  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_UFB));
-}
-#endif /* SYSCFG_CFGR1_UFB */
-
-/**
-  * @brief  Get Boot mode selected by the boot pins status bits
-  * @note   It indicates the boot mode selected by the boot pins. Bit 9
-  *         corresponds to the complement of nBOOT1 bit in the FLASH_OPTR register.
-  *         Its value is defined in the option bytes. Bit 8 corresponds to the
-  *         value sampled on the BOOT0 pin.
-  * @rmtoll SYSCFG_CFGR1 BOOT_MODE      LL_SYSCFG_GetBootMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_BOOTMODE_FLASH
-  *         @arg @ref LL_SYSCFG_BOOTMODE_SYSTEMFLASH
-  *         @arg @ref LL_SYSCFG_BOOTMODE_SRAM
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetBootMode(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE));
-}
-
-/**
-  * @brief  Firewall protection enabled
-  * @rmtoll SYSCFG_CFGR2 FWDIS         LL_SYSCFG_EnableFirewall
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
-{
-  CLEAR_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN);
-}
-
-/**
-  * @brief  Check if Firewall protection is enabled or not
-  * @rmtoll SYSCFG_CFGR2 FWDIS         LL_SYSCFG_IsEnabledFirewall
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
-{
-  return !(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN) == SYSCFG_CFGR2_FWDISEN);
-}
-
-#if defined(SYSCFG_CFGR2_CAPA)
-/**
-  * @brief  Set VLCD rail connection to optional external capacitor
-  * @note   One to three external capacitors can be connected to pads to do
-  *         VLCD biasing.
-  *         - LCD_VLCD1 rail can be connected to PB12 or PE11(*),
-  *         - LCD_VLCD2 rail can be connected to PB2,
-  *         - LCD_VLCD3 rail can be connected to PB0 or PE12(*)
-  * @rmtoll SYSCFG_CFGR2 CAPA      LL_SYSCFG_SetVLCDRailConnection
-  * @param  IoPinConnect This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_CAPA_VLCD1_PB12
-  *         @arg @ref LL_SYSCFG_CAPA_VLCD1_PE11(*)
-  *         @arg @ref LL_SYSCFG_CAPA_VLCD2_PB2
-  *         @arg @ref LL_SYSCFG_CAPA_VLCD3_PB0
-  *         @arg @ref LL_SYSCFG_CAPA_VLCD3_PE12(*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetVLCDRailConnection(uint32_t IoPinConnect)
-{
-  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA, IoPinConnect);
-}
-
-
-/**
-  * @brief  Get VLCD rail connection configuration
-  * @note   One to three external capacitors can be connected to pads to do
-  *         VLCD biasing.
-  *         - LCD_VLCD1 rail can be connected to PB12 or PE11(*),
-  *         - LCD_VLCD2 rail can be connected to PB2,
-  *         - LCD_VLCD3 rail can be connected to PB0 or PE12(*)
-  * @rmtoll SYSCFG_CFGR2 CAPA      LL_SYSCFG_GetVLCDRailConnection
-  * @retval Returned value can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_CAPA_VLCD1_PB12
-  *         @arg @ref LL_SYSCFG_CAPA_VLCD1_PE11(*)
-  *         @arg @ref LL_SYSCFG_CAPA_VLCD2_PB2
-  *         @arg @ref LL_SYSCFG_CAPA_VLCD3_PB0
-  *         @arg @ref LL_SYSCFG_CAPA_VLCD3_PE12(*)
-  *
-  *         (*) value not defined in all devices
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetVLCDRailConnection(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA));
-}
-#endif
-
-/**
-  * @brief  Enable the I2C fast mode plus driving capability.
-  * @rmtoll SYSCFG_CFGR2 I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
-  *         SYSCFG_CFGR2 I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
-  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  SET_BIT(SYSCFG->CFGR2, ConfigFastModePlus);
-}
-
-/**
-  * @brief  Disable the I2C fast mode plus driving capability.
-  * @rmtoll SYSCFG_CFGR2 I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
-  *         SYSCFG_CFGR2 I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
-  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  CLEAR_BIT(SYSCFG->CFGR2, ConfigFastModePlus);
-}
-
-/**
-  * @brief  Select which pad is connected to VREFINT_ADC
-  * @rmtoll SYSCFG_CFGR3 SEL_VREF_OUT  LL_SYSCFG_VREFINT_SetConnection
-  * @param  IoPinConnect This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_NONE
-  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1
-  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO2
-  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1_IO2
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_VREFINT_SetConnection(uint32_t IoPinConnect)
-{
-  MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_VREF_OUT, IoPinConnect);
-}
-
-/**
-  * @brief  Get pad connection to VREFINT_ADC
-  * @rmtoll SYSCFG_CFGR3 SEL_VREF_OUT  LL_SYSCFG_VREFINT_GetConnection
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_NONE
-  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1
-  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO2
-  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1_IO2
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_GetConnection(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_VREF_OUT));
-}
-
-/**
-  * @brief  Buffer used to generate VREFINT reference for ADC enable
-  * @note   The VrefInit buffer to ADC through internal path is also
-  *         enabled using function LL_ADC_SetCommonPathInternalCh()
-  *         with parameter LL_ADC_PATH_INTERNAL_VREFINT
-  * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_ADC   LL_SYSCFG_VREFINT_EnableADC
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_VREFINT_EnableADC(void)
-{
-  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC);
-}
-
-/**
-  * @brief  Buffer used to generate VREFINT reference for ADC disable
-  * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_ADC   LL_SYSCFG_VREFINT_DisableADC
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_VREFINT_DisableADC(void)
-{
-  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC);
-}
-
-/**
-  * @brief  Buffer used to generate temperature sensor reference for ADC enable
-  * @rmtoll SYSCFG_CFGR3 ENBUF_SENSOR_ADC    LL_SYSCFG_TEMPSENSOR_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_TEMPSENSOR_Enable(void)
-{
-  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC);
-}
-
-/**
-  * @brief  Buffer used to generate temperature sensor reference for ADC disable
-  * @rmtoll SYSCFG_CFGR3 ENBUF_SENSOR_ADC    LL_SYSCFG_TEMPSENSOR_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_TEMPSENSOR_Disable(void)
-{
-  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC);
-}
-
-/**
-  * @brief  Buffer used to generate VREFINT reference for comparator enable
-  * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_COMP  LL_SYSCFG_VREFINT_EnableCOMP
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_VREFINT_EnableCOMP(void)
-{
-  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP);
-}
-
-/**
-  * @brief  Buffer used to generate VREFINT reference for comparator disable
-  * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_COMP  LL_SYSCFG_VREFINT_DisableCOMP
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_VREFINT_DisableCOMP(void)
-{
-  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP);
-}
-
-#if defined (RCC_HSI48_SUPPORT)
-/**
-  * @brief  Buffer used to generate VREFINT reference for HSI48 oscillator enable
-  * @rmtoll SYSCFG_CFGR3 ENREF_HSI48         LL_SYSCFG_VREFINT_EnableHSI48
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_VREFINT_EnableHSI48(void)
-{
-  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
-}
-
-/**
-  * @brief  Buffer used to generate VREFINT reference for HSI48 oscillator disable
-  * @rmtoll SYSCFG_CFGR3 ENREF_HSI48         LL_SYSCFG_VREFINT_DisableHSI48
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_VREFINT_DisableHSI48(void)
-{
-  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
-}
-#endif
-
-/**
-  * @brief  Check if VREFINT is ready or not
-  * @note   When set, it indicates that VREFINT is available for BOR, PVD and LCD
-  * @rmtoll SYSCFG_CFGR3 VREFINT_RDYF        LL_SYSCFG_VREFINT_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_IsReady(void)
-{
-  return (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF) == SYSCFG_CFGR3_VREFINT_RDYF);
-}
-
-/**
-  * @brief  Lock the whole content of SYSCFG_CFGR3 register
-  * @note   After SYSCFG_CFGR3 register lock, only read access available.
-  *         Only system hardware reset unlocks SYSCFG_CFGR3 register.
-  * @rmtoll SYSCFG_CFGR3 REF_LOCK            LL_SYSCFG_VREFINT_Lock
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_VREFINT_Lock(void)
-{
-  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK);
-}
-
-/**
-  * @brief  Check if SYSCFG_CFGR3 register is locked (only read access) or not
-  * @note   When set, it indicates that SYSCFG_CFGR3 register is locked, only read access available
-  * @rmtoll SYSCFG_CFGR3 REF_LOCK              LL_SYSCFG_VREFINT_IsLocked
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_IsLocked(void)
-{
-  return (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK) == SYSCFG_CFGR3_REF_LOCK);
-}
-
-/**
-  * @brief  Configure source input for the EXTI external interrupt.
-  * @rmtoll SYSCFG_EXTICR1 EXTI0         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI1         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI2         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI3         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI4         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI5         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI6         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI7         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI8         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI9         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI10        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI11        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI12        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI13        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI14        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI15        LL_SYSCFG_SetEXTISource
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_PORTA
-  *         @arg @ref LL_SYSCFG_EXTI_PORTB
-  *         @arg @ref LL_SYSCFG_EXTI_PORTC
-  *         @arg @ref LL_SYSCFG_EXTI_PORTD (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTE (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTH (*)
-  *
-  *         (*) value not defined in all devices
-  * @param  Line This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_LINE0
-  *         @arg @ref LL_SYSCFG_EXTI_LINE1
-  *         @arg @ref LL_SYSCFG_EXTI_LINE2
-  *         @arg @ref LL_SYSCFG_EXTI_LINE3
-  *         @arg @ref LL_SYSCFG_EXTI_LINE4
-  *         @arg @ref LL_SYSCFG_EXTI_LINE5
-  *         @arg @ref LL_SYSCFG_EXTI_LINE6
-  *         @arg @ref LL_SYSCFG_EXTI_LINE7
-  *         @arg @ref LL_SYSCFG_EXTI_LINE8
-  *         @arg @ref LL_SYSCFG_EXTI_LINE9
-  *         @arg @ref LL_SYSCFG_EXTI_LINE10
-  *         @arg @ref LL_SYSCFG_EXTI_LINE11
-  *         @arg @ref LL_SYSCFG_EXTI_LINE12
-  *         @arg @ref LL_SYSCFG_EXTI_LINE13
-  *         @arg @ref LL_SYSCFG_EXTI_LINE14
-  *         @arg @ref LL_SYSCFG_EXTI_LINE15
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
-{
-  MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], SYSCFG_EXTICR1_EXTI0 << (Line >> 16U), Port << (Line >> 16U));
-}
-
-/**
-  * @brief  Get the configured defined for specific EXTI Line
-  * @rmtoll SYSCFG_EXTICR1 EXTI0         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI1         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI2         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI3         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI4         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI5         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI6         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI7         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI8         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI9         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI10        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI11        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI12        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI13        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI14        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI15        LL_SYSCFG_SetEXTISource
-  * @param  Line This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_LINE0
-  *         @arg @ref LL_SYSCFG_EXTI_LINE1
-  *         @arg @ref LL_SYSCFG_EXTI_LINE2
-  *         @arg @ref LL_SYSCFG_EXTI_LINE3
-  *         @arg @ref LL_SYSCFG_EXTI_LINE4
-  *         @arg @ref LL_SYSCFG_EXTI_LINE5
-  *         @arg @ref LL_SYSCFG_EXTI_LINE6
-  *         @arg @ref LL_SYSCFG_EXTI_LINE7
-  *         @arg @ref LL_SYSCFG_EXTI_LINE8
-  *         @arg @ref LL_SYSCFG_EXTI_LINE9
-  *         @arg @ref LL_SYSCFG_EXTI_LINE10
-  *         @arg @ref LL_SYSCFG_EXTI_LINE11
-  *         @arg @ref LL_SYSCFG_EXTI_LINE12
-  *         @arg @ref LL_SYSCFG_EXTI_LINE13
-  *         @arg @ref LL_SYSCFG_EXTI_LINE14
-  *         @arg @ref LL_SYSCFG_EXTI_LINE15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_PORTA
-  *         @arg @ref LL_SYSCFG_EXTI_PORTB
-  *         @arg @ref LL_SYSCFG_EXTI_PORTC
-  *         @arg @ref LL_SYSCFG_EXTI_PORTD (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTE (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTH (*)
-  *
-  *         (*) value not defined in all devices
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16U))) >> (Line >> 16U));
-}
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
-  * @{
-  */
-
-/**
-  * @brief  Return the device identifier
-  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
-  * @retval Values between Min_Data=0x00 and Max_Data=0x7FF (ex: L053 -> 0x417, L073 -> 0x447)
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
-{
-  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
-}
-
-/**
-  * @brief  Return the device revision identifier
-  * @note This field indicates the revision of the device.
-  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
-  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
-{
-  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
-}
-
-/**
-  * @brief  Enable the Debug Module during SLEEP mode
-  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Disable the Debug Module during SLEEP mode
-  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STOP mode
-  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Disable the Debug Module during STOP mode
-  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STANDBY mode
-  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Disable the Debug Module during STANDBY mode
-  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Freeze APB1 peripherals (group1 peripherals)
-  * @rmtoll APB1FZ      DBG_TIM2_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1FZ      DBG_TIM3_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1FZ      DBG_TIM6_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1FZ      DBG_TIM7_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1FZ      DBG_RTC_STOP      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1FZ      DBG_WWDG_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1FZ      DBG_IWDG_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1FZ      DBG_I2C1_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1FZ      DBG_I2C2_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1FZ      DBG_I2C3_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1FZ      DBG_LPTIMER_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBGMCU->APB1FZ, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
-  * @rmtoll APB1FZ      DBG_TIM2_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1FZ      DBG_TIM3_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1FZ      DBG_TIM6_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1FZ      DBG_TIM7_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1FZ      DBG_RTC_STOP      LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1FZ      DBG_WWDG_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1FZ      DBG_IWDG_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1FZ      DBG_I2C1_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1FZ      DBG_I2C2_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1FZ      DBG_I2C3_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1FZ      DBG_LPTIMER_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
-}
-
-/**
-  * @brief  Freeze APB2 peripherals
-  * @rmtoll APB2FZ      DBG_TIM22_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         APB2FZ      DBG_TIM21_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM22_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM21_STOP
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBGMCU->APB2FZ, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB2 peripherals
-  * @rmtoll APB2FZ      DBG_TIM22_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
-  *         APB2FZ      DBG_TIM21_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM22_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM21_STOP
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EF_FLASH FLASH
-  * @{
-  */
-
-/**
-  * @brief  Set FLASH Latency
-  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
-  * @param  Latency This parameter can be one of the following values:
-  *         @arg @ref LL_FLASH_LATENCY_0
-  *         @arg @ref LL_FLASH_LATENCY_1
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
-{
-  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
-}
-
-/**
-  * @brief  Get FLASH Latency
-  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_FLASH_LATENCY_0
-  *         @arg @ref LL_FLASH_LATENCY_1
-  */
-__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
-{
-  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
-}
-
-/**
-  * @brief  Enable Prefetch
-  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
-}
-
-/**
-  * @brief  Disable Prefetch
-  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
-}
-
-/**
-  * @brief  Check if Prefetch buffer is enabled
-  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
-{
-  return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
-}
-
-
-/**
-  * @brief  Enable Flash Power-down mode during run mode or Low-power run mode
-  * @note Flash memory can be put in power-down mode only when the code is executed
-  *       from RAM
-  * @note Flash must not be accessed when power down is enabled
-  * @note Flash must not be put in power-down while a program or an erase operation
-  *       is on-going
-  * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\n
-  *         FLASH_PDKEYR PDKEY1        LL_FLASH_EnableRunPowerDown\n
-  *         FLASH_PDKEYR PDKEY2        LL_FLASH_EnableRunPowerDown
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
-{
-  /* Following values must be written consecutively to unlock the RUN_PD bit in
-     FLASH_ACR */
-  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
-  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
-  SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
-}
-
-/**
-  * @brief  Disable Flash Power-down mode during run mode or Low-power run mode
-  * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_DisableRunPowerDown\n
-  *         FLASH_PDKEYR PDKEY1        LL_FLASH_DisableRunPowerDown\n
-  *         FLASH_PDKEYR PDKEY2        LL_FLASH_DisableRunPowerDown
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
-{
-  /* Following values must be written consecutively to unlock the RUN_PD bit in
-     FLASH_ACR */
-  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
-  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
-}
-
-/**
-  * @brief  Enable Flash Power-down mode during Sleep or Low-power sleep mode
-  * @note Flash must not be put in power-down while a program or an erase operation
-  *       is on-going
-  * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_EnableSleepPowerDown
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
-}
-
-/**
-  * @brief  Disable Flash Power-down mode during Sleep or Low-power sleep mode
-  * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_DisableSleepPowerDown
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
-}
-
-/**
-  * @brief  Enable buffers used as a cache during read access
-  * @rmtoll FLASH_ACR    DISAB_BUF     LL_FLASH_EnableBuffers
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnableBuffers(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DISAB_BUF);
-}
-
-/**
-  * @brief  Disable buffers used as a cache during read access
-  * @note   When disabled, every read will access the NVM even for
-  *         an address already read (for example, the previous address).
-  * @rmtoll FLASH_ACR    DISAB_BUF     LL_FLASH_DisableBuffers
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisableBuffers(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_DISAB_BUF);
-}
-
-/**
-  * @brief  Enable pre-read
-  * @note   When enabled, the memory interface stores the last address
-  *         read as data and tries to read the next one when no other
-  *         read or write or prefetch operation is ongoing.
-  *         It is automatically disabled every time the buffers are disabled.
-  * @rmtoll FLASH_ACR    PRE_READ      LL_FLASH_EnablePreRead
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnablePreRead(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_PRE_READ);
-}
-
-/**
-  * @brief  Disable pre-read
-  * @rmtoll FLASH_ACR    PRE_READ      LL_FLASH_DisablePreRead
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisablePreRead(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRE_READ);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_SYSTEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h
deleted file mode 100644
index 2f815b5189..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h
+++ /dev/null
@@ -1,3320 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_tim.h
-  * @author  MCD Application Team
-  * @brief   Header file of TIM LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_TIM_H
-#define __STM32L0xx_LL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (TIM2) || defined (TIM3) || defined (TIM21) || defined (TIM22) || defined (TIM6) || defined (TIM7)
-
-/** @defgroup TIM_LL TIM
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Variables TIM Private Variables
-  * @{
-  */
-static const uint8_t OFFSET_TAB_CCMRx[] =
-{
-  0x00U,   /* 0: TIMx_CH1  */
-  0x00U,   /* 1: NA */
-  0x00U,   /* 2: TIMx_CH2  */
-  0x00U,   /* 3: NA */
-  0x04U,   /* 4: TIMx_CH3  */
-  0x00U,   /* 5: NA */
-  0x04U    /* 6: TIMx_CH4  */
-};
-
-static const uint8_t SHIFT_TAB_OCxx[] =
-{
-  0U,            /* 0: OC1M, OC1FE, OC1PE */
-  0U,            /* 1: - NA */
-  8U,            /* 2: OC2M, OC2FE, OC2PE */
-  0U,            /* 3: - NA */
-  0U,            /* 4: OC3M, OC3FE, OC3PE */
-  0U,            /* 5: - NA */
-  8U             /* 6: OC4M, OC4FE, OC4PE */
-};
-
-static const uint8_t SHIFT_TAB_ICxx[] =
-{
-  0U,            /* 0: CC1S, IC1PSC, IC1F */
-  0U,            /* 1: - NA */
-  8U,            /* 2: CC2S, IC2PSC, IC2F */
-  0U,            /* 3: - NA */
-  0U,            /* 4: CC3S, IC3PSC, IC3F */
-  0U,            /* 5: - NA */
-  8U             /* 6: CC4S, IC4PSC, IC4F */
-};
-
-static const uint8_t SHIFT_TAB_CCxP[] =
-{
-  0U,            /* 0: CC1P */
-  0U,            /* 1: NA */
-  4U,            /* 2: CC2P */
-  0U,            /* 3: NA */
-  8U,            /* 4: CC3P */
-  0U,            /* 5: NA */
-  12U            /* 6: CC4P */
-};
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Constants TIM Private Constants
-  * @{
-  */
-
-
-/* Remap mask definitions */
-#define TIMx_OR_RMP_SHIFT  16U
-#define TIMx_OR_RMP_MASK   0x0000FFFFU
-#define TIM2_OR_RMP_MASK   ((TIM2_OR_ETR_RMP | TIM2_OR_TI4_RMP ) << TIMx_OR_RMP_SHIFT)
-#define TIM21_OR_RMP_MASK  ((TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP) << TIMx_OR_RMP_SHIFT)
-#define TIM22_OR_RMP_MASK  ((TIM22_OR_ETR_RMP | TIM22_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT)
-#if defined(TIM3)
-#define TIM3_OR_RMP_MASK   ((TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | \
-                             TIM3_OR_TI4_RMP) << TIMx_OR_RMP_SHIFT)
-#endif /* TIM3 */
-
-
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Macros TIM Private Macros
-  * @{
-  */
-/** @brief  Convert channel id into channel index.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval none
-  */
-#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
-
-/**
-  * @}
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  TIM Time Base configuration structure definition.
-  */
-typedef struct
-{
-  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetPrescaler().*/
-
-  uint32_t CounterMode;       /*!< Specifies the counter mode.
-                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetCounterMode().*/
-
-  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
-                                   Auto-Reload Register at the next update event.
-                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-                                   Some timer instances may support 32 bits counters. In that case this parameter must
-                                   be a number between 0x0000 and 0xFFFFFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetAutoReload().*/
-
-  uint32_t ClockDivision;     /*!< Specifies the clock division.
-                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetClockDivision().*/
-} LL_TIM_InitTypeDef;
-
-/**
-  * @brief  TIM Output Compare configuration structure definition.
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the output mode.
-                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetMode().*/
-
-  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
-                               This feature can be modified afterwards using unitary functions
-                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
-  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
-                               This feature can be modified afterwards using unitary function
-                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetPolarity().*/
-
-
-} LL_TIM_OC_InitTypeDef;
-
-/**
-  * @brief  TIM Input Capture configuration structure definition.
-  */
-
-typedef struct
-{
-
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t ICActiveInput; /*!< Specifies the input.
-                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetFilter().*/
-} LL_TIM_IC_InitTypeDef;
-
-
-/**
-  * @brief  TIM Encoder interface configuration structure definition.
-  */
-typedef struct
-{
-  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
-                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_SetEncoderMode().*/
-
-  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
-                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
-                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetFilter().*/
-
-  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
-                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
-                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetFilter().*/
-
-} LL_TIM_ENCODER_InitTypeDef;
-
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
-  * @{
-  */
-
-/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
-  * @{
-  */
-#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
-#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
-#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
-#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
-#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
-#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
-#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
-#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
-#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
-#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
-  * @{
-  */
-#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
-#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
-#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
-#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
-#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
-#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
-  * @{
-  */
-#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
-#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
-  * @{
-  */
-#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
-  * @{
-  */
-#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
-#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
-#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
-#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
-  * @{
-  */
-#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
-  * @{
-  */
-#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
-#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
-/**
-  * @}
-  */
-
-
-/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
-  * @{
-  */
-#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
-#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
-/**
-  * @}
-  */
-
-
-/** @defgroup TIM_LL_EC_CHANNEL Channel
-  * @{
-  */
-#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
-#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
-#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
-#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
-  * @{
-  */
-#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
-#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
-  * @{
-  */
-#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
-#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
-#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
-#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
-#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
-#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
-#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
-#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
-  * @{
-  */
-#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
-#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
-/**
-  * @}
-  */
-
-
-
-/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
-  * @{
-  */
-#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
-#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
-#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
-  * @{
-  */
-#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
-#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
-#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
-#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
-  * @{
-  */
-#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
-  * @{
-  */
-#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
-#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
-#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
-  * @{
-  */
-#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
-#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
-  * @{
-  */
-#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
-#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TRGO Trigger Output
-  * @{
-  */
-#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
-#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
-#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
-#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
-#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
-/**
-  * @}
-  */
-
-
-/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
-  * @{
-  */
-#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
-#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
-#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
-#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TS Trigger Selection
-  * @{
-  */
-#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
-  * @{
-  */
-#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
-#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
-  * @{
-  */
-#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
-#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
-#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
-#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
-  * @{
-  */
-#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-
-
-
-
-
-
-/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
-  * @{
-  */
-#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_OR            (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_OR register is the DMA base address for DMA burst */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
-  * @{
-  */
-#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
-/**
-  * @}
-  */
-
-
-/** @defgroup TIM_LL_EC_TIM2_ETR_RMP  TIM2 External Trigger Remap
-  * @{
-  */
-#define LL_TIM_TIM2_ETR_RMP_GPIO     TIM2_OR_RMP_MASK                                             /*!< TIM2_ETR is connected to Ored GPIO */
-#if defined(TIM_TIM2_REMAP_HSI_SUPPORT)
-#define LL_TIM_TIM2_ETR_RMP_HSI      (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0 | TIM2_OR_RMP_MASK)   /*!< TIM2_ETR is connected to HSI */
-#endif /* defined(TIM_TIM2_REMAP_HSI_SUPPORT) */
-#if defined(TIM_TIM2_REMAP_HSI48_SUPPORT)
-#define LL_TIM_TIM2_ETR_RMP_HSI48    (TIM2_OR_ETR_RMP_2 | TIM2_OR_RMP_MASK)                       /*!< TIM2_ETR is connected to HSI48 */
-#endif /* defined(TIM_TIM2_REMAP_HSI48_SUPPORT) */
-#define LL_TIM_TIM2_ETR_RMP_LSE      (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0 | TIM2_OR_RMP_MASK)   /*!< TIM2_ETR is connected to LSE */
-#define LL_TIM_TIM2_ETR_RMP_COMP2    (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1 | TIM2_OR_RMP_MASK)   /*!< TIM2_ETR is connected to COMP2_OUT */
-#define LL_TIM_TIM2_ETR_RMP_COMP1    (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK)                         /*!< TIM2_ETR is connected to COMP1_OUT */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 Timer Input Ch4 Remap
-  * @{
-  */
-#define LL_TIM_TIM2_TI4_RMP_GPIO      TIM2_OR_RMP_MASK                           /*!< TIM2 input capture 4 is connected to GPIO */
-#define LL_TIM_TIM2_TI4_RMP_COMP2     (TIM2_OR_TI4_RMP_0 | TIM2_OR_RMP_MASK)     /*!< TIM2 input capture 4 is connected to COMP2_OUT */
-#define LL_TIM_TIM2_TI4_RMP_COMP1     (TIM2_OR_TI4_RMP_1 | TIM2_OR_RMP_MASK)     /*!< TIM2 input capture 4 is connected to COMP1_OUT */
-/**
-  * @}
-  */
-
-#if defined(TIM3_OR_ETR_RMP)
-/** @defgroup TIM_LL_EC_TIM3_ETR_RMP  TIM3 External Trigger Remap
-  * @{
-  */
-#define LL_TIM_TIM3_ETR_RMP_GPIO         TIM3_OR_RMP_MASK                               /*!< TIM3_ETR is connected to GPIO */
-#define LL_TIM_TIM3_ETR_RMP_HSI48DIV6    (TIM3_OR_ETR_RMP_1 | TIM3_OR_RMP_MASK)         /*!< TIM3_ETR is connected to HSI48 divided by 6 */
-/**
-  * @}
-  */
-#endif /* defined(TIM3_OR_ETR_RMP) */
-
-#if defined(TIM3_OR_TI1_RMP) || defined(TIM3_OR_TI2_RMP) || defined(TIM3_OR_TI4_RMP)
-/** @defgroup TIM_LL_EC_TIM3_TI_RMP  TIM3 External Inputs Remap
-  * @{
-  */
-#define LL_TIM_TIM3_TI_RMP_TI1_USB_SOF      TIM3_OR_RMP_MASK                           /*!< TIM3_TI1 input is connected to USB_SOF */
-#define LL_TIM_TIM3_TI_RMP_TI1_GPIO         (TIM3_OR_TI1_RMP | TIM3_OR_RMP_MASK)       /*!< TIM3_TI1 input is connected to PE3, PA6, PC6 or PB4 */
-
-#define LL_TIM_TIM3_TI_RMP_TI2_GPIO_DEF     TIM3_OR_RMP_MASK                           /*!< Mapping PB5 to TIM22_CH2 */
-#define LL_TIM_TIM3_TI_RMP_TI2_GPIOB5_AF4   (TIM3_OR_TI2_RMP | TIM3_OR_RMP_MASK)       /*!< Mapping PB5 to TIM3_CH2 */
-
-#define LL_TIM_TIM3_TI_RMP_TI4_GPIO_DEF     (0x00000000U | TIM3_OR_RMP_MASK)           /*!< Mapping PC9 to USB_OE */
-#define LL_TIM_TIM3_TI_RMP_TI4_GPIOC9_AF2   (TIM3_OR_TI4_RMP | TIM3_OR_RMP_MASK)       /*!< Mapping PC9 to TIM3_CH4 */
-/**
-  * @}
-  */
-#endif /*defined(TIM3_OR_TI1_RMP) or defined(TIM3_OR_TI2_RMP) or defined(TIM3_OR_TI4_RMP)*/
-
-/** @defgroup TIM_LL_EC_TIM21_ETR_RMP  TIM21 External Trigger Remap
-  * @{
-  */
-#define LL_TIM_TIM21_ETR_RMP_GPIO  TIM21_OR_RMP_MASK                           /*!< TIM21_ETR is connected to Ored GPIO1 */
-#define LL_TIM_TIM21_ETR_RMP_COMP2 (TIM21_OR_ETR_RMP_0 | TIM21_OR_RMP_MASK)    /*!< TIM21_ETR is connected to COMP2_OUT */
-#define LL_TIM_TIM21_ETR_RMP_COMP1 (TIM21_OR_ETR_RMP_1 | TIM21_OR_RMP_MASK)    /*!< TIM21_ETR is connected to COMP1_OUT */
-#define LL_TIM_TIM21_ETR_RMP_LSE   (TIM21_OR_ETR_RMP | TIM21_OR_RMP_MASK)      /*!< TIM21_ETR is connected to LSE */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM21_TI1_RMP  TIM21 External Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM21_TI1_RMP_GPIO    TIM21_OR_RMP_MASK                                              /*!< TIM21_TI1 is connected to Ored GPIO1 */
-#define LL_TIM_TIM21_TI1_RMP_RTC_WK  (TIM21_OR_TI1_RMP_0 | TIM21_OR_RMP_MASK)                       /*!< TIM21_TI1 is connected to RTC_WAKEUP */
-#define LL_TIM_TIM21_TI1_RMP_HSE_RTC (TIM21_OR_TI1_RMP_1 | TIM21_OR_RMP_MASK)                       /*!< TIM21_TI1 is connected to HSE_RTC */
-#define LL_TIM_TIM21_TI1_RMP_MSI     (TIM21_OR_TI1_RMP_1 | TIM21_OR_TI1_RMP_0 | TIM21_OR_RMP_MASK)  /*!< TIM21_TI1 is connected to MSI */
-#define LL_TIM_TIM21_TI1_RMP_LSE     (TIM21_OR_TI1_RMP_2 | TIM21_OR_RMP_MASK)                       /*!< TIM21_TI1 is connected to LSE */
-#define LL_TIM_TIM21_TI1_RMP_LSI     (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0 | TIM21_OR_RMP_MASK)  /*!< TIM21_TI1 is connected to LSI */
-#define LL_TIM_TIM21_TI1_RMP_COMP1   (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1 | TIM21_OR_RMP_MASK)  /*!< TIM21_TI1 is connected to COMP1_OUT */
-#define LL_TIM_TIM21_TI1_RMP_MCO     (TIM21_OR_TI1_RMP | TIM21_OR_RMP_MASK)                         /*!< TIM21_TI1 is connected to MCO */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM21_TI2_RMP  TIM21 External Input Ch2 Remap
-  * @{
-  */
-#define LL_TIM_TIM21_TI2_RMP_GPIO    TIM21_OR_RMP_MASK                            /*!< TIM21_TI2 is connected to Ored GPIO1 */
-#define LL_TIM_TIM21_TI2_RMP_COMP2   (TIM21_OR_TI2_RMP | TIM21_OR_RMP_MASK)       /*!< TIM21_TI2 is connected to COMP2_OUT */
-/**
-  * @}
-  */
-
-#if defined(TIM22_OR_ETR_RMP)
-
-/** @defgroup TIM_LL_EC_TIM22_ETR_RMP  TIM22 External Trigger Remap
-  * @{
-  */
-#define LL_TIM_TIM22_ETR_RMP_GPIO  TIM22_OR_RMP_MASK                           /*!< TIM22_ETR is connected to GPIO */
-#define LL_TIM_TIM22_ETR_RMP_COMP2 (TIM22_OR_ETR_RMP_0 | TIM22_OR_RMP_MASK)    /*!< TIM22_ETR is connected to COMP2_OUT */
-#define LL_TIM_TIM22_ETR_RMP_COMP1 (TIM22_OR_ETR_RMP_1 | TIM22_OR_RMP_MASK)    /*!< TIM22_ETR is connected to COMP1_OUT */
-#define LL_TIM_TIM22_ETR_RMP_LSE   (TIM22_OR_ETR_RMP | TIM22_OR_RMP_MASK)      /*!< TIM22_ETR is connected to LSE */
-/**
-  * @}
-  */
-#endif /* defined(TIM22_OR_ETR_RMP) */
-
-#if defined(TIM22_OR_TI1_RMP)
-/** @defgroup TIM_LL_EC_TIM22_TI1_RMP  TIM22 External Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM22_TI1_RMP_GPIO1  TIM22_OR_RMP_MASK                            /*!< TIM22_TI1 is connected to GPIO1 */
-#define LL_TIM_TIM22_TI1_RMP_COMP2  (TIM22_OR_TI1_RMP_0 | TIM22_OR_RMP_MASK)     /*!< TIM22_TI1 is connected to COMP2_OUT */
-#define LL_TIM_TIM22_TI1_RMP_COMP1  (TIM22_OR_TI1_RMP_1 | TIM22_OR_RMP_MASK)     /*!< TIM22_TI1 is connected to COMP1_OUT */
-#define LL_TIM_TIM22_TI1_RMP_GPIO2  (TIM22_OR_TI1_RMP | TIM22_OR_RMP_MASK)       /*!< TIM22_TI1 is connected to GPIO2 */
-/**
-  * @}
-  */
-#endif /* defined(TIM22_OR_TI1_RMP) */
-
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
-  * @{
-  */
-
-/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-/**
-  * @brief  Write a value in TIM register.
-  * @param  __INSTANCE__ TIM Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in TIM register.
-  * @param  __INSTANCE__ TIM Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
-  * @{
-  */
-
-/**
-  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
-  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __CNTCLK__ counter clock frequency (in Hz)
-  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
-  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
-
-/**
-  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
-  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __FREQ__ output signal frequency (in Hz)
-  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
-  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
-
-/**
-  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
-  *         active/inactive delay.
-  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __DELAY__ timer output compare active/inactive delay (in us)
-  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
-  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
-              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
-
-/**
-  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
-  *         (when the timer operates in one pulse mode).
-  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __DELAY__ timer output compare active/inactive delay (in us)
-  * @param  __PULSE__ pulse duration (in us)
-  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
-  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
-              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
-
-/**
-  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
-  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
-  * @param  __ICPSC__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
-  */
-#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
-  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
-
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
-  * @{
-  */
-/**
-  * @brief  Enable timer counter.
-  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
-  * @brief  Disable timer counter.
-  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
-  * @brief  Indicates whether the timer counter is enabled.
-  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable update event generation.
-  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
-  * @brief  Disable update event generation.
-  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
-  * @brief  Indicates whether update event generation is enabled.
-  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval Inverted state of bit (0 or 1).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set update event source
-  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
-  *       generate an update interrupt or DMA request if enabled:
-  *        - Counter overflow/underflow
-  *        - Setting the UG bit
-  *        - Update generation through the slave mode controller
-  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
-  *       overflow/underflow generates an update interrupt or DMA request if enabled.
-  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
-  * @param  TIMx Timer instance
-  * @param  UpdateSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
-  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
-}
-
-/**
-  * @brief  Get actual event update source
-  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
-  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
-}
-
-/**
-  * @brief  Set one pulse mode (one shot v.s. repetitive).
-  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
-  * @param  TIMx Timer instance
-  * @param  OnePulseMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
-  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
-}
-
-/**
-  * @brief  Get actual one pulse mode.
-  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
-  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
-}
-
-/**
-  * @brief  Set the timer counter counting mode.
-  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
-  *       check whether or not the counter mode selection feature is supported
-  *       by a timer instance.
-  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *       requires a timer reset to avoid unexpected direction
-  *       due to DIR bit readonly in center aligned mode.
-  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
-  *         CR1          CMS           LL_TIM_SetCounterMode
-  * @param  TIMx Timer instance
-  * @param  CounterMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERMODE_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
-{
-  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
-}
-
-/**
-  * @brief  Get actual counter mode.
-  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
-  *       check whether or not the counter mode selection feature is supported
-  *       by a timer instance.
-  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
-  *         CR1          CMS           LL_TIM_GetCounterMode
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERMODE_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
-{
-  uint32_t counter_mode;
-
-  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
-
-  if (counter_mode == 0U)
-  {
-    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-  }
-
-  return counter_mode;
-}
-
-/**
-  * @brief  Enable auto-reload (ARR) preload.
-  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
-  * @brief  Disable auto-reload (ARR) preload.
-  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
-  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
-  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
-  *         (when supported) and the digital filters.
-  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
-  *       whether or not the clock division feature is supported by the timer
-  *       instance.
-  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
-  * @param  TIMx Timer instance
-  * @param  ClockDivision This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
-}
-
-/**
-  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
-  *         generators (when supported) and the digital filters.
-  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
-  *       whether or not the clock division feature is supported by the timer
-  *       instance.
-  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
-}
-
-/**
-  * @brief  Set the counter value.
-  * @rmtoll CNT          CNT           LL_TIM_SetCounter
-  * @param  TIMx Timer instance
-  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
-{
-  WRITE_REG(TIMx->CNT, Counter);
-}
-
-/**
-  * @brief  Get the counter value.
-  * @rmtoll CNT          CNT           LL_TIM_GetCounter
-  * @param  TIMx Timer instance
-  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CNT));
-}
-
-/**
-  * @brief  Get the current direction of the counter
-  * @rmtoll CR1          DIR           LL_TIM_GetDirection
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
-  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-}
-
-/**
-  * @brief  Set the prescaler value.
-  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
-  * @note The prescaler can be changed on the fly as this control register is buffered. The new
-  *       prescaler ratio is taken into account at the next update event.
-  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
-  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Prescaler between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
-{
-  WRITE_REG(TIMx->PSC, Prescaler);
-}
-
-/**
-  * @brief  Get the prescaler value.
-  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
-  * @param  TIMx Timer instance
-  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->PSC));
-}
-
-/**
-  * @brief  Set the auto-reload value.
-  * @note The counter is blocked while the auto-reload value is null.
-  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
-  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
-  * @param  TIMx Timer instance
-  * @param  AutoReload between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
-{
-  WRITE_REG(TIMx->ARR, AutoReload);
-}
-
-/**
-  * @brief  Get the auto-reload value.
-  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
-  * @param  TIMx Timer instance
-  * @retval Auto-reload value
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->ARR));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
-  * @{
-  */
-/**
-  * @brief  Set the trigger of the capture/compare DMA request.
-  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
-  * @param  TIMx Timer instance
-  * @param  DMAReqTrigger This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
-  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
-}
-
-/**
-  * @brief  Get actual trigger of the capture/compare DMA request.
-  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
-  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
-  */
-__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
-}
-
-/**
-  * @brief  Enable capture/compare channels.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC4E          LL_TIM_CC_EnableChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  SET_BIT(TIMx->CCER, Channels);
-}
-
-/**
-  * @brief  Disable capture/compare channels.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC4E          LL_TIM_CC_DisableChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  CLEAR_BIT(TIMx->CCER, Channels);
-}
-
-/**
-  * @brief  Indicate whether channel(s) is(are) enabled.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
-  * @{
-  */
-/**
-  * @brief  Configure an output channel.
-  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
-  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
-             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Define the behavior of the output reference signal OCxREF from which
-  *         OCx and OCxN (when relevant) are derived.
-  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
-  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
-  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
-  *         CCMR2        OC4M          LL_TIM_OC_SetMode
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCMODE_FROZEN
-  *         @arg @ref LL_TIM_OCMODE_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_TOGGLE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_PWM1
-  *         @arg @ref LL_TIM_OCMODE_PWM2
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
-  * @brief  Get the output compare mode of an output channel.
-  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
-  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
-  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
-  *         CCMR2        OC4M          LL_TIM_OC_GetMode
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCMODE_FROZEN
-  *         @arg @ref LL_TIM_OCMODE_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_TOGGLE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_PWM1
-  *         @arg @ref LL_TIM_OCMODE_PWM2
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
-  * @brief  Set the polarity of an output channel.
-  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC4P          LL_TIM_OC_SetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
-  *         @arg @ref LL_TIM_OCPOLARITY_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Get the polarity of an output channel.
-  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC4P          LL_TIM_OC_GetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
-  *         @arg @ref LL_TIM_OCPOLARITY_LOW
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Enable fast mode for the output channel.
-  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
-  * @brief  Disable fast mode for the output channel.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
-  * @brief  Indicates whether fast mode is enabled for the output channel.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable clearing the output channel on an external event.
-  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Disable clearing the output channel on an external event.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
-  * @note This function enables clearing the output channel on an external event.
-  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR1, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR2, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR3, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR4, CompareValue);
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 3 is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
-  * @{
-  */
-/**
-  * @brief  Configure input channel.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
-  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
-  *         CCMR1        IC1F          LL_TIM_IC_Config\n
-  *         CCMR1        CC2S          LL_TIM_IC_Config\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
-  *         CCMR1        IC2F          LL_TIM_IC_Config\n
-  *         CCMR2        CC3S          LL_TIM_IC_Config\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
-  *         CCMR2        IC3F          LL_TIM_IC_Config\n
-  *         CCMR2        CC4S          LL_TIM_IC_Config\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
-  *         CCMR2        IC4F          LL_TIM_IC_Config\n
-  *         CCER         CC1P          LL_TIM_IC_Config\n
-  *         CCER         CC1NP         LL_TIM_IC_Config\n
-  *         CCER         CC2P          LL_TIM_IC_Config\n
-  *         CCER         CC2NP         LL_TIM_IC_Config\n
-  *         CCER         CC3P          LL_TIM_IC_Config\n
-  *         CCER         CC3NP         LL_TIM_IC_Config\n
-  *         CCER         CC4P          LL_TIM_IC_Config\n
-  *         CCER         CC4NP         LL_TIM_IC_Config
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
-  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
-             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
-             << SHIFT_TAB_ICxx[iChannel]);
-  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
-             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Set the active input.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICActiveInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the current active input.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the prescaler of input channel.
-  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the current prescaler value acting on an  input channel.
-  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the input filter duration.
-  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
-  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
-  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
-  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the input filter duration.
-  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
-  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
-  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
-  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the input channel polarity.
-  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING
-  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
-  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
-             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Get the current input channel polarity.
-  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING
-  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
-  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
-          SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
-  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
-  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  * a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get captured value for input channel 1.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
-  * @brief  Get captured value for input channel 2.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
-  * @brief  Get captured value for input channel 3.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 3 is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
-  * @brief  Get captured value for input channel 4.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
-  * @{
-  */
-/**
-  * @brief  Enable external clock mode 2.
-  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
-  * @brief  Disable external clock mode 2.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
-  * @brief  Indicate whether external clock mode 2 is enabled.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the clock source of the counter clock.
-  * @note when selected clock source is external clock mode 1, the timer input
-  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
-  *       function. This timer input must be configured by calling
-  *       the @ref LL_TIM_IC_Config() function.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode1.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
-  *         SMCR         ECE           LL_TIM_SetClockSource
-  * @param  TIMx Timer instance
-  * @param  ClockSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
-  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
-  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
-}
-
-/**
-  * @brief  Set the encoder interface mode.
-  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports the encoder mode.
-  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
-  * @param  TIMx Timer instance
-  * @param  EncoderMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
-  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
-  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
-  * @{
-  */
-/**
-  * @brief  Set the trigger output (TRGO) used for timer synchronization .
-  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance can operate as a master timer.
-  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
-  * @param  TIMx Timer instance
-  * @param  TimerSynchronization This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TRGO_RESET
-  *         @arg @ref LL_TIM_TRGO_ENABLE
-  *         @arg @ref LL_TIM_TRGO_UPDATE
-  *         @arg @ref LL_TIM_TRGO_CC1IF
-  *         @arg @ref LL_TIM_TRGO_OC1REF
-  *         @arg @ref LL_TIM_TRGO_OC2REF
-  *         @arg @ref LL_TIM_TRGO_OC3REF
-  *         @arg @ref LL_TIM_TRGO_OC4REF
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
-}
-
-/**
-  * @brief  Set the synchronization mode of a slave timer.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
-  * @param  TIMx Timer instance
-  * @param  SlaveMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
-  *         @arg @ref LL_TIM_SLAVEMODE_RESET
-  *         @arg @ref LL_TIM_SLAVEMODE_GATED
-  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
-}
-
-/**
-  * @brief  Set the selects the trigger input to be used to synchronize the counter.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
-  * @param  TIMx Timer instance
-  * @param  TriggerInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TS_ITR0
-  *         @arg @ref LL_TIM_TS_ITR1
-  *         @arg @ref LL_TIM_TS_ITR2
-  *         @arg @ref LL_TIM_TS_ITR3
-  *         @arg @ref LL_TIM_TS_TI1F_ED
-  *         @arg @ref LL_TIM_TS_TI1FP1
-  *         @arg @ref LL_TIM_TS_TI2FP2
-  *         @arg @ref LL_TIM_TS_ETRF
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
-}
-
-/**
-  * @brief  Enable the Master/Slave mode.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
-  * @brief  Disable the Master/Slave mode.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
-  * @brief Indicates whether the Master/Slave mode is enabled.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  * a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the external trigger (ETR) input.
-  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an external trigger input.
-  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
-  *         SMCR         ETPS          LL_TIM_ConfigETR\n
-  *         SMCR         ETF           LL_TIM_ConfigETR
-  * @param  TIMx Timer instance
-  * @param  ETRPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
-  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
-  * @param  ETRPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
-  * @param  ETRFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
-                                      uint32_t ETRFilter)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
-  * @{
-  */
-/**
-  * @brief  Configures the timer DMA burst feature.
-  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
-  *       not a timer instance supports the DMA burst mode.
-  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
-  *         DCR          DBA           LL_TIM_ConfigDMABurst
-  * @param  TIMx Timer instance
-  * @param  DMABurstBaseAddress This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR
-  * @param  DMABurstLength This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
-{
-  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
-  * @{
-  */
-/**
-  * @brief  Remap TIM inputs (input channel, internal/external triggers).
-  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
-  *       a some timer inputs can be remapped.
-  * @rmtoll TIM2_OR     ETR_RMP      LL_TIM_SetRemap\n
-  *         TIM2_OR     TI4_RMP      LL_TIM_SetRemap\n
-  *         TIM21_OR    ETR_RMP      LL_TIM_SetRemap\n
-  *         TIM21_OR    TI1_RMP      LL_TIM_SetRemap\n
-  *         TIM21_OR    TI2_RMP      LL_TIM_SetRemap\n
-  *         TIM22_OR    ETR_RMP      LL_TIM_SetRemap\n
-  *         TIM22_OR    TI1_RMP      LL_TIM_SetRemap\n
-  *         TIM3_OR     ETR_RMP      LL_TIM_SetRemap\n
-  *         TIM3_OR     TI1_RMP      LL_TIM_SetRemap\n
-  *         TIM3_OR     TI2_RMP      LL_TIM_SetRemap\n
-  *         TIM3_OR     TI4_RMP      LL_TIM_SetRemap
-  * @param  TIMx Timer instance
-  * @param  Remap Remap params depends on the TIMx. Description available only
-  *         in CHM version of the User Manual (not in .pdf).
-  *         Otherwise see Reference Manual description of OR registers.
-  *
-  *         Below description summarizes "Timer Instance" and "Remap" param combinations:
-  *
-  *         TIM2: any combination of ETR_RMP, TI4_RMP where
-  *
-  *            . . ETR_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM2_ETR_RMP_HSI   (*)
-  *            @arg @ref LL_TIM_TIM2_ETR_RMP_HSI48 (*)
-  *            @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
-  *            @arg @ref LL_TIM_TIM2_ETR_RMP_COMP2
-  *            @arg @ref LL_TIM_TIM2_ETR_RMP_COMP1
-  *
-  *            . . TI4_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
-  *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
-  *
-  *         TIM3: any combination of the following values        (**)
-  *
-  *            . . ETR_RMP can be one of the following values    (**)
-  *            @arg @ref LL_TIM_TIM3_ETR_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM3_ETR_RMP_HSI48DIV6
-  *
-  *            . . TI_RMP_TI1 can be one of the following values (**)
-  *            @arg @ref LL_TIM_TIM3_TI_RMP_TI1_USB_SOF
-  *            @arg @ref LL_TIM_TIM3_TI_RMP_TI1_GPIO
-  *
-  *            . . TI_RMP_TI2 can be one of the following values (**)
-  *            @arg @ref LL_TIM_TIM3_TI_RMP_TI2_GPIO_DEF
-  *            @arg @ref LL_TIM_TIM3_TI_RMP_TI2_GPIOB5_AF4
-  *
-  *            . . TI_RMP_TI4 can be one of the following values (**)
-  *            @arg @ref LL_TIM_TIM3_TI_RMP_TI4_GPIO_DEF
-  *            @arg @ref LL_TIM_TIM3_TI_RMP_TI4_GPIOC9_AF2
-  *
-  *         TIM21: any combination of ETR_RMP, TI1_RMP, TI2_RMP where
-  *
-  *            . . ETR_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM21_ETR_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM21_ETR_RMP_COMP2
-  *            @arg @ref LL_TIM_TIM21_ETR_RMP_COMP1
-  *            @arg @ref LL_TIM_TIM21_ETR_RMP_LSE
-  *
-  *            . . TI1_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM21_TI1_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM21_TI1_RMP_RTC_WK
-  *            @arg @ref LL_TIM_TIM21_TI1_RMP_HSE_RTC
-  *            @arg @ref LL_TIM_TIM21_TI1_RMP_MSI
-  *            @arg @ref LL_TIM_TIM21_TI1_RMP_LSE
-  *            @arg @ref LL_TIM_TIM21_TI1_RMP_LSI
-  *            @arg @ref LL_TIM_TIM21_TI1_RMP_COMP1
-  *            @arg @ref LL_TIM_TIM21_TI1_RMP_MCO
-  *
-  *            . . TI2_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM21_TI2_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM21_TI2_RMP_COMP2
-  *
-  *         TIM22: any combination of ETR_RMP, TI1_RMP where  (**)
-  *
-  *            . . ETR_RMP can be one of the following values (**)
-  *            @arg @ref LL_TIM_TIM22_ETR_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM22_ETR_RMP_COMP2
-  *            @arg @ref LL_TIM_TIM22_ETR_RMP_COMP1
-  *            @arg @ref LL_TIM_TIM22_ETR_RMP_LSE
-  *
-  *            . . TI1_RMP can be one of the following values (**)
-  *            @arg @ref LL_TIM_TIM22_TI1_RMP_GPIO1
-  *            @arg @ref LL_TIM_TIM22_TI1_RMP_COMP2
-  *            @arg @ref LL_TIM_TIM22_TI1_RMP_COMP1
-  *            @arg @ref LL_TIM_TIM22_TI1_RMP_GPIO2
-  *
-  *         (*) Value not defined in all devices. \n
-  *         (*) Register not available in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
-{
-  MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
-  * @{
-  */
-/**
-  * @brief  Clear the update interrupt flag (UIF).
-  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
-}
-
-/**
-  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
-  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
-  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
-  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
-  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
-  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
-  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
-  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
-  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
-  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the trigger interrupt flag (TIF).
-  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
-}
-
-/**
-  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
-  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
-  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
-  *         (Capture/Compare 1 interrupt is pending).
-  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
-  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
-  *         (Capture/Compare 2 over-capture interrupt is pending).
-  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
-  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
-  *         (Capture/Compare 3 over-capture interrupt is pending).
-  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
-  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
-  *         (Capture/Compare 4 over-capture interrupt is pending).
-  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_IT_Management IT-Management
-  * @{
-  */
-/**
-  * @brief  Enable update interrupt (UIE).
-  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
-  * @brief  Disable update interrupt (UIE).
-  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
-  * @brief  Indicates whether the update interrupt (UIE) is enabled.
-  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 1 interrupt (CC1IE).
-  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
-  * @brief  Disable capture/compare 1  interrupt (CC1IE).
-  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
-  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 2 interrupt (CC2IE).
-  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
-  * @brief  Disable capture/compare 2  interrupt (CC2IE).
-  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
-  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 3 interrupt (CC3IE).
-  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
-  * @brief  Disable capture/compare 3  interrupt (CC3IE).
-  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
-  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 4 interrupt (CC4IE).
-  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
-  * @brief  Disable capture/compare 4  interrupt (CC4IE).
-  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
-  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable trigger interrupt (TIE).
-  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
-  * @brief  Disable trigger interrupt (TIE).
-  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
-  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
-  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_DMA_Management DMA Management
-  * @{
-  */
-/**
-  * @brief  Enable update DMA request (UDE).
-  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
-  * @brief  Disable update DMA request (UDE).
-  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
-  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
-  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 1 DMA request (CC1DE).
-  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
-  * @brief  Disable capture/compare 1  DMA request (CC1DE).
-  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
-  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 2 DMA request (CC2DE).
-  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
-  * @brief  Disable capture/compare 2  DMA request (CC2DE).
-  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
-  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 3 DMA request (CC3DE).
-  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
-  * @brief  Disable capture/compare 3  DMA request (CC3DE).
-  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
-  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 4 DMA request (CC4DE).
-  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
-  * @brief  Disable capture/compare 4  DMA request (CC4DE).
-  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
-  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable trigger interrupt (TDE).
-  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
-  * @brief  Disable trigger interrupt (TDE).
-  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
-  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
-  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
-  * @{
-  */
-/**
-  * @brief  Generate an update event.
-  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_UG);
-}
-
-/**
-  * @brief  Generate Capture/Compare 1 event.
-  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 2 event.
-  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 3 event.
-  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 4 event.
-  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
-}
-
-/**
-  * @brief  Generate trigger event.
-  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_TG);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
-  * @{
-  */
-
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* TIM1 || TIM3 || TIM21 || TIM22 || TIM6 || TIM7 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_TIM_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h
deleted file mode 100644
index d101ff1eac..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h
+++ /dev/null
@@ -1,3751 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_usart.h
-  * @author  MCD Application Team
-  * @brief   Header file of USART LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_LL_USART_H
-#define STM32L0xx_LL_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (USART1) || defined (USART2) || defined (USART4) || defined (USART5)
-
-/** @defgroup USART_LL USART
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_Private_Macros USART Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_ES_INIT USART Exported Init structures
-  * @{
-  */
-
-/**
-  * @brief LL USART Init Structure definition
-  */
-typedef struct
-{
-
-  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetBaudRate().*/
-
-  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetDataWidth().*/
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetStopBitsLength().*/
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetParity().*/
-
-  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetTransferDirection().*/
-
-  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetHWFlowCtrl().*/
-
-  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
-                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetOverSampling().*/
-
-} LL_USART_InitTypeDef;
-
-/**
-  * @brief LL USART Clock Init Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
-
-                                           USART HW configuration can be modified afterwards using unitary functions
-                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
-                                           For more details, refer to description of this function. */
-
-  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
-
-                                           USART HW configuration can be modified afterwards using unitary
-                                           functions @ref LL_USART_SetClockPolarity().
-                                           For more details, refer to description of this function. */
-
-  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
-
-                                           USART HW configuration can be modified afterwards using unitary
-                                           functions @ref LL_USART_SetClockPhase().
-                                           For more details, refer to description of this function. */
-
-  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
-
-                                           USART HW configuration can be modified afterwards using unitary
-                                           functions @ref LL_USART_SetLastClkPulseOutput().
-                                           For more details, refer to description of this function. */
-
-} LL_USART_ClockInitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Constants USART Exported Constants
-  * @{
-  */
-
-/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_USART_WriteReg function
-  * @{
-  */
-#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error clear flag */
-#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error clear flag */
-#define LL_USART_ICR_NCF                        USART_ICR_NCF                 /*!< Noise error detected clear flag */
-#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error clear flag */
-#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected clear flag */
-#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete clear flag */
-#if defined(USART_TCBGT_SUPPORT)
-#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time clear flag */
-#endif /* USART_TCBGT_SUPPORT */
-#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection clear flag */
-#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag */
-#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout clear flag */
-#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block clear flag */
-#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match clear flag */
-#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_USART_ReadReg function
-  * @{
-  */
-#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
-#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
-#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
-#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
-#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
-#define LL_USART_ISR_RXNE                       USART_ISR_RXNE                /*!< Read data register not empty flag */
-#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
-#define LL_USART_ISR_TXE                        USART_ISR_TXE                 /*!< Transmit data register empty flag */
-#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
-#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
-#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
-#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
-#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
-#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
-#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
-#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
-#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
-#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
-#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
-#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
-#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
-#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
-#if defined(USART_TCBGT_SUPPORT)
-#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
-#endif /* USART_TCBGT_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
-  * @{
-  */
-#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
-#define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
-#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
-#define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
-#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
-#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
-#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
-#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
-#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
-#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
-#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
-#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
-#if defined(USART_TCBGT_SUPPORT)
-#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
-#endif /* USART_TCBGT_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DIRECTION Communication Direction
-  * @{
-  */
-#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
-#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_PARITY Parity Control
-  * @{
-  */
-#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
-#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
-#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_WAKEUP Wakeup
-  * @{
-  */
-#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
-#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
-  * @{
-  */
-#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
-  * @{
-  */
-#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
-#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EC_CLOCK Clock Signal
-  * @{
-  */
-
-#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
-#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
-  * @{
-  */
-#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
-#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_PHASE Clock Phase
-  * @{
-  */
-#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
-#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_POLARITY Clock Polarity
-  * @{
-  */
-#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
-#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_STOPBITS Stop Bits
-  * @{
-  */
-#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
-#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
-#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
-#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
-  * @{
-  */
-#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
-#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
-  * @{
-  */
-#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
-#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
-  * @{
-  */
-#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
-#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
-  * @{
-  */
-#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
-#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_BITORDER Bit Order
-  * @{
-  */
-#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
-#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
-  * @{
-  */
-#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
-#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
-#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
-#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
-  * @{
-  */
-#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
-#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
-  * @{
-  */
-#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
-#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
-#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
-#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
-  * @{
-  */
-#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
-#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
-#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
-  * @{
-  */
-#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
-#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
-  * @{
-  */
-#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
-#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
-  * @{
-  */
-#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
-#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
-  * @{
-  */
-#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
-#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Macros USART Exported Macros
-  * @{
-  */
-
-/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in USART register
-  * @param  __INSTANCE__ USART Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in USART register
-  * @param  __INSTANCE__ USART Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
-  * @{
-  */
-
-/**
-  * @brief  Compute USARTDIV value according to Peripheral Clock and
-  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
-  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
-  * @param  __BAUDRATE__ Baud rate value to achieve
-  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
-  */
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\
-                                                                + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
-
-/**
-  * @brief  Compute USARTDIV value according to Peripheral Clock and
-  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
-  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
-  * @param  __BAUDRATE__ Baud rate value to achieve
-  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
-  */
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup USART_LL_Exported_Functions USART Exported Functions
-  * @{
-  */
-
-/** @defgroup USART_LL_EF_Configuration Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  USART Enable
-  * @rmtoll CR1          UE            LL_USART_Enable
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  USART Disable (all USART prescalers and outputs are disabled)
-  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
-  *         and current operations are discarded. The configuration of the USART is kept, but all the status
-  *         flags, in the USARTx_ISR are set to their default values.
-  * @rmtoll CR1          UE            LL_USART_Disable
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  Indicate if USART is enabled
-  * @rmtoll CR1          UE            LL_USART_IsEnabled
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  USART enabled in STOP Mode.
-  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
-  *         USART clock selection is HSI or LSE in RCC.
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
-}
-
-/**
-  * @brief  USART disabled in STOP Mode.
-  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
-}
-
-/**
-  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  USART Clock enabled in STOP Mode
-  * @note   When this function is called, USART Clock is enabled while in STOP mode
-  * @rmtoll CR3          UCESM         LL_USART_EnableClockInStopMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM);
-}
-
-/**
-  * @brief  USART clock disabled in STOP Mode
-  * @note   When this function is called, USART Clock is disabled while in STOP mode
-  * @rmtoll CR3          UCESM         LL_USART_DisableClockInStopMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM);
-}
-
-/**
-  * @brief  Indicate if USART clock is enabled in STOP Mode
-  * @rmtoll CR3          UCESM         LL_USART_IsClockEnabledInStopMode
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM));
-}
-
-/**
-  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
-  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Receiver Disable
-  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Transmitter Enable
-  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Transmitter Disable
-  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Configure simultaneously enabled/disabled states
-  *         of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
-  *         CR1          TE            LL_USART_SetTransferDirection
-  * @param  USARTx USART Instance
-  * @param  TransferDirection This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DIRECTION_NONE
-  *         @arg @ref LL_USART_DIRECTION_RX
-  *         @arg @ref LL_USART_DIRECTION_TX
-  *         @arg @ref LL_USART_DIRECTION_TX_RX
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
-{
-  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
-}
-
-/**
-  * @brief  Return enabled/disabled states of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
-  *         CR1          TE            LL_USART_GetTransferDirection
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DIRECTION_NONE
-  *         @arg @ref LL_USART_DIRECTION_RX
-  *         @arg @ref LL_USART_DIRECTION_TX
-  *         @arg @ref LL_USART_DIRECTION_TX_RX
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
-}
-
-/**
-  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
-  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
-  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
-  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
-  * @rmtoll CR1          PS            LL_USART_SetParity\n
-  *         CR1          PCE           LL_USART_SetParity
-  * @param  USARTx USART Instance
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
-}
-
-/**
-  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
-  * @rmtoll CR1          PS            LL_USART_GetParity\n
-  *         CR1          PCE           LL_USART_GetParity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  */
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
-}
-
-/**
-  * @brief  Set Receiver Wake Up method from Mute mode.
-  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
-  * @param  USARTx USART Instance
-  * @param  Method This parameter can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_IDLELINE
-  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
-}
-
-/**
-  * @brief  Return Receiver Wake Up method from Mute mode
-  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_IDLELINE
-  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
-  */
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
-}
-
-/**
-  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
-  *         CR1          M1            LL_USART_SetDataWidth
-  * @param  USARTx USART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_7B
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
-}
-
-/**
-  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
-  *         CR1          M1            LL_USART_GetDataWidth
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_7B
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
-}
-
-/**
-  * @brief  Allow switch between Mute Mode and Active mode
-  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
-}
-
-/**
-  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
-  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
-}
-
-/**
-  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
-  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set Oversampling to 8-bit or 16-bit mode
-  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
-  * @param  USARTx USART Instance
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
-}
-
-/**
-  * @brief  Return Oversampling mode
-  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  */
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
-}
-
-/**
-  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
-  * @param  USARTx USART Instance
-  * @param  LastBitClockPulse This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
-}
-
-/**
-  * @brief  Retrieve Clock pulse of the last data bit output configuration
-  *         (Last bit Clock pulse output to the SCLK pin or not)
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  */
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
-}
-
-/**
-  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
-  * @param  USARTx USART Instance
-  * @param  ClockPhase This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
-}
-
-/**
-  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
-}
-
-/**
-  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
-  * @param  USARTx USART Instance
-  * @param  ClockPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
-}
-
-/**
-  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
-}
-
-/**
-  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
-  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
-  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
-  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
-  *         CR2          CPOL          LL_USART_ConfigClock\n
-  *         CR2          LBCL          LL_USART_ConfigClock
-  * @param  USARTx USART Instance
-  * @param  Phase This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  * @param  LBCPOutput This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
-}
-
-/**
-  * @brief  Enable Clock output on SCLK pin
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Disable Clock output on SCLK pin
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Indicate if Clock output on SCLK pin is enabled
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the length of the stop bits
-  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
-  * @param  USARTx USART Instance
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Retrieve the length of the stop bits
-  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  */
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
-}
-
-/**
-  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
-  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
-  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
-  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
-  *         CR1          PCE           LL_USART_ConfigCharacter\n
-  *         CR1          M0            LL_USART_ConfigCharacter\n
-  *         CR1          M1            LL_USART_ConfigCharacter\n
-  *         CR2          STOP          LL_USART_ConfigCharacter
-  * @param  USARTx USART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_7B
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
-                                              uint32_t StopBits)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
-  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Configure TX/RX pins swapping setting.
-  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
-  * @param  USARTx USART Instance
-  * @param  SwapConfig This parameter can be one of the following values:
-  *         @arg @ref LL_USART_TXRX_STANDARD
-  *         @arg @ref LL_USART_TXRX_SWAPPED
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
-}
-
-/**
-  * @brief  Retrieve TX/RX pins swapping configuration.
-  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_TXRX_STANDARD
-  *         @arg @ref LL_USART_TXRX_SWAPPED
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
-}
-
-/**
-  * @brief  Configure RX pin active level logic
-  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
-  * @param  USARTx USART Instance
-  * @param  PinInvMethod This parameter can be one of the following values:
-  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
-}
-
-/**
-  * @brief  Retrieve RX pin active level logic configuration
-  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
-  */
-__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
-}
-
-/**
-  * @brief  Configure TX pin active level logic
-  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
-  * @param  USARTx USART Instance
-  * @param  PinInvMethod This parameter can be one of the following values:
-  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
-}
-
-/**
-  * @brief  Retrieve TX pin active level logic configuration
-  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
-}
-
-/**
-  * @brief  Configure Binary data logic.
-  * @note   Allow to define how Logical data from the data register are send/received :
-  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
-  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
-  * @param  USARTx USART Instance
-  * @param  DataLogic This parameter can be one of the following values:
-  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
-  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
-}
-
-/**
-  * @brief  Retrieve Binary data configuration
-  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
-  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
-}
-
-/**
-  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
-  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
-  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
-  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
-  * @param  USARTx USART Instance
-  * @param  BitOrder This parameter can be one of the following values:
-  *         @arg @ref LL_USART_BITORDER_LSBFIRST
-  *         @arg @ref LL_USART_BITORDER_MSBFIRST
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
-}
-
-/**
-  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
-  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
-  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
-  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_BITORDER_LSBFIRST
-  *         @arg @ref LL_USART_BITORDER_MSBFIRST
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
-}
-
-/**
-  * @brief  Enable Auto Baud-Rate Detection
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
-}
-
-/**
-  * @brief  Disable Auto Baud-Rate Detection
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
-}
-
-/**
-  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set Auto Baud-Rate mode bits
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
-  * @param  USARTx USART Instance
-  * @param  AutoBaudRateMode This parameter can be one of the following values:
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
-}
-
-/**
-  * @brief  Return Auto Baud-Rate mode
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
-  */
-__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
-}
-
-/**
-  * @brief  Enable Receiver Timeout
-  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
-}
-
-/**
-  * @brief  Disable Receiver Timeout
-  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
-}
-
-/**
-  * @brief  Indicate if Receiver Timeout feature is enabled
-  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set Address of the USART node.
-  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
-  *         for wake up with address mark detection.
-  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
-  *         (b7-b4 should be set to 0)
-  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
-  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
-  *         for wake up with 7-bit address mark detection.
-  *         The MSB of the character sent by the transmitter should be equal to 1.
-  *         It may also be used for character detection during normal reception,
-  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
-  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
-  *         value and CMF flag is set on match)
-  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
-  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
-  * @param  USARTx USART Instance
-  * @param  AddressLen This parameter can be one of the following values:
-  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
-  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
-  * @param  NodeAddress 4 or 7 bit Address of the USART node.
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
-             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
-}
-
-/**
-  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
-  * @note   If 4-bit Address Detection is selected in ADDM7,
-  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
-  *         If 7-bit Address Detection is selected in ADDM7,
-  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
-  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
-  * @param  USARTx USART Instance
-  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
-}
-
-/**
-  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
-  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
-  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
-}
-
-/**
-  * @brief  Enable RTS HW Flow Control
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Disable RTS HW Flow Control
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Enable CTS HW Flow Control
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Disable CTS HW Flow Control
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Configure HW Flow Control mode (both CTS and RTS)
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
-  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @param  HardwareFlowControl This parameter can be one of the following values:
-  *         @arg @ref LL_USART_HWCONTROL_NONE
-  *         @arg @ref LL_USART_HWCONTROL_RTS
-  *         @arg @ref LL_USART_HWCONTROL_CTS
-  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
-}
-
-/**
-  * @brief  Return HW Flow Control configuration (both CTS and RTS)
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
-  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_HWCONTROL_NONE
-  *         @arg @ref LL_USART_HWCONTROL_RTS
-  *         @arg @ref LL_USART_HWCONTROL_CTS
-  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
-  */
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
-}
-
-/**
-  * @brief  Enable One bit sampling method
-  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
-  * @brief  Disable One bit sampling method
-  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
-  * @brief  Indicate if One bit sampling method is enabled
-  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Overrun detection
-  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
-  * @brief  Disable Overrun detection
-  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
-  * @brief  Indicate if Overrun detection is enabled
-  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
-  * @param  USARTx USART Instance
-  * @param  Type This parameter can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
-  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
-  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
-}
-
-/**
-  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
-  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
-  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
-}
-
-/**
-  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
-  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
-  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
-  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
-  *         (Baud rate value != 0)
-  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
-  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
-  * @param  USARTx USART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @param  BaudRate Baud Rate
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
-                                          uint32_t BaudRate)
-{
-  uint32_t usartdiv;
-  uint32_t brrtemp;
-
-  if (OverSampling == LL_USART_OVERSAMPLING_8)
-  {
-    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
-    brrtemp = usartdiv & 0xFFF0U;
-    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
-    USARTx->BRR = brrtemp;
-  }
-  else
-  {
-    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
-  }
-}
-
-/**
-  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
-  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
-  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
-  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
-  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
-  * @param  USARTx USART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @retval Baud Rate
-  */
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
-{
-  uint32_t usartdiv;
-  uint32_t brrresult = 0x0U;
-
-  usartdiv = USARTx->BRR;
-
-  if (usartdiv == 0U)
-  {
-    /* Do not perform a division by 0 */
-  }
-  else if (OverSampling == LL_USART_OVERSAMPLING_8)
-  {
-    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
-    if (usartdiv != 0U)
-    {
-      brrresult = (PeriphClk * 2U) / usartdiv;
-    }
-  }
-  else
-  {
-    if ((usartdiv & 0xFFFFU) != 0U)
-    {
-      brrresult = PeriphClk / usartdiv;
-    }
-  }
-  return (brrresult);
-}
-
-/**
-  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
-  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
-  * @param  USARTx USART Instance
-  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
-{
-  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
-}
-
-/**
-  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
-  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
-  */
-__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
-}
-
-/**
-  * @brief  Set Block Length value in reception
-  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
-  * @param  USARTx USART Instance
-  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
-{
-  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
-}
-
-/**
-  * @brief  Get Block Length value in reception
-  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
-  * @{
-  */
-
-/**
-  * @brief  Enable IrDA mode
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_EnableIrda
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Disable IrDA mode
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_DisableIrda
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Indicate if IrDA mode is enabled
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure IrDA Power Mode (Normal or Low Power)
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
-  * @param  USARTx USART Instance
-  * @param  PowerMode This parameter can be one of the following values:
-  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
-  *         @arg @ref LL_USART_IRDA_POWER_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
-}
-
-/**
-  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
-}
-
-/**
-  * @brief  Set Irda prescaler value, used for dividing the USART clock source
-  *         to achieve the Irda Low Power frequency (8 bits value)
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
-  * @param  USARTx USART Instance
-  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
-}
-
-/**
-  * @brief  Return Irda prescaler value, used for dividing the USART clock source
-  *         to achieve the Irda Low Power frequency (8 bits value)
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
-  * @param  USARTx USART Instance
-  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
-  * @{
-  */
-
-/**
-  * @brief  Enable Smartcard NACK transmission
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
-  * @brief  Disable Smartcard NACK transmission
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
-  * @brief  Indicate if Smartcard NACK transmission is enabled
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Smartcard mode
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Disable Smartcard mode
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Indicate if Smartcard mode is enabled
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
-  *         In transmission mode, it specifies the number of automatic retransmission retries, before
-  *         generating a transmission error (FE bit set).
-  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
-  *         reception error (RXNE and PE bits set)
-  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
-  * @param  USARTx USART Instance
-  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
-}
-
-/**
-  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
-  * @param  USARTx USART Instance
-  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
-}
-
-/**
-  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
-  *         source to provide the SMARTCARD Clock (5 bits value)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
-  * @param  USARTx USART Instance
-  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
-}
-
-/**
-  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
-  *         source to provide the SMARTCARD Clock (5 bits value)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
-  * @param  USARTx USART Instance
-  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
-  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
-  *         (GT[7:0] bits : Guard time value)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
-  * @param  USARTx USART Instance
-  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
-{
-  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
-}
-
-/**
-  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
-  *         (GT[7:0] bits : Guard time value)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
-  * @param  USARTx USART Instance
-  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
-  * @{
-  */
-
-/**
-  * @brief  Enable Single Wire Half-Duplex mode
-  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Disable Single Wire Half-Duplex mode
-  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
-  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
-  * @{
-  */
-
-/**
-  * @brief  Set LIN Break Detection Length
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
-  * @param  USARTx USART Instance
-  * @param  LINBDLength This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
-  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
-}
-
-/**
-  * @brief  Return LIN Break Detection Length
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
-  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
-}
-
-/**
-  * @brief  Enable LIN mode
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Disable LIN mode
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Indicate if LIN mode is enabled
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
-  * @{
-  */
-
-/**
-  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
-  * @param  USARTx USART Instance
-  * @param  Time Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
-}
-
-/**
-  * @brief  Return DEDT (Driver Enable De-Assertion Time)
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
-  * @param  USARTx USART Instance
-  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
-}
-
-/**
-  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
-  * @param  USARTx USART Instance
-  * @param  Time Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
-}
-
-/**
-  * @brief  Return DEAT (Driver Enable Assertion Time)
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
-  * @param  USARTx USART Instance
-  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
-}
-
-/**
-  * @brief  Enable Driver Enable (DE) Mode
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_DEM);
-}
-
-/**
-  * @brief  Disable Driver Enable (DE) Mode
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
-}
-
-/**
-  * @brief  Indicate if Driver Enable (DE) Mode is enabled
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Select Driver Enable Polarity
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
-  * @param  USARTx USART Instance
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DE_POLARITY_HIGH
-  *         @arg @ref LL_USART_DE_POLARITY_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
-}
-
-/**
-  * @brief  Return Driver Enable Polarity
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DE_POLARITY_HIGH
-  *         @arg @ref LL_USART_DE_POLARITY_LOW
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
-  * @{
-  */
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
-  * @note   In UART mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  * @note   Other remaining configurations items related to Asynchronous Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
-  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
-  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
-  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
-  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
-{
-  /* In Asynchronous mode, the following bits must be kept cleared:
-  - LINEN, CLKEN bits in the USART_CR2 register,
-  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
-  * @note   In Synchronous mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also sets the USART in Synchronous mode.
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
-  * @note   Other remaining configurations items related to Synchronous Mode
-  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
-  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
-  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
-  *         CR3          IREN          LL_USART_ConfigSyncMode\n
-  *         CR3          HDSEL         LL_USART_ConfigSyncMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
-{
-  /* In Synchronous mode, the following bits must be kept cleared:
-  - LINEN bit in the USART_CR2 register,
-  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-  /* set the UART/USART in Synchronous mode */
-  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
-  * @note   In LIN mode, the following bits must be kept cleared:
-  *           - STOP and CLKEN bits in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also set the UART/USART in LIN mode.
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
-  * @note   Other remaining configurations items related to LIN Mode
-  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
-  *         CR2          STOP          LL_USART_ConfigLINMode\n
-  *         CR2          LINEN         LL_USART_ConfigLINMode\n
-  *         CR3          IREN          LL_USART_ConfigLINMode\n
-  *         CR3          SCEN          LL_USART_ConfigLINMode\n
-  *         CR3          HDSEL         LL_USART_ConfigLINMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
-{
-  /* In LIN mode, the following bits must be kept cleared:
-  - STOP and CLKEN bits in the USART_CR2 register,
-  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
-  /* Set the UART/USART in LIN mode */
-  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
-  * @note   In Half Duplex mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *         This function also sets the UART/USART in Half Duplex mode.
-  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
-  * @note   Other remaining configurations items related to Half Duplex Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
-  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
-{
-  /* In Half Duplex mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN and IREN bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
-  /* set the UART/USART in Half Duplex mode */
-  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
-  * @note   In Smartcard mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also configures Stop bits to 1.5 bits and
-  *         sets the USART in Smartcard mode (SCEN bit).
-  *         Clock Output is also enabled (CLKEN).
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
-  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
-  * @note   Other remaining configurations items related to Smartcard Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
-  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
-  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
-  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
-  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
-{
-  /* In Smartcard mode, the following bits must be kept cleared:
-  - LINEN bit in the USART_CR2 register,
-  - IREN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
-  /* Configure Stop bits to 1.5 bits */
-  /* Synchronous mode is activated by default */
-  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
-  /* set the UART/USART in Smartcard mode */
-  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
-  * @note   In IRDA mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - STOP and CLKEN bits in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also sets the UART/USART in IRDA mode (IREN bit).
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
-  * @note   Other remaining configurations items related to Irda Mode
-  *         (as Baud Rate, Word length, Power mode, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
-  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
-  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
-  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
-  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
-  *         CR3          IREN          LL_USART_ConfigIrdaMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
-{
-  /* In IRDA mode, the following bits must be kept cleared:
-  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
-  - SCEN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-  /* set the UART/USART in IRDA mode */
-  SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
-  *         (several USARTs connected in a network, one of the USARTs can be the master,
-  *         its TX output connected to the RX inputs of the other slaves USARTs).
-  * @note   In MultiProcessor mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  * @note   Other remaining configurations items related to Multi processor Mode
-  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
-  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
-  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
-  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
-  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
-{
-  /* In Multi Processor mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if the USART Parity Error Flag is set or not
-  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Framing Error Flag is set or not
-  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Noise error detected Flag is set or not
-  * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART OverRun Error Flag is set or not
-  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART IDLE line detected Flag is set or not
-  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
-  * @rmtoll ISR          RXNE          LL_USART_IsActiveFlag_RXNE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Transmission Complete Flag is set or not
-  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
-  * @rmtoll ISR          TXE           LL_USART_IsActiveFlag_TXE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART LIN Break Detection Flag is set or not
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART CTS interrupt Flag is set or not
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART CTS Flag is set or not
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Receiver Time Out Flag is set or not
-  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART End Of Block Flag is set or not
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Busy Flag is set or not
-  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Character Match Flag is set or not
-  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Send Break Flag is set or not
-  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
-  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
-  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
-  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
-}
-
-#if defined(USART_TCBGT_SUPPORT)
-/* Function available only on devices supporting Transmit Complete before Guard Time feature */
-/**
-  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
-  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
-}
-
-#endif /* USART_TCBGT_SUPPORT */
-/**
-  * @brief  Clear Parity Error Flag
-  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
-}
-
-/**
-  * @brief  Clear Framing Error Flag
-  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
-}
-
-/**
-  * @brief  Clear Noise Error detected Flag
-  * @rmtoll ICR          NCF           LL_USART_ClearFlag_NE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_NCF);
-}
-
-/**
-  * @brief  Clear OverRun Error Flag
-  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
-}
-
-/**
-  * @brief  Clear IDLE line detected Flag
-  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
-}
-
-/**
-  * @brief  Clear Transmission Complete Flag
-  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
-}
-
-#if defined(USART_TCBGT_SUPPORT)
-/* Function available only on devices supporting Transmit Complete before Guard Time feature */
-/**
-  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
-  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
-}
-#endif /* USART_TCBGT_SUPPORT */
-
-/**
-  * @brief  Clear LIN Break Detection Flag
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
-}
-
-/**
-  * @brief  Clear CTS Interrupt Flag
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
-}
-
-/**
-  * @brief  Clear Receiver Time Out Flag
-  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
-}
-
-/**
-  * @brief  Clear End Of Block Flag
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
-}
-
-/**
-  * @brief  Clear Character Match Flag
-  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
-}
-
-/**
-  * @brief  Clear Wake Up from stop mode Flag
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/**
-  * @brief  Enable RX Not Empty Interrupt
-  * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
-  * @brief  Enable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/**
-  * @brief  Enable TX Empty Interrupt
-  * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
-  * @brief  Enable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Enable Character Match Interrupt
-  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
-  * @brief  Enable Receiver Timeout Interrupt
-  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
-}
-
-/**
-  * @brief  Enable End Of Block Interrupt
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
-}
-
-/**
-  * @brief  Enable LIN Break Detection Interrupt
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
-  * @brief  Enable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
-  *           0: Interrupt is inhibited
-  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
-  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Enable CTS Interrupt
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Enable Wake Up from Stop Mode Interrupt
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
-}
-
-#if defined(USART_TCBGT_SUPPORT)
-/* Function available only on devices supporting Transmit Complete before Guard Time feature */
-/**
-  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
-}
-#endif /* USART_TCBGT_SUPPORT */
-
-/**
-  * @brief  Disable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/**
-  * @brief  Disable RX Not Empty Interrupt
-  * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
-  * @brief  Disable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/**
-  * @brief  Disable TX Empty Interrupt
-  * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
-  * @brief  Disable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Disable Character Match Interrupt
-  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
-  * @brief  Disable Receiver Timeout Interrupt
-  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
-}
-
-/**
-  * @brief  Disable End Of Block Interrupt
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
-}
-
-/**
-  * @brief  Disable LIN Break Detection Interrupt
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
-  * @brief  Disable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
-  *           0: Interrupt is inhibited
-  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
-  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Disable CTS Interrupt
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Disable Wake Up from Stop Mode Interrupt
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
-}
-
-#if defined(USART_TCBGT_SUPPORT)
-/* Function available only on devices supporting Transmit Complete before Guard Time feature */
-/**
-  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
-}
-#endif /* USART_TCBGT_SUPPORT */
-
-/**
-  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
-  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
-  * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
-  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
-  * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U);
-}
-
-/**
-  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
-  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
-  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
-  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Error Interrupt is enabled or disabled.
-  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
-}
-
-#if defined(USART_TCBGT_SUPPORT)
-/* Function available only on devices supporting Transmit Complete before Guard Time feature */
-/**
-  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
-}
-#endif /* USART_TCBGT_SUPPORT */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_DMA_Management DMA_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Disable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for reception
-  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Disable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for transmission
-  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Disabling on Reception Error
-  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
-  * @brief  Disable DMA Disabling on Reception Error
-  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
-  * @brief  Indicate if DMA Disabling on Reception Error is disabled
-  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the data register address used for DMA transfer
-  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
-  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
-  * @param  USARTx USART Instance
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
-  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
-{
-  uint32_t data_reg_addr;
-
-  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
-  {
-    /* return address of TDR register */
-    data_reg_addr = (uint32_t) &(USARTx->TDR);
-  }
-  else
-  {
-    /* return address of RDR register */
-    data_reg_addr = (uint32_t) &(USARTx->RDR);
-  }
-
-  return data_reg_addr;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
-  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
-{
-  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
-}
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
-  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
-  */
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
-{
-  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
-  * @rmtoll TDR          TDR           LL_USART_TransmitData8
-  * @param  USARTx USART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
-{
-  USARTx->TDR = Value;
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
-  * @rmtoll TDR          TDR           LL_USART_TransmitData9
-  * @param  USARTx USART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
-{
-  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Execution Execution
-  * @{
-  */
-
-/**
-  * @brief  Request an Automatic Baud Rate measurement on next received data frame
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
-}
-
-/**
-  * @brief  Request Break sending
-  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
-}
-
-/**
-  * @brief  Put USART in mute mode and set the RWU flag
-  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
-}
-
-/**
-  * @brief  Request a Receive Data flush
-  * @note   Allows to discard the received data without reading them, and avoid an overrun
-  *         condition.
-  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
-}
-
-/**
-  * @brief  Request a Transmit data flush
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
-void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* USART1 || USART2 || USART4 || USART5 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_LL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usb.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usb.h
deleted file mode 100644
index 6add4e176b..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usb.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_usb.h
-  * @author  MCD Application Team
-  * @brief   Header file of USB Low Layer HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_LL_USB_H
-#define STM32L0xx_LL_USB_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal_def.h"
-
-#if defined (USB)
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup USB_LL
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  USB Mode definition
-  */
-
-
-
-typedef enum
-{
-  USB_DEVICE_MODE  = 0
-} USB_ModeTypeDef;
-
-/**
-  * @brief  USB Initialization Structure definition
-  */
-typedef struct
-{
-  uint32_t dev_endpoints;           /*!< Device Endpoints number.
-                                         This parameter depends on the used USB core.
-                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
-  uint32_t speed;                   /*!< USB Core speed.
-                                         This parameter can be any value of @ref PCD_Speed/HCD_Speed
-                                                                                 (HCD_SPEED_xxx, HCD_SPEED_xxx) */
-
-  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */
-
-  uint32_t phy_itface;              /*!< Select the used PHY interface.
-                                         This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module  */
-
-  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */
-
-  uint32_t low_power_enable;        /*!< Enable or disable Low Power mode                                       */
-
-  uint32_t lpm_enable;              /*!< Enable or disable Battery charging.                                    */
-
-  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */
-} USB_CfgTypeDef;
-
-typedef struct
-{
-  uint8_t   num;             /*!< Endpoint number
-                                  This parameter must be a number between Min_Data = 1 and Max_Data = 15    */
-
-  uint8_t   is_in;           /*!< Endpoint direction
-                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-
-  uint8_t   is_stall;        /*!< Endpoint stall condition
-                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-
-  uint8_t   type;            /*!< Endpoint type
-                                  This parameter can be any value of @ref USB_EP_Type                       */
-
-  uint8_t   data_pid_start;  /*!< Initial data PID
-                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-
-  uint16_t  pmaadress;       /*!< PMA Address
-                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */
-
-  uint16_t  pmaaddr0;        /*!< PMA Address0
-                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */
-
-  uint16_t  pmaaddr1;        /*!< PMA Address1
-                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */
-
-  uint8_t   doublebuffer;    /*!< Double buffer enable
-                                  This parameter can be 0 or 1                                              */
-
-  uint16_t  tx_fifo_num;     /*!< This parameter is not required by USB Device FS peripheral, it is used
-                                  only by USB OTG FS peripheral
-                                  This parameter is added to ensure compatibility across USB peripherals    */
-
-  uint32_t  maxpacket;       /*!< Endpoint Max packet size
-                                  This parameter must be a number between Min_Data = 0 and Max_Data = 64KB  */
-
-  uint8_t   *xfer_buff;      /*!< Pointer to transfer buffer                                                */
-
-  uint32_t  xfer_len;        /*!< Current transfer length                                                   */
-
-  uint32_t  xfer_count;      /*!< Partial transfer length in case of multi packet transfer                  */
-
-  uint32_t  xfer_len_db;      /*!< double buffer transfer length used with bulk double buffer in           */
-
-  uint8_t   xfer_fill_db;     /*!< double buffer Need to Fill new buffer  used with bulk_in                */
-
-} USB_EPTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
-  * @{
-  */
-
-
-/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
-  * @{
-  */
-#define EP_MPS_64                              0U
-#define EP_MPS_32                              1U
-#define EP_MPS_16                              2U
-#define EP_MPS_8                               3U
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
-  * @{
-  */
-#define EP_TYPE_CTRL                           0U
-#define EP_TYPE_ISOC                           1U
-#define EP_TYPE_BULK                           2U
-#define EP_TYPE_INTR                           3U
-#define EP_TYPE_MSK                            3U
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL Device Speed
-  * @{
-  */
-#define USBD_FS_SPEED                          2U
-/**
-  * @}
-  */
-
-#define BTABLE_ADDRESS                         0x000U
-#define PMA_ACCESS                             1U
-
-#define EP_ADDR_MSK                            0x7U
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
-  * @{
-  */
-
-
-HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
-
-#if defined (HAL_PCD_MODULE_ENABLED)
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-#endif /* defined (HAL_PCD_MODULE_ENABLED) */
-
-HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
-uint32_t          USB_ReadInterrupts(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
-
-void              USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
-                               uint16_t wPMABufAddr, uint16_t wNBytes);
-
-void              USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
-                              uint16_t wPMABufAddr, uint16_t wNBytes);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined (USB) */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L0xx_LL_USB_H */
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h
deleted file mode 100644
index b509381c2a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_utils.h
-  * @author  MCD Application Team
-  * @brief   Header file of UTILS LL module.
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL UTILS driver contains a set of generic APIs that can be
-    used by user:
-      (+) Device electronic signature
-      (+) Timing functions
-      (+) PLL configuration functions
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_LL_UTILS_H
-#define __STM32L0xx_LL_UTILS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-/** @defgroup UTILS_LL UTILS
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
-  * @{
-  */
-
-/* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY                  0xFFFFFFFFU
-
-/**
- * @brief Unique device ID register base address
- */
-#define UID_BASE_ADDRESS              UID_BASE
-
-/**
- * @brief Flash size data register base address
- */
-#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
-
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
-  * @{
-  */
-/**
-  * @brief  UTILS PLL structure definition
-  */
-typedef struct
-{
-  uint32_t PLLMul;   /*!< Multiplication factor for PLL VCO input clock.
-                          This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
-
-                          This feature can be modified afterwards using unitary function
-                          @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
-  uint32_t PLLDiv;   /*!< Division factor for PLL VCO output clock.
-                          This parameter can be a value of @ref RCC_LL_EC_PLL_DIV 
-  
-                          This feature can be modified afterwards using unitary function
-                          @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-} LL_UTILS_PLLInitTypeDef;
-
-/**
-  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
-  */
-typedef struct
-{
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAHBPrescaler(). */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAPB1Prescaler(). */
-
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAPB2Prescaler(). */
-
-} LL_UTILS_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
-  * @{
-  */
-
-/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
-  * @{
-  */
-#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
-#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
-  * @{
-  */
-
-/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
-  * @{
-  */
-
-/**
-  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[31:0]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
-}
-
-/**
-  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[63:32]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x04U))));
-}
-
-/**
-  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[95:64]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x14U))));
-}
-
-/**
-  * @brief  Get Flash memory size
-  * @note   This bitfield indicates the size of the device Flash memory expressed in
-  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
-  * @retval FLASH_SIZE[15:0]: Flash memory size
-  */
-__STATIC_INLINE uint32_t LL_GetFlashSize(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_LL_EF_DELAY DELAY
-  * @{
-  */
-
-/**
-  * @brief  This function configures the Cortex-M SysTick source of the time base.
-  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
-  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick 
-  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
-  * @param  Ticks Number of ticks
-  * @retval None
-  */
-__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
-{
-  /* Configure the SysTick to have interrupt in 1ms time base */
-  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
-  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
-}
-
-void        LL_Init1msTick(uint32_t HCLKFrequency);
-void        LL_mDelay(uint32_t Delay);
-
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_EF_SYSTEM SYSTEM
-  * @{
-  */
-
-void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
-ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
-                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
-                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_LL_UTILS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_wwdg.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_wwdg.h
deleted file mode 100644
index f28861c555..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_wwdg.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_wwdg.h
-  * @author  MCD Application Team
-  * @brief   Header file of WWDG LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L0xx_LL_WWDG_H
-#define STM32L0xx_LL_WWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (WWDG)
-
-/** @defgroup WWDG_LL WWDG
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup WWDG_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
-  * @{
-  */
-#define LL_WWDG_CFR_EWI                     WWDG_CFR_EWI
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
-  * @{
-  */
-#define LL_WWDG_PRESCALER_1                 0x00000000u                                               /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define LL_WWDG_PRESCALER_2                 WWDG_CFR_WDGTB_0                                          /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define LL_WWDG_PRESCALER_4                 WWDG_CFR_WDGTB_1                                          /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define LL_WWDG_PRESCALER_8                 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/8 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
-  * @{
-  */
-/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
-  * @{
-  */
-/**
-  * @brief  Write a value in WWDG register
-  * @param  __INSTANCE__ WWDG Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in WWDG register
-  * @param  __INSTANCE__ WWDG Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
-  * @{
-  */
-
-/** @defgroup WWDG_LL_EF_Configuration Configuration
-  * @{
-  */
-/**
-  * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
-  * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
-  *         then it cannot be disabled again except by a reset.
-  *         This bit is set by software and only cleared by hardware after a reset.
-  *         When WDGA = 1, the watchdog can generate a reset.
-  * @rmtoll CR           WDGA          LL_WWDG_Enable
-  * @param  WWDGx WWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
-{
-  SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
-}
-
-/**
-  * @brief  Checks if Window Watchdog is enabled
-  * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
-  * @param  WWDGx WWDG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
-{
-  return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
-  * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
-  *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
-  *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
-  *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
-  * @rmtoll CR           T             LL_WWDG_SetCounter
-  * @param  WWDGx WWDG Instance
-  * @param  Counter 0..0x7F (7 bit counter value)
-  * @retval None
-  */
-__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
-{
-  MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
-}
-
-/**
-  * @brief  Return current Watchdog Counter Value (7 bits counter value)
-  * @rmtoll CR           T             LL_WWDG_GetCounter
-  * @param  WWDGx WWDG Instance
-  * @retval 7 bit Watchdog Counter value
-  */
-__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
-{
-  return (READ_BIT(WWDGx->CR, WWDG_CR_T));
-}
-
-/**
-  * @brief  Set the time base of the prescaler (WDGTB).
-  * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
-  *         is decremented every (4096 x 2expWDGTB) PCLK cycles
-  * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
-  * @param  WWDGx WWDG Instance
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_WWDG_PRESCALER_1
-  *         @arg @ref LL_WWDG_PRESCALER_2
-  *         @arg @ref LL_WWDG_PRESCALER_4
-  *         @arg @ref LL_WWDG_PRESCALER_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
-{
-  MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
-}
-
-/**
-  * @brief  Return current Watchdog Prescaler Value
-  * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
-  * @param  WWDGx WWDG Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_WWDG_PRESCALER_1
-  *         @arg @ref LL_WWDG_PRESCALER_2
-  *         @arg @ref LL_WWDG_PRESCALER_4
-  *         @arg @ref LL_WWDG_PRESCALER_8
-  */
-__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
-{
-  return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
-}
-
-/**
-  * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
-  * @note   This window value defines when write in the WWDG_CR register
-  *         to program Watchdog counter is allowed.
-  *         Watchdog counter value update must occur only when the counter value
-  *         is lower than the Watchdog window register value.
-  *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
-  *         (in the control register) is refreshed before the downcounter has reached
-  *         the watchdog window register value.
-  *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
-  *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
-  * @rmtoll CFR          W             LL_WWDG_SetWindow
-  * @param  WWDGx WWDG Instance
-  * @param  Window 0x00..0x7F (7 bit Window value)
-  * @retval None
-  */
-__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
-{
-  MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
-}
-
-/**
-  * @brief  Return current Watchdog Window Value (7 bits value)
-  * @rmtoll CFR          W             LL_WWDG_GetWindow
-  * @param  WWDGx WWDG Instance
-  * @retval 7 bit Watchdog Window value
-  */
-__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
-{
-  return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-/**
-  * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
-  * @note   This bit is set by hardware when the counter has reached the value 0x40.
-  *         It must be cleared by software by writing 0.
-  *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
-  * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
-  * @param  WWDGx WWDG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
-{
-  return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
-  * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
-  * @param  WWDGx WWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
-{
-  WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_LL_EF_IT_Management IT_Management
-  * @{
-  */
-/**
-  * @brief  Enable the Early Wakeup Interrupt.
-  * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
-  *         This interrupt is only cleared by hardware after a reset
-  * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
-  * @param  WWDGx WWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
-{
-  SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
-}
-
-/**
-  * @brief  Check if Early Wakeup Interrupt is enabled
-  * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
-  * @param  WWDGx WWDG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
-{
-  return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* WWDG */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L0xx_LL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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-<center>
-<h1 id="release-notes-for-stm32l0xx-hal-drivers"><small>Release Notes for</small> <mark>STM32L0xx HAL Drivers</mark></h1>
-<p>Copyright © 2017 STMicroelectronics<br />
-</p>
-<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
-</center>
-</div>
-</div>
-<h1 id="license">License</h1>
-<p>Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
-<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
-<h1 id="purpose">Purpose</h1>
-<p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p>
-<p>The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.</p>
-<p>The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:</p>
-<ul>
-<li>New set of inline functions for direct and atomic register access</li>
-<li>One-shot operations that can be used by the HAL drivers or from application level</li>
-<li>Full independence from HAL and standalone usage (without HAL drivers)</li>
-<li>Full features coverage of all the supported peripherals</li>
-</ul>
-</div>
-<section id="update-history" class="col-sm-12 col-lg-8">
-<h1>Update History</h1>
-<div class="collapse">
-<input type="checkbox" id="collapse-section1_10_5" aria-hidden="true"> <label for="collapse-section1_10_5" aria-hidden="true">V1.10.5 / 16-July-2021</label>
-<div>
-<h2 id="main-changes">Main Changes</h2>
-<h3 id="patch-release-to-fix-known-defects-and-enhancements-implementation.">Patch release to fix known defects and enhancements implementation.</h3>
-<h2 id="contents">Contents</h2>
-<ul>
-<li><strong>HAL</strong> updates
-<ul>
-<li><strong>HAL EXTI</strong> update
-<ul>
-<li>Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each corresponding registers.</li>
-</ul></li>
-<li><strong>HAL GPIO</strong> driver
-<ul>
-<li>Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected.</li>
-</ul></li>
-<li><strong>HAL ADC</strong> update
-<ul>
-<li>Update timeout mechanism to avoid false timeout detection in case of preemption.</li>
-<li>Update LL_ADC driver to prevent unused argument compilation warning.</li>
-</ul></li>
-<li><strong>HAL/LL DAC</strong> update
-<ul>
-<li>Fix compilation error when USE_DAC_REGISTER_CALLBACKS is activated.</li>
-<li>Remove ‘register’ storage class specifier from LL DAC driver.</li>
-<li>Update LL_ADC_DMA_GetRegAddr() API to prevent unused argument compilation warning.</li>
-<li>Update HAL timeout mechanism to avoid false timeout detection in case of preemption.</li>
-</ul></li>
-<li><strong>HAL IWDG</strong> update
-<ul>
-<li>Update HAL_IWDG_Init() API in order to fix HAL_GetTick() timeout vulnerability issue.</li>
-</ul></li>
-<li><strong>HAL/LL RTC</strong> update
-<ul>
-<li>Update __RTC_…(__HANDLE__, …) macros to access registers through (__HANDLE__)-&gt;Instance pointer and avoid “unused variable” warnings.</li>
-<li>Correct month management in IS_LL_RTC_MONTH() macro.</li>
-<li>Update implementations of LL_RTC_BAK_SetRegister() and LL_RTC_BAK_GetRegister() to comply to MISRAC rule 17.4.</li>
-</ul></li>
-<li><strong>HAL TIM</strong> update
-<ul>
-<li>Update HAL_TIMEx_OnePulseN_Start and HAL_TIMEx_OnePulseN_Stop (pooling and IT mode) to take into consideration all OutputChannel parameters.</li>
-<li>Update input capture measurement in DMA mode to avoid zero return values at high frequencies.</li>
-<li>Correct reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse Mode.</li>
-</ul></li>
-<li><strong>HAL LPTIM</strong> update
-<ul>
-<li>Update HAL_LPTIM_Init implementation to configure digital filter for external clock when LPTIM is clocked by an internal clock source.</li>
-</ul></li>
-<li><strong>HAL I2C</strong> update
-<ul>
-<li>Update I2C_IsAcknowledgeFailed() API to avoid I2C in busy state if NACK received after transmitting register address.</li>
-</ul></li>
-<li><strong>LL USART</strong> update
-<ul>
-<li>Remove useless check on maximum BRR value by removing IS_LL_USART_BRR_MAX() macro.</li>
-<li>Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)</li>
-</ul></li>
-<li><strong>HAL SMBUS</strong> update
-<ul>
-<li>Add the support of wake up capability.</li>
-</ul></li>
-<li><strong>HAL/LL SPI</strong> update
-<ul>
-<li>Update to fix MISRA-C 2012 Rule-13.2</li>
-<li>Update LL_SPI_TransmitData8() API to avoid casting the result to 8 bits.</li>
-</ul></li>
-<li><strong>HAL UART</strong> update
-<ul>
-<li>Fix erroneous UART’s handle state in case of error returned after DMA reception start within UART_Start_Receive_DMA().</li>
-<li>Correction on UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent callback.</li>
-<li>Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART).</li>
-</ul></li>
-<li><strong>HAL RNG</strong> update
-<ul>
-<li>Update timeout mechanism to avoid false timeout detection in case of preemption.</li>
-</ul></li>
-<li><strong>HAL USB_FS</strong> update
-<ul>
-<li>HAL PCD: add fix transfer complete for IN Interrupt transaction in single buffer mode.</li>
-<li>Race condition in USB PCD control endpoint receive ISR.</li>
-</ul></li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section1_10_4" aria-hidden="true"> <label for="collapse-section1_10_4" aria-hidden="true">V1.10.4 / 28-October-2020</label>
-<div>
-<h2 id="main-changes-1">Main Changes</h2>
-<ul>
-<li>General updates to fix known defects and enhancements implementation</li>
-<li>Add new <strong>HAL EXTI</strong> driver</li>
-<li>Add new <strong>HAL SMBUS extended</strong> driver to support SMBUS fast Mode Plus.</li>
-<li>Remove <strong>HAL LPTIM Extended</strong> driver to move its contain to HAL LPTIM header file.</li>
-<li>Correct MISRA-C 2012: Rule-10.5, Rule-10.4_a, Rule-2.7 and Rule-21.1</li>
-<li>Remove useless casts</li>
-</ul>
-<h2 id="contents-1">Contents</h2>
-<ul>
-<li><strong>HAL</strong> driver
-<ul>
-<li>Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms:
-<ul>
-<li>Add the following new API’s :
-<ul>
-<li>HAL_GetTickPrio(): Returns a tick priority.</li>
-<li>HAL_SetTickFreq(): Sets new tick frequency.</li>
-<li>HAL_GetTickFreq(): Returns tick frequency.</li>
-</ul></li>
-<li>Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and 1KHz (default).</li>
-</ul></li>
-<li>Update HAL_Init_Tick() API to proporely store the priority when using the non-default time base.</li>
-<li>Add new defines for ARM compiler V6:
-<ul>
-<li>__weak</li>
-<li>__packed</li>
-<li>__NOINLINE</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL ADC</strong> update
-<ul>
-<li>Update HAL_ADC_Stop_DMA() API to check if DMA state is Busy before calling HAL_DMA_Abort() API to avoid DMA internal error.</li>
-<li>Update LL_ADC_REG_Init() API to avoid enabling continuous mode and discontinuous mode simultaneously.</li>
-</ul></li>
-<li><strong>HAL/LL IWDG</strong> update
-<ul>
-<li>Update HAL_IWDG_DEFAULT_TIMEOUT define value to consider LSI value instead of hardcoded value</li>
-</ul></li>
-<li><strong>HAL/LL WWDG</strong> update
-<ul>
-<li>Update WWDG frequency, min and max timeout values</li>
-<li>Update HAL WWDG driver description</li>
-</ul></li>
-<li><strong>HAL CORTEX</strong> update
-<ul>
-<li>Update IS_NVIC_PREEMPTION_PRIORITY macro in order to prevent PreemptPriority assert failure</li>
-</ul></li>
-<li><strong>HAL/LL PWR</strong> update
-<ul>
-<li>Reset bit ULP before entering in low power modes in case ULP=1 and EN_VREFINT = 1.
-<ul>
-<li>Update HAL_PWR_EnterSLEEPMode() and HAL_PWR_EnterSTOPMode() APIs</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL RTC</strong> update
-<ul>
-<li>Optimize HAL implementation Daylight saving feature to subtract or add one hour to the calendar in one single operation without going through the initialization procedure:
-<ul>
-<li>Add HAL_RTC_DST_Add1Hour(), HAL_RTC_DST_Sub1Hour(), HAL_RTC_DST_SetStoreOperation(), HAL_RTC_DST_ClearStoreOperation(), HAL_RTC_DST_ReadStoreOperation() APIs.</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL SPI</strong> update
-<ul>
-<li>Bug fix to support the data packing mode
-<ul>
-<li>Update SPI Transmit/Receive APIs with assert for 8-bit.</li>
-</ul></li>
-<li>Update SPI_DMAReceiveCplt() API to handle efficiently the repeated transfers.
-<ul>
-<li>Disable TX DMA request only in bidirectional receive mode</li>
-</ul></li>
-<li>Update HAL_SPI_Init() API
-<ul>
-<li>To avoid setting the BaudRatePrescaler in case of Slave Motorola Mode</li>
-<li>Use the bit-mask for SPI configuration</li>
-</ul></li>
-<li>Update Transmit/Receive processes in half-duplex mode
-<ul>
-<li>Disable the SPI instance before setting BDIOE bit</li>
-</ul></li>
-<li>Fix wrong timeout management
-<ul>
-<li>Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled</li>
-</ul></li>
-<li>Update to implement Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode.</li>
-</ul></li>
-<li><strong>HAL/LL I2S</strong> update
-<ul>
-<li>Update HAL_I2S_DMAStop() API to be more safe
-<ul>
-<li>Add a check on BSY, TXE and RXNE flags before disabling the I2S</li>
-</ul></li>
-<li>Update HAL_I2S_DMAStop() API to fix multi-call transfer issue(to avoid re-initializing the I2S for the next transfer).
-<ul>
-<li>Add __HAL_I2SEXT_FLUSH_RX_DR() and __HAL_I2S_FLUSH_RX_DR() macros to flush the remaining data inside DR registers.</li>
-<li>Add new ErrorCode define: HAL_I2S_ERROR_BUSY_LINE_RX</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL SMBUS</strong> update
-<ul>
-<li>Add support of Fast Mode Plus to be SMBus rev 3 compliant.
-<ul>
-<li>Add HAL_SMBUSEx_EnableFastModePlus() and HAL_SMBUSEx_DisableFastModePlus() APIs to manage Fm+.</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL TIM</strong> update
-<ul>
-<li>Add new macros to enable and disable the fast mode when using the one pulse mode to output a waveform with a minimum delay
-<ul>
-<li>__HAL_TIM_ENABLE_OCxFAST() and __HAL_TIM_DISABLE_OCxFAST().</li>
-</ul></li>
-<li>Update Encoder interface mode to keep TIM_CCER_CCxNP bits low
-<ul>
-<li>Add TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING definitions to determine encoder input polarity.</li>
-<li>Add IS_TIM_ENCODERINPUT_POLARITY() macro to check the encoder input polarity.</li>
-<li>Update HAL_TIM_Encoder_Init() API</li>
-<li>Replace IS_TIM_IC_POLARITY() macro by IS_TIM_ENCODERINPUT_POLARITY() macro.</li>
-</ul></li>
-<li>Update driver to handle channel state and DMA burst state independently allowing to use multiple DMA request with different channels of same timer
-<ul>
-<li>Introduce DMA burst state management mechanism
-<ul>
-<li>Add a new structure for DMA Burst States definition : HAL_TIM_DMABurstStateTypeDef</li>
-<li>Update __HAL_TIM_RESET_HANDLE_STATE to support DMABurstState</li>
-<li>Add a new API HAL_TIM_DMABurstState() to get the actual state of a DMA burst operation</li>
-</ul></li>
-<li>Add HAL_TIM_DMABurstStateTypeDef enumeration
-<ul>
-<li>Add DMABurstState, the DMA burst operation state, to the TIM_HandleTypeDef structure<br />
-</li>
-</ul></li>
-<li>Implement TIM channel state management mechanism
-<ul>
-<li>Add new private macro
-<ul>
-<li>TIM_CHANNEL_STATE_SET_ALL</li>
-<li>TIM_CHANNEL_STATE_SET</li>
-<li>TIM_CHANNEL_STATE_GET</li>
-</ul></li>
-</ul></li>
-<li>Add new API HAL_TIM_GetActiveChannel()
-<ul>
-<li>Add new API HAL_TIM_GetChannelState() to get actual state of the TIM channel</li>
-<li>Add a new structure for TIM channel States definition : HAL_TIM_ChannelStateTypeDef</li>
-<li>Update __HAL_TIM_RESET_HANDLE_STATE to support ChannelState</li>
-</ul></li>
-<li>Add HAL_TIM_ChannelStateTypeDef enumeration
-<ul>
-<li>Add ChannelState to the TIM_HandleTypeDef structure to manage TIM channel operation state</li>
-</ul></li>
-</ul></li>
-<li>Update HAL_TIMEx_MasterConfigSynchronization() API to avoid functional errors and assert fails when using some TIM instances as input trigger.
-<ul>
-<li>Replace IS_TIM_SYNCHRO_INSTANCE() macro by IS_TIM_MASTER_INSTANCE() macro.</li>
-<li>Add IS_TIM_SLAVE_INSTANCE() macro to check on TIM_SMCR_MSM bit.</li>
-</ul></li>
-<li>Add new API HAL_TIM_DMABurst_MultiWriteStart() allowing to configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral</li>
-<li>Add new API HAL_TIM_DMABurst_MultiReadStart() allowing to configure the DMA Burst to transfer Data from the TIM peripheral to the memory</li>
-<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
-<li>Correct inverted values of LL_TIM_COUNTERMODE_CENTER_DOWN and LL_TIM_COUNTERMODE_CENTER_UP</li>
-<li>Remove extra DMABurst Base Addresses not consistent with reference manual</li>
-<li>Move the TIM input remapping TIM3_TI4_GPIOC9_AF2 and TIM3_TI1_GPIO definition from USB section</li>
-<li>Update LL_TIM_GetCounterMode() implementation to return adequate values to the routine expected ones.</li>
-</ul></li>
-<li><strong>LL LPTIM</strong> update
-<ul>
-<li>Fix typos introduced in some comments</li>
-<li>Remove useless check on LPTIM2 instance introduced in the driver not consistent with the referance manual</li>
-<li>Update HAL_LPTIM_Init implementation to configure digital filter for external clock when LPTIM is clocked by an internal clock source</li>
-<li>Add a polling mechanism to check on LPTIM_FLAG_XXOK flags in different API
-<ul>
-<li>Add LPTIM_WaitForFlag() to wait for flag set.</li>
-<li>Perform new checks on HAL_LPTIM_STATE_TIMEOUT.</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL IRDA</strong> update
-<ul>
-<li>Align HAL IRDA driver with latest updates and enhancements</li>
-<li>Optimize HAL IRDA to avoid using macros as argument of function calls</li>
-<li>Update description of “HAL_IRDA_Transmit_XXX”, “HAL_IRDA_Receive_XXX” APIs with more details about the data size management</li>
-</ul></li>
-<li><strong>HAL/LL SMARTCARD</strong> update
-<ul>
-<li>Update HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_Transmit_DMA() and SMARTCARD_EndTransmit_IT() APIs implementation to fix an issue when No repetition after NACK is received in smartcard T=0</li>
-<li>Optimize HAL SMARTCARD to avoid using macros as argument of function calls</li>
-</ul></li>
-<li><strong>HAL/LL UART</strong> update
-<ul>
-<li>Implementation of ReceptionToIdle reception services enhancement
-<ul>
-<li>Align the HAL UART driver with latest updates and enhancements to support the new enhancement of ReceptionToIdle</li>
-</ul></li>
-<li>Add HAL_UART_RxTypeTypeDef to the UART_HandleTypeDef structure to identify the type of ongoing Reception
-<ul>
-<li>HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RECEPTION_TORTO, HAL_UART_RECEPTION_TOCHARMATCH</li>
-</ul></li>
-<li>Add UART Reception Event Callback registration features
-<ul>
-<li>Add HAL_UART_RegisterRxEventCallback, HAL_UART_UnRegisterRxEventCallback and HAL_UARTEx_RxEventCallback APIs</li>
-<li>Add pUART_RxEventCallbackTypeDef pointer to a UART Rx Event specific callback function</li>
-<li>Add a set of APIs specific to Reception to Idle transfer in different mode
-<ul>
-<li>Add HAL_UARTEx_ReceiveToIdle API to receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.</li>
-</ul></li>
-<li>Add HAL_UARTEx_ReceiveToIdle_IT() API to receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.</li>
-<li>Add HAL_UARTEx_ReceiveToIdle_DMA() API to receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.</li>
-<li>Update impelmentation of HAL_UART_Receive(), HAL_UART_Receive_IT() and HAL_UART_Receive_DMA() to support the new enhancement of ReceptionToIdle
-<ul>
-<li>Add UART_Start_Receive_IT() to start Receive operation in interrupt mode</li>
-<li>Add UART_Start_Receive_DMA() to start Receive operation in DMA mode.</li>
-</ul></li>
-</ul></li>
-<li>Rework BRR register value computation in HAL_UART_Init() for code footprint size optimization</li>
-<li>Update UART polling processes to handle efficiently the Lock mechanism
-<ul>
-<li>Move the process unlock at the top of the HAL_UART_Receive() and HAL_UART_Transmit() API.<br />
-</li>
-</ul></li>
-<li>Add RTO (Receiver Time Out) support to UART HAL flags and IRQ macros
-<ul>
-<li>Add HAL_UART_ERROR_RTO define of Receiver Timeout error to the UART Error Definition section</li>
-</ul></li>
-<li>Add UART_FLAG_RTOF define of Receiver Timeout flag to the UART Flags section</li>
-<li>Add UART_IT_RTO define of Receiver Timeout interruption to the UART interrupts definition</li>
-<li>Add UART_CLEAR_RTOF define of Receiver Timeout clear flag to the UART Clear Flags section</li>
-<li>Implementation of a new macro IS_UART_RECEIVER_TIMEOUT_VALUE to check the receiver timeout value</li>
-<li>Add new APIs HAL_UART_DisableReceiverTimeout(), HAL_UART_DisableReceiverTimeout() to Enable/Disable the UART receiver timeout feature.</li>
-<li>Add new API HAL_UART_ReceiverTimeout_Config() to update on the fly the receiver timeout value in RTOR register</li>
-<li>Update HAL_UART_IRQHandler() to handle UART_ISR_RTOF flag and IT</li>
-</ul></li>
-<li><strong>LL LPUART</strong> update
-<ul>
-<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
-<li>Align LL LPUART driver with latest updates and enhancements</li>
-</ul></li>
-<li><strong>HAL/LL USART</strong> update
-<ul>
-<li>Add RTO (Receiver Time Out) support to USART HAL flags and IRQ macros
-<ul>
-<li>Add HAL_USART_ERROR_RTO define of Receiver Timeout error to the USART Error Definition section</li>
-</ul></li>
-<li>Add USART_FLAG_RTOF define of Receiver Timeout flag to the USART Flags section</li>
-<li>Add USART_CLEAR_RTOF define of Receiver Timeout clear flag to the USART Clear Flags section
-<ul>
-<li>Update HAL_USART_IRQHandler to add support to the Receiver Timeout Interruption</li>
-</ul></li>
-<li>Optimize HAL USART to avoid using macros as argument of function calls</li>
-<li>Update description of “HAL_USART_Transmit_XXX”, “HAL_USART_Receive_XXX” APIs with more details about the data size management</li>
-<li>Fix typos introduced in some APIs descriptions</li>
-<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
-</ul></li>
-<li><strong>LL UTILS</strong> update
-<ul>
-<li>UTILS_SetFlashLatency() API renamed to LL_SetFlashLatency() and set exportable.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section1_10_3" aria-hidden="true"> <label for="collapse-section1_10_3" aria-hidden="true">V1.10.3 / 07-August-2020</label>
-<div>
-<h2 id="main-changes-2">Main Changes</h2>
-<ul>
-<li>General updates to fix known defects and enhancements implementation</li>
-</ul>
-<h2 id="contents-2">Contents</h2>
-<ul>
-<li><strong>HAL Generic</strong> update
-<ul>
-<li>Add new template driver to configure timebase using TIMER :
-<ul>
-<li>stm32l0xx_hal_timebase_tim_template.c</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL GPIO</strong> update
-<ul>
-<li>Update GPIO initialization sequence to avoid unwanted pulse on GPIO Pin’s.</li>
-<li>Update HAL_GPIO_TogglePin() API to improve robustness: allow multi Pin’s toggling</li>
-</ul></li>
-<li><strong>HAL/LL I2C</strong> update
-<ul>
-<li>Update HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with I2C memory IT processes
-<ul>
-<li>Add stop condition generation when NACK occurs.</li>
-</ul></li>
-<li>Update I2C_DMAXferCplt(), I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer).
-<ul>
-<li>Add additional check on hi2c-&gt;hdmtx and hi2c-&gt;hdmarx before resetting DMA Tx/Rx complete callbacks</li>
-</ul></li>
-<li>Update Sequential transfer APIs to adjust xfermode condition.
-<ul>
-<li>Replace hi2c-&gt;XferCount &lt; MAX_NBYTE_SIZE by hi2c-&gt;XferCount &lt;= MAX_NBYTE_SIZE which corresponds to a case without reload</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL USB</strong> driver
-<ul>
-<li>Bug fix: USB_ReadPMA() and USB_WritePMA() by ensuring 16-bits access to USB PMA memory</li>
-<li>Bug fix: correct USB RX count calculation</li>
-<li>Fix USB Bulk transfer double buffer mode</li>
-<li>Remove register keyword from USB defined macros as no more supported by C++ compiler</li>
-<li>Minor rework on USBD_Start() and USBD_Stop() APIs: stopping device will be handled by HAL_PCD_DeInit() API.</li>
-<li>Remove non used API for USB device mode.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V1.10.2 / 22-February-2019</label>
-<div>
-<h2 id="main-changes-3">Main Changes</h2>
-<h3 id="patch-release">Patch release</h3>
-<ul>
-<li>Update of <strong>HAL</strong> driver to include latest corrections and ensure compatibility with legacy code.</li>
-<li>The <strong>V1.10.2</strong> version contains all the updates implemented in <strong>V1.10.1</strong> version. For more details, please refer to the History.</li>
-</ul>
-<h2 id="contents-3">Contents</h2>
-<ul>
-<li><strong>HAL </strong>
-<ul>
-<li>Updated HAL_GetUID() functions to correct address offset.</li>
-</ul></li>
-<li><strong>Legacy</strong>
-<ul>
-<li>Updated stm32_hal_legacy.h file to add missing definitions and ensure compatibility with legacy code.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.10.1 / 08-February-2019</label>
-<div>
-<h2 id="main-changes-4">Main Changes</h2>
-<h3 id="patch-release-1">Patch release</h3>
-<ul>
-<li>Update of <strong>HAL FLASH, RCC and SPI</strong> drivers to include latest corrections</li>
-</ul>
-<h2 id="contents-4">Contents</h2>
-<ul>
-<li><strong>HAL RCC</strong>
-<ul>
-<li>Updated HAL_RCC_OscConfig() to add missing checks and to modify return status.</li>
-</ul></li>
-<li><strong>HAL FLASH</strong>
-<ul>
-<li>Updated HAL_FLASH_Unlock() and HAL_FLASH_OB_Unlock() to handle interrupts disabling.</li>
-<li>Updated FLASH_OB_GetRDP() to return the correct RDP level.</li>
-</ul></li>
-<li><strong>HAL SPI</strong>
-<ul>
-<li>Updated HAL SPI driver to handle STM32L0 erratasheets.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.10.0 / 26-October-2018</label>
-<div>
-<h2 id="main-changes-5">Main Changes</h2>
-<h3 id="major-maintenance-release">Major maintenance release</h3>
-<ul>
-<li>Add support of new <strong>L0 Value Line</strong> devices</li>
-<li>Add support of <strong>HAL callback registration</strong> feature</li>
-<li>Add several enhancements implementation</li>
-<li>Fix known defects to be aligned with others STM32 series</li>
-</ul>
-<h2 id="contents-5">Contents</h2>
-<ul>
-<li><strong>HAL/LL generic</strong>
-<ul>
-<li>Add support of HAL callback registration feature
-<ul>
-<li>The feature disabled by default is available for the following HAL drivers:
-<ul>
-<li>ADC, COMP, DAC, I2C, I2S, IRDA, LPTIM, PCD, RNG, RTC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART and WWDG</li>
-</ul></li>
-<li>The feature may be enabled individually per HAL PPP driver by setting the corresponding definition USE_HAL_PPP_REGISTER_CALLBACKS to 1U in stm32l0xx_hal_conf.h project configuration file (template file stm32l0xx_hal_conf_template.h available from Drivers/STM32L0xx_HAL_Driver/Inc)</li>
-<li>Once enabled, the user application may resort to HAL_PPP_RegisterCallback() to register specific callback function(s) and unregister it(them) with HAL_PPP_UnRegisterCallback().</li>
-<li>Updated HAL/LL Driver compliancy with MISRA C 2004 rules
-<ul>
-<li>MISRA C 2004 rules 10.4, 11.4, 12.4</li>
-</ul></li>
-<li>Updated HAL/LL Driver compliancy with MISRA C 2012 rules
-<ul>
-<li>MISRA C 2012 rules 16.3, 17.4, 21.1</li>
-</ul></li>
-<li>Corrected Doxygen tags in macros description to have generate correct CHM format.</li>
-<li>stm32l0xx_hal_def.h
-<ul>
-<li>Updated file to avoid compiler warnings from __packed definitions.</li>
-<li>Updated UNUSED() macro to fix compilation warning with g++ compiler.</li>
-<li>Replaced include stdio.h by stddef.h.</li>
-<li>Updated __RAM_FUNC define to not impose function type.</li>
-</ul></li>
-<li>stm32l0xx_hal_conf_template.h
-<ul>
-<li>Updated default MSI_VALUE reset value set in SystemCoreClock.</li>
-<li>Added USE_SPI_CRC definition to be aligned with SPI driver.</li>
-</ul></li>
-</ul></li>
-</ul></li>
-<li><strong>HAL</strong>
-<ul>
-<li>Added HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2() for 96-bit UID.</li>
-<li>Modified default HAL_Delay implementation to guarantee minimum delay.</li>
-</ul></li>
-<li><strong>HAL/LL ADC</strong>
-<ul>
-<li>Updated IS_ADC_EOC_SELECTION macro (removed unused literal).</li>
-<li>Updated LL_ADC_Init function to apply correct clock settings in init structure.</li>
-<li>Added missing define for regular external trigger source definitions.</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_ADC_RegisterCallback() and HAL_ADC_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_ADC_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL COMP</strong>
-<ul>
-<li>Updated HAL_COMP_Init, HAL_COMPEx_EnableVREFINT, HAL_COMPEx_DisableVREFINT functions after reintroduction of EN_VREFINT bit in SYSCFG_CFGR3 register.</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_COMP_RegisterCallback() and HAL_COMP_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_COMP_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL CORTEX</strong>
-<ul>
-<li>Modified HAL_MPU_Enable()/HAL_MPU_Disable() functions to allow clear of the whole control register.</li>
-</ul></li>
-<li><strong>HAL CRC</strong>
-<ul>
-<li>Aligned HAL/LL CRC driver with latest updates and enhancements.</li>
-<li>Updated CRC driver to remove compilation warnings.</li>
-</ul></li>
-<li><strong>HAL DAC</strong>
-<ul>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_DAC_RegisterCallback() and HAL_DAC_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_DAC_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL DMA</strong>
-<ul>
-<li>Aligned HAL/LL DMA drivers with latest updates and enhancements .</li>
-</ul></li>
-<li><strong>HAL FIREWALL</strong>
-<ul>
-<li>Ensured Non-Volatile Data Segment length is set to protect code segment.</li>
-</ul></li>
-<li><strong>HAL FLASH</strong>
-<ul>
-<li>Corrected inconsistency between HAL_Flash_Lock and HAL_Flash_Unlock.</li>
-<li>Corrected __HAL_FLASH_BUFFER_CACHE_ENABLE() and __HAL_FLASH_BUFFER_CACHE_DISABLE() for FLASH Buffer cache management.</li>
-<li>Updated HAL_FLASHEx_DATAEEPROM_Unlock() to protect writing of PEKEY1/PEKEY2 against interrupts.</li>
-<li>Updated IS_OBEX macro to fix issue in FLASH_DualBoot Example.</li>
-</ul></li>
-<li><strong>LL GPIO</strong>
-<ul>
-<li>Renamed GPIO_AFRL_AFRLx and GPIO_AFRL_AFRHx bit to GPIO_AFRL_AFSELx.</li>
-</ul></li>
-<li><strong>HAL/LL I2C</strong>
-<ul>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), HAL_I2C_RegisterAddrCallback() and HAL_I2C_UnRegisterAddrCallback() APIs</li>
-<li>Add callback identifiers in HAL_I2C_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-<li>Added missing cast in I2C_GET_DMA_REMAIN_DATA macro definition.</li>
-<li>Updated I2C_WaitOnRXNEFlagUntilTimeout function to check I2C_FLAG_RXNE.</li>
-<li>Updated comments about Device Address parameter (DevAddress) description in I2C functions header.</li>
-<li>Updated IS_I2C_TRANSFER_OPTIONS_REQUEST definition by adding I2C_LAST_FRAME_NO_STOP option, which allows to call transmit or receive at any know time.</li>
-<li>Added restart condition for each call of HAL_I2C_Master_Sequential_xxxx_IT.</li>
-<li>Updated ErrorCode to correct wrong returned value after waiting until BUSY flag is reset.</li>
-<li>Updated error management in I2C_ITSlaveCplt() function.</li>
-<li>Corrected issue in HAL_I2C_Mem_Read_DMA() function.</li>
-<li>Corrected issue in I2C slave when master sends RESTART instead of STOP.</li>
-<li>Fix issue with clearing ADDR flag in I2C_ITSlaveCplt() function.</li>
-<li>Fix MISRAC2012 issue
-<ul>
-<li>Renamed HAL_I2C_Master_Sequential_Transmit_IT(DMA) to HAL_I2C_Master_Seq_Transmit_IT(DMA).</li>
-<li>Renamed HAL_I2C_Master_Sequential_Receive_IT(DMA) to HAL_I2C_Master_Seq_Receive_IT(DMA).</li>
-<li>Renamed HAL_I2C_Slave_Sequential_Transmit_IT(DMA) to HAL_I2C_Slave_Seq_Transmit_IT(DMA).</li>
-<li>Renamed HAL_I2C_Slave_Sequential_Receive_IT(DMA) to HAL_I2C_Slave_Seq_Receive_IT(DMA).</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL I2S</strong>
-<ul>
-<li>Aligned HAL I2S driver with latest updates and enhancements.</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_I2S_RegisterCallback() and HAL_I2S_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_I2S_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL IRDA</strong>
-<ul>
-<li>Aligned HAL IRDA driver with latest updates and enhancements.</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_IRDA_RegisterCallback() and HAL_IRDA_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_IRDA_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL LPTIM</strong>
-<ul>
-<li>Aligned HAL/LL LPTIM driver with updates and enhancements.</li>
-<li>Corrected LL_LPTIM_TRIG_SOURCE_RTCTAMP1 and LL_LPTIM_TRIG_SOURCE_RTCTAMP3 definitions according to supported devices.</li>
-<li>Corrected management of EXTI line during LPTIM wakeup</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_LPTIM_RegisterCallback() and HAL_LPTIM_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_LPTIM_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL PWR</strong>
-<ul>
-<li>Rename LL_PWR_IsActiveFlag_VOSF() to LL_PWR_IsActiveFlag_VOS() to be compliant with all STM32 families.</li>
-<li>Updated HAL_PWR_EnterSLEEPMode() to add NOP to ensure all pending instructions are flushed before entering low power mode.</li>
-</ul></li>
-<li><strong>HAL RNG</strong>
-<ul>
-<li>Aligned HAL RNG driver with latest updates and enhancements.</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_RNG_RegisterCallback(), HAL_RNG_UnRegisterCallback(), HAL_RNG_RegisterReadyDataCallback() and HAL_RNG_UnRegisterReadyDataCallback() APIs</li>
-<li>Add callback identifiers in HAL_RNG_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL RCC</strong>
-<ul>
-<li>Updated HAL_RCC_OscConfig(), which returns HAL_ERROR to apply HSI divider 4 when HSI used as clock source.</li>
-<li>Updated HAL_RCC_OscConfig() to reset HSI on state when RCC_HSI_OUTEN configuration is selected .</li>
-<li>Updated value of RCC_FLAG_FWRST.</li>
-<li>Changed HAL_RCC_DeInit() to HAL_StatusTypeDef.</li>
-<li>Updated HAL_RCC_DeInit() and LL_RCC_DeInit() to also clear interrupts and reset flags.</li>
-<li>Updated HAL_RCC_DeInit() and LL_RCC_DeInit() to add check on PLLRDY before clearing PLLCFGR register.</li>
-<li>Added new LL_RCC_PLL_SetMainSource macro to set the PLL source without enabling any PLL.</li>
-<li>Updated RCC_GetSystemClockFreq() by checking HSIDIVF for divider 4 when HSI is used.</li>
-<li>Updated HAL_RCC_OscConfig() to not return HAL_ERROR if request repeats the current configuration.</li>
-</ul></li>
-<li><strong>HAL/LL RTC</strong>
-<ul>
-<li>Aligned HAL/LL RTC driver with latest updates and enhancements.</li>
-<li>Updated RTC driver to use the bit RTC_CR_BKP instead of RTC_CR_BCK.</li>
-<li>Updated implementation of LL_RTC_DATE_Get() function().</li>
-<li>Corrected __HAL_RTC_TAMPER_GET_IT() macro definition.</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_RTC_RegisterCallback() and HAL_RTC_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_RTC_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL SMARTCARD</strong>
-<ul>
-<li>Aligned HAL SMARTCARD driver with latest updates and enhancements.</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_SMARTCARD_RegisterCallback() and HAL_SMARTCARD_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_SMARTCARD_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL SMBUS</strong>
-<ul>
-<li>Aligned HAL SMBUS driver with latest updates and enhancements.</li>
-<li>Updated HAL_SMBUS_ER_IRQHandler function to manage SMBUS interrupts error handler.</li>
-<li>Updated SMBUS_TransferConfig function (I2C_CR2 register update).</li>
-<li>Updated comments about Device Address parameter (DevAddress) description in SMBUS functions header.</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), HAL_SMBUS_RegisterAddrCallback() and HAL_SMBUS_UnRegisterAddrCallback() APIs</li>
-<li>Add callback identifiers in HAL_SMBUS_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL SPI</strong>
-<ul>
-<li>Aligned HAL/LL SPI driver with latest updates and enhancements.</li>
-<li>Fixed issue in HAL_SPI_Transmit() and HAL_SPI_TransmitReceive() functions.</li>
-<li>Removed define LL_SPI_SR_UDR which available only for I2S feature.</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_SPI_RegisterCallback() and HAL_SPI_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_SPI_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL TIM</strong>
-<ul>
-<li>Aligned L0 HAL/LL TIM driver with latest updates and enhancements.</li>
-<li>Fixed error in LL_TIM_EnableUpdateEvent, LL_TIM_DisableUpdateEvent functions.</li>
-<li>Updated comments in HAL/LL functions to describe how to switch from Center Aligned counter mode to Edge Aligned Down mode.</li>
-<li>Corrected offset definitions (TIM_DMABASE_DMAR, TIM_DMABASE_OR) for burst access.</li>
-<li>Updated HAL_TIM_OnePulse_xxx functions to prevent unused argument(s) compilation warnings.</li>
-<li>Add support of preload control in HAL TIM API.</li>
-<li>Removed usage of STM32L0 device compilation switch in remap constant and HAL_TIMEx_RemapConfig definitions.</li>
-<li>Remove reference to TIMx_SMCR.OCCS related constants/functions, not supported by L0 serie.</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_TIM_RegisterCallback() and HAL_TIM_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_TIM_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL TSC</strong>
-<ul>
-<li>Aligned HAL TSC driver with latest updates and enhancements.</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_TSC_RegisterCallback() and HAL_TSC_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_TSC_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL UART/USART/LPUART</strong>
-<ul>
-<li>Aligned HAL UART/USART/LPUART drivers with latest updates and enhancements.</li>
-<li>Aligned __HAL_UART_GET_IT and __HAL_UART_GET_IT_SOURCE macros with others series.</li>
-<li>Add missing HAL_UARTEx_EnableClockStopMode() function.</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_UART_RegisterCallback() and HAL_UART_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_UART_CallbackIDTypeDef enumerated typedef</li>
-<li>Add HAL_USART_RegisterCallback() and HAL_USART_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_USART_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>LL UTILS</strong>
-<ul>
-<li>Corrected LL_GetUID_Word2 function to fix error in UID flash location.</li>
-<li>Fixed mismatch return type in LL_GetPackageType(void).</li>
-<li>Update UTILS_MAX_FREQUENCY_SCALE3 value.</li>
-</ul></li>
-<li><strong>HAL USB</strong>
-<ul>
-<li>Aligned HAL USB driver with latest updates and enhancements.</li>
-<li>Upgrade to USB Device Library v2.5.1.</li>
-</ul></li>
-<li><strong>HAL WWDG</strong>
-<ul>
-<li>ligned HAL WWDG driver with latest updates and enhancements.</li>
-<li>dd callback registration feature
-<ul>
-<li>Add HAL_WWDG_RegisterCallback() and HAL_WWDG_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_WWDG_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.9.0 / 12-January-2018</label>
-<h2 id="main-changes-6">Main Changes</h2>
-<h3 id="internal-release">Internal release</h3>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.8.2 / 25-August-2017</label>
-<div>
-<h2 id="main-changes-7">Main Changes</h2>
-<h3 id="maintenance-release">Maintenance release</h3>
-<h2 id="contents-6">Contents</h2>
-<ul>
-<li><strong>HAL/LL generic</strong>
-<ul>
-<li>Updated :</li>
-<li>Removed DATE and VERSION fields from header files.</li>
-<li>Updated CHM User Manual for Drivers/STM32L0xx_HAL_Driver.</li>
-</ul></li>
-<li><strong>LL ADC</strong>
-<ul>
-<li>Updated LL ADC driver to exclude __LL_ADC_CALC_TEMPERATURE macro for STM32L011xx devices.</li>
-</ul></li>
-<li><strong>HAL COMP</strong>
-<ul>
-<li>Updated HAL_COMP_Init manage default case as LPTIM1 for COMP1 and LPTIM2 for COMP2.</li>
-</ul></li>
-<li><strong>HAL/LL I2C</strong>
-<ul>
-<li>Replaced POSITION val notion by associated I2C_xxx_pos CMSIS definition.</li>
-<li>Updated LL_I2C_Init() function to add condition to test the value of OwnAddress1 before calling the inline LL function LL_I2C_EnableOwnAddress1().</li>
-<li>Updated implementation of I2C_TransferConfig() function.</li>
-</ul></li>
-<li><strong>HAL PCD</strong>
-<ul>
-<li>Removed the lock/unlock from HAL_PCD_EP_Receive/HAL_PCD_EP_Transmit functions.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.8.1 / 14-April-2017</label>
-<div>
-<h2 id="main-changes-8">Main Changes</h2>
-<h3 id="patch-release-2">Patch release</h3>
-<h2 id="contents-7">Contents</h2>
-<ul>
-<li><strong>HAL LCD</strong>
-<ul>
-<li>Update of stm32l0xx_hal_lcd.h to avoid C++ compilation errors.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.8.0 / 25-November-2016</label>
-<div>
-<h2 id="main-changes-9">Main Changes</h2>
-<h3 id="maintenance-release-1">Maintenance release</h3>
-<h2 id="contents-8">Contents</h2>
-<ul>
-<li><strong>HAL generic</strong>
-<ul>
-<li>Updated HAL Driver compliancy with MISRA C 2004 rules:
-<ul>
-<li>MISRA C 2004 rule 2.2 (source code shall only use /* */ style comments)</li>
-<li>MISRA C 2004 rule 5.2 (tmpreg variable shall not be used inside MACRO)</li>
-<li>MISRA C 2004 rule 10.3 (illegal explicit conversion from type unsigned int to uint16_t *)</li>
-<li>MISRA C 2004 rule 10.4 (value of a complex expression of floating type shall only be cast to a floating type that is narrower or of the same size)</li>
-<li>MISRA C 2004 rule 10.6 (U suffix applied to all constants of unsigned type)</li>
-<li>MISRA C 2004 rule 12.6 (logical operators should not be confused with bitwise operators)</li>
-<li>MISRA C 2004 rule 14.3 (a null statement shall only occur on a line by itself)</li>
-<li>MISRA C 2004 rule 14.8 (statement forming the body of a switch, while, do while or for statement shall be a compound statement)</li>
-<li>MISRA C 2004 rule 14.9 (if {expression} / else construct shall be followed by a compound statement)</li>
-<li>MISRA C 2004 rule 19.10 (in function-like macro definition, each instance of a parameter shall be enclosed in parenthesis)</li>
-<li>MISRA C 2004 rule 19.11 (all macro identifiers in preprocessor directives shall be defined before use)</li>
-<li>MISRA C 2004 rule 19.15 (precautions shall be taken in order to prevent the contents of a header file being included twice)</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL ADC</strong>
-<ul>
-<li>Corrected ADC_SAMPLETIME_xCYCLE_5 naming to be aligned to reference manual.</li>
-<li>Enabled management of low power auto-wait: flags must be cleared by user when fetching ADC conversion data.</li>
-<li>Disabled DMA transfer during ADC calibration.</li>
-</ul></li>
-<li><strong>HAL CRC</strong>
-<ul>
-<li>Updated HAL_CRC_DeInit() function (restored IDR Register to Reset value).</li>
-</ul></li>
-<li><strong>HAL COMP</strong>
-<ul>
-<li>Updated HAL_COMP_Init() function to clear EXTI interrupt mode in case comparator is re-configured in mode trigger none.</li>
-<li>Updated HAL_COMP_IRQHandler() function in window mode, so that both EXTI flags are cleared and HAL_COMP_TriggerCallback() function is called only once.</li>
-<li>Updated HAL COMP init() function: VrefInt startup delay is taken into account, with delay of duration COMP_DELAY_VOLTAGE_SCALER_STAB_US.</li>
-<li>Updated HAL_COMPEx_EnableVREFINT() by adding Wait Time.</li>
-</ul></li>
-<li><strong>HAL DMA</strong>
-<ul>
-<li>Provided new function HAL_DMA_Abort_IT() to abort current DMA transfer under interrupt mode without polling for DMA enable bit.</li>
-</ul></li>
-<li><strong>HAL FLASH </strong>
-<ul>
-<li>Updated HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase_IT(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT() functions.</li>
-<li>Renamed HAL_FLASHRAMFUNC_GetError() sto HAL_FLASHEx_GetError().</li>
-</ul></li>
-<li><strong>HAL GPIO</strong>
-<ul>
-<li>Updated IS_GPIO_PIN() macro to cover full u32 bits.</li>
-<li>Updated HAL_GPIO_DeInit() function to configure GPIO port mode register to input state.</li>
-</ul></li>
-<li><strong>HAL I2C</strong>
-<ul>
-<li>Aligned HAL I2C driver with the new state machine definition.</li>
-<li>Added support of repeated start feature with the following new APIs
-<ul>
-<li>HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Sequential_Receive_IT() and HAL_I2C_Master_Abort_IT(),</li>
-<li>HAL_I2C_Slave_Sequential_Transmit_IT() and HAL_I2C_Slave_Sequential_Receive_IT()</li>
-<li>HAL_I2C_EnableListen_IT() and HAL_I2C_DisableListen_IT()</li>
-<li>New user callbacks HAL_I2C_ListenCpltCallback() and HAL_I2C_AddrCallback()</li>
-</ul></li>
-<li>Reworked DMA end process and I2C error management during DMA transfer.</li>
-<li>Updated WaitOnFlag management (timeout measurement should be always cumulative).</li>
-<li>Optimized HAL_I2C_XX_IRQHandler() functions (read status registers only once).</li>
-<li>Added error management in case of DMA transfer through HAL_DMA_Abort_IT() and DMA XferAbortCallback().</li>
-<li>Updated HAL_I2CEx_EnableFastModePlus() enabling fast mode plus driving capability through CFGR2 register.</li>
-<li>Disabled I2C_OARx_EN bit before any configuration in OAR1 or 2 in HAL_I2C_Init().</li>
-<li>Add I2C_FIRST_AND_NEXT_FRAME for I2C Sequential transfer options: allow to manage a sequence with start condition, address and data to transfer without a final stop condition, an then permit a call to the same master sequential interface several times.</li>
-<li>Updated HAL_I2C_Master_Sequential_Transmit_IT() function (wrong state check).</li>
-<li>Moved I2C_NO_OPTION_FRAME to private section.</li>
-<li>Updated I2C driver documentation concerning I2C address management.</li>
-<li>Updated I2C driver to reset state to LISTEN before calling HAL_I2C_Slave_Sequential_Transmit_IT() function.</li>
-</ul></li>
-<li><strong>HAL I2S</strong>
-<ul>
-<li>Updated LL_I2S_Init() function to use default ou computed values for prescaler.</li>
-</ul></li>
-<li><strong>HAL IWDG</strong>
-<ul>
-<li>Overall driver rework for better implementation
-<ul>
-<li>Removed HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs.</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL PWR</strong>
-<ul>
-<li>Added new HAL_PWREx_GetVoltageRange()function returning Voltage Scaling range, to be aligned with L1 serie.</li>
-</ul></li>
-<li><strong>HAL RCC</strong>
-<ul>
-<li>Aligned HAL RCC driver with others series.</li>
-<li>Renamed RCC_PLLMUL_x to RCC_PLL_MULx and RCC_PLLDIV_x to RCC_PLL_DIVx, to be aligned with L1 serie.</li>
-<li>Updated declaration of HAL_RCC_NMI_IRQHandler() function.</li>
-<li>Updated HAL IRQHandler and callbacks API for CRS management.</li>
-</ul></li>
-<li><strong>HAL SMBUS</strong>
-<ul>
-<li>Aligned driver with others series: fix known defects and added several enhancements implementation.</li>
-<li>Added support of new feature Zone Read/Write.</li>
-</ul></li>
-<li><strong>HAL SPI</strong>
-<ul>
-<li>Added missing __IO in SPI_HandleTypeDef definition.</li>
-</ul></li>
-<li><strong>HAL TIM</strong>
-<ul>
-<li>Corrected TIM22_ETR_GPIO and TIM22_ETR_LSE definitions for STM32L011xx and STM32L021xx devices.</li>
-</ul></li>
-<li><strong>HAL UART-USART / IRDA / SMARTCARD</strong>
-<ul>
-<li>Added missing __IO in UART/USART/IRDA/SMARTCARD_HandleTypeDef definition (for TxXferCount and RxXferCount).</li>
-<li>Modified UART/SMARTCARD configuration sequence order in HAL_UART/SMARTCARD_Init() function, to avoid issue on Transmit line when UART/SMARTCARD_SetConfig() is called before UART/SMARTCARD_AdvFeatureConfig().</li>
-<li>Removed RXNE check in UART/USART/IRDA/SMARTCARD_Receive_IT() function, as RXNE is already cleared by reading RDR, or by writing 1 to RXFRQ in the RQR register.</li>
-<li>Reviewed UART/IRDA/SMARTCARD state machine to avoid cases where UART/IRDA/SMARTCARD state is overwritten by UART/IRDA/SMARTCARD IRQ.</li>
-<li>Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.</li>
-<li>Optimized WaitOnFlag management in HAL_UART/USART/IRDA/SMARTCARD_Transmit() function.</li>
-<li>Optimized all HAL IRQ Handler routines.</li>
-<li>Implemented new APIs for HAL UART/USART/IRDA/SMARTCARD Abort management: HAL_PPP_Abort(), HAL_PPP_AbortTransmit(), HAL_PPP_AbortReceive(), HAL_PPP_Abort_IT(), HAL_PPP_AbortTransmit_IT(), HAL_PPP_AbortReceive_IT().</li>
-<li>Added definition of USART_STOPBITS_0_5 (in addition to 1, 1.5, 2 stop bits).</li>
-<li>Updated USART_GETCLOCKSOURCE() macro definition in order to reflect USART instances availability on L0 devices.</li>
-<li>Updated HAL_UART_Init() that can not be performed on USART4 and USART5 instances for L07x/L08x.</li>
-</ul></li>
-<li><strong>HAL USB</strong>
-<ul>
-<li>Added missing USB_CNTR_SOFM in the setting of wInterrupt_Mask global variable.</li>
-<li>Updated HAL_PCD_ActivateRemoteWakeup() and HAL_PCD_DeActivateRemoteWakeup() functions to check on LPM state before USB resume.</li>
-</ul></li>
-<li><strong>HAL WWDG</strong>
-<ul>
-<li>Overall driver rework for better implementation
-<ul>
-<li>Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs.</li>
-<li>Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter) function and API by removing the “counter” parameter.</li>
-</ul></li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.7.0 / 31-May-2016</label>
-<div>
-<h2 id="main-changes-10">Main Changes</h2>
-<h3 id="maintenance-release-2">Maintenance release</h3>
-<h2 id="contents-9">Contents</h2>
-<ul>
-<li><strong>HAL/LL COMP</strong> update
-<ul>
-<li>Added missing definition for COMP_INPUT_PLUS_IO6 and LL_COMP_INPUT_PLUS_IO6, supported by STM32L0 Category1 (STM32L011xx, STM32L021xx).</li>
-<li>Removed COMP_INVERTINGINPUT_IO3 definition.</li>
-<li>Renamed COMP_INVERTINGINPUT_IO2 to COMP_INPUT_MINUS_DAC1_CH2.</li>
-<li>The EXTI set-up is now managed by HAL_COMP_Init() function, using updated definitions of COMP_TRIGGERMODE_xxx.
-<ul>
-<li>Therefore, the functions HAL_COMP_Start_IT() and HAH_COMP_Stop_IT() have been removed.</li>
-<li>In any mode, the application must use HAL_COMP_Start() and HAL_COMP_Stop().
-<ul>
-<li>For information, this update was already available in V1.6.0.</li>
-</ul></li>
-</ul></li>
-</ul></li>
-<li><strong>HAL RTC</strong> update
-<ul>
-<li>Updated HAL_RTCEx_SetWakeUpTimer_IT() function by adding clear of Wake-Up flag before enabling the interrupt.</li>
-</ul></li>
-<li><strong>HAL LCD</strong> update
-<ul>
-<li>Corrected SYSCFG LCD External Capacitors definitions.</li>
-<li>Added new __HAL_SYSCFG_VLCD_CAPA_CONFIG() macro to configure the VLCD Decoupling capacitance connection.</li>
-<li>Added new __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() macro to return the decoupling of LCD capacitance configured by user.</li>
-<li>Added LCD Voltage output buffer enable macro definitions.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.6.0/ 15-April-2016</label>
-<div>
-<h2 id="main-changes-11">Main Changes</h2>
-<h3 id="maintenance-release-3">Maintenance release</h3>
-<ul>
-<li>First official release supporting the <strong>Low Level</strong> drivers for the <strong>STM32L0xx</strong> family:
-<ul>
-<li>Low Layer drivers APIs provide register level programming: they require deep knowledge of peripherals described in STM32L0xx Reference Manual.</li>
-<li>Low Layer drivers are available for: ADC, COMP, CORTEX, CRC, CRS,DAC, DMA, EXTI, GPIO, I2C, IWDG, LPTIM, LPUART, PWR, RCC, RNG, RTC, SPI, TIM, USART, WWDG peripherals and additional Low Level Bus, System and Utilities APIs.</li>
-<li>Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l0xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l0xx_ll_ppp.h file must be included in user code.</li>
-</ul></li>
-</ul>
-<h2 id="contents-10">Contents</h2>
-<ul>
-<li><strong>Updates of the HAL</strong>
-<ul>
-<li>HAL_SYSCFG_EnableVREFINT() and HAL_SYSCFG_DisableVREFINT() functions and HAL_VREFINT_Cmd macro suppressed since VREFINT is managed by the system.</li>
-<li>Several updates on dedicated HAL as specified in the list below. The major changes concerns HAL_COMP and HAL_UART.</li>
-</ul></li>
-<li><strong>HAL</strong> update
-<ul>
-<li>Change the way the APB AHB prescaler table is defined inside the HAL.</li>
-<li>Change the variable ‘uwTick’ from ‘static’ to ‘global’.</li>
-<li>Compliancy with MISRA C 2004 rule 10.6 (A “U” suffix shall be applied to all constants of unsigned type)</li>
-<li>Compliancy with MISRA C 2004 rule 16.4. (The identifiers used in the declaration and definition of a function shall be identical)</li>
-</ul></li>
-<li><strong>HAL COMP</strong> update
-<ul>
-<li>Major rework on the lock and on the state machine associated to the COMP HAL.</li>
-<li>Optimization of several functions and uniformization of the driver within the whole STM32 family.</li>
-</ul></li>
-<li><strong>HAL CRYPT</strong> update
-<ul>
-<li>Correct the usage of several compilation switches related to STM32L081xx.</li>
-</ul></li>
-<li><strong>HAL DMA</strong> update
-<ul>
-<li>Add the following macro : HAL_DMA_GET_COUNTER.</li>
-</ul></li>
-<li><strong>HAL FLASH</strong> update
-<ul>
-<li>Update the two following macros : __HAL_FLASH_PREFETCH_BUFFER_ENABLE and __HAL_FLASH_PREFETCH_BUFFER_DISABLE.</li>
-</ul></li>
-<li><strong>HAL IRDA</strong> update
-<ul>
-<li>Improve management of the EIE bits for Tx and Rx transfers.</li>
-</ul></li>
-<li><strong>HAL I2C</strong> update
-<ul>
-<li>Allow I2C transmission with data size equal to 0.</li>
-<li>Add new macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE.</li>
-</ul></li>
-<li><strong>HAL LPTIM</strong> update
-<ul>
-<li>Update of the LPTIM driver in order to support the exti line 23.</li>
-</ul></li>
-<li><strong>HAL UART</strong> update
-<ul>
-<li>Improve UART state machine behavior in case of interrupts.</li>
-<li>Update the macros UART_DIV_SAMPLING8 and UART_DIV_SAMPLING16 to correct UART baudrate calculation</li>
-<li>Add an RXDATA flush request inside the UART_Receive_IT function when the RxState is not in reception state.</li>
-</ul></li>
-<li><strong>HAL RCC</strong> update
-<ul>
-<li>Correct the setup of the global variable ‘SystemCoreClock’.</li>
-<li>Update of the CRS interrupt sources.</li>
-<li>Renamed RCC_CRS_SYNCWARM into RCC_CRS_SYNCWARN and renamed RCC_CRS_TRIMOV into RCC_CRS_TRIMOVF.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.5.0/ 8-January-2016</label>
-<div>
-<h2 id="main-changes-12">Main Changes</h2>
-<h3 id="maintenance-release-4">Maintenance release</h3>
-<h2 id="contents-11">Contents</h2>
-<ul>
-<li><strong>Main HAL</strong> updates
-<ul>
-<li>Compliancy with MISRA coding rules (MISRA C 2004 rule 10.5 except for hal_pcd.c file and MISRA C 2004 rule 5.3).</li>
-<li>Several functions inside the HAL have been updated in order to prevent unused argument compilation warnings.</li>
-<li>The startup timeout value for many clocks (as HSE, HSI, LSI, MSI, PLL) have been updated to reach a more accurate value (alignement to the Datasheet).</li>
-<li>The macro __HAL_CORTEX_SYSTICKCLK_CONFIG() has been removed since this service is already covered by the function HAL_SYSTICK_CLKSourceConfig().</li>
-</ul></li>
-<li><strong>HAL</strong> update
-<ul>
-<li>Update the SYSCFG_BOOT_SYSTEMFLASH definition. (SYSCFG_BOOT_SYSTEMFLASH is now equal to SYSCFG_CFGR1_BOOT_MODE_0 instead of SYSCFG_CFGR1_MEM_MODE_0)</li>
-<li>The HSE_STARTUP_TIMEOUT is now equal to 100 instead of 5000.</li>
-</ul></li>
-<li><strong>HAL I2C</strong> update
-<ul>
-<li>Update the HAL_I2C_Slave_Receive function. Store last data received when requested.</li>
-<li>Improvement of the HAL_I2C_MasterReceive function. Error management update. (HAL_ERROR detection versus HAL_TIMEOUT)</li>
-<li>Improvement of the I2C_MasterTransmit_ISR function. Adding of several error checks, unlock of the process when requested.</li>
-<li>Improvement of the I2C_MasterReceive_DMA function. Adding of several error checks and abort DMA when requested.</li>
-</ul></li>
-<li><strong>HAL UART</strong> update
-<ul>
-<li>Update the check of parameters inside the function HAL_LIN_SendBreak().</li>
-<li>Correction of an error present on the V1.4.0 release. On the V1.4.0 release, the clock used inside the function USART_SetConfig(..) was never set.</li>
-</ul></li>
-<li><strong>HAL DMA</strong> update
-<ul>
-<li>Update the DMA_handler structure in order to be MISRA-C 2004 rule 5.3 compliant.</li>
-</ul></li>
-<li><strong>HAL SPI</strong> update
-<ul>
-<li>Update the SPI_handler structure in order to be MISRA-C 2004 rule 5.3 compliant.</li>
-</ul></li>
-<li><strong>HAL RCC</strong> update
-<ul>
-<li>Update support of RCC_MC03 when requested.</li>
-<li>Update support of dynamic HSE prescaler configuration for LCD/RTC peripherals.</li>
-<li>Some updates inside the HAL_RCC_ClockConfig function.</li>
-<li>Some updates inside the HAL_RCC_MCOConfig function. The enabling of the MCO clocks (__MC01_CLK_ENABLE() or __MCO2_CLK_ENABLE()) is done separately depending on the MCO selected.</li>
-<li>The function HAL_RCCEx_GetPeriphCLKFreq() has been reworked.</li>
-<li>The function HAL_RCCEx_PeriphCLKConfig() has been updated. A new error is now detected when trying to update the HSE divider dynamically.</li>
-</ul></li>
-<li><strong>HAL TSC</strong> update
-<ul>
-<li>Several updates inside the HAL_TSC_Start function and HAL_TSC_Init function. Check of input parameters</li>
-</ul></li>
-<li><strong>HAL ADC</strong> update
-<ul>
-<li>The channel 16 (ADC_CHANNEL_16) is not available on all devices.</li>
-</ul></li>
-<li><strong>HAL CORTEX</strong> update
-<ul>
-<li>The macro __HAL_CORTEX_SYSTICKCLK_CONFIG(..) has been removed since this service is already covered by the function HAL_SYSTICK_CLKSourceConfig().</li>
-</ul></li>
-<li><strong>HAL FLASH</strong> update
-<ul>
-<li>The restriction which was present on V1.4.0 and linked to the OPTVERR bit usage on STM32L031xx and STM32L041xx has been removed.
-<ul>
-<li>This is due to the fact that the new STM32L031xx/STM32L041xx devices supports now this feature.</li>
-<li>On the first revision of the STM32L031xx/STM32L031xx devices (RevID = 0x1000 retrieved via HAL_GetREVID()), the OPTVERR bit was not functional. The OPTVERR (Option valid error bit) is set by hardware when, during an Option byte loading, there was a mismatch for one or more configurations.</li>
-</ul></li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.4.0/ 16-October-2015</label>
-<div>
-<h2 id="main-changes-13">Main Changes</h2>
-<h3 id="maintenance-release-5">Maintenance release</h3>
-<ul>
-<li>This release includes the support of the support of <strong>STM32L011xx</strong> and <strong>STM32L021xx</strong> devices</li>
-<li>On STM32L011xx/STM32L021xx, compared to STM32L07xxx/STM32L08xxx, some of the main differences are listed hereafter :
-<ul>
-<li>SRAM size set to 2KB (instead of 20KB)</li>
-<li>Flash size set to 16KB (instead of 192KB)</li>
-<li>GPIO available :A,B,C (instead of A,B,C,D,E,H)</li>
-<li>Timers available : TIM2,TIM21,LPTIM1 (instead of TIM2,TIM3,TIM6,TIM7,TIM21,TIM22,LPTIM1)</li>
-</ul></li>
-</ul>
-<h2 id="contents-12">Contents</h2>
-<ul>
-<li><strong>HAL COMP</strong> update
-<ul>
-<li>Update of the non inverting inputs available on the whole L0 family.</li>
-</ul></li>
-<li><strong>HAL RCC</strong> update
-<ul>
-<li>Usage of a common PLLMulTable[] defined in system_stm32l0xx.c.</li>
-<li>Update in the definition of the different tampers.</li>
-<li>Minor renaming of several macros.</li>
-</ul></li>
-<li><strong>HAL TIMER</strong> update
-<ul>
-<li>Handle lock initialization in all TIM init functions.</li>
-</ul></li>
-<li><strong>HAL LCD</strong> update
-<ul>
-<li>Add support of new MuxSegment field inside the init structure.</li>
-</ul></li>
-<li><strong>HAL DMA</strong> update
-<ul>
-<li>Alignment of the different channels within the L0 family.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.3.0/ 09-September-2015</label>
-<div>
-<h2 id="main-changes-14">Main Changes</h2>
-<h3 id="major-maintenance-release-1">Major maintenance release</h3>
-<ul>
-<li>Major update of the HAL API :
-<ul>
-<li>all MACROs and LITERALs values have been reworked to align all STM32 Families as much as possible</li>
-<li>Important information : A stm32_hal_legacy.h file has been added to the FW package in order to support the old MACROs and LITERAL values used in the previous versions of customer applications</li>
-<li>In HAL MACROs definitions : do { } while(0) have been used in multi statement macros</li>
-</ul></li>
-<li>This release includes the support of the support of <strong>STM32L031xx</strong> and <strong>STM32L041xx</strong> devices On STM32L031xx/STM32L041xx, compared to STM32L07xxx/STM32L08xxx, the main differences are as follow :
-<ul>
-<li>SRAM size set to 8KB (instead of 20KB)</li>
-<li>Flash size set to 32KB (instead of 192KB)</li>
-<li>GPIO available :A,B,C,H (instead of A,B,C,D,E,H)</li>
-<li>Timers available : TIM2,TIM21,TIM22,LPTIM1 (instead of TIM2,TIM3,TIM6,TIM7,TIM21,TIM22,LPTIM1)</li>
-</ul></li>
-</ul>
-<h2 id="contents-13">Contents</h2>
-<ul>
-<li><strong>HAL ADC</strong> update
-<ul>
-<li>ADC assert param needs to be more specific for discontinuous mode, nb of discont conversions</li>
-<li>ADC external trigger definition is not complete Flag EOS should not be reset in HAL_ADC_GetValue()</li>
-<li>ADC poll for event must return timeout instead of error</li>
-<li>ADC state machine update - States with bitfields are now used for a more accurate status</li>
-<li>ADC run in LPrun mode needs SYSCFG buffers enabled</li>
-<li>ADC_CLOCK_SYNC_PCLK_DIVx was not correct</li>
-<li>Remove WaitLoopIndex at the beginning of the function HAL_ADC_Enable</li>
-<li>ADC parameter “ADC_SOFTWARE_START” for compatibility with other STM32 devices</li>
-<li>ADC poll for conversion must return error status in case of ADC-DMA mode</li>
-<li>ADC identical error code returned generates confusion</li>
-<li>Issue observed with ADC start simultaneous commands</li>
-<li>The HAl_Delay() is not required when ADVREGEN is set</li>
-<li>[STM32L07xxx/STM32L08xxx] ADC Interface modification : ADC_Init structure** update</li>
-<li>[STM32L07xxx/STM32L08xxx] ADC Interface modification LowPowerAutoOff is now LowPowerAutoPowerOff</li>
-<li>ADC_Enable does not support the LowPowerAutoOff function</li>
-</ul></li>
-<li><strong>HAL COMP</strong> update
-<ul>
-<li>COMP_TRIGGERMODE_NONE missing in stm32l0xx_hal_comp.h</li>
-<li>COMP wrong implementation of the macro : IS_COMP_WINDOWMODE_INSTANCE</li>
-<li>Misplaced user callback at HAL_COMP_IRQHandler</li>
-<li>EXTI Usage model update - add MACROs __HAL_COMP_COMPx_EXTI_GENERATE_SWIT()</li>
-<li>HAL COMP update in HAL_COMP_Lock() to handle state change and prevent C++ compilation error</li>
-<li>Add the LPTIM Comparator connection</li>
-</ul></li>
-<li><strong>HAL Cortex</strong> update
-<ul>
-<li>[MISRA] bitwise operators ~ and &lt;&lt; (MISRA C 2004 rule 10.5)</li>
-<li>Cortex The function HAL_NVIC_GetPriority(IRQn_Type IRQn) was missing</li>
-<li>Cortex HAL_NVIC_DisableIRQ()/HAL_NVIC_EnableIRQ() Add a check on negative parameter values</li>
-</ul></li>
-<li><strong>HAL CRC</strong> update
-<ul>
-<li>__HAL_CRC_SET_IDR macro improvement</li>
-<li>CRC wrong definition of __HAL_CRC_SET_IDR macro</li>
-<li>Uncorrect CRC functions naming, portability failing, out of topic comments</li>
-<li>Useless Assignment in stm32l0xx_hal_crc.c detected by CodeSonar</li>
-</ul></li>
-<li><strong>HAL DAC</strong> update
-<ul>
-<li>Missing define for DAC Trigger (010: Timer 3 CH3 event)</li>
-<li>Complete DAC update as per HAL_API_Reference</li>
-<li>DAC HAL_DAC_Stop_DMA() code clean up</li>
-<li>HAL_DAC_ConfigChannel: use “hdac-&gt;Instance-&gt;XXX” instead of “DAC-&gt;XXX”</li>
-<li>No reset of previous bits WAVEx / MAMPx before setting values in HAL_DACEx_NoiseWaveGenerate &amp; HAL_DACEx_TriangleWaveGenerate</li>
-</ul></li>
-<li><strong>HAL DMA</strong> update
-<ul>
-<li>The description of __HAL_DMA_GET_IT_SOURCE() was incorrect</li>
-</ul></li>
-<li><strong>HAL FLASH</strong> update
-<ul>
-<li>FLASH Missing macro __HAL_FLASH_GET_LATENCY</li>
-<li>FLASH_WaitForLastOperation issue</li>
-<li>FLASH_Program_IT unlock() issue</li>
-<li>FLASH Crash during HAL_FLASHEx_HalfPageProgram and HAL_FLASHEx_ProgramParallelHalfPage</li>
-<li>FLASH Ramfunc error management</li>
-<li>FLASH IS_OPTIONBYTE(VALUE) is not correct if all options are selected</li>
-<li>HAL_FLASH Otpion Byte “BootConfig” and “BOOTBit1Config”</li>
-<li>FLASH SPRMOD option bit is impacted by FLASH_OB_RDPConfig()</li>
-<li>__HAL_FLASH_GET_FLAG was not functional</li>
-</ul></li>
-<li><strong>HAL GPIO</strong> update
-<ul>
-<li>GPIO The Clear of the External Interrupt is not properly done</li>
-<li>GPIO GPIO_SPEED LITERALS renaming</li>
-<li>GPIO_AF for LPTIM is no more compatible with HAL L0 V1.1</li>
-<li>GPIO AF2 defines for RTC should be aligned for all L0 devices</li>
-<li>GPIO AF defines for LPTIM1 should be the same for all devices.</li>
-<li>GPIO Bug at EXTi register GPIO config in HAL_GPIO_Init() function</li>
-<li>GPIO GPIO_AF5_I2S3ext Update the defined name to be more generic</li>
-<li>GPIO Protect init from impossible AF configuration</li>
-<li>GPIO interrupt mode is not reset</li>
-<li>GPIO Check of the Pin availability according to the GPIO in use</li>
-<li>GPIO rework GPIO_GET_SOURCE</li>
-<li>[STM32L07xxx/STM32L08xxx] GPIO updates (HAL driver and associated validation test prg)</li>
-<li>The GET_GPIO_SOURCE() macro is wrongly implemented</li>
-<li>GPIO alternate functions defined in stm32l0xx_hal_gpio_ex.h not aligned with the spec</li>
-<li>GPIO private Macro __HAL_GET_GPIO_SOURCE must be renamed GET_GPIO_SOURCE</li>
-</ul></li>
-<li><strong>HAL I2C</strong> update
-<ul>
-<li>New SYSCFG Define MACROs to manage FM+ on GPIOs</li>
-<li>NACK is not treated during wait on flag treatment</li>
-</ul></li>
-<li><strong>HAL I2S</strong> update
-<ul>
-<li>I2S HAL_I2S_Transmit() API update to keep the check on busy flag only for the slave</li>
-<li>I2S busy flag issue</li>
-<li>I2S Management of the bit ASTREN for the I2S various modes</li>
-</ul></li>
-<li><strong>HAL LCD</strong> update
-<ul>
-<li>LCD HD field initialization of LCD_FCR register is missing in HAL_LCD_init() function</li>
-</ul></li>
-<li><strong>HAL LPUART </strong> update
-<ul>
-<li>HAL _DIV_LPUART macro possible value saturation</li>
-<li>LPUART CR3 register bit 11 must be kept at reset value.</li>
-</ul></li>
-<li><strong>HAL PWR</strong> update
-<ul>
-<li>Cortex SCR SLEEPONEXIT and SEVONPEND bits management</li>
-<li>PWR PVD feature need falling/rising Event modes</li>
-<li>PWR REGLPF and VOSF polling request</li>
-</ul></li>
-<li><strong>HAL RCC</strong> update
-<ul>
-<li>RCC Bug in HAL_RCC_GetSysClockFreq</li>
-<li>Missing RCC IRQ handler for LSE CSS interrupt</li>
-<li>Missing external macro __HAL_RCC_MCO_CONFIG</li>
-<li>RCC Enable automatically backup domain</li>
-<li>In HAL_RCCEx_PeriphCLKConfig, Reset backup domain only if RTC clock source has been changed</li>
-<li>RCC update LSE_CONFIG to remove transaction LSE On to LSE Bypass</li>
-<li>Issue on MSI setting</li>
-<li>Rework __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass</li>
-<li>Rename HSI48_TIMEOUT_VALUE into RCC_HSI_TIMEOUT_VALUE</li>
-<li>Add defines for RCC_System_Clock_Source_Status</li>
-<li>New HAL RCC macro to configure the SYSCLK clock source</li>
-<li>Wrong calculation of sysclk in case of PLL clocked by HSI_Div4</li>
-<li>RCC_CRSStatusTypeDef must be typed uint32_t</li>
-<li>RCC Implement workaround to cover RCC limitation regarding Peripheral enable delay</li>
-<li>RCC issue in HAL_RCC_OscConfig when RCC_OscInitStruct-&gt;HSEState = RCC_HSE_BYPASS</li>
-<li>RCC Check if need to add interface HAL_RCCEx_GetPeriphCLKFreq</li>
-<li>RCC Add a comment in the How to use section to mention the Peripheral enable delay</li>
-<li>RCC Some values in MSIRangeTable are wrong</li>
-<li>RCC missing macros to easily Enable/Disable HSI48(RC) clock for RNG analog config</li>
-<li>RCC HSERDY must be checked even in HSE_BYPASS mode</li>
-<li>RCC Improve HAL_RCC_OscCOnfig() function</li>
-</ul></li>
-<li><strong>HAL RNG</strong> update
-<ul>
-<li>RNG Type inconsistency of value returned by HAL_RNG_GetRandomNumber() and HAL_RNG_GetRandomNumber_IT() functions.</li>
-<li>RNG Process lock and array of random numbers generation in interrupt mode</li>
-<li>RNG Incorrect DRDY flag resetting</li>
-<li>RNG Incorrect interrupt mode random number generation</li>
-<li>RNG Incorrect TimeOut handling in polling mode random number generation</li>
-</ul></li>
-<li><strong>HAL RTC</strong> update
-<ul>
-<li>RTC macro __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG erroneous definition</li>
-<li>RTC alignment of different HAL_RTC_XXIRQHandler() implementations</li>
-<li>RTC Bits Mask literals to be used in macro definition</li>
-<li>RTC macro __HAL_RTC_TAMPER_GET_IT() issue in param: <strong>INTERRUPT</strong> <span class="citation" data-cites="arg">@arg</span> list</li>
-<li>RTC wrong description of the subsecond item of RTC_TimeTypeDef structure in the header file</li>
-<li>RTC WUTWF is not reliable</li>
-<li>HAL_RTC_GetTime function does not return the actual subfraction</li>
-<li>[STM32L031xx/STM32L041xx] RTC macros renaming for RTC_OUTPUT_REMAP_XX and RTC_TIMESTAMPPIN_XX</li>
-<li>Enhance <span class="citation" data-cites="note">@note</span> describing the use of HAL RTC APIs</li>
-</ul></li>
-<li><strong>HAL SPI</strong> update
-<ul>
-<li>SPI HAL_SPI_TransmitReceive_DMA() Remove DMA Tx Callback in case of RxOnly mode</li>
-<li>SPI HandleTypeDef.ErrorCode must be typed uint32_t</li>
-<li>Warnings with True Studio IDE (tempreg variable not used)</li>
-</ul></li>
-<li><strong>HAL TIM</strong> update
-<ul>
-<li>TIM problem to use ETR as OCrefClear source</li>
-<li>TIM Wrong remaping of the TIM2_ETR</li>
-<li>TIM register BDTR does not exist</li>
-<li>The assert on trigger polarity for TI1F_ED should be removed</li>
-<li>TIM Add macros to ENABLE/DISABLE URS bit in TIM CR1 register</li>
-<li>TIM HAL_TIM_OC_ConfigChannel() / HAL_TIM_PWM_ConfigChannel() Missed/Unused assert param to be added/removed</li>
-<li>TIM Remove HAL_TIM_SlaveConfigSynchronization_DMA() from HAL_TIM API</li>
-<li>TIM Trigger DMA request should be activated when working with a slave mode</li>
-<li>TIM Timer Register Corruption using HAL_TIM_IC_ConfigChannel</li>
-<li>TIM DMA transfer should be aborted when stopping a DMA burst</li>
-<li>Add “TIM_CHANNEL_ALL” as an argument for all Encoder Start/Stop process in the comment section</li>
-<li>HAL_TIM_DMADelayPulseCplt callback missing information</li>
-<li>HAL_TIM_DMACaptureCplt callback missing information</li>
-<li>TIM Trigger DMA request should be activated when working with a slave mode</li>
-<li>TIM Trigger interrupt should be activated when working with a slave mode</li>
-<li>__HAL_TIM_PRESCALER() shall be corrected: use ‘=’ instead of ‘|=’</li>
-</ul></li>
-<li><strong>HAL UART/USART</strong> update
-<ul>
-<li>UART Incorrect UART speed setting on HSI clock</li>
-<li>Wrong Baud Rate calculation in case of OVER8</li>
-<li>UART missing closing bracket in header file</li>
-<li>UART Circular mode when transmitting data not well supported</li>
-<li>UART/LPUART number of stop bits to correct</li>
-<li>USART Incorrect number of stop bits definition</li>
-<li>UART HAL_UART_IRQHandler function not clearing correctly the interrupt flags</li>
-<li>USART Setting of BRR register bit3:0 not inline with RM when OVER8 sampling mode is used</li>
-<li>UART UART_WaitOnFlagUntilTimeout should not assign UART handle state to HAL_UART_STATE_TIMEOUT</li>
-<li>USART Wrong values used as parameter of __HAL_USART_CLEAR_IT() in HAL_USART_IRQHandler()</li>
-<li>USART BRR setting is wrong compared to Baudrate value</li>
-<li>USART HAL_USART_Init() update to reach max frequencies (enable oversampling by 8)</li>
-<li>USART USART_DMAReceiveCplt() Update to set the USART state after performing the test on it</li>
-<li>UART The code associated to several macros need to be completed</li>
-<li>USART UART DMA implementation issue: missed clear the TC bit in the SR</li>
-<li>Wrong USART_IT_CM defined value</li>
-<li>Issue with Lin mode data length</li>
-<li>Wrong description for Interrupt mode IO operation within HAL UART driver</li>
-<li>Change UART_DMATransmitCplt- new implementation to remove WaitOnFlag in ISR</li>
-<li>Change UART TX-IT implementation to remove WaitOnFlag in ISR</li>
-<li>The IS_UART_OVERSAMPLING(SAMPLING) is not called in UART_SetConfig()</li>
-<li>HAL UART enhancement: remove the check on RXNE flag after reading the DR register</li>
-<li>UART/USART/IRDA/SMARTCARD transmit process enhancement to use TXE instead of TC</li>
-<li>Add MACRO to UART HAL to control CTS and RTS from the customer application</li>
-</ul></li>
-<li><strong>HAL PCD</strong> update
-<ul>
-<li>HAL_PCD_EP_Transmit() not functional</li>
-<li>HAL PCD clear flag macros configuration</li>
-<li>Bad IN/OUT EndPoint parameter array size</li>
-<li>HAL PCD miss #define for ep0_mps parameter</li>
-<li>USB HAL PCD missing #define PCD_SPEED_HIGH</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 06-Feb-2015</label>
-<div>
-<h2 id="main-changes-15">Main Changes</h2>
-<h3 id="official-release">Official release</h3>
-<ul>
-<li>This release includes the support of the <strong>STM32L071xx, STM32L072xx, STM32L073xx, STM32L082xx, STM32L083xx</strong> devices</li>
-<li>Fix known defects and add several enhancements implementation</li>
-</ul>
-<h2 id="contents-14">Contents</h2>
-<ul>
-<li><strong>HAL Flash</strong>** update
-<ul>
-<li>Flash : 192K Dual Bank</li>
-</ul></li>
-<li><strong>HAL TIM</strong>** update
-<ul>
-<li>4 new instances : TIM3, TIM7, TIM21, TIM22</li>
-</ul></li>
-<li><strong>HAL USART</strong>** update
-<ul>
-<li>2 new instances : USART 4, USART 5</li>
-</ul></li>
-<li><strong>HAL I2C</strong>** update
-<ul>
-<li>1 new instance I2C3</li>
-</ul></li>
-<li><strong>HAL GPIO</strong>** update
-<ul>
-<li>GPIO Port E</li>
-</ul></li>
-<li><strong>HAL DAC</strong>** update
-<ul>
-<li>A second channel has been introduced</li>
-</ul></li>
-<li><strong>HAL FIREWALL</strong> introduction</li>
-</ul>
-<h2 id="known-limitations">Known Limitations</h2>
-<ul>
-<li>Introduced a FW patch to deactivate the HW SPI-V2.3 correction in case of I2S PCM Short mode usage (Please refer to the STM32L073xx Errata Sheet for more details). In this use case, we come back to the HW SPI 2.2 behavior which is correct for the I2S PCM short mode</li>
-</ul>
-<p><br />
-</p>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 18-June-2014</label>
-<div>
-<h2 id="main-changes-16">Main Changes</h2>
-<h3 id="official-release-1">Official release</h3>
-<h2 id="contents-15">Contents</h2>
-<ul>
-<li><strong>HAL generic</strong>** update
-<ul>
-<li>Fix flag clear procedure: use atomic write operation “=” instead of ready-modify-write operation “|=” or “&amp;=”</li>
-<li>Fix on Timeout management, Timeout value set to 0 passed to API automatically exits the function after checking the flag without any wait</li>
-<li>Common update for the following communication peripherals: SPI, UART, USART and IRDA
-<ul>
-<li>Add DMA circular mode support</li>
-<li>Remove lock from recursive process</li>
-</ul></li>
-<li>Add new macro __HAL_RESET_HANDLE_STATE to reset a given handle state</li>
-<li>When USE_RTOS == 1 (in stm32l0xx_hal_conf.h), the __HAL_LOCK() is not defined instead of being defined empty</li>
-<li>Use "__IO const" instead of "__I", to avoid any compilation issue when __cplusplus switch is defined</li>
-<li>Add new functions for the DBGMCU module
-<ul>
-<li>HAL_EnableDBGSleepMode()</li>
-<li>HAL_DisableDBGSleepMode()</li>
-<li>HAL_EnableDBGStopMode()</li>
-<li>HAL_DisableDBGStopMode()</li>
-<li>HAL_EnableDBGStandbyMode()</li>
-<li>HAL_DisableDBGStandbyMode()</li>
-</ul></li>
-<li>Miscellaneous comments update</li>
-</ul></li>
-<li><strong>HAL FLASH</strong>** update
-<ul>
-<li>Add new functions: HAL_FLASHEx_OB_SelectPCROP() and HAL_FLASHEx_OB_DeSelectPCROP()</li>
-<li>Some functions was renamed and moved to the extension files (stm32l0xx_hal_flash_ex.h/.c)
-<ul>
-<li>Rename FLASH_HalfPageProgram() into HAL_FLASHEx_HalfPageProgram()</li>
-<li>Rename FLASH_EnableRunPowerDown() into HAL_FLASHEx_EnableRunPowerDown()</li>
-<li>Rename FLASH_DisableRunPowerDown() into HAL_FLASHEx_DisableRunPowerDown()</li>
-<li>Rename all HAL_DATA_EEPROMEx_xxx() functions into HAL_FLASHEx_DATAEEPROM_xxx()</li>
-<li>Note: aliases has been added to keep compatibility with previous version</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL GPIO</strong>** update
-<ul>
-<li>Remove IS_GET_GPIO_PIN macro</li>
-<li>Add a new function HAL_GPIO_LockPin()</li>
-<li>Private Macro __HAL_GET_GPIO_SOURCE renamed into GET_GPIO_SOURCE</li>
-</ul></li>
-<li><strong>HAL DMA</strong>** update
-<ul>
-<li>Fix in HAL_DMA_PollForTransfer() to set error code HAL_DMA_ERROR_TE in case of HAL_ERROR status</li>
-</ul></li>
-<li><strong>HAL PWR</strong>** update
-<ul>
-<li>HAL_PWR_PVDConfig(): add clear of the EXTI trigger before new configuration</li>
-<li>Fix in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function</li>
-</ul></li>
-<li><strong>HAL RCC</strong>** update
-<ul>
-<li>Allow to calibrate the HSI when it is used as system clock source</li>
-<li>Fix implementation of IS_RCC_OSCILLATORTYPE() macro</li>
-</ul></li>
-<li><strong>HAL ADC</strong>** update
-<ul>
-<li>Update ADC internal channels mapping: TEMPSENSOR connected to ADC_CHANNEL_18 and VLCD mapped to ADC_CHANNEL_16</li>
-<li>Skip polling for ADRDY flag when Low Power Auto Off mode is enabled</li>
-</ul></li>
-<li><strong>HAL COMP</strong>** update
-<ul>
-<li>Add LPTIMConnection field in the COMP_InitTypeDef structure.</li>
-<li>Add new defines: COMP_LPTIMCONNECTION_DISABLED, COMP_LPTIMCONNECTION_ENABLED</li>
-<li>Add new macro IS_COMP_LPTIMCONNECTION</li>
-</ul></li>
-<li><strong>HAL LPTIM</strong>** update
-<ul>
-<li>Add CKPOL configuration for encoder mode</li>
-</ul></li>
-<li><strong>HAL WWDG</strong>** update
-<ul>
-<li>Miscellaneous minor update on the source code</li>
-</ul></li>
-<li><strong>HAL IWDG</strong>** update
-<ul>
-<li>Miscellaneous minor update on the source code</li>
-</ul></li>
-<li><strong>HAL CRC</strong>** update
-<ul>
-<li>Some functions was renamed and moved to the extension files (stm32l0xx_hal_crc_ex.h/.c)
-<ul>
-<li>HAL_CRC_Input_Data_Reverse() renamed into HAL_CRCEx_Input_Data_Reverse()</li>
-<li>HAL_CRC_Output_Data_Reverse() renamed into HAL_CRCEx_Output_Data_Reverse()</li>
-<li>Note: aliases has been added to keep compatibility with previous version</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL CRYP</strong>** update
-<ul>
-<li>HAL_CRYP_ComputationCpltCallback() renamed into HAL_CRYPEx_ComputationCpltCallback() and moved to the extension files (stm32l0xx_hal_cryp_ex.h/.c)</li>
-<li>Note: alias has been added to keep compatibility with previous version</li>
-</ul></li>
-<li><strong>HAL I2C</strong>** update
-<ul>
-<li>Add management of NACK event in Master transmitter mode and Slave transmitter/receiver modes (only in polling mode), in that case the current transfer is stopped.</li>
-</ul></li>
-<li><strong>HAL SMBUS</strong>** update
-<ul>
-<li>Add a new function: HAL_SMBUS_DisableListen_IT()</li>
-<li>Add aliases for the following functions
-<ul>
-<li>#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT</li>
-<li>#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback</li>
-<li>#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback</li>
-</ul></li>
-<li>Add alias HAL_SMBUS_STATE_SLAVE_LISTEN for the constant HAL_SMBUS_STATE_LISTEN</li>
-</ul></li>
-<li><strong>HAL UART</strong>** update
-<ul>
-<li>HAL_UART_WakeupCallback() renamed into HAL_UART_WakeupCallback() and moved to the extension files (stm32l0xx_hal_cryp_ex.h/.c)</li>
-<li>Add new macros to control CTS and RTS</li>
-<li>Add specific macros to manage the flags cleared only by a software sequence
-<ul>
-<li>__HAL_UART_CLEAR_PEFLAG()</li>
-<li>__HAL_UART_CLEAR_FEFLAG()</li>
-<li>__HAL_UART_CLEAR_NEFLAG()</li>
-<li>__HAL_UART_CLEAR_OREFLAG()</li>
-<li>__HAL_UART_CLEAR_IDLEFLAG()</li>
-</ul></li>
-<li>Add several enhancements without affecting the driver functionalities
-<ul>
-<li>Remove the check on RXNE set after reading the Data in the DR register</li>
-<li>Update the transmit processes to use TXE instead of TC</li>
-<li>Update HAL_UART_Transmit_IT() to enable UART_IT_TXE instead of UART_IT_TC</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL USART</strong>** update
-<ul>
-<li>Add specific macros to manage the flags cleared only by a software sequence
-<ul>
-<li>__HAL_USART_CLEAR_PEFLAG()</li>
-<li>__HAL_USART_CLEAR_FEFLAG()</li>
-<li>__HAL_USART_CLEAR_NEFLAG()</li>
-<li>__HAL_USART_CLEAR_OREFLAG()</li>
-<li>__HAL_USART_CLEAR_IDLEFLAG()</li>
-</ul></li>
-<li>Update HAL_USART_Transmit_IT() to enable USART_IT_TXE instead of USART_IT_TC</li>
-</ul></li>
-<li><strong>HAL IRDA</strong>** update
-<ul>
-<li>Add specific macros to manage the flags cleared only by a software sequence
-<ul>
-<li>__HAL_IRDA_CLEAR_PEFLAG()</li>
-<li>__HAL_ IRDA _CLEAR_FEFLAG()</li>
-<li>__HAL_ IRDA _CLEAR_NEFLAG()</li>
-<li>__HAL_ IRDA _CLEAR_OREFLAG()</li>
-<li>__HAL_ IRDA _CLEAR_IDLEFLAG()</li>
-</ul></li>
-<li>Add several enhancements without affecting the driver functionalities
-<ul>
-<li>Remove the check on RXNE set after reading the Data in the DR register</li>
-<li>Update HAL_IRDA_Transmit_IT() to enable IRDA_IT_TXE instead of IRDA_IT_TC</li>
-</ul></li>
-<li>Add the following APIs used within DMA process
-<ul>
-<li>HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);</li>
-<li>HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);</li>
-<li>HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);</li>
-<li>void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);</li>
-<li>void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL SMARTCARD</strong>** update
-<ul>
-<li>Add specific macros to manage the flags cleared only by a software sequence
-<ul>
-<li>__HAL_SMARTCARD_CLEAR_PEFLAG()</li>
-<li>__HAL_SMARTCARD_CLEAR_FEFLAG()</li>
-<li>__HAL_SMARTCARD_CLEAR_NEFLAG()</li>
-<li>__HAL_SMARTCARD_CLEAR_OREFLAG()</li>
-<li>__HAL_SMARTCARD_CLEAR_IDLEFLAG()</li>
-</ul></li>
-<li>Add several enhancements without affecting the driver functionalities
-<ul>
-<li>Add a new state HAL_SMARTCARD_STATE_BUSY_TX_RX and all processes has been updated accordingly</li>
-<li>Update HAL_SMARTCARD_Transmit_IT() to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL SPI</strong>** update
-<ul>
-<li>Bugs fix
-<ul>
-<li>SPI interface is used in synchronous polling mode: at high clock rates like SPI prescaler 2 and 4, calling HAL_SPI_TransmitReceive() returns with error HAL_TIMEOUT</li>
-<li>HAL_SPI_TransmitReceive_DMA() does not clean up the TX DMA, so any subsequent SPI calls return the DMA error</li>
-<li>HAL_SPI_Transmit_DMA() is failing when data size is equal to 1 byte</li>
-</ul></li>
-<li>Add the following APIs used within the DMA process
-<ul>
-<li>HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);</li>
-<li>HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);</li>
-<li>HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);</li>
-<li>void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);</li>
-<li>void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);</li>
-<li>void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL TSC</strong>** update
-<ul>
-<li>Fix value of the constant TSC_ACQ_MODE_SYNCHRO</li>
-</ul></li>
-<li><strong>HAL PCD</strong>** update
-<ul>
-<li>Add new macro __HAL_USB_EXTI_GENERATE_SWIT()</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 22-April-2014</label>
-<h2 id="main-changes-17">Main Changes</h2>
-<h3 id="first-official-release">First official release</h3>
-</div>
-</section>
-</div>
-<footer class="sticky">
-For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a>
-</footer>
-</body>
-</html>
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c
deleted file mode 100644
index 6e0fd7071a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c
+++ /dev/null
@@ -1,674 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal.c
-  * @author  MCD Application Team
-  * @brief   HAL module driver.
-  *          This is the common part of the HAL initialization
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The common HAL driver contains a set of generic and common APIs that can be
-    used by the PPP peripheral drivers and the user to start using the HAL.
-    [..]
-    The HAL contains two APIs categories:
-         (+) Common HAL APIs
-         (+) Services HAL APIs
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_MODULE_ENABLED
-
-/** @addtogroup HAL
-  * @brief HAL module driver.
-  * @{
-  */
-
-/** @addtogroup HAL_Exported_Constants
-  * @{
-  */
-
-/** @defgroup HAL_Version HAL Version
-  * @{
-  */
-
-/**
- * @brief STM32L0xx HAL Driver version number
- */
-#define __STM32L0xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32L0xx_HAL_VERSION_SUB1   (0x0AU) /*!< [23:16] sub1 version */
-#define __STM32L0xx_HAL_VERSION_SUB2   (0x05U) /*!< [15:8]  sub2 version */
-#define __STM32L0xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
-#define __STM32L0xx_HAL_VERSION         ((__STM32L0xx_HAL_VERSION_MAIN << 24U)\
-                                        |(__STM32L0xx_HAL_VERSION_SUB1 << 16U)\
-                                        |(__STM32L0xx_HAL_VERSION_SUB2 << 8U )\
-                                        |(__STM32L0xx_HAL_VERSION_RC))
-
-#define IDCODE_DEVID_MASK    (0x00000FFFU)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported variables --------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Variables
-  * @{
-  */
-__IO uint32_t uwTick;
-uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
-HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group1
- *  @brief    Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-   [..]  This section provides functions allowing to:
-      (+) Initialize the Flash interface, the NVIC allocation and initial clock
-          configuration. It initializes the source of time base also when timeout
-          is needed and the backup domain when enabled.
-      (+) De-initialize common part of the HAL.
-      (+) Configure the time base source to have 1ms time base with a dedicated
-          Tick interrupt priority.
-        (++) SysTick timer is used by default as source of time base, but user
-             can eventually implement his proper time base source (a general purpose
-             timer for example or other time source), keeping in mind that Time base
-             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
-             handled in milliseconds basis.
-        (++) Time base configuration function (HAL_InitTick ()) is called automatically
-             at the beginning of the program after reset by HAL_Init() or at any time
-             when clock is configured, by HAL_RCC_ClockConfig().
-        (++) Source of time base is configured  to generate interrupts at regular
-             time intervals. Care must be taken if HAL_Delay() is called from a
-             peripheral ISR process, the Tick interrupt line must have higher priority
-            (numerically lower) than the peripheral interrupt. Otherwise the caller
-            ISR process will be blocked.
-       (++) functions affecting time base configurations are declared as __weak
-             to make  override possible  in case of other  implementations in user file.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief This function configures the Flash prefetch, Flash preread and Buffer cache,
-  *        Configures time base source, NVIC and Low level hardware
-  * @note This function is called at the beginning of program after reset and before
-  *       the clock configuration
-  * @note The time base configuration is based on MSI clock when exiting from Reset.
-  *       Once done, time base tick start incrementing.
-  *        In the default implementation,Systick is used as source of time base.
-  *        the tick variable is incremented each 1ms in its ISR.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_Init(void)
-{
-  HAL_StatusTypeDef  status = HAL_OK;
-
-  /* Configure Buffer cache, Flash prefetch,  Flash preread */
-#if (BUFFER_CACHE_DISABLE != 0)
-  __HAL_FLASH_BUFFER_CACHE_DISABLE();
-#endif /* BUFFER_CACHE_DISABLE */
-
-#if (PREREAD_ENABLE != 0)
-  __HAL_FLASH_PREREAD_BUFFER_ENABLE();
-#endif /* PREREAD_ENABLE */
-
-#if (PREFETCH_ENABLE != 0)
-  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
-  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
-  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Init the low level hardware */
-    HAL_MspInit();
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief This function de-initializes common part of the HAL and stops the source
-  *        of time base.
-  * @note This function is optional.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DeInit(void)
-{
-  /* Reset of all peripherals */
-  __HAL_RCC_APB1_FORCE_RESET();
-  __HAL_RCC_APB1_RELEASE_RESET();
-
-  __HAL_RCC_APB2_FORCE_RESET();
-  __HAL_RCC_APB2_RELEASE_RESET();
-
-  __HAL_RCC_AHB_FORCE_RESET();
-  __HAL_RCC_AHB_RELEASE_RESET();
-
-  __HAL_RCC_IOP_FORCE_RESET();
-  __HAL_RCC_IOP_RELEASE_RESET();
-
-  /* De-Init the low level hardware */
-  HAL_MspDeInit();
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the MSP.
-  * @retval None
-  */
-__weak void HAL_MspInit(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes the MSP.
-  * @retval None
-  */
-__weak void HAL_MspDeInit(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief This function configures the source of the time base:
-  *        The time source is configured  to have 1ms time base with a dedicated 
-  *        Tick interrupt priority.
-  * @note This function is called  automatically at the beginning of program after
-  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
-  * @note In the default implementation, SysTick timer is the source of time base. 
-  *       It is used to generate interrupts at regular time intervals. 
-  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process, 
-  *       The SysTick interrupt must have higher priority (numerically lower)
-  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
-  *       The function is declared as __weak  to be overwritten  in case of other
-  *       implementation  in user file.
-  * @param TickPriority Tick interrupt priority.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
-  /* Configure the SysTick to have interrupt in 1ms time basis*/
-  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Configure the SysTick IRQ priority */
-  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
-  {
-    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
-    uwTickPrio = TickPriority;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group2
- *  @brief    HAL Control functions
- *
-@verbatim
- ===============================================================================
-                      ##### HAL Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Provide a tick value in millisecond
-      (+) Provide a blocking delay in millisecond
-      (+) Suspend the time base source interrupt
-      (+) Resume the time base source interrupt
-      (+) Get the HAL API driver version
-      (+) Get the device identifier
-      (+) Get the device revision identifier
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief This function is called to increment a global variable "uwTick"
-  *        used as application time base.
-  * @note In the default implementation, this variable is incremented each 1ms
-  *       in SysTick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
-  *      implementations in user file.
-  * @retval None
-  */
-__weak void HAL_IncTick(void)
-{
-  uwTick += uwTickFreq;
-}
-
-/**
-  * @brief Provides a tick value in millisecond.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval tick value
-  */
-__weak uint32_t HAL_GetTick(void)
-{
-  return uwTick;
-}
-
-/**
-  * @brief This function returns a tick priority.
-  * @retval tick priority
-  */
-uint32_t HAL_GetTickPrio(void)
-{
-  return uwTickPrio;
-}
-
-/**
-  * @brief Set new tick Freq.
-  * @retval Status
-  */
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
-{
-  HAL_StatusTypeDef status  = HAL_OK;
-  HAL_TickFreqTypeDef prevTickFreq;
-
-  assert_param(IS_TICKFREQ(Freq));
-
-  if (uwTickFreq != Freq)
-  {
-    /* Back up uwTickFreq frequency */
-    prevTickFreq = uwTickFreq;
-
-    /* Update uwTickFreq global variable used by HAL_InitTick() */
-    uwTickFreq = Freq;
-
-    /* Apply the new tick Freq  */
-    status = HAL_InitTick(uwTickPrio);
-
-    if (status != HAL_OK)
-    {
-      /* Restore previous tick frequency */
-      uwTickFreq = prevTickFreq;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief Return tick frequency.
-  * @retval tick period in Hz
-  */
-HAL_TickFreqTypeDef HAL_GetTickFreq(void)
-{
-  return uwTickFreq;
-}
-
-/**
-  * @brief This function provides minimum delay (in milliseconds) based
-  *        on variable incremented.
-  * @note In the default implementation , SysTick timer is the source of time base.
-  *       It is used to generate interrupts at regular time intervals where uwTick
-  *       is incremented.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @param Delay specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-__weak void HAL_Delay(uint32_t Delay)
-{
-  uint32_t tickstart = HAL_GetTick();
-  uint32_t wait = Delay;
-
-  /* Add a freq to guarantee minimum wait */
-  if (wait < HAL_MAX_DELAY)
-  {
-    wait += (uint32_t)(uwTickFreq);
-  }
-
-  while((HAL_GetTick() - tickstart) < wait)
-  {
-  }
-}
-
-/**
-  * @brief Suspends the Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
-  *       is called, the SysTick interrupt will be disabled and so Tick increment
-  *       is suspended.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_SuspendTick(void)
-{
-  /* Disable SysTick Interrupt */
-  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
-  * @brief Resumes the Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
-  *       is called, the SysTick interrupt will be enabled and so Tick increment
-  *       is resumed.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_ResumeTick(void)
-{
-  /* Enable SysTick Interrupt */
-  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
-  * @brief Returns the HAL revision
-  * @retval version: 0xXYZR (8bits for each decimal, R for RC)
-  */
-uint32_t HAL_GetHalVersion(void)
-{
-  return __STM32L0xx_HAL_VERSION;
-}
-
-/**
-  * @brief Returns the device revision identifier.
-  * @retval Device revision identifier
-  */
-uint32_t HAL_GetREVID(void)
-{
-  return((DBGMCU->IDCODE) >> 16U);
-}
-
-/**
-  * @brief  Returns the device identifier.
-  * @retval Device identifier
-  */
-uint32_t HAL_GetDEVID(void)
-{
-   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
-}
-
-/**
-  * @brief  Returns the first word of the unique device identifier (UID based on 96 bits)
-  * @retval Device identifier
-  */
-uint32_t HAL_GetUIDw0(void)
-{
-  return(READ_REG(*((uint32_t *)UID_BASE)));
-}
-
-/**
-  * @brief  Returns the second word of the unique device identifier (UID based on 96 bits)
-  * @retval Device identifier
-  */
-uint32_t HAL_GetUIDw1(void)
-{
-  return(READ_REG(*((uint32_t *)(UID_BASE + 0x04U))));
-}
-
-/**
-  * @brief  Returns the third word of the unique device identifier (UID based on 96 bits)
-  * @retval Device identifier
-  */
-uint32_t HAL_GetUIDw2(void)
-{
-  return(READ_REG(*((uint32_t *)(UID_BASE + 0x14U))));
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group2
- *  @brief    HAL Debug functions
- *
-@verbatim
- ===============================================================================
-                      ##### HAL Debug functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Enable/Disable Debug module during SLEEP mode
-      (+) Enable/Disable Debug module during STOP mode
-      (+) Enable/Disable Debug module during STANDBY mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables the Debug Module during SLEEP mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGSleepMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Disables the Debug Module during SLEEP mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGSleepMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Enables the Debug Module during STOP mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Disables the Debug Module during STOP mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Enables the Debug Module during STANDBY mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Disables the Debug Module during STANDBY mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Enable low power mode behavior when the MCU is in Debug mode.
-  * @param Periph: specifies the low power mode.
-  *   This parameter can be any combination of the following values:
-  *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
-  *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode
-  *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
-  * @retval None
-  */
-void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph)
-{
-  /* Check the parameters */
-  assert_param(IS_DBGMCU_PERIPH(Periph));
-
-  DBGMCU->CR |= Periph;
-
-}
-/**
-  * @brief  Disable low power mode behavior when the MCU is in Debug mode.
-  * @param Periph: specifies the low power mode.
-  *   This parameter can be any combination of the following values:
-  *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
-  *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode
-  *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
-  * @retval None
-  */
-void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph)
-{
-  /* Check the parameters */
-  assert_param(IS_DBGMCU_PERIPH(Periph));
-  {
-    DBGMCU->CR &= ~Periph;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group3
- *  @brief    HAL SYSCFG configuration functions
- *
-@verbatim
- ===============================================================================
-                      ##### HAL SYSCFG configuration functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Return the boot mode
-      (+) Select the output of internal reference voltage (VREFINT)
-      (+) Lock/Unlock the SYSCFG VREF register values
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the boot mode as configured by user.
-  * @retval The boot mode as configured by user. The returned value can be one
-  *         of the following values:
-  *              - 0x00000000 : Boot is configured in Main Flash memory
-  *              - 0x00000100 : Boot is configured in System Flash memory
-  *              - 0x00000300 : Boot is configured in Embedded SRAM memory
-  */
-uint32_t  HAL_SYSCFG_GetBootMode(void)
-{
-  return (SYSCFG->CFGR1 & SYSCFG_CFGR1_BOOT_MODE);
-}
-
-/**
-  * @brief Selects the output of internal reference voltage (VREFINT).
-  *        The VREFINT output can be routed to(PB0) or
-  *        (PB1) or both.
-  * @param SYSCFG_Vrefint_OUTPUT: new state of the Vrefint output.
-  *        This parameter can be one of the following values:
-  *     @arg SYSCFG_VREFINT_OUT_NONE
-  *     @arg SYSCFG_VREFINT_OUT_PB0
-  *     @arg SYSCFG_VREFINT_OUT_PB1
-  *     @arg SYSCFG_VREFINT_OUT_PB0_PB1
-  * @retval None
-  */
-void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSCFG_VREFINT_OUT_SELECT(SYSCFG_Vrefint_OUTPUT));
-
-  /* Set the output Vrefint pin */
-  SYSCFG->CFGR3 &= ~(SYSCFG_CFGR3_VREF_OUT);
-  SYSCFG->CFGR3 |= (uint32_t)(SYSCFG_Vrefint_OUTPUT);
-}
-
-/**
-  * @brief  Lock the SYSCFG VREF register values
-  * @retval None
-  */
-void HAL_SYSCFG_Enable_Lock_VREFINT(void)
-{
-    /* Enable the LOCK by setting REF_LOCK bit in the CFGR3 register */
-    SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK);
-}
-
-/**
-  * @brief  Unlock the overall SYSCFG VREF register values
-  * @retval None
-  */
-void HAL_SYSCFG_Disable_Lock_VREFINT(void)
-{
-    /* Disable the LOCK by setting REF_LOCK bit in the CFGR3 register */
-    CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* HAL_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c
deleted file mode 100644
index 753c0bef40..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c
+++ /dev/null
@@ -1,2516 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_adc.c
-  * @author  MCD Application Team
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Analog to Digital Convertor (ADC)
-  *          peripheral:
-  *           + Initialization and de-initialization functions
-  *             ++ Initialization and Configuration of ADC
-  *           + Operation functions
-  *             ++ Start, stop, get result of conversions of regular
-  *                group, using 3 possible modes: polling, interruption or DMA.
-  *           + Control functions
-  *             ++ Channels configuration on regular group
-  *             ++ Analog Watchdog configuration
-  *           + State functions
-  *             ++ ADC state machine management
-  *             ++ Interrupts and flags management
-  *          Other functions (extended functions) are available in file 
-  *          "stm32l0xx_hal_adc_ex.c".
-  *
-  @verbatim
-  ==============================================================================
-                     ##### ADC peripheral features #####
-  ==============================================================================
-  [..]
-  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
-
-  (+) Interrupt generation at the end of regular conversion and in case of 
-      analog watchdog or overrun events.
-  
-  (+) Single and continuous conversion modes.
-  
-  (+) Scan mode for conversion of several channels sequentially.
-  
-  (+) Data alignment with in-built data coherency.
-  
-  (+) Programmable sampling time (common for all channels)
-  
-  (+) External trigger (timer or EXTI) with configurable polarity
-  
-  (+) DMA request generation for transfer of conversions data of regular group.
-
-  (+) ADC calibration
-  
-  (+) ADC conversion of regular group.
-  
-  (+) ADC supply requirements: 1.62 V to 3.6 V.
-  
-  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to 
-      Vdda or to an external voltage reference).
-
-
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-
-     *** Configuration of top level parameters related to ADC ***
-     ============================================================
-     [..]
-
-    (#) Enable the ADC interface
-        (++) As prerequisite, ADC clock must be configured at RCC top level.
-             Caution: On STM32L0, ADC clock frequency max is 16MHz (refer
-                      to device datasheet).
-                      Therefore, ADC clock prescaler must be configured in 
-                      function of ADC clock source frequency to remain below
-                      this maximum frequency.
-
-        (++) Two clock settings are mandatory: 
-             (+++) ADC clock (core clock, also possibly conversion clock).
-
-             (+++) ADC clock (conversions clock).
-                   Two possible clock sources: synchronous clock derived from APB clock
-                   or asynchronous clock derived from ADC dedicated HSI RC oscillator
-                   16MHz.
-                   If asynchronous clock is selected, parameter "HSIState" must be set either:
-                   - to "...HSIState = RCC_HSI_ON" to maintain the HSI16 oscillator
-                     always enabled: can be used to supply the main system clock.
-
-             (+++) Example:
-                   Into HAL_ADC_MspInit() (recommended code location) or with
-                   other device clock parameters configuration:
-               (+++) __HAL_RCC_ADC1_CLK_ENABLE();                 (mandatory)
-
-               HSI enable                                         (optional: if asynchronous clock selected)
-               (+++) RCC_OscInitTypeDef   RCC_OscInitStructure;
-               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-               (+++) RCC_OscInitStructure.HSI16CalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON;
-               (+++) RCC_OscInitStructure.PLL...   (optional if used for system clock)
-               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
-
-        (++) ADC clock source and clock prescaler are configured at ADC level with
-             parameter "ClockPrescaler" using function HAL_ADC_Init().
-
-    (#) ADC pins configuration
-         (++) Enable the clock for the ADC GPIOs
-              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
-         (++) Configure these ADC pins in analog mode
-              using function HAL_GPIO_Init()
-
-    (#) Optionally, in case of usage of ADC with interruptions:
-         (++) Configure the NVIC for ADC
-              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
-         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 
-              into the function of corresponding ADC interruption vector 
-              ADCx_IRQHandler().
-
-    (#) Optionally, in case of usage of DMA:
-         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
-              using function HAL_DMA_Init().
-         (++) Configure the NVIC for DMA
-              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
-         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 
-              into the function of corresponding DMA interruption vector 
-              DMAx_Channelx_IRQHandler().
-
-     *** Configuration of ADC, group regular, channels parameters ***
-     ================================================================
-     [..]
-
-    (#) Configure the ADC parameters (resolution, data alignment, ...)
-        and regular group parameters (conversion trigger, sequencer, ...)
-        using function HAL_ADC_Init().
-
-    (#) Configure the channels for regular group parameters (channel number, 
-        channel rank into sequencer, ..., into regular group)
-        using function HAL_ADC_ConfigChannel().
-
-    (#) Optionally, configure the analog watchdog parameters (channels
-        monitored, thresholds, ...)
-        using function HAL_ADC_AnalogWDGConfig().
-
-
-    (#) When device is in mode low-power (low-power run, low-power sleep or stop mode), 
-        function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init().
-        In case of internal temperature sensor to be measured:
-        function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly
-
-     *** Execution of ADC conversions ***
-     ====================================
-     [..]
-
-    (#) Optionally, perform an automatic ADC calibration to improve the
-        conversion accuracy
-        using function HAL_ADCEx_Calibration_Start().
-
-    (#) ADC driver can be used among three modes: polling, interruption,
-        transfer by DMA.
-
-        (++) ADC conversion by polling:
-          (+++) Activate the ADC peripheral and start conversions
-                using function HAL_ADC_Start()
-          (+++) Wait for ADC conversion completion 
-                using function HAL_ADC_PollForConversion()
-          (+++) Retrieve conversion results 
-                using function HAL_ADC_GetValue()
-          (+++) Stop conversion and disable the ADC peripheral 
-                using function HAL_ADC_Stop()
-
-        (++) ADC conversion by interruption: 
-          (+++) Activate the ADC peripheral and start conversions
-                using function HAL_ADC_Start_IT()
-          (+++) Wait for ADC conversion completion by call of function
-                HAL_ADC_ConvCpltCallback()
-                (this function must be implemented in user program)
-          (+++) Retrieve conversion results 
-                using function HAL_ADC_GetValue()
-          (+++) Stop conversion and disable the ADC peripheral 
-                using function HAL_ADC_Stop_IT()
-
-        (++) ADC conversion with transfer by DMA:
-          (+++) Activate the ADC peripheral and start conversions
-                using function HAL_ADC_Start_DMA()
-          (+++) Wait for ADC conversion completion by call of function
-                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
-                (these functions must be implemented in user program)
-          (+++) Conversion results are automatically transferred by DMA into
-                destination variable address.
-          (+++) Stop conversion and disable the ADC peripheral 
-                using function HAL_ADC_Stop_DMA()
-
-     [..]
-
-    (@) Callback functions must be implemented in user program:
-      (+@) HAL_ADC_ErrorCallback()
-      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
-      (+@) HAL_ADC_ConvCpltCallback()
-      (+@) HAL_ADC_ConvHalfCpltCallback
-
-     *** Deinitialization of ADC ***
-     ============================================================
-     [..]
-
-    (#) Disable the ADC interface
-      (++) ADC clock can be hard reset and disabled at RCC top level.
-        (++) Hard reset of ADC peripherals
-             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
-        (++) ADC clock disable
-             using the equivalent macro/functions as configuration step.
-             (+++) Example:
-                   Into HAL_ADC_MspDeInit() (recommended code location) or with
-                   other device clock parameters configuration:
-               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
-               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
-
-    (#) ADC pins configuration
-         (++) Disable the clock for the ADC GPIOs
-              using macro __HAL_RCC_GPIOx_CLK_DISABLE()
-
-    (#) Optionally, in case of usage of ADC with interruptions:
-         (++) Disable the NVIC for ADC
-              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
-
-    (#) Optionally, in case of usage of DMA:
-         (++) Deinitialize the DMA
-              using function HAL_DMA_Init().
-         (++) Disable the NVIC for DMA
-              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
-
-    [..]
-
-    *** Callback registration ***
-    =============================================
-    [..]
-
-     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
-     allows the user to configure dynamically the driver callbacks.
-     Use Functions HAL_ADC_RegisterCallback()
-     to register an interrupt callback.
-    [..]
-
-     Function HAL_ADC_RegisterCallback() allows to register following callbacks:
-       (+) ConvCpltCallback               : ADC conversion complete callback
-       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
-       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
-       (+) ErrorCallback                  : ADC error callback
-       (+) MspInitCallback                : ADC Msp Init callback
-       (+) MspDeInitCallback              : ADC Msp DeInit callback
-     This function takes as parameters the HAL peripheral handle, the Callback ID
-     and a pointer to the user callback function.
-    [..]
-
-     Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
-     weak function.
-    [..]
-
-     HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
-     and the Callback ID.
-     This function allows to reset following callbacks:
-       (+) ConvCpltCallback               : ADC conversion complete callback
-       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
-       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
-       (+) ErrorCallback                  : ADC error callback
-       (+) MspInitCallback                : ADC Msp Init callback
-       (+) MspDeInitCallback              : ADC Msp DeInit callback
-     [..]
-
-     By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
-     all callbacks are set to the corresponding weak functions:
-     examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
-     Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
-     these callbacks are null (not registered beforehand).
-    [..]
-
-     If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
-     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-     [..]
-
-     Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
-     Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
-     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-    [..]
-
-     Then, the user first registers the MspInit/MspDeInit user callbacks
-     using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
-     or HAL_ADC_Init() function.
-     [..]
-
-     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
-     not defined, the callback registration feature is not available and all callbacks
-     are set to the corresponding weak functions.
-  
-    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup ADC ADC
-  * @brief ADC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Constants ADC Private Constants
-  * @{
-  */
-
-/* Delay for ADC stabilization time.                                          */
-/* Maximum delay is 1us (refer to device datasheet, parameter tSTART). */
-/* Unit: us */
-#define ADC_STAB_DELAY_US       (1U)
-
-/* Delay for temperature sensor stabilization time. */
-/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
-/* Unit: us */
-#define ADC_TEMPSENSOR_DELAY_US (10U) 
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup ADC_Private_Functions ADC Private Functions
-  * @{
-  */
-static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
-static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
-static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc);
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-static void ADC_DMAError(DMA_HandleTypeDef *hdma);
-static void ADC_DelayMicroSecond(uint32_t microSecond);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Functions ADC Exported Functions
-  * @{
-  */
-
-/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief    ADC Initialization and Configuration functions
-  *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the ADC. 
-      (+) De-initialize the ADC.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the ADC peripheral and regular group according to  
-  *         parameters specified in structure "ADC_InitTypeDef".
-  * @note   As prerequisite, ADC clock must be configured at RCC top level
-  *         depending on possible clock sources: APB clock of HSI clock.
-  *         See commented example code below that can be copied and uncommented
-  *         into HAL_ADC_MspInit().
-  * @note   Possibility to update parameters on the fly:
-  *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
-  *         coming from ADC state reset. Following calls to this function can
-  *         be used to reconfigure some parameters of ADC_InitTypeDef  
-  *         structure on the fly, without modifying MSP configuration. If ADC  
-  *         MSP has to be modified again, HAL_ADC_DeInit() must be called
-  *         before HAL_ADC_Init().
-  *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
-  *         "ADC_InitTypeDef".
-  * @note   This function configures the ADC within 2 scopes: scope of entire 
-  *         ADC and scope of regular group. For parameters details, see comments 
-  *         of structure "ADC_InitTypeDef".
-  * @note   When device is in mode low-power (low-power run, low-power sleep or stop mode), 
-  *         function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init() 
-  *         (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first).
-  *         In case of internal temperature sensor to be measured:
-  *         function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly.  
-  * @param  hadc ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
-{
- 
-  /* Check ADC handle */
-  if(hadc == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
-  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
-  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
-  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
-  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-  assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
-  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
-  assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerFrequencyMode));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
-  assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTime));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
-
-  /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured    */
-  /* at RCC top level depending on both possible clock sources:               */
-  /* APB clock or HSI clock.                                                  */
-  /* Refer to header of this file for more details on clock enabling procedure*/
-  
-  /* Actions performed only if ADC is coming from state reset:                */
-  /* - Initialization of ADC MSP                                              */
-  /* - ADC voltage regulator enable                                           */
-  if(hadc->State == HAL_ADC_STATE_RESET)
-  {
-    /* Initialize ADC error code */
-    ADC_CLEAR_ERRORCODE(hadc);
-    
-    /* Allocate lock resource and initialize it */
-    hadc->Lock = HAL_UNLOCKED;
-    
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-    /* Init the ADC Callback settings */
-    hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
-    hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
-    hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
-    hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
-    
-    if (hadc->MspInitCallback == NULL)
-    {
-      hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
-    }
-    
-    /* Init the low level hardware */
-    hadc->MspInitCallback(hadc);
-#else
-    /* Init the low level hardware */
-    HAL_ADC_MspInit(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-  }
-  
-  /* Configuration of ADC parameters if previous preliminary actions are      */ 
-  /* correctly completed.                                                     */
-  /* and if there is no conversion on going on regular group (ADC can be      */
-  /* enabled anyway, in case of call of this function to update a parameter   */
-  /* on the fly).                                                             */
-  if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) ||
-     (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET)  )
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-        
-    /* Process unlocked */
-    __HAL_UNLOCK(hadc);
-    return HAL_ERROR;
-  }
-
-  /* Set ADC state */
-  ADC_STATE_CLR_SET(hadc->State,
-                    HAL_ADC_STATE_REG_BUSY,
-                    HAL_ADC_STATE_BUSY_INTERNAL);
-
-  /* Parameters update conditioned to ADC state:                            */
-  /* Parameters that can be updated only when ADC is disabled:              */
-  /*  - ADC clock mode                                                      */
-  /*  - ADC clock prescaler                                                 */
-  /*  - ADC Resolution                                                      */
-  if (ADC_IS_ENABLE(hadc) == RESET)
-  {
-    /* Some parameters of this register are not reset, since they are set   */
-    /* by other functions and must be kept in case of usage of this         */
-    /* function on the fly (update of a parameter of ADC_InitTypeDef        */
-    /* without needing to reconfigure all other ADC groups/channels         */
-    /* parameters):                                                         */
-    /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
-    /*     (set into HAL_ADC_ConfigChannel() )                              */
-   
-    /* Configuration of ADC clock: clock source PCLK or asynchronous with 
-    selectable prescaler */
-    __HAL_ADC_CLOCK_PRESCALER(hadc);
-    
-    /* Configuration of ADC:                                                */
-    /*  - Resolution                                                        */
-    hadc->Instance->CFGR1 &= ~( ADC_CFGR1_RES);
-    hadc->Instance->CFGR1 |= hadc->Init.Resolution;    
-  }
-  
-  /* Set the Low Frequency mode */
-  ADC->CCR &= (uint32_t)~ADC_CCR_LFMEN;
-  ADC->CCR |=__HAL_ADC_CCR_LOWFREQUENCY(hadc->Init.LowPowerFrequencyMode);  
-   
-  /* Enable voltage regulator (if disabled at this step) */
-  if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
-  {
-    /* Set ADVREGEN bit */
-    hadc->Instance->CR |= ADC_CR_ADVREGEN;
-  }
-  
-  /* Configuration of ADC:                                                    */
-  /*  - Resolution                                                            */
-  /*  - Data alignment                                                        */
-  /*  - Scan direction                                                        */
-  /*  - External trigger to start conversion                                  */
-  /*  - External trigger polarity                                             */
-  /*  - Continuous conversion mode                                            */
-  /*  - DMA continuous request                                                */
-  /*  - Overrun                                                               */
-  /*  - AutoDelay feature                                                     */
-  /*  - Discontinuous mode                                                    */
-  hadc->Instance->CFGR1 &= ~(ADC_CFGR1_ALIGN   |
-                             ADC_CFGR1_SCANDIR |
-                             ADC_CFGR1_EXTSEL  |
-                             ADC_CFGR1_EXTEN   |
-                             ADC_CFGR1_CONT    |
-                             ADC_CFGR1_DMACFG  |
-                             ADC_CFGR1_OVRMOD  |
-                             ADC_CFGR1_AUTDLY  |
-                             ADC_CFGR1_AUTOFF  |
-                             ADC_CFGR1_DISCEN   );
-  
-  hadc->Instance->CFGR1 |= (hadc->Init.DataAlign                             |
-                            ADC_SCANDIR(hadc->Init.ScanConvMode)             |
-                            ADC_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)    |
-                            ADC_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) |
-                            hadc->Init.Overrun                               |
-                            __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) |
-                            __HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoPowerOff));
-  
-  /* Enable external trigger if trigger selection is different of software  */
-  /* start.                                                                 */
-  /* Note: This configuration keeps the hardware feature of parameter       */
-  /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
-  /*       software start.                                                  */
-  if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
-  {
-    hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv |
-                             hadc->Init.ExternalTrigConvEdge;
-  }
-  
-  /* Enable discontinuous mode only if continuous mode is disabled */
-  if (hadc->Init.DiscontinuousConvMode == ENABLE)
-  {
-    if (hadc->Init.ContinuousConvMode == DISABLE)
-    {
-      /* Enable the selected ADC group regular discontinuous mode */
-      hadc->Instance->CFGR1 |= (ADC_CFGR1_DISCEN);
-    }
-    else
-    {
-      /* ADC regular group discontinuous was intended to be enabled,        */
-      /* but ADC regular group modes continuous and sequencer discontinuous */
-      /* cannot be enabled simultaneously.                                  */
-      
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-      
-      /* Set ADC error code to ADC peripheral internal error */
-      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-    }
-  }
-  
-  if (hadc->Init.OversamplingMode == ENABLE)
-  {
-    assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversample.Ratio));
-    assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversample.RightBitShift));
-    assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversample.TriggeredMode));
-
-    /* Configuration of Oversampler:                                          */
-    /*  - Oversampling Ratio                                                  */
-    /*  - Right bit shift                                                     */
-    /*  - Triggered mode                                                      */
-    
-    hadc->Instance->CFGR2 &= ~( ADC_CFGR2_OVSR |
-                                ADC_CFGR2_OVSS |
-                                ADC_CFGR2_TOVS );
-    
-    hadc->Instance->CFGR2 |= ( hadc->Init.Oversample.Ratio         |
-                               hadc->Init.Oversample.RightBitShift             |
-                               hadc->Init.Oversample.TriggeredMode );
-    
-    /* Enable OverSampling mode */
-     hadc->Instance->CFGR2 |= ADC_CFGR2_OVSE;
-  }
-  else
-  {
-    if(HAL_IS_BIT_SET(hadc->Instance->CFGR2, ADC_CFGR2_OVSE))
-    {
-      /* Disable OverSampling mode if needed */
-      hadc->Instance->CFGR2 &= ~ADC_CFGR2_OVSE;
-    }
-  }    
-  
-  /* Clear the old sampling time */
-  hadc->Instance->SMPR &= (uint32_t)(~ADC_SMPR_SMPR);
-  
-  /* Set the new sample time */
-  hadc->Instance->SMPR |= hadc->Init.SamplingTime;
-  
-  /* Clear ADC error code */
-  ADC_CLEAR_ERRORCODE(hadc);
-
-  /* Set the ADC state */
-  ADC_STATE_CLR_SET(hadc->State,
-                    HAL_ADC_STATE_BUSY_INTERNAL,
-                    HAL_ADC_STATE_READY);
-
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deinitialize the ADC peripheral registers to their default reset
-  *         values, with deinitialization of the ADC MSP.
-  * @note   For devices with several ADCs: reset of ADC common registers is done 
-  *         only if all ADCs sharing the same common group are disabled.
-  *         If this is not the case, reset of these common parameters reset is  
-  *         bypassed without error reporting: it can be the intended behavior in
-  *         case of reset of a single ADC while the other ADCs sharing the same 
-  *         common group is still running.
-  * @param  hadc ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check ADC handle */
-  if(hadc == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Set ADC state */
-  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
-  
-  /* Stop potential conversion on going, on regular group */
-  tmp_hal_status = ADC_ConversionStop(hadc);
-  
-  /* Disable ADC peripheral if conversions are effectively stopped */
-  if (tmp_hal_status == HAL_OK)
-  {   
-    /* Disable the ADC peripheral */
-    tmp_hal_status = ADC_Disable(hadc);
-    
-    /* Check if ADC is effectively disabled */
-    if (tmp_hal_status != HAL_ERROR)
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_READY;
-    }
-  }
-  
-  
-  /* Configuration of ADC parameters if previous preliminary actions are      */ 
-  /* correctly completed.                                                     */
-  if (tmp_hal_status != HAL_ERROR)
-  {
-    
-    /* ========== Reset ADC registers ========== */
-    /* Reset register IER */
-    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | ADC_IT_EOCAL | ADC_IT_EOS |  \
-                                ADC_IT_EOC | ADC_IT_RDY | ADC_IT_EOSMP ));
-  
-        
-    /* Reset register ISR */
-    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_EOCAL | ADC_FLAG_OVR | ADC_FLAG_EOS |  \
-                                ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY));
-  
-    
-    /* Reset register CR */
-    /* Disable voltage regulator */
-    /* Note: Regulator disable useful for power saving */
-    /* Reset ADVREGEN bit */
-    hadc->Instance->CR &= ~ADC_CR_ADVREGEN;
-    
-    /* Bits ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode "read-set": no direct reset applicable */
-    /* No action */
-    
-    /* Reset register CFGR1 */
-    hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH  | ADC_CFGR1_AWDEN  | ADC_CFGR1_AWDSGL | \
-                               ADC_CFGR1_DISCEN | ADC_CFGR1_AUTOFF | ADC_CFGR1_AUTDLY | \
-                               ADC_CFGR1_CONT   | ADC_CFGR1_OVRMOD | ADC_CFGR1_EXTEN  | \
-                               ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN  | ADC_CFGR1_RES    | \
-                               ADC_CFGR1_SCANDIR| ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN);
-  
-    /* Reset register CFGR2 */
-    hadc->Instance->CFGR2 &= ~(ADC_CFGR2_TOVS  | ADC_CFGR2_OVSS  | ADC_CFGR2_OVSR | \
-                               ADC_CFGR2_OVSE  | ADC_CFGR2_CKMODE );
-  
-    
-    /* Reset register SMPR */
-    hadc->Instance->SMPR &= ~(ADC_SMPR_SMPR);
-    
-    /* Reset register TR */
-    hadc->Instance->TR &= ~(ADC_TR_LT | ADC_TR_HT);
-    
-    /* Reset register CALFACT */
-    hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT);
-  
-  
-  
-  
-    
-    /* Reset register DR */
-    /* bits in access mode read only, no direct reset applicable*/
-  
-    /* Reset register CALFACT */
-    hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT);
-  
-    /* ========== Hard reset ADC peripheral ========== */
-    /* Performs a global reset of the entire ADC peripheral: ADC state is     */
-    /* forced to a similar state after device power-on.                       */
-    /* If needed, copy-paste and uncomment the following reset code into      */
-    /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)":              */
-    /*                                                                        */
-    /*  __HAL_RCC_ADC1_FORCE_RESET()                                                  */
-    /*  __HAL_RCC_ADC1_RELEASE_RESET()                                                */
-  
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-    if (hadc->MspDeInitCallback == NULL)
-    {
-      hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
-    }
-    
-    /* DeInit the low level hardware */
-    hadc->MspDeInitCallback(hadc);
-#else
-    /* DeInit the low level hardware */
-    HAL_ADC_MspDeInit(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-    
-    /* Set ADC error code to none */
-    ADC_CLEAR_ERRORCODE(hadc);
-    
-    /* Set ADC state */
-    hadc->State = HAL_ADC_STATE_RESET;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Initialize the ADC MSP.
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_MspInit must be implemented in the user file.
-   */ 
-}
-
-/**
-  * @brief  DeInitialize the ADC MSP.
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_MspDeInit must be implemented in the user file.
-   */ 
-}
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User ADC Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
-  *                the configuration information for the specified ADC.
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
-  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion complete callback ID
-  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
-  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
-  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
-  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
-  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
-  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  
-  if ((hadc->State & HAL_ADC_STATE_READY) != 0)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
-        hadc->ConvCpltCallback = pCallback;
-        break;
-      
-      case HAL_ADC_CONVERSION_HALF_CB_ID :
-        hadc->ConvHalfCpltCallback = pCallback;
-        break;
-      
-      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
-        hadc->LevelOutOfWindowCallback = pCallback;
-        break;
-      
-      case HAL_ADC_ERROR_CB_ID :
-        hadc->ErrorCallback = pCallback;
-        break;
-      
-      case HAL_ADC_MSPINIT_CB_ID :
-        hadc->MspInitCallback = pCallback;
-        break;
-      
-      case HAL_ADC_MSPDEINIT_CB_ID :
-        hadc->MspDeInitCallback = pCallback;
-        break;
-      
-      default :
-        /* Update the error code */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_ADC_STATE_RESET == hadc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ADC_MSPINIT_CB_ID :
-        hadc->MspInitCallback = pCallback;
-        break;
-      
-      case HAL_ADC_MSPDEINIT_CB_ID :
-        hadc->MspDeInitCallback = pCallback;
-        break;
-      
-      default :
-        /* Update the error code */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-      
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-    
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Unregister a ADC Callback
-  *         ADC callback is redirected to the weak predefined callback
-  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
-  *                the configuration information for the specified ADC.
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
-  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion complete callback ID
-  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
-  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
-  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
-  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
-  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
-  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  if ((hadc->State & HAL_ADC_STATE_READY) != 0)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
-        hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
-        break;
-      
-      case HAL_ADC_CONVERSION_HALF_CB_ID :
-        hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
-        break;
-      
-      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
-        hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
-        break;
-      
-      case HAL_ADC_ERROR_CB_ID :
-        hadc->ErrorCallback = HAL_ADC_ErrorCallback;
-        break;
-      
-      case HAL_ADC_MSPINIT_CB_ID :
-        hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
-        break;
-      
-      case HAL_ADC_MSPDEINIT_CB_ID :
-        hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
-        break;
-      
-      default :
-        /* Update the error code */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-        
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_ADC_STATE_RESET == hadc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ADC_MSPINIT_CB_ID :
-        hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
-        break;
-        
-      case HAL_ADC_MSPDEINIT_CB_ID :
-        hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-        
-      default :
-        /* Update the error code */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-        
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-    
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-  
-  return status;
-}
-
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
- *  @brief    ADC IO operation functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start conversion of regular group.
-      (+) Stop conversion of regular group.
-      (+) Poll for conversion complete on regular group.
-      (+) Poll for conversion event.
-      (+) Get result of regular channel conversion.
-      (+) Start conversion of regular group and enable interruptions.
-      (+) Stop conversion of regular group and disable interruptions.
-      (+) Handle ADC interrupt request
-      (+) Start conversion of regular group and enable DMA transfer.
-      (+) Stop conversion of regular group and disable ADC DMA transfer.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enable ADC, start conversion of regular group.
-  * @note   Interruptions enabled in this function: None.
-  * @param  hadc ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Perform ADC enable and conversion start if no conversion is on going */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
-  {
-    /* Process locked */
-    __HAL_LOCK(hadc);
-    
-    /* Enable the ADC peripheral */
-    /* If low power mode AutoPowerOff is enabled, power-on/off phases are     */
-    /* performed automatically by hardware.                                   */
-    if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
-    {
-      tmp_hal_status = ADC_Enable(hadc);
-    }
-    
-    /* Start conversion if ADC is effectively enabled */
-    if (tmp_hal_status == HAL_OK)
-    {
-      /* Set ADC state                                                        */
-      /* - Clear state bitfield related to regular group conversion results   */
-      /* - Set state bitfield related to regular operation                    */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
-                        HAL_ADC_STATE_REG_BUSY);
-      
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-      
-      /* Process unlocked */
-      /* Unlock before starting ADC conversions: in case of potential         */
-      /* interruption, to let the process to ADC IRQ Handler.                 */
-      __HAL_UNLOCK(hadc);
-      
-      /* Clear regular group conversion flag and overrun flag */
-      /* (To ensure of no unknown state from potential previous ADC           */
-      /* operations)                                                          */
-      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-      
-      /* Enable conversion of regular group.                                  */
-      /* If software start has been selected, conversion starts immediately.  */
-      /* If external trigger has been selected, conversion will start at next */
-      /* trigger event.                                                       */
-      hadc->Instance->CR |= ADC_CR_ADSTART;
-    }
-  }
-  else
-  {
-    tmp_hal_status = HAL_BUSY;
-  }
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Stop ADC conversion of regular group (and injected channels in 
-  *         case of auto_injection mode), disable ADC peripheral.
-  * @param  hadc ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* 1. Stop potential conversion on going, on ADC group regular */
-  tmp_hal_status = ADC_ConversionStop(hadc);
-  
-  /* Disable ADC peripheral if conversions are effectively stopped */
-  if (tmp_hal_status == HAL_OK)
-  {
-    /* 2. Disable the ADC peripheral */
-    tmp_hal_status = ADC_Disable(hadc);
-    
-    /* Check if ADC is effectively disabled */
-    if (tmp_hal_status == HAL_OK)
-    {
-      /* Set ADC state */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_REG_BUSY,
-                        HAL_ADC_STATE_READY);
-    }
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Wait for regular group conversion to be completed.
-  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
-  *         conversion) are cleared by this function, with an exception:
-  *         if low power feature "LowPowerAutoWait" is enabled, flags are 
-  *         not cleared to not interfere with this feature until data register
-  *         is read using function HAL_ADC_GetValue().
-  * @note   This function cannot be used in a particular setup: ADC configured 
-  *         in DMA mode and polling for end of each conversion (ADC init
-  *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
-  *         In this case, DMA resets the flag EOC and polling cannot be
-  *         performed on each conversion. Nevertheless, polling can still 
-  *         be performed on the complete sequence (ADC init
-  *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
-  * @param  hadc ADC handle
-  * @param  Timeout Timeout value in millisecond.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-  uint32_t tmp_Flag_EOC   = 0x00;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* If end of conversion selected to end of sequence conversions */
-  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
-  {
-    tmp_Flag_EOC = ADC_FLAG_EOS;
-  }
-  /* If end of conversion selected to end of unitary conversion */
-  else /* ADC_EOC_SINGLE_CONV */
-  {
-    /* Verification that ADC configuration is compliant with polling for      */
-    /* each conversion:                                                       */
-    /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
-    /* several ranks and polling for end of each conversion.                  */
-    /* For code simplicity sake, this particular case is generalized to       */
-    /* ADC configured in DMA mode and and polling for end of each conversion. */
-    if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN))
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-      
-      /* Process unlocked */
-      __HAL_UNLOCK(hadc);
-      
-      return HAL_ERROR;
-    }
-    else
-    {
-      tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
-    }
-  }
-  
-  /* Get tick count */
-  tickstart = HAL_GetTick();
-  
-  /* Wait until End of unitary conversion or sequence conversions flag is raised */
-  while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
-  {
-    /* Check if timeout is disabled (set to infinite wait) */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
-      {
-        /* New check to avoid false timeout detection in case of preemption */
-        if(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
-        {
-          /* Update ADC state machine to timeout */
-          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hadc);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  
-  /* Update ADC state machine */
-  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-  
-  /* Determine whether any further conversion upcoming on group regular       */
-  /* by external trigger, continuous mode or scan sequence on going.          */
-  if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
-     (hadc->Init.ContinuousConvMode == DISABLE)   )
-  {
-    /* If End of Sequence is reached, disable interrupts */
-    if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
-    {
-      /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit             */
-      /* ADSTART==0 (no conversion on going)                                  */
-      if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
-      {
-        /* Disable ADC end of single conversion interrupt on group regular */
-        /* Note: Overrun interrupt was enabled with EOC interrupt in          */
-        /* HAL_Start_IT(), but is not disabled here because can be used       */
-        /* by overrun IRQ process below.                                      */
-        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
-        
-        /* Set ADC state */
-        ADC_STATE_CLR_SET(hadc->State,
-                          HAL_ADC_STATE_REG_BUSY,
-                          HAL_ADC_STATE_READY);
-      }
-      else
-      {
-        /* Change ADC state to error state */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-        
-        /* Set ADC error code to ADC peripheral internal error */
-        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-      }
-    }
-  }
-  
-  /* Clear end of conversion flag of regular group if low power feature       */
-  /* "LowPowerAutoWait " is disabled, to not interfere with this feature      */
-  /* until data register is read using function HAL_ADC_GetValue().           */
-  if (hadc->Init.LowPowerAutoWait == DISABLE)
-  {
-    /* Clear regular group conversion flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Poll for ADC event.
-  * @param  hadc ADC handle
-  * @param  EventType the ADC event type.
-  *          This parameter can be one of the following values:
-  *            @arg ADC_AWD_EVENT: ADC Analog watchdog event
-  *            @arg ADC_OVR_EVENT: ADC Overrun event
-  * @param  Timeout Timeout value in millisecond.
-  * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
-  *         Indeed, the latter is reset only if hadc->Init.Overrun field is set  
-  *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten 
-  *         by a new converted data as soon as OVR is cleared.
-  *         To reset OVR flag once the preserved data is retrieved, the user can resort
-  *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U; 
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_EVENT_TYPE(EventType));
-  
-  /* Get tick count */
-  tickstart = HAL_GetTick();
-  
-  /* Check selected event flag */
-  while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
-  {
-    /* Check if timeout is disabled (set to infinite wait) */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U) ||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* New check to avoid false timeout detection in case of preemption */
-        if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
-        {
-          /* Update ADC state machine to timeout */
-          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hadc);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  
-  switch(EventType)
-  {
-  /* Analog watchdog (level out of window) event */
-  case ADC_AWD_EVENT:
-    /* Set ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-    
-    /* Clear ADC analog watchdog flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
-    break;
-    
-  /* Overrun event */
-  default: /* Case ADC_OVR_EVENT */
-    /* If overrun is set to overwrite previous data, overrun event is not     */
-    /* considered as an error.                                                */
-    /* (cf ref manual "Managing conversions without using the DMA and without */
-    /* overrun ")                                                             */
-    if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
-    {
-      /* Set ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
-        
-      /* Set ADC error code to overrun */
-      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-    }
-    
-    /* Clear ADC Overrun flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-    break;
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enable ADC, start conversion of regular group with interruption.
-  * @note   Interruptions enabled in this function according to initialization
-  *         setting : EOC (end of conversion), EOS (end of sequence), 
-  *         OVR overrun.
-  *         Each of these interruptions has its dedicated callback function.
-  * @note   To guarantee a proper reset of all interruptions once all the needed
-  *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure 
-  *         a correct stop of the IT-based conversions.
-  * @note   By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling 
-  *         interruption. If required (e.g. in case of oversampling with trigger
-  *         mode), the user must:
-  *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)             
-  *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)     
-  *          before calling HAL_ADC_Start_IT().
-  * @param  hadc ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Perform ADC enable and conversion start if no conversion is on going */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
-  {
-    /* Process locked */
-    __HAL_LOCK(hadc);
-    
-    /* Enable the ADC peripheral */
-    /* If low power mode AutoPowerOff is enabled, power-on/off phases are     */
-    /* performed automatically by hardware.                                   */
-    if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
-    {
-      tmp_hal_status = ADC_Enable(hadc);
-    }
-    
-    /* Start conversion if ADC is effectively enabled */
-    if (tmp_hal_status == HAL_OK)
-    {
-      /* Set ADC state                                                        */
-      /* - Clear state bitfield related to regular group conversion results   */
-      /* - Set state bitfield related to regular operation                    */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
-                        HAL_ADC_STATE_REG_BUSY);
-      
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-      
-      /* Process unlocked */
-      /* Unlock before starting ADC conversions: in case of potential         */
-      /* interruption, to let the process to ADC IRQ Handler.                 */
-      __HAL_UNLOCK(hadc);
-      
-      /* Clear regular group conversion flag and overrun flag */
-      /* (To ensure of no unknown state from potential previous ADC           */
-      /* operations)                                                          */
-      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-      
-      /* Enable ADC end of conversion interrupt */
-      /* Enable ADC overrun interrupt */  
-      switch(hadc->Init.EOCSelection)
-      {
-        case ADC_EOC_SEQ_CONV: 
-          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-          __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR));
-          break;
-        /* case ADC_EOC_SINGLE_CONV */
-        default:
-          __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-          break;
-      }
-      
-      /* Enable conversion of regular group.                                  */
-      /* If software start has been selected, conversion starts immediately.  */
-      /* If external trigger has been selected, conversion will start at next */
-      /* trigger event.                                                       */
-      hadc->Instance->CR |= ADC_CR_ADSTART;
-    }
-  }
-  else
-  {
-    tmp_hal_status = HAL_BUSY;
-  }
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Stop ADC conversion of regular group (and injected group in 
-  *         case of auto_injection mode), disable interrution of 
-  *         end-of-conversion, disable ADC peripheral.
-  * @param  hadc ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* 1. Stop potential conversion on going, on ADC group regular */
-  tmp_hal_status = ADC_ConversionStop(hadc);
-  
-  /* Disable ADC peripheral if conversions are effectively stopped */
-  if (tmp_hal_status == HAL_OK)
-  {
-    /* Disable ADC end of conversion interrupt for regular group */
-    /* Disable ADC overrun interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-    
-    /* 2. Disable the ADC peripheral */
-    tmp_hal_status = ADC_Disable(hadc);
-    
-    /* Check if ADC is effectively disabled */
-    if (tmp_hal_status == HAL_OK)
-    {
-      /* Set ADC state */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_REG_BUSY,
-                        HAL_ADC_STATE_READY);
-    }
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
-  * @note   Interruptions enabled in this function:
-  *         overrun (if applicable), DMA half transfer, DMA transfer complete. 
-  *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc ADC handle
-  * @param  pData Destination Buffer address.
-  * @param  Length Length of data to be transferred from ADC peripheral to memory (in bytes)
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Perform ADC enable and conversion start if no conversion is on going */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
-  {
-    /* Process locked */
-    __HAL_LOCK(hadc);
-    
-    /* Enable ADC DMA mode */
-    hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
-
-    /* Enable the ADC peripheral */
-    /* If low power mode AutoPowerOff is enabled, power-on/off phases are       */
-    /* performed automatically by hardware.                                     */
-    if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
-    {
-      tmp_hal_status = ADC_Enable(hadc);
-    }
-    
-    /* Start conversion if ADC is effectively enabled */
-    if (tmp_hal_status == HAL_OK)
-    {
-      /* Set ADC state                                                        */
-      /* - Clear state bitfield related to regular group conversion results   */
-      /* - Set state bitfield related to regular operation                    */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
-                        HAL_ADC_STATE_REG_BUSY);
-      
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-      
-      /* Process unlocked */
-      /* Unlock before starting ADC conversions: in case of potential         */
-      /* interruption, to let the process to ADC IRQ Handler.                 */
-      __HAL_UNLOCK(hadc);
-
-      /* Set the DMA transfer complete callback */
-      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-      
-      /* Set the DMA half transfer complete callback */
-      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-      
-      /* Set the DMA error callback */
-      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-      
-      
-      /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC   */
-      /* start (in case of SW start):                                         */
-      
-      /* Clear regular group conversion flag and overrun flag */
-      /* (To ensure of no unknown state from potential previous ADC           */
-      /* operations)                                                          */
-      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-      
-      /* Enable ADC overrun interrupt */
-      __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-      
-      /* Start the DMA channel */
-      HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-      
-      /* Enable conversion of regular group.                                  */
-      /* If software start has been selected, conversion starts immediately.  */
-      /* If external trigger has been selected, conversion will start at next */
-      /* trigger event.                                                       */
-      hadc->Instance->CR |= ADC_CR_ADSTART;
-    }
-  }
-  else
-  {
-    tmp_hal_status = HAL_BUSY;
-  }
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Stop ADC conversion of regular group (and injected group in 
-  *         case of auto_injection mode), disable ADC DMA transfer, disable 
-  *         ADC peripheral.
-  *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* 1. Stop potential ADC group regular conversion on going */
-  tmp_hal_status = ADC_ConversionStop(hadc);
-  
-  /* Disable ADC peripheral if conversions are effectively stopped */
-  if (tmp_hal_status == HAL_OK)
-  {
-    /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
-    CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
-    
-    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
-    /* while DMA transfer is on going)                                        */
-    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
-    {
-      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-      
-      /* Check if DMA channel effectively disabled */
-      if (tmp_hal_status != HAL_OK)
-      {
-        /* Update ADC state machine to error */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
-      }
-    }
-    
-    /* Disable ADC overrun interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-    
-    /* 2. Disable the ADC peripheral */
-    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep  */
-    /* in memory a potential failing status.                                  */
-    if (tmp_hal_status == HAL_OK)
-    {
-      tmp_hal_status = ADC_Disable(hadc);
-    }
-    else
-    {
-      ADC_Disable(hadc);
-    }
-
-    /* Check if ADC is effectively disabled */
-    if (tmp_hal_status == HAL_OK)
-    {
-      /* Set ADC state */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_REG_BUSY,
-                        HAL_ADC_STATE_READY);
-    }
-    
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Get ADC regular group conversion result.
-  * @note   Reading register DR automatically clears ADC flag EOC
-  *         (ADC group regular end of unitary conversion).
-  * @note   This function does not clear ADC flag EOS 
-  *         (ADC group regular end of sequence conversion).
-  *         Occurrence of flag EOS rising:
-  *          - If sequencer is composed of 1 rank, flag EOS is equivalent
-  *            to flag EOC.
-  *          - If sequencer is composed of several ranks, during the scan
-  *            sequence flag EOC only is raised, at the end of the scan sequence
-  *            both flags EOC and EOS are raised.
-  *         To clear this flag, either use function:
-  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
-  *         model polling: @ref HAL_ADC_PollForConversion()
-  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
-  * @param  hadc ADC handle
-  * @retval ADC group regular conversion data
-  */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Note: EOC flag is not cleared here by software because automatically     */
-  /*       cleared by hardware when reading register DR.                      */
-  
-  /* Return ADC converted value */ 
-  return hadc->Instance->DR;
-}
-
-/**
-  * @brief  Handle ADC interrupt request.
-  * @param  hadc ADC handle
-  * @retval None
-  */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
-  
-  /* ========== Check End of Conversion flag for regular group ========== */
-  if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || 
-      (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS))   )
-  {
-    /* Update state machine on conversion status if not in error state */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-    {
-      /* Set ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-    }
-    
-    /* Determine whether any further conversion upcoming on group regular     */
-    /* by external trigger, continuous mode or scan sequence on going.        */
-    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
-       (hadc->Init.ContinuousConvMode == DISABLE)   )
-    {
-      /* If End of Sequence is reached, disable interrupts */
-      if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
-      {
-        /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
-        /* ADSTART==0 (no conversion on going)                                */
-        if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
-        {
-          /* Disable ADC end of single conversion interrupt on group regular */
-          /* Note: Overrun interrupt was enabled with EOC interrupt in        */
-          /* HAL_Start_IT(), but is not disabled here because can be used     */
-          /* by overrun IRQ process below.                                    */
-          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
-          
-          /* Set ADC state */
-          ADC_STATE_CLR_SET(hadc->State,
-                            HAL_ADC_STATE_REG_BUSY,
-                            HAL_ADC_STATE_READY);
-        }
-        else
-        {
-          /* Change ADC state to error state */
-          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-          
-          /* Set ADC error code to ADC peripheral internal error */
-          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-        }
-      }
-    }
-    
-    /* Note: into callback, to determine if conversion has been triggered     */
-    /*       from EOC or EOS, possibility to use:                             */
-    /*        " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "                */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-      hadc->ConvCpltCallback(hadc);
-#else
-    HAL_ADC_ConvCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-    
-    /* Clear regular group conversion flag */
-    /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
-    /*       conversion flags clear induces the release of the preserved data.*/
-    /*       Therefore, if the preserved data value is needed, it must be     */
-    /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
-    /* Note: Management of low power auto-wait enabled: flags must be cleared */
-    /*       by user when fetching ADC conversion data.                       */
-    /*       This case is managed in IRQ handler, but this low-power mode     */
-    /*       should not be used with programming model IT or DMA.             */
-    /*       Refer to comment of parameter "LowPowerAutoWait".                */
-    if (hadc->Init.LowPowerAutoWait != ENABLE)
-    {
-      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
-    }
-  }
-  
-  /* ========== Check analog watchdog 1 flag ========== */
-  if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
-  {
-    /* Set ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-    
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-      hadc->LevelOutOfWindowCallback(hadc);
-#else
-    HAL_ADC_LevelOutOfWindowCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-    
-    /* Clear ADC Analog watchdog flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
-   
-  }
-  
-  
-  /* ========== Check Overrun flag ========== */
-  if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
-  {
-    /* If overrun is set to overwrite previous data (default setting),        */
-    /* overrun event is not considered as an error.                           */
-    /* (cf ref manual "Managing conversions without using the DMA and without */
-    /* overrun ")                                                             */
-    /* Exception for usage with DMA overrun event always considered as an     */
-    /* error.                                                                 */
-    if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)            ||
-        HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)  )
-    {
-      /* Set ADC error code to overrun */
-      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-      
-      /* Clear ADC overrun flag */
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-      
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-      hadc->ErrorCallback(hadc);
-#else
-      HAL_ADC_ErrorCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-    }
-    
-    /* Clear the Overrun flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-  }
-  
-}
-
-/**
-  * @brief  Conversion complete callback in non-blocking mode.
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Conversion DMA half-transfer callback in non-blocking mode.
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
-  */
-}
-
-/**
-  * @brief  Analog watchdog 1 callback in non-blocking mode.
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
-  */
-}
-
-/**
-  * @brief  ADC error callback in non-blocking mode
-  *         (ADC conversion with interruption or transfer by DMA).
-  * @note   In case of error due to overrun when using ADC with DMA transfer 
-  *         (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
-  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
-  *         - If needed, restart a new ADC conversion using function
-  *           "HAL_ADC_Start_DMA()"
-  *           (this function is also clearing overrun flag)
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_ErrorCallback must be implemented in the user file.
-  */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions 
- *
-@verbatim   
- ===============================================================================
-             ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure channels on regular group
-      (+) Configure the analog watchdog
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure a channel to be assigned to ADC group regular.
-  * @note   In case of usage of internal measurement channels:
-  *         VrefInt/Vlcd(STM32L0x3xx only)/TempSensor.
-  *         Sampling time constraints must be respected (sampling time can be 
-  *         adjusted in function of ADC clock frequency and sampling time 
-  *         setting).
-  *         Refer to device datasheet for timings values, parameters TS_vrefint,
-  *         TS_vlcd (STM32L0x3xx only), TS_temp (values rough order: 5us to 17us).
-  *         These internal paths can be be disabled using function 
-  *         HAL_ADC_DeInit().
-  * @note   Possibility to update parameters on the fly:
-  *         This function initializes channel into ADC group regular,
-  *         following calls to this function can be used to reconfigure
-  *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
-  *         without resetting the ADC.
-  *         The setting of these parameters is conditioned to ADC state:
-  *         Refer to comments of structure "ADC_ChannelConfTypeDef".
-  * @param  hadc ADC handle
-  * @param  sConfig Structure of ADC channel assigned to ADC group regular.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
-  assert_param(IS_ADC_RANK(sConfig->Rank));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Parameters update conditioned to ADC state:                              */
-  /* Parameters that can be updated when ADC is disabled or enabled without   */
-  /* conversion on going on regular group:                                    */
-  /*  - Channel number                                                        */
-  /*  - Management of internal measurement channels: Vbat/VrefInt/TempSensor  */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET)
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-    /* Process unlocked */
-    __HAL_UNLOCK(hadc);
-    return HAL_ERROR;
-  }
-  
-  if (sConfig->Rank != ADC_RANK_NONE)
-  {
-    /* Enable selected channels */
-    hadc->Instance->CHSELR |= (uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK);
-    
-    /* Management of internal measurement channels: Vlcd (STM32L0x3xx only)/VrefInt/TempSensor */
-    /* internal measurement paths enable: If internal channel selected, enable  */
-    /* dedicated internal buffers and path.                                     */
-    
-    #if defined(ADC_CCR_TSEN)
-    /* If Temperature sensor channel is selected, then enable the internal      */
-    /* buffers and path  */
-    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK))
-    {
-      ADC->CCR |= ADC_CCR_TSEN;   
-      
-      /* Delay for temperature sensor stabilization time */
-      ADC_DelayMicroSecond(ADC_TEMPSENSOR_DELAY_US);
-    }
-    #endif
-    
-    /* If VRefInt channel is selected, then enable the internal buffers and path   */
-    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
-    {
-      ADC->CCR |= ADC_CCR_VREFEN;   
-    }
-    
-#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
-    /* If Vlcd channel is selected, then enable the internal buffers and path   */
-    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK))
-    {
-      ADC->CCR |= ADC_CCR_VLCDEN;   
-    }
-#endif
-  }
-  else
-  {
-    /* Regular sequence configuration */
-    /* Reset the channel selection register from the selected channel */
-    hadc->Instance->CHSELR &= ~((uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK));
-    
-    /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
-    /* internal measurement paths disable: If internal channel selected,    */
-    /* disable dedicated internal buffers and path.                         */
-    #if defined(ADC_CCR_TSEN)
-    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK))
-    {
-      ADC->CCR &= ~ADC_CCR_TSEN;   
-    }
-    #endif
-    
-    /* If VRefInt channel is selected, then enable the internal buffers and path   */
-    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
-    {
-      ADC->CCR &= ~ADC_CCR_VREFEN;   
-    }
-    
-#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
-    /* If Vlcd channel is selected, then enable the internal buffers and path   */
-    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK))
-    {
-      ADC->CCR &= ~ADC_CCR_VLCDEN;   
-    }
-#endif
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the analog watchdog.
-  * @note   Possibility to update parameters on the fly:
-  *         This function initializes the selected analog watchdog, successive  
-  *         calls to this function can be used to reconfigure some parameters 
-  *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting 
-  *         the ADC.
-  *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
-  *         "ADC_AnalogWDGConfTypeDef".
-  * @note   Analog watchdog thresholds can be modified while ADC conversion
-  *         is on going.
-  *         In this case, some constraints must be taken into account:
-  *         the programmed threshold values are effective from the next
-  *         ADC EOC (end of unitary conversion).
-  *         Considering that registers write delay may happen due to
-  *         bus activity, this might cause an uncertainty on the
-  *         effective timing of the new programmed threshold values.
-  * @param  hadc ADC handle
-  * @param  AnalogWDGConfig Structure of ADC analog watchdog configuration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  uint32_t tmpAWDHighThresholdShifted;
-  uint32_t tmpAWDLowThresholdShifted;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
-  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
-  
-  if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
-  {
-    assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
-  }
-
-  /* Verify if threshold is within the selected ADC resolution */
-  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
-  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Parameters update conditioned to ADC state:                              */
-  /* Parameters that can be updated when ADC is disabled or enabled without   */
-  /* conversion on going on regular group:                                    */
-  /*  - Analog watchdog channels                                              */
-  /*  - Analog watchdog thresholds                                            */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
-  {
-    /* Configure ADC Analog watchdog interrupt */
-    if(AnalogWDGConfig->ITMode == ENABLE)
-    {
-      /* Enable the ADC Analog watchdog interrupt */
-      __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
-    }
-    else
-    {
-      /* Disable the ADC Analog watchdog interrupt */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
-    }
-    
-    /* Configuration of analog watchdog:                                        */
-    /*  - Set the analog watchdog mode                                          */
-    /*  - Set the Analog watchdog channel (is not used if watchdog              */
-    /*    mode "all channels": ADC_CFGR1_AWD1SGL=0)                             */
-    hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL |
-                               ADC_CFGR1_AWDEN  |
-                               ADC_CFGR1_AWDCH);
-    
-    hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode |
-                              (AnalogWDGConfig->Channel & ADC_CHANNEL_AWD_MASK));
-    
-    
-    /* Shift the offset in function of the selected ADC resolution: Thresholds  */
-    /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0     */
-    tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
-    tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
-    
-    /* Clear High & Low high thresholds */
-    hadc->Instance->TR &= (uint32_t) ~ (ADC_TR_HT | ADC_TR_LT);
-    
-    /* Set the high threshold */
-    hadc->Instance->TR = ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted);
-    /* Set the low threshold */
-    hadc->Instance->TR |= tmpAWDLowThresholdShifted;
-  }
-  /* If a conversion is on going on regular group, no update could be done    */
-  /* on neither of the AWD configuration structure parameters.                */
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-    
-    tmp_hal_status = HAL_ERROR;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
- *  @brief    ADC Peripheral State functions
- *
-@verbatim
- ===============================================================================
-            ##### Peripheral state and errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions to get in run-time the status of the  
-    peripheral.
-      (+) Check the ADC state
-      (+) Check the ADC error code
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the ADC handle state.
-  * @note   ADC state machine is managed by bitfields, ADC status must be 
-  *         compared with states bits.
-  *         For example:                                                         
-  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
-  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
-  * @param  hadc ADC handle
-  * @retval ADC handle state (bitfield on 32 bits)
-  */
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Return ADC handle state */
-  return hadc->State;
-}
-
-/**
-  * @brief  Return the ADC error code.
-  * @param  hadc ADC handle
-  * @retval ADC error code (bitfield on 32 bits)
-  */
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  return hadc->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Private_Functions ADC Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Enable the selected ADC.
-  * @note   Prerequisite condition to use this function: ADC must be disabled
-  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
-  * @note   If low power mode AutoPowerOff is enabled, power-on/off phases are
-  *         performed automatically by hardware.
-  *         In this mode, this function is useless and must not be called because 
-  *         flag ADC_FLAG_RDY is not usable.
-  *         Therefore, this function must be called under condition of
-  *         "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
-  * @param  hadc ADC handle
-  * @retval HAL status.
-  */
-static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
-{
-  uint32_t tickstart = 0U;
-
-  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
-  /* enabling phase not yet completed: flag ADC ready not yet set).           */
-  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
-  /* causes: ADC clock not running, ...).                                     */
-  if (ADC_IS_ENABLE(hadc) == RESET)
-  {
-    /* Check if conditions to enable the ADC are fulfilled */
-    if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-      
-      /* Set ADC error code to ADC peripheral internal error */
-      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-      
-      return HAL_ERROR;
-    }
-    
-    /* Enable the ADC peripheral */
-    __HAL_ADC_ENABLE(hadc);
-    
-    /* Delay for ADC stabilization time. */
-    ADC_DelayMicroSecond(ADC_STAB_DELAY_US);
-
-    /* Get tick count */
-    tickstart = HAL_GetTick();
-    
-    /* Wait for ADC effectively enabled */
-    while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
-      {
-        /* New check to avoid false timeout detection in case of preemption */
-        if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
-        {
-          /* Update ADC state machine to error */
-          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
-          /* Set ADC error code to ADC peripheral internal error */
-          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
-          return HAL_ERROR;
-        }
-      }
-    }
-  }
-   
-  /* Return HAL status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the selected ADC.
-  * @note   Prerequisite condition to use this function: ADC conversions must be
-  *         stopped.
-  * @param  hadc ADC handle
-  * @retval HAL status.
-  */
-static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
-{
-  uint32_t tickstart = 0U;
-  
-  /* Verification if ADC is not already disabled:                             */
-  /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
-  /*       disabled.                                                          */
-  if (ADC_IS_ENABLE(hadc) != RESET)
-  {
-    /* Check if conditions to disable the ADC are fulfilled */
-    if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
-    {
-      /* Disable the ADC peripheral */
-      __HAL_ADC_DISABLE(hadc);
-    }
-    else
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-      
-      /* Set ADC error code to ADC peripheral internal error */
-      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-      
-      return HAL_ERROR;
-    }
-     
-    /* Wait for ADC effectively disabled */
-    /* Get tick count */
-    tickstart = HAL_GetTick();
-    
-    while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
-    {
-      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
-      {
-        /* New check to avoid false timeout detection in case of preemption */
-        if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
-        {
-          /* Update ADC state machine to error */
-          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
-          /* Set ADC error code to ADC peripheral internal error */
-          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
-          return HAL_ERROR;
-        }
-      }
-    }
-  }
-  
-  /* Return HAL status */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Stop ADC conversion.
-  * @note   Prerequisite condition to use this function: ADC conversions must be
-  *         stopped to disable the ADC.
-  * @param  hadc ADC handle
-  * @retval HAL status.
-  */
-static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
-{
-  uint32_t tickstart = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-    
-  /* Verification if ADC is not already stopped on regular group to bypass    */
-  /* this function if not needed.                                             */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
-  {
-    
-    /* Stop potential conversion on going on regular group */
-    /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
-    if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 
-        HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)                  )
-    {
-      /* Stop conversions on regular group */
-      hadc->Instance->CR |= ADC_CR_ADSTP;
-    }
-    
-    /* Wait for conversion effectively stopped */
-    /* Get tick count */
-    tickstart = HAL_GetTick();
-      
-    while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
-    {
-      if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
-      {
-        /* New check to avoid false timeout detection in case of preemption */
-        if((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
-        {
-        /* Update ADC state machine to error */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-      
-        /* Set ADC error code to ADC peripheral internal error */
-        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-        
-        return HAL_ERROR;
-        }
-      }
-    }
-  }
-   
-  /* Return HAL status */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  DMA transfer complete callback. 
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Update state machine on conversion status if not in error state */
-  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
-  {
-    /* Set ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-    
-    /* Determine whether any further conversion upcoming on group regular     */
-    /* by external trigger, continuous mode or scan sequence on going.        */
-    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
-       (hadc->Init.ContinuousConvMode == DISABLE)   )
-    {
-      /* If End of Sequence is reached, disable interrupts */
-      if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
-      {
-        /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
-        /* ADSTART==0 (no conversion on going)                                */
-        if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
-        {
-          /* Disable ADC end of single conversion interrupt on group regular */
-          /* Note: Overrun interrupt was enabled with EOC interrupt in        */
-          /* HAL_Start_IT(), but is not disabled here because can be used     */
-          /* by overrun IRQ process below.                                    */
-          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
-          
-          /* Set ADC state */
-          ADC_STATE_CLR_SET(hadc->State,
-                            HAL_ADC_STATE_REG_BUSY,
-                            HAL_ADC_STATE_READY);
-        }
-        else
-        {
-          /* Change ADC state to error state */
-          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-          
-          /* Set ADC error code to ADC peripheral internal error */
-          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-        }
-      }
-    }
-
-    /* Conversion complete callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-    hadc->ConvCpltCallback(hadc);
-#else
-    HAL_ADC_ConvCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* Call DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback(hdma);
-  }
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Half conversion callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-    hadc->ConvHalfCpltCallback(hadc);
-#else
-  HAL_ADC_ConvHalfCpltCallback(hadc); 
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA error callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void ADC_DMAError(DMA_HandleTypeDef *hdma)
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Set ADC state */
-  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
-  
-  /* Set ADC error code to DMA error */
-  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
-  
-  /* Error callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-  hadc->ErrorCallback(hadc);
-#else
-  HAL_ADC_ErrorCallback(hadc); 
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  Delay micro seconds 
-  * @param  microSecond  delay
-  * @retval None
-  */
-static void ADC_DelayMicroSecond(uint32_t microSecond)
-{
-  /* Compute number of CPU cycles to wait for */
-  __IO uint32_t waitLoopIndex = (microSecond * (SystemCoreClock / 1000000U));
-
-  while(waitLoopIndex != 0U)
-  {
-    waitLoopIndex--;
-  } 
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c
deleted file mode 100644
index 313053a768..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_adc_ex.c
-  * @author  MCD Application Team
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Analog to Digital Convertor (ADC)
-  *          peripheral:
-  *           + Operation functions
-  *             ++ Calibration
-  *               +++ ADC automatic self-calibration
-  *               +++ Calibration factors get or set
-  *          Other functions (generic functions) are available in file 
-  *          "stm32l0xx_hal_adc.c".
-  *
-  @verbatim
-  [..] 
-  (@) Sections "ADC peripheral features" and "How to use this driver" are
-      available in file of generic functions "stm32l0xx_hal_adc.c".
-  [..]
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup ADCEx ADCEx
-  * @brief ADC Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
-  * @{
-  */
-
-  /* Fixed timeout values for ADC calibration, enable settling time, disable  */
-  /* settling time.                                                           */
-  /* Values defined to be higher than worst cases: low clock frequency,       */
-  /* maximum prescaler.                                                       */
-  /* Unit: ms                                                                 */
-  #define ADC_CALIBRATION_TIMEOUT      10U      
-
-/* Delay for VREFINT stabilization time. */
-/* Internal reference startup time max value is 3ms  (refer to device datasheet, parameter TVREFINT). */
-/* Unit: ms */
-#define SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT       (3U)
-
-/* Delay for TEMPSENSOR stabilization time. */
-/* Temperature sensor startup time max value is 10us  (refer to device datasheet, parameter tSTART). */
-/* Unit: ms */
-#define SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT    (1U)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
-  * @{
-  */
-
-/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
-  * @brief    Extended IO operation functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Perform the ADC calibration.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Perform an ADC automatic self-calibration
-  *         Calibration prerequisite: ADC must be disabled (execute this
-  *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
-  * @note   Calibration factor can be read after calibration, using function
-  *         HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
-  * @param  hadc       ADC handle
-  * @param  SingleDiff Selection of single-ended or differential input
-  *          This parameter can be only of the following values:
-  *            @arg ADC_SINGLE_ENDED: Channel in mode input single ended
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  uint32_t tickstart = 0U;
-  uint32_t backup_setting_adc_dma_transfer = 0U; /* Note: Variable not declared as volatile because register read is already declared as volatile */
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Calibration prerequisite: ADC must be disabled. */
-  if (ADC_IS_ENABLE(hadc) == RESET)
-  {
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State, 
-                      HAL_ADC_STATE_REG_BUSY,
-                      HAL_ADC_STATE_BUSY_INTERNAL);
-    
-    /* Disable ADC DMA transfer request during calibration */
-    /* Note: Specificity of this STM32 serie: Calibration factor is           */
-    /*       available in data register and also transfered by DMA.           */
-    /*       To not insert ADC calibration factor among ADC conversion data   */
-    /*       in array variable, DMA transfer must be disabled during          */
-    /*       calibration.                                                     */
-    backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
-    CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
-    
-    /* Start ADC calibration */
-    hadc->Instance->CR |= ADC_CR_ADCAL;
-    
-    tickstart = HAL_GetTick();  
-    
-    /* Wait for calibration completion */
-    while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
-    {
-      if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
-      {
-        /* New check to avoid false timeout detection in case of preemption */
-        if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
-        {
-          /* Update ADC state machine to error */
-          ADC_STATE_CLR_SET(hadc->State,
-                            HAL_ADC_STATE_BUSY_INTERNAL,
-                            HAL_ADC_STATE_ERROR_INTERNAL);
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hadc);
-
-          return HAL_ERROR;
-        }
-      }
-    }
-    
-    /* Restore ADC DMA transfer request after calibration */
-    SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer);
-    
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_BUSY_INTERNAL,
-                      HAL_ADC_STATE_READY);
-  }
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-    
-    tmp_hal_status = HAL_ERROR;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Get the calibration factor.
-  * @param  hadc ADC handle.
-  * @param  SingleDiff This parameter can be only:
-  *           @arg ADC_SINGLE_ENDED: Channel in mode input single ended.
-  * @retval Calibration value.
-  */
-uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 
-  
-  /* Return the ADC calibration value */ 
-  return ((hadc->Instance->CALFACT) & 0x0000007FU);
-}
-
-/**
-  * @brief  Set the calibration factor to overwrite automatic conversion result.
-  *         ADC must be enabled and no conversion is ongoing.
-  * @param  hadc ADC handle
-  * @param  SingleDiff This parameter can be only:
-  *           @arg ADC_SINGLE_ENDED: Channel in mode input single ended.
-  * @param  CalibrationFactor Calibration factor (coded on 7 bits maximum)
-  * @retval HAL state
-  */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 
-  assert_param(IS_ADC_CALFACT(CalibrationFactor)); 
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Verification of hardware constraints before modifying the calibration    */
-  /* factors register: ADC must be enabled, no conversion on going.           */
-  if ( (ADC_IS_ENABLE(hadc) != RESET)                            &&
-       (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)  )
-  {
-    /* Set the selected ADC calibration value */ 
-    hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT;
-    hadc->Instance->CALFACT |= CalibrationFactor;
-  }
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-    
-    /* Update ADC state machine to error */
-    tmp_hal_status = HAL_ERROR;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Enables the buffer of Vrefint for the ADC, required when device is in mode low-power (low-power run, low-power sleep or stop mode)
-  *         This function must be called before function HAL_ADC_Init() 
-  *         (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first)
-  *         For more details on procedure and buffer current consumption, refer to device reference manual.
-  * @note   This is functional only if the LOCK is not set.
-  * @note   This API is obsolete. This configuration is done in HAL_ADC_ConfigChannel().
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void)
-{
-  uint32_t tickstart = 0U;
-  
-  /* Enable the Buffer for the ADC by setting ENBUF_SENSOR_ADC bit in the CFGR3 register */
-  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC);
-  
-  /* Wait for Vrefint buffer effectively enabled */
-  /* Get tick count */
-  tickstart = HAL_GetTick();
-  
-  while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF))
-  {
-    if((HAL_GetTick() - tickstart) > SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT)
-    {
-      /* New check to avoid false timeout detection in case of preemption */
-      if(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF))
-      {
-        return HAL_ERROR;
-      }
-    }
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Disables the Buffer Vrefint for the ADC.
-  * @note This is functional only if the LOCK is not set.
-  * @note This API is obsolete. This configuration is done in HAL_ADC_ConfigChannel().
-  * @retval None
-  */
-void HAL_ADCEx_DisableVREFINT(void)
-{
-  /* Disable the Vrefint by resetting ENBUF_SENSOR_ADC bit in the CFGR3 register */
-  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC);
-}
-
-/**
-  * @brief  Enables the buffer of temperature sensor for the ADC, required when device is in mode low-power (low-power run, low-power sleep or stop mode)
-  *         This function must be called before function HAL_ADC_Init()
-  *         (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first)
-  *         For more details on procedure and buffer current consumption, refer to device reference manual.
-  * @note   This is functional only if the LOCK is not set.
-  * @note   This API is obsolete. This configuration is done in HAL_ADC_ConfigChannel().
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void)
-{
-  uint32_t tickstart = 0U;
-  
-  /* Enable the Buffer for the ADC by setting ENBUF_SENSOR_ADC bit in the CFGR3 register */
-  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC);
-  
-  /* Wait for Vrefint buffer effectively enabled */
-  /* Get tick count */
-  tickstart = HAL_GetTick();
-  
-  while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF))
-  {
-    if((HAL_GetTick() - tickstart) > SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT)
-    {
-      /* New check to avoid false timeout detection in case of preemption */
-      if(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF))
-      {
-        return HAL_ERROR;
-      }
-    }
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Disables the VREFINT and Sensor for the ADC.
-  * @note This is functional only if the LOCK is not set.
-  * @note This API is obsolete. This configuration is done in HAL_ADC_ConfigChannel().
-  * @retval None
-  */
-void HAL_ADCEx_DisableVREFINTTempSensor(void)
-{
-  /* Disable the Vrefint by resetting ENBUF_SENSOR_ADC bit in the CFGR3 register */
-  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp.c
deleted file mode 100644
index ae148ee1d4..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp.c
+++ /dev/null
@@ -1,1068 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_comp.c
-  * @author  MCD Application Team
-  * @brief   COMP HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the COMP peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Start/Stop operation functions in polling mode
-  *           + Start/Stop operation functions in interrupt mode (through EXTI interrupt)
-  *           + Peripheral control functions
-  *           + Peripheral state functions
-  *         
-  @verbatim
-================================================================================
-          ##### COMP Peripheral features #####
-================================================================================
-           
-  [..]       
-      The STM32L0xx device family integrates two analog comparators instances
-      COMP1 and COMP2:
-      (#) The COMP input minus (inverting input) and input plus (non inverting input)
-          can be set to internal references or to GPIO pins
-          (refer to GPIO list in reference manual).
-  
-      (#) The COMP output level is available using HAL_COMP_GetOutputLevel()
-          and can be redirected to other peripherals: GPIO pins (in mode
-          alternate functions for comparator), timers.
-          (refer to GPIO list in reference manual).
-  
-      (#) Pairs of comparators instances can be combined in window mode
-          (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
-  
-      (#) The comparators have interrupt capability through the EXTI controller
-          with wake-up from sleep and stop modes:
-          (++) COMP1 is internally connected to EXTI Line 21
-          (++) COMP2 is internally connected to EXTI Line 22
-
-          From the corresponding IRQ handler, the right interrupt source can be retrieved
-          using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
-
-            ##### How to use this driver #####
-================================================================================
-  [..]
-      This driver provides functions to configure and program the comparator instances
-      of STM32L0xx devices.
-
-      To use the comparator, perform the following steps:
-      
-      (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
-      (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
-           using HAL_GPIO_Init().
-      (++) If needed, configure the GPIO connected to comparator output in alternate function mode
-           using HAL_GPIO_Init().
-      (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and 
-           selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
-           interrupt vector using HAL_NVIC_EnableIRQ() function.
-      
-      (#) Configure the comparator using HAL_COMP_Init() function:
-      (++) Select the input minus (inverting input)
-      (++) Select the input plus (non-inverting input)
-      (++) Select the output polarity  
-      (++) Select the power mode
-      (++) Select the window mode
-      
-      -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
-          to enable internal control clock of the comparators.
-          However, this is a legacy strategy. In future STM32 families,
-          COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
-          Therefore, for compatibility anticipation, it is recommended to 
-          implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
-      
-      (#) Reconfiguration on-the-fly of comparator can be done by calling again
-          function HAL_COMP_Init() with new input structure parameters values.
-      
-      (#) Enable the comparator using HAL_COMP_Start() function.
-      
-      (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
-          to manage comparator outputs (events and output level).
-      
-      (#) Disable the comparator using HAL_COMP_Stop() function.
-      
-      (#) De-initialize the comparator using HAL_COMP_DeInit() function.
-      
-      (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
-          The only way to unlock the comparator is a device hardware reset.
-  
-    *** Callback registration ***
-    =============================================
-    [..]
-
-     The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
-     allows the user to configure dynamically the driver callbacks.
-     Use Functions HAL_COMP_RegisterCallback()
-     to register an interrupt callback.
-    [..]
-
-     Function HAL_COMP_RegisterCallback() allows to register following callbacks:
-       (+) TriggerCallback       : callback for COMP trigger.
-       (+) MspInitCallback       : callback for Msp Init.
-       (+) MspDeInitCallback     : callback for Msp DeInit.
-     This function takes as parameters the HAL peripheral handle, the Callback ID
-     and a pointer to the user callback function.
-    [..]
-
-     Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
-     weak function.
-    [..]
-
-     HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
-     and the Callback ID.
-     This function allows to reset following callbacks:
-       (+) TriggerCallback       : callback for COMP trigger.
-       (+) MspInitCallback       : callback for Msp Init.
-       (+) MspDeInitCallback     : callback for Msp DeInit.
-     [..]
-
-     By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
-     all callbacks are set to the corresponding weak functions:
-     example HAL_COMP_TriggerCallback().
-     Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
-     these callbacks are null (not registered beforehand).
-    [..]
-
-     If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
-     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-     [..]
-
-     Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
-     Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
-     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-    [..]
-
-     Then, the user first registers the MspInit/MspDeInit user callbacks
-     using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
-     or HAL_COMP_Init() function.
-     [..]
-
-     When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
-     not defined, the callback registration feature is not available and all callbacks
-     are set to the corresponding weak functions.
-  
-  @endverbatim
-  ******************************************************************************
-
-  Table 1. COMP inputs and output for STM32L0xx devices
-  +---------------------------------------------------------+
-  |                |                |   COMP1   |   COMP2   |
-  |----------------|----------------|-----------|-----------|
-  |                | IO1            |    PA1    |    PA3    |
-  | Input plus     | IO2            |    ---    |    PA4    |
-  |                | IO3            |    ---    |    PB5    |
-  |                | IO4            |    ---    |    PB6    |
-  |                | IO5            |    ---    |    PB7    |
-  |----------------|----------------|-----------------------|
-  |                | 1/4 VrefInt    |    ---    | Available |
-  |                | 1/2 VrefInt    |    ---    | Available |
-  |                | 3/4 VrefInt    |    ---    | Available |
-  | Input minus    | VrefInt        | Available | Available |
-  |                | DAC1 channel 1 | Available | Available |
-  |                | DAC1 channel 2 | Available | Available |
-  |                | IO1            |    PA0    |    PA2    |
-  |                | IO2            |    PA5    |    PA5    |
-  |                | IO3            |    ---    |    PB3    |
-  +---------------------------------------------------------+
-  | Output         |                |  PA0  (1) |  PA2  (1) |
-  |                |                |  PA6  (1) |  PA7  (1) |
-  |                |                |  PA11 (1) |  PA12 (1) |
-  |                |                |  LPTIM    |  LPTIM    |
-  |                |                |  TIM  (2) |  TIM  (2) |
-  +-----------------------------------------------------------+
-  (1) GPIO must be set to alternate function for comparator
-  (2) Comparators output to timers is set in timers instances.
-
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */
-
-#if !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup COMP COMP
-  * @brief COMP HAL module driver
-  * @{
-  */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup COMP_Private_Constants
-  * @{
-  */
-
-/* Delay for COMP startup time.                                               */
-/* Note: Delay required to reach propagation delay specification.             */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "tSTART").                                                       */
-/* Unit: us                                                                   */
-#define COMP_DELAY_STARTUP_US             (25U)  /*!< Delay for COMP startup time */
-
-/* Delay for COMP voltage scaler stabilization time (voltage from VrefInt,    */
-/* delay based on VrefInt startup time).                                      */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "TVREFINT").                                                     */
-/* Unit: us                                                                   */
-#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (3000U)  /*!< Delay for COMP voltage scaler stabilization time */
-
-#define COMP_OUTPUT_LEVEL_BITOFFSET_POS  (30U)
-
-#define C_REV_ID_A              0x1000U /* Cut1.0 */
-#define C_REV_ID_Z              0x1008U /* Cut1.1 */
-#define C_REV_ID_Y              0x1003U /* Cut1.2 */
-
-#define C_DEV_ID_L073           0x447U
-#define C_DEV_ID_L053           0x417U
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup COMP_Exported_Functions COMP Exported Functions
-  * @{
-  */
-
-/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions 
- *  @brief    Initialization and de-initialization functions. 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions to initialize and de-initialize comparators 
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the COMP according to the specified
-  *         parameters in the COMP_InitTypeDef and initialize the associated handle.
-  * @note   If the selected comparator is locked, initialization can't be performed.
-  *         To unlock the configuration, perform a system reset.
-  * @note   When the LPTIM connection is enabled, the following pins LPTIM_IN1(PB5, PC0)
-            and LPTIM_IN2(PB7, PC2) should not be configured in alternate function.
-  * @param  hcomp  COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
-{
-  uint32_t tmp_csr = 0U;
-  uint32_t exti_line = 0U;
-  uint32_t comp_voltage_scaler_not_initialized = 0U;
-  __IO uint32_t wait_loop_index = 0U;
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameters */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-    assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.NonInvertingInput));
-    assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InvertingInput));
-    assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
-    assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
-    assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
-    assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
-    
-    if(hcomp->State == HAL_COMP_STATE_RESET)
-    {
-      /* Allocate lock resource and initialize it */
-      hcomp->Lock = HAL_UNLOCKED;
-      
-      /* Init SYSCFG and the low level hardware to access comparators */
-      /* Note: HAL_COMP_Init() calls __HAL_RCC_SYSCFG_CLK_ENABLE()            */
-      /*       to enable internal control clock of the comparators.           */
-      /*       However, this is a legacy strategy. In future STM32 families,  */
-      /*       COMP clock enable must be implemented by user                  */
-      /*       in "HAL_COMP_MspInit()".                                       */
-      /*       Therefore, for compatibility anticipation, it is recommended   */
-      /*       to implement __HAL_RCC_SYSCFG_CLK_ENABLE()                     */
-      /*       in "HAL_COMP_MspInit()".                                       */
-      __HAL_RCC_SYSCFG_CLK_ENABLE();
-      
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-      /* Init the COMP Callback settings */
-      hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
-
-      if (hcomp->MspInitCallback == NULL)
-      {
-        hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit  */
-      }
-      
-      /* Init the low level hardware */
-      hcomp->MspInitCallback(hcomp);
-#else
-      /* Init the low level hardware */
-      HAL_COMP_MspInit(hcomp);
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-    }
-    
-    /* Set COMP parameters */
-    tmp_csr = (hcomp->Init.InvertingInput   |
-               hcomp->Init.OutputPol         );
-    
-    /* Configuration specific to comparator instance: COMP2 */
-    if ((hcomp->Instance) == COMP2)
-    {
-      /* Comparator input plus configuration is available on COMP2 only */
-      /* Comparator power mode configuration is available on COMP2 only */
-      tmp_csr |= (hcomp->Init.NonInvertingInput |
-                  hcomp->Init.Mode               );
-      
-      /* COMP2 specificity: when using VrefInt or subdivision of VrefInt,     */
-      /* specific path must be enabled.                                       */
-      if((hcomp->Init.InvertingInput == COMP_INPUT_MINUS_VREFINT)    ||
-         (hcomp->Init.InvertingInput == COMP_INPUT_MINUS_1_4VREFINT) ||
-         (hcomp->Init.InvertingInput == COMP_INPUT_MINUS_1_2VREFINT) ||
-         (hcomp->Init.InvertingInput == COMP_INPUT_MINUS_3_4VREFINT)   )
-      {
-        /* Memorize voltage scaler state before initialization */
-        comp_voltage_scaler_not_initialized = (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP) == 0U);
-        
-        SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_EN_VREFINT           |
-                               SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP  );
-        
-        /* Delay for COMP scaler bridge voltage stabilization */
-        /* Apply the delay if voltage scaler bridge is enabled for the first time */
-        if (comp_voltage_scaler_not_initialized != 0U)
-        {
-          /* Wait loop initialization and execution */
-          /* Note: Variable divided by 2 to compensate partially              */
-          /*       CPU processing cycles.                                     */
-          wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000U * 2U)));
-          while(wait_loop_index != 0U)
-          {
-            wait_loop_index--;
-          }
-        }
-      }
-    }
-    
-    /* Set comparator output connection to LPTIM */
-    if (hcomp->Init.LPTIMConnection != COMP_LPTIMCONNECTION_DISABLED)
-    {
-      /* LPTIM connexion requested on COMP1 */
-      if ((hcomp->Instance) == COMP1)
-      {
-        /* Note : COMP1 can be connected to the input 1 of LPTIM if requested */
-        assert_param(IS_COMP1_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
-        
-        /* Note: Compatibility with previous driver version using             */
-        /* generic literal COMP_LPTIMCONNECTION_ENABLED corresponding         */
-        /* to LPTIM input 1 for COMP1.                                        */
-          tmp_csr |= (COMP_CSR_COMP1LPTIM1IN1);
-        }
-      else
-      {
-        /* Note : COMP2 can be connected to input 1 or input 2 of LPTIM if requested */
-        assert_param(IS_COMP2_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
-        
-        switch (hcomp->Init.LPTIMConnection)
-        {
-        case  COMP_LPTIMCONNECTION_IN1_ENABLED :
-          tmp_csr |= (COMP_CSR_COMP2LPTIM1IN1);
-          break;
-        case  COMP_LPTIMCONNECTION_IN2_ENABLED :
-        default :
-          /* Note: Default case for compatibility with previous driver version*/
-          /* using generic literal COMP_LPTIMCONNECTION_ENABLED corresponding */
-          /* to LPTIM input 2 for COMP2.                                      */
-          
-          /* Check the MCU_ID in order to allow or not the COMP2 connection to LPTIM input 2 */
-          if (((HAL_GetDEVID() == C_DEV_ID_L073) && (HAL_GetREVID() == C_REV_ID_A))
-                            ||
-              ((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_A))
-                            ||
-              ((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_Z)))
-          {
-            assert_param(IS_COMP2_LPTIMCONNECTION_RESTRICTED(hcomp->Init.LPTIMConnection));
-            
-            /* Error: On the selected device, COMP2 cannot be connected to LPTIM input 2 */
-            status = HAL_ERROR;
-          }
-          else
-          {
-            tmp_csr |= (COMP_CSR_COMP2LPTIM1IN2);
-          }
-          break;
-        }
-      }
-    }
-    
-    /* Update comparator register */
-    if ((hcomp->Instance) == COMP1)
-    {
-      MODIFY_REG(hcomp->Instance->CSR,
-                 COMP_CSR_COMP1INNSEL     | COMP_CSR_COMP1WM       |
-                 COMP_CSR_COMP1LPTIM1IN1  | COMP_CSR_COMP1POLARITY  ,
-                 tmp_csr
-                );
-    }
-    else /* Instance == COMP2 */
-    {
-      MODIFY_REG(hcomp->Instance->CSR,
-                 COMP_CSR_COMP2SPEED     | COMP_CSR_COMP2INNSEL    |
-                 COMP_CSR_COMP2INPSEL    | COMP_CSR_COMP2POLARITY  |
-                 COMP_CSR_COMP2LPTIM1IN2 | COMP_CSR_COMP2LPTIM1IN1  ,
-                 tmp_csr
-                );
-    }
-    
-    /* Set window mode */
-    /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP     */
-    /*       instances. Therefore, this function can update another COMP      */
-    /*       instance that the one currently selected.                        */
-    if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
-    {
-      SET_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
-    }
-    else
-    {
-      CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
-    }
-    
-    /* Get the EXTI line corresponding to the selected COMP instance */
-    exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
-    
-    /* Manage EXTI settings */
-    if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != RESET)
-    {
-      /* Configure EXTI rising edge */
-      if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != RESET)
-      {
-        SET_BIT(EXTI->RTSR, exti_line);
-      }
-      else
-      {
-        CLEAR_BIT(EXTI->RTSR, exti_line);
-      }
-      
-      /* Configure EXTI falling edge */
-      if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != RESET)
-      {
-        SET_BIT(EXTI->FTSR, exti_line);
-      }
-      else
-      {
-        CLEAR_BIT(EXTI->FTSR, exti_line);
-      }
-      
-      /* Clear COMP EXTI pending bit (if any) */
-      WRITE_REG(EXTI->PR, exti_line);
-      
-      /* Configure EXTI event mode */
-      if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != RESET)
-      {
-        SET_BIT(EXTI->EMR, exti_line);
-      }
-      else
-      {
-        CLEAR_BIT(EXTI->EMR, exti_line);
-      }
-      
-      /* Configure EXTI interrupt mode */
-      if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != RESET)
-      {
-        SET_BIT(EXTI->IMR, exti_line);
-      }
-      else
-      {
-        CLEAR_BIT(EXTI->IMR, exti_line);
-      }
-    }
-    else
-    {
-      /* Disable EXTI event mode */
-      CLEAR_BIT(EXTI->EMR, exti_line);
-      
-      /* Disable EXTI interrupt mode */
-      CLEAR_BIT(EXTI->IMR, exti_line);
-    }
-    
-    /* Set HAL COMP handle state */
-    /* Note: Transition from state reset to state ready,                      */
-    /*       otherwise (coming from state ready or busy) no state update.     */
-    if (hcomp->State == HAL_COMP_STATE_RESET)
-    {
-      hcomp->State = HAL_COMP_STATE_READY;
-    }
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  DeInitialize the COMP peripheral.
-  * @note   Deinitialization cannot be performed if the COMP configuration is locked.
-  *         To unlock the configuration, perform a system reset.
-  * @param  hcomp  COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-    
-    /* Set COMP_CSR register to reset value */
-    WRITE_REG(hcomp->Instance->CSR, 0x00000000U);
-    
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-    if (hcomp->MspDeInitCallback == NULL)
-    {
-      hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit  */
-    }
-    
-    /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-    hcomp->MspDeInitCallback(hcomp);
-#else
-    /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-    HAL_COMP_MspDeInit(hcomp);
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-    
-    /* Set HAL COMP handle state */
-    hcomp->State = HAL_COMP_STATE_RESET;
-    
-    /* Release Lock */
-    __HAL_UNLOCK(hcomp);
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Initialize the COMP MSP.
-  * @param  hcomp  COMP handle
-  * @retval None
-  */
-__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcomp);
-  
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_COMP_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize the COMP MSP.
-  * @param  hcomp  COMP handle
-  * @retval None
-  */
-__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcomp);
-  
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_COMP_MspDeInit could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User COMP Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
-  *                the configuration information for the specified COMP.
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
-  *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  
-  if (HAL_COMP_STATE_READY == hcomp->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_COMP_TRIGGER_CB_ID :
-        hcomp->TriggerCallback = pCallback;
-        break;
-      
-      case HAL_COMP_MSPINIT_CB_ID :
-        hcomp->MspInitCallback = pCallback;
-        break;
-      
-      case HAL_COMP_MSPDEINIT_CB_ID :
-        hcomp->MspDeInitCallback = pCallback;
-        break;
-      
-      default :
-        /* Update the error code */
-        hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-        
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_COMP_STATE_RESET == hcomp->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_COMP_MSPINIT_CB_ID :
-        hcomp->MspInitCallback = pCallback;
-        break;
-      
-      case HAL_COMP_MSPDEINIT_CB_ID :
-        hcomp->MspDeInitCallback = pCallback;
-        break;
-      
-      default :
-        /* Update the error code */
-        hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-        
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-    
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Unregister a COMP Callback
-  *         COMP callback is redirected to the weak predefined callback
-  * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
-  *                the configuration information for the specified COMP.
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
-  *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (HAL_COMP_STATE_READY == hcomp->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_COMP_TRIGGER_CB_ID :
-        hcomp->TriggerCallback = HAL_COMP_TriggerCallback;         /* Legacy weak callback */
-        break;
-      
-      case HAL_COMP_MSPINIT_CB_ID :
-        hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
-        break;
-
-      case HAL_COMP_MSPDEINIT_CB_ID :
-        hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
-        break;
-
-      default :
-        /* Update the error code */
-        hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_COMP_STATE_RESET == hcomp->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_COMP_MSPINIT_CB_ID :
-        hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
-        break;
-
-      case HAL_COMP_MSPDEINIT_CB_ID :
-        hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
-        break;
-
-      default :
-        /* Update the error code */
-        hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  return status;
-}
-
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions 
- *  @brief   Start-Stop operation functions. 
- *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start a comparator instance.
-      (+) Stop a comparator instance.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the comparator.
-  * @param  hcomp  COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
-{
-  __IO uint32_t wait_loop_index = 0U;
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-    if(hcomp->State == HAL_COMP_STATE_READY)
-    {
-      /* Enable the selected comparator */
-      SET_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxEN);
-      
-      /* Set HAL COMP handle state */
-      hcomp->State = HAL_COMP_STATE_BUSY;
-      
-      /* Delay for COMP startup time */
-      /* Wait loop initialization and execution */
-      /* Note: Variable divided by 2 to compensate partially                  */
-      /*       CPU processing cycles.                                         */
-      wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000U * 2U)));
-      while(wait_loop_index != 0U)
-      {
-        wait_loop_index--;
-      }
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Stop the comparator.
-  * @param  hcomp  COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-    
-    if((hcomp->State == HAL_COMP_STATE_BUSY)  ||
-       (hcomp->State == HAL_COMP_STATE_READY)   )
-    {
-      /* Disable the selected comparator */
-      CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxEN);
-
-      /* Set HAL COMP handle state */
-      hcomp->State = HAL_COMP_STATE_READY;
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Comparator IRQ handler.
-  * @param  hcomp  COMP handle
-  * @retval None
-  */
-void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
-{
-  /* Get the EXTI line corresponding to the selected COMP instance */
-  uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
-  
-  /* Check COMP EXTI flag */
-  if(READ_BIT(EXTI->PR, exti_line) != RESET)
-  {
-    /* Check whether comparator is in independent or window mode */
-    if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0)
-    {
-      /* Clear COMP EXTI line pending bit of the pair of comparators          */
-      /* in window mode.                                                      */
-      /* Note: Pair of comparators in window mode can both trig IRQ when      */
-      /*       input voltage is changing from "out of window" area            */
-      /*       (low or high ) to the other "out of window" area (high or low).*/
-      /*       Both flags must be cleared to call comparator trigger          */
-      /*       callback is called once.                                       */
-      WRITE_REG(EXTI->PR, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
-    }
-    else
-    {
-      /* Clear COMP EXTI line pending bit */
-      WRITE_REG(EXTI->PR, exti_line);
-    }
-    
-    /* COMP trigger callback */
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-    hcomp->TriggerCallback(hcomp);
-#else
-    HAL_COMP_TriggerCallback(hcomp);
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions 
- *  @brief   Management functions.
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the comparators. 
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Lock the selected comparator configuration.
-  * @note   A system reset is required to unlock the comparator configuration.
-  * @note   Locking the comparator from reset state is possible
-  *         if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
-  * @param  hcomp  COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-    
-    /* Set HAL COMP handle state */
-    hcomp->State = ((HAL_COMP_StateTypeDef)(hcomp->State | COMP_STATE_BITFIELD_LOCK));
-  }
-  
-  if(status == HAL_OK)
-  {
-    /* Set the lock bit corresponding to selected comparator */
-    __HAL_COMP_LOCK(hcomp);
-  }
-  
-  return status; 
-}
-
-/**
-  * @brief  Return the output level (high or low) of the selected comparator. 
-  *         The output level depends on the selected polarity.
-  *         If the polarity is not inverted:
-  *           - Comparator output is low when the input plus is at a lower
-  *             voltage than the input minus
-  *           - Comparator output is high when the input plus is at a higher
-  *             voltage than the input minus
-  *         If the polarity is inverted:
-  *           - Comparator output is high when the input plus is at a lower
-  *             voltage than the input minus
-  *           - Comparator output is low when the input plus is at a higher
-  *             voltage than the input minus
-  * @param  hcomp  COMP handle
-  * @retval Returns the selected comparator output level: 
-  *         @arg @ref COMP_OUTPUT_LEVEL_LOW
-  *         @arg @ref COMP_OUTPUT_LEVEL_HIGH
-  *       
-  */
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
-{
-  /* Check the parameter */
-  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-  
-  return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxOUTVALUE)
-                    >> COMP_OUTPUT_LEVEL_BITOFFSET_POS);
-}
-
-/**
-  * @brief  Comparator trigger callback.
-  * @param  hcomp  COMP handle
-  * @retval None
-  */
-__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcomp);
-  
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_COMP_TriggerCallback should be implemented in the user file
-   */
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions 
- *  @brief   Peripheral State functions. 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permit to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the COMP handle state.
-  * @param  hcomp  COMP handle
-  * @retval HAL state
-  */
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
-{
-  /* Check the COMP handle allocation */
-  if(hcomp == NULL)
-  {
-    return HAL_COMP_STATE_RESET;
-  }
-
-  /* Check the parameter */
-  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-  /* Return HAL COMP handle state */
-  return hcomp->State;
-}
-
-/**
-  * @brief  Return the COMP error code.
-  * @param hcomp COMP handle
-  * @retval COMP error code
-  */
-uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
-{
-  /* Check the parameters */
-  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-  
-  return hcomp->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_COMP_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp_ex.c
deleted file mode 100644
index 361fd382d1..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp_ex.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_comp_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended COMP HAL module driver.
-  * @brief   This file provides firmware functions to manage voltage reference
-  *          VrefInt that must be specifically controled for comparator
-  *          instance COMP2.
-  @verbatim 
-  ==============================================================================
-               ##### COMP peripheral Extended features  #####
-  ==============================================================================
-
-  [..] Comparing to other previous devices, the COMP interface for STM32L0XX
-       devices contains the following additional features
-
-       (+) Possibility to enable or disable the VREFINT which is used as input
-           to the comparator.
-
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-#if !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-
-/** @addtogroup COMPEx
-  * @brief Extended COMP HAL module driver
-  * @{
-  */
-
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup COMP_Private_Constants
-  * @{
-  */
-
-/* Delay for COMP voltage scaler stabilization time (voltage from VrefInt,    */
-/* delay based on VrefInt startup time).                                      */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "TVREFINT").                                                     */
-/* Unit: us                                                                   */
-#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (3000U)  /*!< Delay for COMP voltage scaler stabilization time */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup COMPEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup COMPEx_Exported_Functions_Group1
-  * @brief  Extended functions to manage VREFINT for the comparator
-  *
-  * @{
-  */
-
-/**
-  * @brief  Enable Vrefint and path to comparator, used by comparator
-  *         instance COMP2 input based on VrefInt or subdivision of VrefInt.
-  * @note   The equivalent of this function is managed automatically when
-  *         using function "HAL_COMP_Init()".
-  * @note   VrefInt requires a startup time
-  *         (refer to device datasheet, parameter "TVREFINT").
-  *         This function waits for the startup time
-  *         (alternative solution: poll for bit SYSCFG_CFGR3_VREFINT_RDYF set).
-  * @note   VrefInt must be disabled before entering in low-power mode.
-  *         Refer to description of bit EN_VREFINT in reference manual.
-  * @retval None
-  */
-void HAL_COMPEx_EnableVREFINT(void)
-{
-  __IO uint32_t wait_loop_index = 0U;
-  
-  /* Enable VrefInt voltage reference and buffer */
-  SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP | SYSCFG_CFGR3_EN_VREFINT);
-  
-  /* Wait loop initialization and execution */
-  /* Note: Variable divided by 2 to compensate partially              */
-  /*       CPU processing cycles.                                     */
-  wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000U * 2U)));
-  while(wait_loop_index != 0U)
-  {
-    wait_loop_index--;
-  }
-}
-
-/**
-  * @brief  Disable Vrefint and path to comparator, used by comparator
-  *         instance COMP2 input based on VrefInt or subdivision of VrefInt.
-  * @note   VrefInt must be disabled before entering in low-power mode.
-  *         Refer to description of bit EN_VREFINT in reference manual.
-  * @retval None
-  */
-void HAL_COMPEx_DisableVREFINT(void)
-{
-  /* Disable VrefInt voltage reference and buffer */
-  SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP | SYSCFG_CFGR3_EN_VREFINT));
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-/**
-  * @}
-  */ 
-#endif /* #if !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c
deleted file mode 100644
index 4d0d72b8a4..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c
+++ /dev/null
@@ -1,415 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_cortex.c
-  * @author  MCD Application Team
-  * @brief   CORTEX HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the CORTEX:
-  *           + Initialization and Configuration functions
-  *           + Peripheral Control functions 
-  *
-  @verbatim  
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]  
-    *** How to configure Interrupts using CORTEX HAL driver ***
-    ===========================================================
-    [..]     
-    This section provides functions allowing to configure the NVIC interrupts (IRQ).
-    The Cortex M0+ exceptions are managed by CMSIS functions.
-      (#) Enable and Configure the priority of the selected IRQ Channels. 
-             The priority can be 0..3. 
-
-        -@- Lower priority values gives higher priority.
-        -@- Priority Order:
-            (#@) Lowest priority.
-            (#@) Lowest hardware priority (IRQn position).  
-    
-     (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() 
-
-     (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() 
-      
-    [..]  
-    *** How to configure Systick using CORTEX HAL driver ***
-    ========================================================
-    [..]
-    Setup SysTick Timer for time base.
-           
-   (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
-       is a CMSIS function that:
-        (++) Configures the SysTick Reload register with value passed as function parameter.
-        (++) Configures the SysTick IRQ priority to the lowest value (0x03).
-        (++) Resets the SysTick Counter register.
-        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
-        (++) Enables the SysTick Interrupt.
-        (++) Starts the SysTick Counter.
-	
-   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function
-       HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
-       HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() function is defined
-       inside the stm32l0xx_hal_cortex.c file.
-
-   (+) You can change the SysTick IRQ priority by calling the
-       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 
-       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
-
-   (+) To adjust the SysTick time base, use the following formula:
-                            
-       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
-       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
-       (++) Reload Value should not exceed 0xFFFFFF
-   
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/** @addtogroup CORTEX
-  * @brief CORTEX HAL module driver
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CORTEX_Exported_Functions
-  * @{
-  */
-
-
-/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and Configuration functions #####
-  ==============================================================================
-    [..]
-      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
-      Systick functionalities 
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets the priority of an interrupt.
-  * @param  IRQn External interrupt number .
-  *         This parameter can be an enumerator of  IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
-  * @param  PreemptPriority The pre-emption priority for the IRQn channel.
-  *         This parameter can be a value between 0 and 3.
-  *         A lower priority value indicates a higher priority 
-  * @param  SubPriority the subpriority level for the IRQ channel.
-  *         with stm32l0xx devices, this parameter is a dummy value and it is ignored, because 
-  *         no subpriority supported in Cortex M0+ based products.   
-  * @retval None
-  */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{ 
-    /* Check the parameters */
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-  NVIC_SetPriority(IRQn,PreemptPriority);
-}
-
-/**
-  * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
-  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
-  *         function should be called before. 
-  * @param  IRQn External interrupt number .
-  *         This parameter can be an enumerator of  IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)  
-  * @retval None
-  */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Enable interrupt */
-  NVIC_EnableIRQ(IRQn);
-}
-
-/**
-  * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
-  * @param  IRQn External interrupt number .
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)  
-  * @retval None
-  */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Disable interrupt */
-  NVIC_DisableIRQ(IRQn);
-}
-
-/**
-  * @brief  Initiate a system reset request to reset the MCU.
-  * @retval None
-  */
-void HAL_NVIC_SystemReset(void)
-{
-  /* System Reset */
-  NVIC_SystemReset();
-}
-
-/**
-  * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick)
-  *         Counter is in free running mode to generate periodic interrupts.
-  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
-  * @retval status:  - 0  Function succeeded.
-  *                  - 1  Function failed.
-  */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
-   return SysTick_Config(TicksNumb);
-}
-/**
-  * @}
-  */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 
- *  @brief   Cortex control functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================  
-    [..]
-      This subsection provides a set of functions allowing to control the CORTEX
-      (NVIC, SYSTICK) functionalities. 
- 
-      
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Gets the priority of an interrupt.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l0xxxx.h))
-  * @retval None
-  */
-uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
-{
-  /* Get priority for Cortex-M system or device specific interrupts */
-  return NVIC_GetPriority(IRQn);
-}
-
-/**
-  * @brief  Sets Pending bit of an external interrupt.
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)  
-  * @retval None
-  */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{ 
-  /* Set interrupt pending */
-  NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief  Get Pending Interrupt (read the pending register in the NVIC 
-  *         and return the pending bit for the specified interrupt).
-  * @param  IRQn External interrupt number .
-  *          This parameter can be an enumerator of  IRQn_Type enumeration
-  *          (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)  
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{ 
-  /* Return 1 if pending else 0 */
-  return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief  Clear the pending bit of an external interrupt.
-  * @param  IRQn External interrupt number .
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)  
-  * @retval None
-  */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{ 
-  /* Clear pending interrupt */
-  NVIC_ClearPendingIRQ(IRQn);
-}
-
-
-/**
-  * @brief  Configure the SysTick clock source.
-  * @param  CLKSource specifies the SysTick clock source.
-  *          This parameter can be one of the following values:
-  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
-  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
-  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
-  {
-    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
-  }
-  else
-  {
-    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
-  }
-}
-
-/**
-  * @brief  Handle SYSTICK interrupt request.
-  * @retval None
-  */
-void HAL_SYSTICK_IRQHandler(void)
-{
-  HAL_SYSTICK_Callback();
-}
-
-/**
-  * @brief  SYSTICK callback.
-  * @retval None
-  */
-__weak void HAL_SYSTICK_Callback(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SYSTICK_Callback could be implemented in the user file
-   */
-}
-
-#if (__MPU_PRESENT == 1U)
-/**
-  * @brief  Disable the MPU.
-  * @retval None
-  */
-void HAL_MPU_Disable(void)
-{
-
-  /*Data Memory Barrier setup */
-  __DMB();
-  /* Disable the MPU */
-  MPU->CTRL = 0;
-}
-
-/**
-  * @brief  Enable the MPU.
-  * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
-  *          NMI, FAULTMASK and privileged access to the default memory
-  *          This parameter can be one of the following values:
-  *            @arg MPU_HFNMI_PRIVDEF_NONE
-  *            @arg MPU_HARDFAULT_NMI
-  *            @arg MPU_PRIVILEGED_DEFAULT
-  *            @arg MPU_HFNMI_PRIVDEF
-  * @retval None
-  */
-
-void HAL_MPU_Enable(uint32_t MPU_Control)
-{
-  /* Enable the MPU */
-   MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
-  /* Data Synchronization Barrier setup */
-  __DSB();
-  /* Instruction Synchronization Barrier setup */
-  __ISB();
-
-}
-
-/**
-  * @brief  Initialize and configure the Region and the memory to be protected.
-  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
-  *                the initialization and configuration information.
-  * @retval None
-  */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-{
-  /* Check the parameters */
-  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
-  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
-  /* Set the Region number */
-  MPU->RNR = MPU_Init->Number;
-
-  if ((MPU_Init->Enable) == MPU_REGION_ENABLE)
-  {
-    /* Check the parameters */
-    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
-    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
-    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
-    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
-    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
-    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
-    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
-    /* Set the base adsress and set the 4 LSB to 0 */
-    MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0U;
-
-    /* Fill the field RASR */
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec        << MPU_RASR_XN_Pos)   |
-                ((uint32_t)MPU_Init->AccessPermission   << MPU_RASR_AP_Pos)   |
-                ((uint32_t)MPU_Init->IsShareable        << MPU_RASR_S_Pos)    |
-                ((uint32_t)MPU_Init->IsCacheable        << MPU_RASR_C_Pos)    |
-                ((uint32_t)MPU_Init->IsBufferable       << MPU_RASR_B_Pos)    |
-                ((uint32_t)MPU_Init->SubRegionDisable   << MPU_RASR_SRD_Pos)  |
-                ((uint32_t)MPU_Init->Size               << MPU_RASR_SIZE_Pos) |
-                ((uint32_t)MPU_Init->Enable             << MPU_RASR_ENABLE_Pos);
-  }
-  else
-  {
-    MPU->RBAR = 0x00U;
-    MPU->RASR = 0x00U;
-  }
-}
-#endif /* __MPU_PRESENT */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c
deleted file mode 100644
index 4f945ed1f9..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c
+++ /dev/null
@@ -1,518 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_crc.c
-  * @author  MCD Application Team
-  * @brief   CRC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
- ===============================================================================
-                     ##### How to use this driver #####
- ===============================================================================
-    [..]
-         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
-         (+) Initialize CRC calculator
-             (++) specify generating polynomial (peripheral default or non-default one)
-             (++) specify initialization value (peripheral default or non-default one)
-             (++) specify input data format
-             (++) specify input or output data inversion mode if any
-         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
-             input data buffer starting with the previously computed CRC as
-             initialization value
-         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
-             input data buffer starting with the defined initialization value
-             (default or non-default) to initiate CRC calculation
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CRC CRC
-  * @brief CRC HAL module driver.
-  * @{
-  */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CRC_Private_Functions CRC Private Functions
-  * @{
-  */
-static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
-static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
-  * @{
-  */
-
-/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions.
-  *
-@verbatim
- ===============================================================================
-            ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the CRC according to the specified parameters
-          in the CRC_InitTypeDef and create the associated handle
-      (+) DeInitialize the CRC peripheral
-      (+) Initialize the CRC MSP (MCU Specific Package)
-      (+) DeInitialize the CRC MSP
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the CRC according to the specified
-  *         parameters in the CRC_InitTypeDef and create the associated handle.
-  * @param  hcrc CRC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
-{
-  /* Check the CRC handle allocation */
-  if (hcrc == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
-  if (hcrc->State == HAL_CRC_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hcrc->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_CRC_MspInit(hcrc);
-  }
-
-  hcrc->State = HAL_CRC_STATE_BUSY;
-
-  /* check whether or not non-default generating polynomial has been
-   * picked up by user */
-  assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
-  if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
-  {
-    /* initialize peripheral with default generating polynomial */
-    WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
-    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
-  }
-  else
-  {
-    /* initialize CRC peripheral with generating polynomial defined by user */
-    if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  /* check whether or not non-default CRC initial value has been
-   * picked up by user */
-  assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
-  if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
-  {
-    WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
-  }
-  else
-  {
-    WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
-  }
-
-
-  /* set input data inversion mode */
-  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
-  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
-
-  /* set output data inversion mode */
-  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
-  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
-
-  /* makes sure the input data format (bytes, halfwords or words stream)
-   * is properly specified by user */
-  assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the CRC peripheral.
-  * @param  hcrc CRC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
-{
-  /* Check the CRC handle allocation */
-  if (hcrc == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
-  /* Check the CRC peripheral state */
-  if (hcrc->State == HAL_CRC_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-
-  /* Reset CRC calculation unit */
-  __HAL_CRC_DR_RESET(hcrc);
-
-  /* Reset IDR register content */
-  CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
-
-  /* DeInit the low level hardware */
-  HAL_CRC_MspDeInit(hcrc);
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_RESET;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hcrc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRC MSP.
-  * @param  hcrc CRC handle
-  * @retval None
-  */
-__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcrc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_CRC_MspInit can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize the CRC MSP.
-  * @param  hcrc CRC handle
-  * @retval None
-  */
-__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcrc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_CRC_MspDeInit can be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
-  *  @brief    management functions.
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
-          using combination of the previous CRC value and the new one.
-
-       [..]  or
-
-      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
-          independently of the previous CRC value.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
-  *         starting with the previously computed CRC as initialization value.
-  * @param  hcrc CRC handle
-  * @param  pBuffer pointer to the input data buffer, exact input data format is
-  *         provided by hcrc->InputDataFormat.
-  * @param  BufferLength input data buffer length (number of bytes if pBuffer
-  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
-  *         number of words if pBuffer type is * uint32_t).
-  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
-  *        Input buffer pointers with other types simply need to be cast in uint32_t
-  *        and the API will internally adjust its input data processing based on the
-  *        handle field hcrc->InputDataFormat.
-  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
-  */
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
-{
-  uint32_t index;      /* CRC input data buffer index */
-  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-
-  switch (hcrc->InputDataFormat)
-  {
-    case CRC_INPUTDATA_FORMAT_WORDS:
-      /* Enter Data to the CRC calculator */
-      for (index = 0U; index < BufferLength; index++)
-      {
-        hcrc->Instance->DR = pBuffer[index];
-      }
-      temp = hcrc->Instance->DR;
-      break;
-
-    case CRC_INPUTDATA_FORMAT_BYTES:
-      temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
-      break;
-
-    case CRC_INPUTDATA_FORMAT_HALFWORDS:
-      temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
-      break;
-    default:
-      break;
-  }
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_READY;
-
-  /* Return the CRC computed value */
-  return temp;
-}
-
-/**
-  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
-  *         starting with hcrc->Instance->INIT as initialization value.
-  * @param  hcrc CRC handle
-  * @param  pBuffer pointer to the input data buffer, exact input data format is
-  *         provided by hcrc->InputDataFormat.
-  * @param  BufferLength input data buffer length (number of bytes if pBuffer
-  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
-  *         number of words if pBuffer type is * uint32_t).
-  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
-  *        Input buffer pointers with other types simply need to be cast in uint32_t
-  *        and the API will internally adjust its input data processing based on the
-  *        handle field hcrc->InputDataFormat.
-  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
-  */
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
-{
-  uint32_t index;      /* CRC input data buffer index */
-  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-
-  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
-  *  written in hcrc->Instance->DR) */
-  __HAL_CRC_DR_RESET(hcrc);
-
-  switch (hcrc->InputDataFormat)
-  {
-    case CRC_INPUTDATA_FORMAT_WORDS:
-      /* Enter 32-bit input data to the CRC calculator */
-      for (index = 0U; index < BufferLength; index++)
-      {
-        hcrc->Instance->DR = pBuffer[index];
-      }
-      temp = hcrc->Instance->DR;
-      break;
-
-    case CRC_INPUTDATA_FORMAT_BYTES:
-      /* Specific 8-bit input data handling  */
-      temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
-      break;
-
-    case CRC_INPUTDATA_FORMAT_HALFWORDS:
-      /* Specific 16-bit input data handling  */
-      temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
-      break;
-
-    default:
-      break;
-  }
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_READY;
-
-  /* Return the CRC computed value */
-  return temp;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
-  *  @brief    Peripheral State functions.
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the CRC handle state.
-  * @param  hcrc CRC handle
-  * @retval HAL state
-  */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
-{
-  /* Return CRC handle state */
-  return hcrc->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup CRC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Enter 8-bit input data to the CRC calculator.
-  *         Specific data handling to optimize processing time.
-  * @param  hcrc CRC handle
-  * @param  pBuffer pointer to the input data buffer
-  * @param  BufferLength input data buffer length
-  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
-  */
-static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
-{
-  uint32_t i; /* input data buffer index */
-  uint16_t data;
-  __IO uint16_t *pReg;
-
-  /* Processing time optimization: 4 bytes are entered in a row with a single word write,
-   * last bytes must be carefully fed to the CRC calculator to ensure a correct type
-   * handling by the peripheral */
-  for (i = 0U; i < (BufferLength / 4U); i++)
-  {
-    hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
-                         ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
-                         ((uint32_t)pBuffer[(4U * i) + 2U] << 8U)  | \
-                         (uint32_t)pBuffer[(4U * i) + 3U];
-  }
-  /* last bytes specific handling */
-  if ((BufferLength % 4U) != 0U)
-  {
-    if ((BufferLength % 4U) == 1U)
-    {
-      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i];         /* Derogation MisraC2012 R.11.5 */
-    }
-    if ((BufferLength % 4U) == 2U)
-    {
-      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
-      pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
-      *pReg = data;
-    }
-    if ((BufferLength % 4U) == 3U)
-    {
-      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
-      pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
-      *pReg = data;
-
-      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U];  /* Derogation MisraC2012 R.11.5 */
-    }
-  }
-
-  /* Return the CRC computed value */
-  return hcrc->Instance->DR;
-}
-
-/**
-  * @brief  Enter 16-bit input data to the CRC calculator.
-  *         Specific data handling to optimize processing time.
-  * @param  hcrc CRC handle
-  * @param  pBuffer pointer to the input data buffer
-  * @param  BufferLength input data buffer length
-  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
-  */
-static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
-{
-  uint32_t i;  /* input data buffer index */
-  __IO uint16_t *pReg;
-
-  /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
-   * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
-   * a correct type handling by the peripheral */
-  for (i = 0U; i < (BufferLength / 2U); i++)
-  {
-    hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
-  }
-  if ((BufferLength % 2U) != 0U)
-  {
-    pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                 /* Derogation MisraC2012 R.11.5 */
-    *pReg = pBuffer[2U * i];
-  }
-
-  /* Return the CRC computed value */
-  return hcrc->Instance->DR;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CRC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c
deleted file mode 100644
index 1cd4442430..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_crc_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended CRC HAL module driver.
-  *          This file provides firmware functions to manage the extended
-  *          functionalities of the CRC peripheral.
-  *
-  @verbatim
-================================================================================
-            ##### How to use this driver #####
-================================================================================
-    [..]
-         (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
-         (+) Configure Input or Output data inversion
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CRCEx CRCEx
-  * @brief CRC Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
-  * @{
-  */
-
-/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
-  * @brief    Extended Initialization and Configuration functions.
-  *
-@verbatim
- ===============================================================================
-            ##### Extended configuration functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure the generating polynomial
-      (+) Configure the input data inversion
-      (+) Configure the output data inversion
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Initialize the CRC polynomial if different from default one.
-  * @param  hcrc CRC handle
-  * @param  Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
-  *         This parameter is written in normal representation, e.g.
-  *         @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
-  *         @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
-  * @param  PolyLength CRC polynomial length.
-  *         This parameter can be one of the following values:
-  *          @arg @ref CRC_POLYLENGTH_7B  7-bit long CRC (generating polynomial of degree 7)
-  *          @arg @ref CRC_POLYLENGTH_8B  8-bit long CRC (generating polynomial of degree 8)
-  *          @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
-  *          @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
-
-  /* Check the parameters */
-  assert_param(IS_CRC_POL_LENGTH(PolyLength));
-
-  /* check polynomial definition vs polynomial size:
-   * polynomial length must be aligned with polynomial
-   * definition. HAL_ERROR is reported if Pol degree is
-   * larger than that indicated by PolyLength.
-   * Look for MSB position: msb will contain the degree of
-   *  the second to the largest polynomial member. E.g., for
-   *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
-  while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
-  {
-  }
-
-  switch (PolyLength)
-  {
-    case CRC_POLYLENGTH_7B:
-      if (msb >= HAL_CRC_LENGTH_7B)
-      {
-        status =   HAL_ERROR;
-      }
-      break;
-    case CRC_POLYLENGTH_8B:
-      if (msb >= HAL_CRC_LENGTH_8B)
-      {
-        status =   HAL_ERROR;
-      }
-      break;
-    case CRC_POLYLENGTH_16B:
-      if (msb >= HAL_CRC_LENGTH_16B)
-      {
-        status =   HAL_ERROR;
-      }
-      break;
-
-    case CRC_POLYLENGTH_32B:
-      /* no polynomial definition vs. polynomial length issue possible */
-      break;
-    default:
-      status =  HAL_ERROR;
-      break;
-  }
-  if (status == HAL_OK)
-  {
-    /* set generating polynomial */
-    WRITE_REG(hcrc->Instance->POL, Pol);
-
-    /* set generating polynomial size */
-    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
-  }
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Set the Reverse Input data mode.
-  * @param  hcrc CRC handle
-  * @param  InputReverseMode Input Data inversion mode.
-  *         This parameter can be one of the following values:
-  *          @arg @ref CRC_INPUTDATA_INVERSION_NONE     no change in bit order (default value)
-  *          @arg @ref CRC_INPUTDATA_INVERSION_BYTE     Byte-wise bit reversal
-  *          @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
-  *          @arg @ref CRC_INPUTDATA_INVERSION_WORD     Word-wise bit reversal
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
-{
-  /* Check the parameters */
-  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-
-  /* set input data inversion mode */
-  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the Reverse Output data mode.
-  * @param  hcrc CRC handle
-  * @param  OutputReverseMode Output Data inversion mode.
-  *         This parameter can be one of the following values:
-  *          @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
-  *          @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE  bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
-{
-  /* Check the parameters */
-  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-
-  /* set output data inversion mode */
-  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-#endif /* HAL_CRC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c
deleted file mode 100644
index b536844f7a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c
+++ /dev/null
@@ -1,2161 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_cryp.c
-  * @author  MCD Application Team
-  * @brief   CRYP HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Cryptography (CRYP) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Processing functions by algorithm using polling mode
-  *           + Processing functions by algorithm using interrupt mode
-  *           + Processing functions by algorithm using DMA mode
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The CRYP HAL driver can be used as follows:
-
-      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
-         (##) Enable the CRYP interface clock using __HAL_RCC_AES_CLK_ENABLE()
-         (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
-             (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
-             (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
-             (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
-         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
-             (+) Enable the DMA1 interface clock using 
-                 (++) __HAL_RCC_DMA1_CLK_ENABLE()
-             (+) Configure and enable two DMA Channels one for managing data transfer from
-                 memory to peripheral (input channel) and another channel for managing data
-                 transfer from peripheral to memory (output channel)
-             (+) Associate the initialized DMA handle to the CRYP DMA handle
-                 using  __HAL_LINKDMA()
-             (+) Configure the priority and enable the NVIC for the transfer complete
-                 interrupt on the two DMA Streams. The output stream should have higher
-                 priority than the input stream.
-                 (++) HAL_NVIC_SetPriority()
-                 (++) HAL_NVIC_EnableIRQ()
-    
-      (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
-         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
-         (##) The encryption/decryption key.
-         (##) The initialization vector (counter). It is not used ECB mode.
-    
-      (#)Three processing (encryption/decryption) functions are available:
-         (##) Polling mode: encryption and decryption APIs are blocking functions
-              i.e. they process the data and wait till the processing is finished
-              e.g. HAL_CRYP_AESCBC_Encrypt()
-         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
-              i.e. they process the data under interrupt
-              e.g. HAL_CRYP_AESCBC_Encrypt_IT()
-         (##) DMA mode: encryption and decryption APIs are not blocking functions
-              i.e. the data transfer is ensured by DMA
-              e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
-    
-      (#)When the processing function is called for the first time after HAL_CRYP_Init()
-         the CRYP peripheral is initialized and processes the buffer in input.
-         At second call, the processing function performs an append of the already
-         processed buffer.
-         When a new data block is to be processed, call HAL_CRYP_Init() then the
-         processing function.
-         
-      (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */ 
-
-#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CRYP
-  * @brief CRYP HAL module driver.
-  * @{
-  */
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @addtogroup CRYP_Private CRYP Private
-  * @{
-  */
-
-#define  CRYP_ALGO_CHAIN_MASK         (AES_CR_MODE | AES_CR_CHMOD)
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @addtogroup CRYP_Private
-  * @{
-  */
-
-static HAL_StatusTypeDef  CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp);
-static void               CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
-static void               CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key);
-static HAL_StatusTypeDef  CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
-static void               CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
-static void               CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
-static void               CRYP_DMAError(DMA_HandleTypeDef *hdma);
-static void               CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup CRYP_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions. 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the CRYP according to the specified parameters 
-          in the CRYP_InitTypeDef and creates the associated handle
-      (+) DeInitialize the CRYP peripheral
-      (+) Initialize the CRYP MSP
-      (+) DeInitialize CRYP MSP 
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CRYP according to the specified
-  *         parameters in the CRYP_InitTypeDef and creates the associated handle.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
-{ 
-  /* Check the CRYP handle allocation */
-  if(hcryp == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance));
-  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
-  
-  if(hcryp->State == HAL_CRYP_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hcryp->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware */
-    HAL_CRYP_MspInit(hcryp);
-  }
-  
-  /* Check if AES already enabled */
-  if (HAL_IS_BIT_CLR(hcryp->Instance->CR, AES_CR_EN))
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;  
-
-    /* Set the data type*/
-    MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-    
-    /* Reset CrypInCount and CrypOutCount */
-    hcryp->CrypInCount = 0U;
-    hcryp->CrypOutCount = 0U;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Set the default CRYP phase */
-    hcryp->Phase = HAL_CRYP_PHASE_READY;
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is */
-    /* enabled is forbidden to avoid unpredictable AES behavior.*/
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-
-}
-
-/**
-  * @brief  DeInitializes the CRYP peripheral. 
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
-{
-  /* Check the CRYP handle allocation */
-  if(hcryp == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set the default CRYP phase */
-  hcryp->Phase = HAL_CRYP_PHASE_READY;
-  
-  /* Reset CrypInCount and CrypOutCount */
-  hcryp->CrypInCount = 0U;
-  hcryp->CrypOutCount = 0U;
-  
-  /* Disable the CRYP Peripheral Clock */
-  __HAL_CRYP_DISABLE(hcryp);
-  
-  /* DeInit the low level hardware: CLOCK, NVIC.*/
-  HAL_CRYP_MspDeInit(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_RESET;
-  
-  /* Release Lock */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP MSP.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcryp);
-
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_MspInit can be implemented in the user file */
-}
-
-/**
-  * @brief  DeInitializes CRYP MSP.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcryp);
-
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_MspDeInit can be implemented in the user file */
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup CRYP_Exported_Functions_Group2
- *  @brief   processing functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### AES processing functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Encrypt plaintext using AES algorithm in different chaining modes
-      (+) Decrypt cyphertext using AES algorithm in different chaining modes
-    [..]  Three processing functions are available:
-      (+) Polling mode
-      (+) Interrupt mode
-      (+) DMA mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Timeout Specify Timeout value 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-
-  /* Check that data aligned on u32 and Size multiple of 16*/
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-	
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Timeout Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Timeout Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{  
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Timeout Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Cypher Data and Get Plain Data */
-    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Timeout Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Cypher Data and Get Plain Data */
-    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Timeout Specify Timeout value   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{  
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if initialization phase has already been performed */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->Phase == HAL_CRYP_PHASE_READY))
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey);
-    
-    /* Reset the CHMOD & MODE bits */
-    CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-    
-    /* Set the CRYP peripheral in AES CTR decryption mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
-    
-    /* Set the Initialization Vector */
-    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-  
-  /* Write Cypher Data and Get Plain Data */
-  if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0U;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16U;
-    hcryp->CrypInCount -= 16U;
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0U;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16U;
-    hcryp->CrypInCount -= 16U;
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-   
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0U;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16U;
-    hcryp->CrypInCount -= 16U;
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr = 0U;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16U;
-    hcryp->CrypInCount -= 16U;    
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC decryption mode using IT.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr = 0U;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16U;
-    hcryp->CrypInCount -= 16U;    
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr = 0U;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CTR decryption mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16U;
-    hcryp->CrypInCount -= 16U;    
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0U, outputaddr = 0U;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {  
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0U, outputaddr = 0U;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Set the CRYP peripheral in AES CBC mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0U, outputaddr = 0U;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{  
-  uint32_t inputaddr = 0U, outputaddr = 0U;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr = 0U, outputaddr = 0U;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{  
-  uint32_t inputaddr = 0U, outputaddr = 0U;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup CRYP_Exported_Functions_Group3
- *  @brief   DMA callback functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### DMA callback functions  #####
-  ==============================================================================  
-    [..]  This section provides DMA callback functions:
-      (+) DMA Input data transfer complete
-      (+) DMA Output data transfer complete
-      (+) DMA error
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  CRYP error callback.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
- __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcryp);
-
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_ErrorCallback can be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Input transfer completed callback.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcryp);
-
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_InCpltCallback can be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Output transfer completed callback.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcryp);
-
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_OutCpltCallback can be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup CRYP_Exported_Functions_Group4
- *  @brief   CRYP IRQ handler.
- *
-@verbatim   
-  ==============================================================================
-                ##### CRYP IRQ handler management #####
-  ==============================================================================  
-[..]  This section provides CRYP IRQ handler function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  This function handles CRYP interrupt request.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
-{
-  /* Check if error occurred*/
-  if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERR) != RESET)
-  {
-    if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_RDERR) != RESET)
-    {
-      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_RDERR);
-    }
-    
-    if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_WRERR) != RESET)
-    {
-      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_WRERR);
-    }
-    
-    if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_CCF) != RESET)
-    {
-      __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CLEARFLAG_CCF);
-    }
-    
-    hcryp->State= HAL_CRYP_STATE_ERROR;
-    /* Disable Computation Complete Interrupt */
-    __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC);
-    __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR);
-    
-    HAL_CRYP_ErrorCallback(hcryp);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    return;
-  }
-  
-  /* Check if computation complete interrupt was enabled*/
-  if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CC) != RESET)
-  {
-    /* Clear CCF Flag */
-    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
-  
-    CRYP_EncryptDecrypt_IT(hcryp);
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup CRYP_Exported_Functions_Group5
- *  @brief   Peripheral State functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral State functions #####
-  ==============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the CRYP state.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL state
-  */
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
-{
-  return hcryp->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup CRYP_Private
-  * @{
-  */
-
-/**
-  * @brief  IT function called under interruption context to continue encryption or decryption
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp)
-{
-  uint32_t inputaddr = 0U, outputaddr = 0U;
-
-  /* Get the last Output data adress */
-  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-  
-  /* Read the Output block from the Output Register */
-  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-  outputaddr+=4U;
-  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-  outputaddr+=4U;
-  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-  outputaddr+=4U;
-  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-  
-  hcryp->pCrypOutBuffPtr += 16U;
-  hcryp->CrypOutCount -= 16U;
-  
-  /* Check if all input text is encrypted or decrypted */
-  if(hcryp->CrypOutCount == 0U)
-  {
-    /* Disable Computation Complete Interrupt */
-    __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC);
-    __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Call computation complete callback */
-    HAL_CRYPEx_ComputationCpltCallback(hcryp);
-  }
-  else /* Process the rest of input text */
-  {
-    /* Get the last Intput data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16U;
-    hcryp->CrypInCount -= 16U;      
-  }
-  return HAL_OK;
-}
-/**
-  * @brief  DMA CRYP Input Data process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)  
-{
-  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Disable the DMA transfer for input request  */
-  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
-  
-  /* Call input data transfer complete callback */
-  HAL_CRYP_InCpltCallback(hcryp);
-}
-
-/**
-  * @brief  DMA CRYP Output Data process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
-  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Disable the DMA transfer for output request by resetting the DMAOUTEN bit
-     in the DMACR register */
-  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
-
-  /* Clear CCF Flag */
-  __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
-
-  /* Disable CRYP */
-  __HAL_CRYP_DISABLE(hcryp);
-  
-  /* Change the CRYP state to ready */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Call output data transfer complete callback */
-  HAL_CRYP_OutCpltCallback(hcryp);
-}
-
-/**
-  * @brief  DMA CRYP communication error callback. 
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
-{
-  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  hcryp->State= HAL_CRYP_STATE_ERROR;
-  HAL_CRYP_ErrorCallback(hcryp);
-}
-
-/**
-  * @brief  Writes the Key in Key registers. 
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  Key Pointer to Key buffer
-  * @note Key must be written as little endian.
-  *         If Key pointer points at address n, 
-  *         n[15:0] contains key[96:127], 
-  *         (n+4)[15:0] contains key[64:95], 
-  *         (n+8)[15:0] contains key[32:63] and 
-  *         (n+12)[15:0] contains key[0:31]
-  * @retval None
-  */
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key)
-{  
-  uint32_t keyaddr = (uint32_t)Key;
-  
-  hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
-  keyaddr+=4U;
-  hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
-  keyaddr+=4U;
-  hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
-  keyaddr+=4U;
-  hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
-}
-
-/**
-  * @brief  Writes the InitVector/InitCounter in IV registers. 
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  InitVector Pointer to InitVector/InitCounter buffer
-  * @note Init Vector must be written as little endian.
-  *         If Init Vector pointer points at address n, 
-  *         n[15:0] contains Vector[96:127], 
-  *         (n+4)[15:0] contains Vector[64:95], 
-  *         (n+8)[15:0] contains Vector[32:63] and 
-  *         (n+12)[15:0] contains Vector[0:31]
-  * @retval None
-  */
-static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
-{
-  uint32_t ivaddr = (uint32_t)InitVector;
-  
-  hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
-  ivaddr+=4U;
-  hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
-  ivaddr+=4U;
-  hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
-  ivaddr+=4U;
-  hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
-}
-
-/**
-  * @brief  Process Data: Writes Input data in polling mode and reads the output data
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  Input Pointer to the Input buffer
-  * @param  Ilength Length of the Input buffer, must be a multiple of 16.
-  * @param  Output Pointer to the returned buffer
-  * @param  Timeout Specify Timeout value  
-  * @retval None
-  */
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U;
-  
-  uint32_t index = 0U;
-  uint32_t inputaddr  = (uint32_t)Input;
-  uint32_t outputaddr = (uint32_t)Output;
-  
-  for(index=0U; (index < Ilength); index += 16U)
-  {
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4U;
-    
-    /* Get timeout */
-    tickstart = HAL_GetTick();
-    
-    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
-    {    
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Change state */
-          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-          
-          /* Process Unlocked */          
-          __HAL_UNLOCK(hcryp);
-          
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    /* Clear CCF Flag */
-    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
-    
-    /* Read the Output block from the Data Output Register */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-    outputaddr+=4U;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-    outputaddr+=4U;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-    outputaddr+=4U;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-    outputaddr+=4U;
-  }
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the DMA configuration and start the DMA transfer
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  inputaddr address of the Input buffer
-  * @param  Size Size of the Input buffer, must be a multiple of 16.
-  * @param  outputaddr address of the Output buffer
-  * @retval None
-  */
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
-  /* Set the CRYP DMA transfer complete callback */
-  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
-  /* Set the DMA error callback */
-  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
-  
-  /* Set the CRYP DMA transfer complete callback */
-  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
-  /* Set the DMA error callback */
-  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
-
-  /* Enable the DMA In DMA Stream */
-  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);
-
-  /* Enable the DMA Out DMA Stream */
-  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);
-
-  /* Enable In and Out DMA requests */
-  SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
-
-  /* Enable CRYP */
-  __HAL_CRYP_ENABLE(hcryp);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CRYP_MODULE_ENABLED */
-#endif /* STM32L021xx || STM32L041xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp_ex.c
deleted file mode 100644
index a268eaf11c..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp_ex.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_cryp_ex.c
-  * @author  MCD Application Team
-  * @brief   CRYPEx HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Cryptography (CRYP) extension peripheral:
-  *           + Computation completed callback.
-  *         
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */ 
-
-#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-#ifdef HAL_CRYP_MODULE_ENABLED
-
-
-/** @addtogroup CRYPEx
-  * @brief CRYP HAL Extended module driver.
-  * @{
-  */
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup CRYPEx_Exported_Functions
-  * @{
-  */
-
-
-/** @addtogroup CRYPEx_Exported_Functions_Group1
- *  @brief    Extended features functions. 
- *
-@verbatim   
- ===============================================================================
-                 ##### Extended features functions #####
- =============================================================================== 
-    [..]  This section provides callback functions:
-      (+) Computation completed.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Computation completed callbacks.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcryp);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CRYP_ComputationCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-#endif /* STM32L021xx || STM32L041xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac.c
deleted file mode 100644
index abb9967ec9..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac.c
+++ /dev/null
@@ -1,1027 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_dac.c
-  * @author  MCD Application Team
-  * @brief   DAC HAL module driver.
-  *         This file provides firmware functions to manage the following
-  *         functionalities of the Digital to Analog Converter (DAC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions      
-  *     
-  *
-  @verbatim
-  ==============================================================================
-                      ##### DAC Peripheral features #####
-  ==============================================================================
-    [..]        
-      *** DAC Channels ***
-      ====================
-    [..]  
-    STM32L0 devices integrate one or two 12-bit Digital Analog Converters
-    (i.e. one or 2 channel(s))
-    1 channel : STM32L05x STM32L06x devices
-    2 channels: STM32L07x STM32L08x devices
-
-    When 2 channels are available, the 2 converters (i.e. channel1 & channel2)
-    can be used independently or simultaneously (dual mode):
-      (#) DAC channel1 with DAC_OUT1 (PA4) as output
-      (#) DAC channel2 with DAC_OUT2 (PA5) as output (STM32L07x/STM32L08x only)
-      (#) Channel1 & channel2 can be used independently or simultaneously in dual mode (STM32L07x/STM32L08x only)
-  
-      *** DAC Triggers ***
-      ====================
-    [..]
-    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
-    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
-    [..]
-    Digital to Analog conversion can be triggered by:
-      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
-          The used pin (GPIOx_PIN_9) must be configured in input mode.
-
-      (#) Timers TRGO: 
-          STM32L05x/STM32L06x : TIM2, TIM6 and TIM21
-          STM32L07x/STM32L08x : TIM2, TIM3, TIM6, TIM7 and TIM21
-          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T6_TRGO...)
-
-      (#) Software using DAC_TRIGGER_SOFTWARE
-
-      *** DAC Buffer mode feature ***
-      ===============================
-      [..] 
-      Each DAC channel integrates an output buffer that can be used to
-      reduce the output impedance, and to drive external loads directly
-      without having to add an external operational amplifier.
-      To enable, the output buffer use
-      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
-      [..]
-      (@) Refer to the device datasheet for more details about output
-          impedance value with and without output buffer.
-
-       *** DAC wave generation feature ***
-       ===================================
-       [..]
-       Both DAC channels can be used to generate
-         (#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
-         (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()
-
-       *** DAC data format ***
-       =======================
-       [..]
-       The DAC data format can be:
-         (#) 8-bit right alignment using DAC_ALIGN_8B_R
-         (#) 12-bit left alignment using DAC_ALIGN_12B_L
-         (#) 12-bit right alignment using DAC_ALIGN_12B_R
-
-       *** DAC data value to voltage correspondence ***
-       ================================================
-       [..]
-       The analog output voltage on each DAC channel pin is determined
-       by the following equation: 
-       [..]
-       DAC_OUTx = VREF+ * DOR / 4095
-       (+) with  DOR is the Data Output Register
-       [..]
-          VEF+ is the input voltage reference (refer to the device datasheet)
-       [..]
-        e.g. To set DAC_OUT1 to 0.7V, use
-       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-
-       *** DMA requests  ***
-       =====================
-       [..]
-       A DMA1 request can be generated when an external trigger (but not a software trigger)
-       occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
-       DMA1 requests are mapped as following:
-         (#) DAC channel1 : mapped on DMA1 Request9 channel2 which must be
-             already configured
-         (#) DAC channel2 : mapped on DMA1 Request15 channel4 which must be 
-             already configured (STM32L07x/STM32L08x only)
-       
-    -@- For Dual mode (STM32L07x/STM32L08x only) and specific signal (Triangle and noise) generation please 
-        refer to Extension Features Driver description        
-
-
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (+) DAC APB clock must be enabled to get write access to DAC
-          registers using HAL_DAC_Init()
-      (+) Configure DAC_OUT1: PA4 in analog mode.
-      (+) Configure DAC_OUT2: PA5 in analog mode (STM32L07x/STM32L08x only).
-      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
-      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Start the DAC peripheral using HAL_DAC_Start() 
-       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
-       (+) Stop the DAC peripheral using HAL_DAC_Stop()
-       
-     *** DMA mode IO operation ***    
-     ==============================
-     [..]    
-       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length 
-           of data to be transferred at each end of conversion
-       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1()or HAL_DAC_ConvHalfCpltCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
-           HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2
-       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
-           HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
-       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can 
-           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
-       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
-           HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DAC_DMAUnderrunCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
-           HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DAC_DMAUnderrunCallbackCh2
-           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
-       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
-
-    *** Callback registration ***
-    =============================================
-    [..]
-      The compilation define  USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
-      allows the user to configure dynamically the driver callbacks.
-
-    Use Functions HAL_DAC_RegisterCallback() to register a user callback,
-      it allows to register following callbacks:
-      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.                 
-      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
-      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
-      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
-      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.   
-      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.        
-      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.                
-      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
-      (+) MspInitCallback         : DAC MspInit.  
-      (+) MspDeInitCallback       : DAC MspdeInit.
-      This function takes as parameters the HAL peripheral handle, the Callback ID
-      and a pointer to the user callback function.
-
-    Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function. It allows to reset following callbacks:
-      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.                 
-      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
-      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
-      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
-      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.   
-      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.        
-      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.                
-      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
-      (+) MspInitCallback         : DAC MspInit.  
-      (+) MspDeInitCallback       : DAC MspdeInit.
-      (+) All Callbacks
-      This function) takes as parameters the HAL peripheral handle and the Callback ID.
-
-      By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
-      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
-      Exception done for MspInit and MspDeInit callbacks that are respectively
-      reset to the legacy weak (surcharged) functions in the HAL_DAC_Init 
-      and  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
-      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
-      Callbacks can be registered/unregistered in READY state only.
-      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
-      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
-      during the Init/DeInit.
-      In that case first register the MspInit/MspDeInit user callbacks
-      using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit 
-      or HAL_DAC_Init function.
-
-      When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
-      not defined, the callback registering feature is not available 
-      and weak (surcharged) callbacks are used.
-
-     *** DAC HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in DAC HAL driver.
-       
-      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
-      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
-      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
-      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
-      
-     [..]
-      (@) You can refer to the DAC HAL driver header file for more useful macros  
-   
- @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-
-#if !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) && !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-#ifdef HAL_DAC_MODULE_ENABLED
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DAC
-  * @brief DAC driver modules
-  * @{
-  */
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup DAC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group1
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the DAC.
-      (+) De-initialize the DAC.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the DAC peripheral according to the specified parameters
-  *         in the DAC_InitStruct and initialize the associated handle.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
-{
-  /* Check DAC handle */
-  if(hdac == NULL)
-  {
-     return HAL_ERROR;
-  }
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
-  if(hdac->State == HAL_DAC_STATE_RESET)
-  {
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-    /* Init the DAC Callback settings */
-    hdac->ConvCpltCallbackCh1           = HAL_DAC_ConvCpltCallbackCh1;
-    hdac->ConvHalfCpltCallbackCh1       = HAL_DAC_ConvHalfCpltCallbackCh1;
-    hdac->ErrorCallbackCh1              = HAL_DAC_ErrorCallbackCh1;
-    hdac->DMAUnderrunCallbackCh1        = HAL_DAC_DMAUnderrunCallbackCh1;
-
-#if defined (DAC_CHANNEL2_SUPPORT)
-    hdac->ConvCpltCallbackCh2           = HAL_DACEx_ConvCpltCallbackCh2;
-    hdac->ConvHalfCpltCallbackCh2       = HAL_DACEx_ConvHalfCpltCallbackCh2;
-    hdac->ErrorCallbackCh2              = HAL_DACEx_ErrorCallbackCh2;
-    hdac->DMAUnderrunCallbackCh2        = HAL_DACEx_DMAUnderrunCallbackCh2;
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-    if(hdac->MspInitCallback == NULL)
-    {
-      hdac->MspInitCallback               = HAL_DAC_MspInit;
-    }
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-    /* Allocate lock resource and initialize it */
-    hdac->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-    /* Init the low level hardware */
-    hdac->MspInitCallback(hdac);
-#else
-    /* Init the low level hardware */
-    HAL_DAC_MspInit(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-  }
-
-  /* Initialize the DAC state*/
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Set DAC error code to none */
-  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
-  /* Initialize the DAC state*/
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deinitialize the DAC peripheral registers to their default reset values.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
-{
-  /* Check DAC handle */
-  if(hdac == NULL)
-  {
-     return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  if(hdac->MspDeInitCallback == NULL)
-  {
-    hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  hdac->MspDeInitCallback(hdac);
-#else
-  /* DeInit the low level hardware */
-  HAL_DAC_MspDeInit(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-  /* Set DAC error code to none */
-  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_RESET;
-  
-  /* Release Lock */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the DAC MSP.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize the DAC MSP.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.  
-  * @retval None
-  */
-__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group2
- *  @brief    IO operation functions 
- *
-@verbatim
-  ==============================================================================
-             ##### IO operation functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start conversion.
-      (+) Stop conversion.
-      (+) Start conversion and enable DMA transfer.
-      (+) Stop conversion and disable DMA transfer.
-      (+) Get result of conversion.
-      (+) Get result of dual mode conversion (STM32L07xx/STM32L08xx only)
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  UNUSED(Channel);
-
-  /* Note : This function is defined into this file for library reference. */
-  /*        Function content is located into file stm32l0xx_hal_dac_ex.c   */
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Disable the Peripheral */
-  __HAL_DAC_DISABLE(hdac, Channel);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables DAC and starts conversion of channel using DMA.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
-  * @param  pData The destination peripheral Buffer address.
-  * @param  Length The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment Specifies the data alignment for DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  UNUSED(Channel);
-  UNUSED(pData);
-  UNUSED(Length);
-  UNUSED(Alignment);
-
-  /* Note : This function is defined into this file for library reference. */
-  /*        Function content is located into file stm32l0xx_hal_dac_ex.c   */
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  UNUSED(Channel);
-
-  /* Note : This function is defined into this file for library reference. */
-  /*        Function content is located into file stm32l0xx_hal_dac_ex.c   */
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
-  * @retval The selected DAC channel data output value.
-  */
-__weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  UNUSED(Channel);
-
-  /* Note : This function is defined into this file for library reference. */
-  /*        Function content is located into file stm32l0xx_hal_dac_ex.c   */
-
-  /* Return function status */
-  return 0U;
-}
-
-/**
-  * @brief  Handles DAC interrupt request
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* Note : This function is defined into this file for library reference. */
-  /*        Function content is located into file stm32l0xx_hal_dac_ex.c   */
-
-}
-
-/**
-  * @brief  Conversion complete callback in non-blocking mode for Channel1
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel1
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error DAC callback for Channel1.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA underrun DAC callback for channel1.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-  
-/** @addtogroup DAC_Exported_Functions_Group3
- *  @brief    Peripheral Control functions 
- *
-@verbatim
-  ==============================================================================
-             ##### Peripheral Control functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure channels.
-      (+) Set the specified data holding register value for DAC channel.
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the selected DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  sConfig DAC configuration structure.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
-{
-  uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
-
-  /* Check the DAC parameters */
-  assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
-  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Get the DAC CR value */
-  tmpreg1 = hdac->Instance->CR;
-  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
-  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
-  /* Configure for the selected DAC channel: buffer output, trigger */
-  /* Set TSELx and TENx bits according to DAC_Trigger value */
-  /* Set BOFFx bit according to DAC_OutputBuffer value */   
-  tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
-  /* Calculate CR register value depending on DAC_Channel */
-  tmpreg1 |= tmpreg2 << Channel;
-  /* Write to DAC CR */
-  hdac->Instance->CR = tmpreg1;
-  /* Disable wave generation */
-  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << Channel));
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group4
- *  @brief   Peripheral State and Errors functions 
- *
-@verbatim
-  ==============================================================================
-            ##### Peripheral State and Errors functions #####
-  ==============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DAC state.
-      (+) Check the DAC Errors.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  return the DAC handle state
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL state
-  */
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
-{
-  /* Return DAC handle state */
-  return hdac->State;
-}
-
-
-/**
-  * @brief  Return the DAC error code
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval DAC Error Code
-  */
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
-{
-  return hdac->ErrorCode;
-}
-
-/**
-  * @brief  Set the specified data holding register value for DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
-  * @param  Alignment Specifies the data alignment.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data Data to be loaded in the selected data holding register.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  UNUSED(Channel);
-  UNUSED(Alignment);
-  UNUSED(Data);
-  /* Note : This function is defined into this file for library reference. */
-  /*        Function content is located into file stm32l0xx_hal_dac_ex.c   */
-
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User DAC Callback
-  *         To be used instead of the weak (surcharged) predefined callback 
-  * @param hdac DAC handle
-  * @param CallbackID ID of the callback to be registered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK   DAC Error Callback ID
-  *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID       DAC CH1 Complete Callback ID
-  *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID  DAC CH1 Half Complete Callback ID
-  *          @arg @ref HAL_DAC_CH1_ERROR_ID             DAC CH1 Error Callback ID
-  *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID       DAC CH1 UnderRun Callback ID
-  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID       DAC CH2 Complete Callback ID      
-  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID  DAC CH2 Half Complete Callback ID 
-  *          @arg @ref HAL_DAC_CH2_ERROR_ID             DAC CH2 Error Callback ID         
-  *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID       DAC CH2 UnderRun Callback ID         
-  *          @arg @ref HAL_DAC_MSP_INIT_CB_ID           DAC MSP Init Callback ID        
-  *          @arg @ref HAL_DAC_MSP_DEINIT_CB_ID         DAC MSP DeInit Callback ID   
-  *
-    * @param pCallback pointer to the Callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId, pDAC_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if(pCallback == NULL)
-  {
-    /* Update the error code */
-    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  if(hdac->State == HAL_DAC_STATE_READY)
-  {
-    switch (CallbackId)
-    {
-    case HAL_DAC_CH1_COMPLETE_CB_ID :
-      hdac->ConvCpltCallbackCh1 = pCallback;
-      break;
-    case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
-      hdac->ConvHalfCpltCallbackCh1 = pCallback;
-      break;
-    case HAL_DAC_CH1_ERROR_ID :
-      hdac->ErrorCallbackCh1 = pCallback;
-      break;
-    case HAL_DAC_CH1_UNDERRUN_CB_ID :
-      hdac->DMAUnderrunCallbackCh1 = pCallback;
-      break;
-    case HAL_DAC_CH2_COMPLETE_CB_ID :
-      hdac->ConvCpltCallbackCh2 = pCallback;
-      break;
-    case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
-      hdac->ConvHalfCpltCallbackCh2 = pCallback;
-      break;
-    case HAL_DAC_CH2_ERROR_ID :
-      hdac->ErrorCallbackCh2 = pCallback;
-      break;
-    case HAL_DAC_CH2_UNDERRUN_CB_ID :
-      hdac->DMAUnderrunCallbackCh2 = pCallback;
-      break;
-    case HAL_DAC_MSP_INIT_CB_ID :
-      hdac->MspInitCallback = pCallback;
-      break;
-    case HAL_DAC_MSP_DEINIT_CB_ID :
-      hdac->MspDeInitCallback = pCallback;
-      break;
-    default :
-      /* Update the error code */
-      hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else if (hdac->State == HAL_DAC_STATE_RESET)
-  {
-    switch (CallbackId)
-    {
-    case HAL_DAC_MSP_INIT_CB_ID :
-      hdac->MspInitCallback = pCallback;
-      break;
-    case HAL_DAC_MSP_DEINIT_CB_ID :
-      hdac->MspDeInitCallback = pCallback;
-      break;
-    default :
-      /* Update the error code */
-      hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdac);
-  return status;
-}
-
-/**
-  * @brief  Unregister a User DAC Callback
-  *         DAC Callback is redirected to the weak (surcharged) predefined callback 
-  * @param hdac DAC handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID          DAC CH1 tranfer Complete Callback ID     
-  *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID     DAC CH1 Half Complete Callback ID        
-  *          @arg @ref HAL_DAC_CH1_ERROR_ID                DAC CH1 Error Callback ID                
-  *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID          DAC CH1 UnderRun Callback ID
-  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID          DAC CH2 Complete Callback ID             
-  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID     DAC CH2 Half Complete Callback ID        
-  *          @arg @ref HAL_DAC_CH2_ERROR_ID                DAC CH2 Error Callback ID                
-  *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID          DAC CH2 UnderRun Callback ID
-  *          @arg @ref HAL_DAC_MSP_INIT_CB_ID              DAC MSP Init Callback ID                 
-  *          @arg @ref HAL_DAC_MSP_DEINIT_CB_ID            DAC MSP DeInit Callback ID               
-  *          @arg @ref HAL_DAC_ALL_CB_ID                   DAC All callbacks
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  if(hdac->State == HAL_DAC_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-    case HAL_DAC_CH1_COMPLETE_CB_ID :
-      hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
-      break;
-    case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
-      hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
-      break;
-    case HAL_DAC_CH1_ERROR_ID :
-      hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
-      break;
-    case HAL_DAC_CH1_UNDERRUN_CB_ID :
-      hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
-      break;
-#if defined (DAC_CHANNEL2_SUPPORT)
-    case HAL_DAC_CH2_COMPLETE_CB_ID :
-      hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
-      break;
-    case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
-      hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
-      break;
-    case HAL_DAC_CH2_ERROR_ID :
-      hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
-      break;
-    case HAL_DAC_CH2_UNDERRUN_CB_ID :
-      hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
-      break;
-#endif /* DAC_CHANNEL2_SUPPORT */
-    case HAL_DAC_MSP_INIT_CB_ID :
-      hdac->MspInitCallback = HAL_DAC_MspInit;
-      break;
-    case HAL_DAC_MSP_DEINIT_CB_ID :
-      hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
-      break;
-    case HAL_DAC_ALL_CB_ID :
-      hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
-      hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
-      hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
-      hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
-#if defined (DAC_CHANNEL2_SUPPORT)
-      hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
-      hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
-      hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
-      hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
-#endif /* DAC_CHANNEL2_SUPPORT */
-      hdac->MspInitCallback = HAL_DAC_MspInit;
-      hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
-      break;
-    default :
-      /* Update the error code */
-      hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else if (hdac->State == HAL_DAC_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-    case HAL_DAC_MSP_INIT_CB_ID :
-      hdac->MspInitCallback = HAL_DAC_MspInit;
-      break;
-    case HAL_DAC_MSP_DEINIT_CB_ID :
-      hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
-      break;
-    default :
-      /* Update the error code */
-      hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdac);
-  return status;
-}
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* HAL_DAC_MODULE_ENABLED */
-#endif /* !STM32L010xB && !STM32L010x8 && !STM32L010x6 && !STM32L010x4 && !STM32L011xx && !STM32L021xx && !STM32L031xx && !STM32L041xx && !STM32L051xx !STM32L071xx&& !STM32L081xx */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c
deleted file mode 100644
index 373e712929..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c
+++ /dev/null
@@ -1,1049 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_dac_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended DAC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of DAC extension peripheral:
-  *           + Extended features functions
-  *     
-  *     
-  @verbatim
-  ==============================================================================
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]          
-      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
-          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
-          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.  
-      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
-      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
-  
- @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-
-#if !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) && !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-#ifdef HAL_DAC_MODULE_ENABLED
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DACEx DACEx
-  * @brief DAC driver modules
-  * @{
-  */
-
-/** @addtogroup DACEx_Private
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
-static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); 
-#endif
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @addtogroup DACEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DACEx_Exported_Functions_Group1
- *  @brief    Extended features functions 
- *
-
-  * @{
-  */
-
-#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
-{
-  uint32_t tmp = 0U;
-  
-  tmp |= hdac->Instance->DOR1;
-  
-  tmp |= hdac->Instance->DOR2 << 16U;
-  
-  /* Returns the DAC channel data output register value */
-  return tmp;
-}
-#endif
-
-/**
-  * @brief  Enable or disable the selected DAC channel wave generation.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
-  * @param  Amplitude Select max triangle amplitude. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
-  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
-  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
-  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
-  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
-  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
-  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
-  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
-  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
-  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
-  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
-  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Enable the triangle wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
- 
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enable or disable the selected DAC channel wave generation.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC. 
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
-  * @param  Amplitude Unmask DAC channel LFSR for noise wave generation.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-/* Enable the noise wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
-/**
-  * @brief  Set the specified data holding register value for dual DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *               the configuration information for the specified DAC.
-  * @param  Alignment Specifies the data alignment for dual channel DAC.
-  *          This parameter can be one of the following values:
-  *            DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
-  * @param  Data2 Data for DAC Channel2 to be loaded in the selected data holding register.
-  * @note   In dual mode, a unique register access is required to write in both
-  *          DAC channels at the same time.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{  
-  uint32_t data = 0U, tmp = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data1));
-  assert_param(IS_DAC_DATA(Data2));
-  
-  /* Calculate and set dual DAC data holding register value */
-  if (Alignment == DAC_ALIGN_8B_R)
-  {
-    data = ((uint32_t)Data2 << 8U) | Data1; 
-  }
-  else
-  {
-    data = ((uint32_t)Data2 << 16U) | Data1;
-  }
-  
-  tmp = (uint32_t)hdac->Instance;
-  tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
-
-  /* Set the dual DAC selected data holding register */
-  *(__IO uint32_t *)tmp = data;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Conversion complete callback in non blocking mode for Channel2 
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2 
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error DAC callback for Channel2.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA underrun DAC callback for Channel2.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Enable the Peripharal */
-  __HAL_DAC_ENABLE(hdac, Channel);
-
-  if(Channel == DAC_CHANNEL_1)
-  {
-    tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
-    tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
-    /* Check if software trigger enabled */
-    if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))
-    {
-      /* Enable the selected DAC software conversion */
-      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
-    }
-  }
-  else
-  {
-    tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
-    tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
-    /* Check if software trigger enabled */
-    if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
-    {
-      /* Enable the selected DAC software conversion*/
-      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
-    }
-  }
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables DAC and starts conversion of channel using DMA.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  pData The destination peripheral Buffer address.
-  * @param  Length The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment Specifies the data alignment for DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
-{
-  uint32_t tmpreg = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  if(Channel == DAC_CHANNEL_1)
-  {
-    /* Set the DMA transfer complete callback for channel1 */
-    hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
-    /* Set the DMA half transfer complete callback for channel1 */
-    hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
-    /* Set the DMA error callback for channel1 */
-    hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
-    /* Enable the selected DAC channel1 DMA request */
-    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-       
-    /* Case of use of channel 1 */
-    switch(Alignment)
-    {
-      case DAC_ALIGN_12B_R:
-        /* Get DHR12R1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
-        break;
-      case DAC_ALIGN_12B_L:
-        /* Get DHR12L1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
-        break;
-      case DAC_ALIGN_8B_R:
-        /* Get DHR8R1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
-        break;
-      default:
-        break;
-    }
-    UNUSED(tmpreg);		/* avoid warning on tmpreg affectation with stupid compiler */
-  }
-  else
-  {
-    /* Set the DMA transfer complete callback for channel2 */
-    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-
-    /* Set the DMA half transfer complete callback for channel2 */
-    hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-    
-    /* Set the DMA error callback for channel2 */
-    hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-
-    /* Enable the selected DAC channel2 DMA request */
-    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
-    /* Case of use of channel 2 */
-    switch(Alignment)
-    {
-      case DAC_ALIGN_12B_R:
-        /* Get DHR12R2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
-        break;
-      case DAC_ALIGN_12B_L:
-        /* Get DHR12L2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
-        break;
-      case DAC_ALIGN_8B_R:
-        /* Get DHR8R2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
-        break;
-      default:
-        break;
-    }
-  }
-  
-  /* Enable the DMA Stream */
-  if(Channel == DAC_CHANNEL_1)
-  {
-    /* Enable the DAC DMA underrun interrupt */
-    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-    
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
-  } 
-  else
-  {
-    /* Enable the DAC DMA underrun interrupt */
-    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
-    
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
-  }
-  
-  /* Enable the Peripharal */
-  __HAL_DAC_ENABLE(hdac, Channel);
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Disable the selected DAC channel DMA request */
-  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_DMAEN1 << Channel));
-
-  /* Disable the Peripharal */
-  __HAL_DAC_DISABLE(hdac, Channel);
-
-  /* Disable the DMA Channel */
-  /* Channel1 is used */
-  if(Channel == DAC_CHANNEL_1)
-  { 
-    status = HAL_DMA_Abort(hdac->DMA_Handle1);
-  }
-  else /* Channel2 is used for */
-  { 
-    status = HAL_DMA_Abort(hdac->DMA_Handle2); 
-  }
-
-  /* Check if DMA Channel effectively disabled */
-  if(status != HAL_OK)
-  {
-    /* Update DAC state machine to error */
-    hdac->State = HAL_DAC_STATE_ERROR;
-  }
-  else
-  {
-    /* Change DAC state */
-    hdac->State = HAL_DAC_STATE_READY;
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Returns the DAC channel data output register value */
-  if(Channel == DAC_CHANNEL_1)
-  {
-    return hdac->Instance->DOR1;
-  }
-  else
-  {
-    return hdac->Instance->DOR2;
-  }
-}
-
-/**
-  * @brief  Handles DAC interrupt request
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
-{
-  /* Check underrun flag of DAC channel 1 */
-  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
-  {
-    /* Change DAC state to error state */
-    hdac->State = HAL_DAC_STATE_ERROR;
-
-    /* Set DAC error code to chanel1 DMA underrun error */
-    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
-
-    /* Clear the underrun flag */
-    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-
-    /* Disable the selected DAC channel1 DMA request */
-    CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
-    /* Error callback */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-      hdac->DMAUnderrunCallbackCh1(hdac);
-#else
-    HAL_DAC_DMAUnderrunCallbackCh1(hdac);
-#endif
-  }
-  
-  /* Check underrun flag of DAC channel 2 */
-  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
-  {
-    /* Change DAC state to error state */
-    hdac->State = HAL_DAC_STATE_ERROR;
-    
-    /* Set DAC error code to channel2 DMA underrun error */
-    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
-    
-    /* Clear the underrun flag */
-    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
-    
-    /* Disable the selected DAC channel1 DMA request */
-    CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-      
-    /* Error callback */ 
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-      hdac->DMAUnderrunCallbackCh2(hdac);
-#else
-    HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
-#endif
-  }
-}
-
-
-/**
-  * @brief  Set the specified data holding register value for DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  Alignment Specifies the data alignment.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data Data to be loaded in the selected data holding register.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{
-  __IO uint32_t tmp = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data));
-
-  tmp = (uint32_t)hdac->Instance; 
-  if(Channel == DAC_CHANNEL_1)
-  {
-    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
-  }
-  else
-  {
-    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
-  }
-
-  /* Set the DAC channel selected data holding register */
-  *(__IO uint32_t *) tmp = Data;
-
-  /* Return function status */
-  return HAL_OK;
-}
-#else /* All products with only one channel */
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Enable the Peripharal */
-  __HAL_DAC_ENABLE(hdac, Channel);
-
-  tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
-  tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
-  /* Check if software trigger enabled */
-  if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))
-  {
-    /* Enable the selected DAC software conversion */
-    SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
-  }
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables DAC and starts conversion of channel using DMA.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  * @param  pData The destination peripheral Buffer address.
-  * @param  Length The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment Specifies the data alignment for DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
-{
-  uint32_t tmpreg = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Set the DMA transfer complete callback for channel1 */
-  hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
-  /* Set the DMA half transfer complete callback for channel1 */
-  hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
-  /* Set the DMA error callback for channel1 */
-  hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
-  /* Enable the selected DAC channel1 DMA request */
-  SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-     
-  /* Case of use of channel 1 */
-  switch(Alignment)
-  {
-    case DAC_ALIGN_12B_R:
-      /* Get DHR12R1 address */
-      tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
-      break;
-    case DAC_ALIGN_12B_L:
-      /* Get DHR12L1 address */
-      tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
-      break;
-    case DAC_ALIGN_8B_R:
-      /* Get DHR8R1 address */
-      tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
-      break;
-    default:
-      break;
-  }
-  UNUSED(tmpreg);		/* avoid warning on tmpreg affectation with stupid compiler */
-  
-  /* Enable the DMA Stream */
-  /* Enable the DAC DMA underrun interrupt */
-  __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-  
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
-  
-  /* Enable the Peripharal */
-  __HAL_DAC_ENABLE(hdac, Channel);
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Disable the selected DAC channel DMA request */
-  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_DMAEN1 << Channel));
-
-  /* Disable the Peripharal */
-  __HAL_DAC_DISABLE(hdac, Channel);
-
-  /* Disable the DMA Channel */
-  status = HAL_DMA_Abort(hdac->DMA_Handle1);
-
-  /* Check if DMA Channel effectively disabled */
-  if(status != HAL_OK)
-  {
-    /* Update DAC state machine to error */
-    hdac->State = HAL_DAC_STATE_ERROR;
-  }
-  else
-  {
-    /* Change DAC state */
-    hdac->State = HAL_DAC_STATE_READY;
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Returns the DAC channel data output register value */
-  return hdac->Instance->DOR1;
-}
-
-/**
-  * @brief  Handles DAC interrupt request
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
-{
-  /* Check underrun flag of DAC channel 1 */
-  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
-  {
-    /* Change DAC state to error state */
-    hdac->State = HAL_DAC_STATE_ERROR;
-
-    /* Set DAC error code to chanel1 DMA underrun error */
-    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
-
-    /* Clear the underrun flag */
-    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-
-    /* Disable the selected DAC channel1 DMA request */
-    CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
-    /* Error callback */
-    HAL_DAC_DMAUnderrunCallbackCh1(hdac);
-  }
-}
-
-/**
-  * @brief  Set the specified data holding register value for DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  * @param  Alignment Specifies the data alignment.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data Data to be loaded in the selected data holding register.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{
-  __IO uint32_t tmp = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data));
-
-  tmp = (uint32_t)hdac->Instance; 
-  tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
-
-  /* Set the DAC channel selected data holding register */
-  *(__IO uint32_t *) tmp = Data;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-#endif  /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DACEx_Private
-  * @{
-  */
-#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
-/**
-  * @brief  DMA conversion complete callback. 
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  HAL_DACEx_ConvCpltCallbackCh2(hdac); 
-  
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   
-{
-    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); 
-}
-
-/**
-  * @brief  DMA error callback 
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
-  /* Set DAC error code to DMA error */
-  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-    
-  HAL_DACEx_ErrorCallbackCh2(hdac); 
-    
-  hdac->State= HAL_DAC_STATE_READY;
-}
-#endif /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
-
-/**
-  * @brief  DMA conversion complete callback. 
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  hdac->ConvCpltCallbackCh1(hdac);
-#else
-  HAL_DAC_ConvCpltCallbackCh1(hdac); 
-#endif
-  
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @brief  DMA half transfer complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Conversion complete callback */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  hdac->ConvHalfCpltCallbackCh1(hdac);
-#else
-  HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
-#endif  
-}
-
-/**
-  * @brief  DMA error callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Set DAC error code to DMA error */
-  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
-  HAL_DAC_ErrorCallbackCh1(hdac);
-
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* HAL_DAC_MODULE_ENABLED */
-#endif /* #if !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) && !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c
deleted file mode 100644
index e583c346c5..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c
+++ /dev/null
@@ -1,885 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_dma.c
-  * @author  MCD Application Team
-  * @brief   DMA HAL module driver.
-  *         This file provides firmware functions to manage the following
-  *         functionalities of the Direct Memory Access (DMA) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and errors functions
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-   (#) Enable and configure the peripheral to be connected to the DMA Channel
-       (except for internal SRAM / FLASH memories: no initialization is
-       necessary).
-
-   (#) For a given Channel, program the required configuration through the following parameters:
-       Channel request, Transfer Direction, Source and Destination data formats,
-       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
-       using HAL_DMA_Init() function.
-
-   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
-       detection.
-
-   (#) Use HAL_DMA_Abort() function to abort the current transfer
-
-     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
-
-     *** Polling mode IO operation ***
-     =================================
-    [..]
-          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
-              address and destination address and the Length of data to be transferred
-          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
-              case a fixed Timeout can be configured by User depending from his application.
-
-     *** Interrupt mode IO operation ***
-     ===================================
-    [..]
-          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
-          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
-          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
-              Source address and destination address and the Length of data to be transferred.
-              In this case the DMA interrupt is configured
-          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
-          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
-              add his own function to register callbacks with HAL_DMA_RegisterCallback().
-
-     *** DMA HAL driver macros list ***
-     =============================================
-      [..]
-       Below the list of macros in DMA HAL driver.
-
-       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
-       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
-       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
-       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
-       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
-       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
-       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
-
-     [..]
-      (@) You can refer to the DMA HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DMA DMA
-  * @brief DMA HAL module driver
-  * @{
-  */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
-  * @{
-  */
-
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
-  * @{
-  */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief   Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
-             ##### Initialization and de-initialization functions  #####
- ===============================================================================
-    [..]
-    This section provides functions allowing to initialize the DMA Channel source
-    and destination addresses, incrementation and data sizes, transfer direction,
-    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
-    [..]
-    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
-    reference manual.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the DMA according to the specified
-  *         parameters in the DMA_InitTypeDef and initialize the associated handle.
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tmp;
-
-  /* Check the DMA handle allocation */
-  if(hdma == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-  assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
-  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
-  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
-  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
-  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
-  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
-  assert_param(IS_DMA_MODE(hdma->Init.Mode));
-  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-
-  /* Compute the channel index */
-  /* Only one DMA: DMA1 */
-  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
-  hdma->DmaBaseAddress = DMA1;
-
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
-
-  /* Get the CR register value */
-  tmp = hdma->Instance->CCR;
-
-  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
-  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  |
-                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |
-                      DMA_CCR_DIR   | DMA_CCR_MEM2MEM));
-
-  /* Prepare the DMA Channel configuration */
-  tmp |=  hdma->Init.Direction        |
-          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
-          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
-          hdma->Init.Mode                | hdma->Init.Priority;
-
-  /* Write to DMA Channel CR register */
-  hdma->Instance->CCR = tmp;
-
-  /* Set request selection */
-  if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
-  {
-    /* Write to DMA channel selection register */
-    /* Reset request selection for DMA1 Channelx */
-    DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
-
-    /* Configure request selection for DMA1 Channelx */
-    DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
-  }
-
-  /* Initialise the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-  /* Initialize the DMA state*/
-  hdma->State  = HAL_DMA_STATE_READY;
-
-  /* Allocate lock resource and initialize it */
-  hdma->Lock = HAL_UNLOCKED;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the DMA peripheral.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
-{
-
-  /* Check the DMA handle allocation */
-  if (NULL == hdma )
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
-  /* Disable the selected DMA Channelx */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Compute the channel index */
-  /* DMA1 */
-  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
-  hdma->DmaBaseAddress = DMA1;
-
-  /* Reset DMA Channel control register */
-  hdma->Instance->CCR  = 0U;
-
-  /* Clear all flags */
-  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
-
-  /* Reset DMA channel selection register */
-  /* DMA1 */
-  DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
-
-  /* Clean callbacks */
-  hdma->XferCpltCallback = NULL;
-  hdma->XferHalfCpltCallback = NULL;
-  hdma->XferErrorCallback = NULL;
-  hdma->XferAbortCallback = NULL;
-
-  /* Initialise the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-  /* Initialize the DMA state */
-  hdma->State = HAL_DMA_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
- *  @brief   Input and Output operation functions
- *
-@verbatim
- ===============================================================================
-                      #####  IO operation functions  #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure the source, destination address and data length and Start DMA transfer
-      (+) Configure the source, destination address and data length and
-          Start DMA transfer with interrupt
-      (+) Abort DMA transfer
-      (+) Poll for transfer complete
-      (+) Handle DMA interrupt request
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the DMA Transfer.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-    /* Disable the peripheral */
-    __HAL_DMA_DISABLE(hdma);
-
-    /* Configure the source, destination address and the data length & clear flags*/
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-    /* Enable the Peripheral */
-    __HAL_DMA_ENABLE(hdma);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-    status = HAL_BUSY;
-  }
-  return status;
-}
-
-/**
-  * @brief  Start the DMA Transfer with interrupt enabled.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-    /* Disable the peripheral */
-    __HAL_DMA_DISABLE(hdma);
-
-    /* Configure the source, destination address and the data length & clear flags*/
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-    /* Enable the transfer complete interrupt */
-    /* Enable the transfer Error interrupt */
-    if(NULL != hdma->XferHalfCpltCallback )
-    {
-      /* Enable the Half transfer complete interrupt as well */
-      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-    }
-    else
-    {
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
-      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
-    }
-
-    /* Enable the Peripheral */
-    __HAL_DMA_ENABLE(hdma);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    /* Remain BUSY */
-    status = HAL_BUSY;
-  }
-  return status;
-}
-
-/**
-  * @brief  Abort the DMA Transfer.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-    * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the DMA peripheral state */
-  if(hdma->State != HAL_DMA_STATE_BUSY)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Disable DMA IT */
-    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
-    /* Disable the channel */
-    __HAL_DMA_DISABLE(hdma);
-
-    /* Clear all flags */
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
-
-    /* Change the DMA state */
-    hdma->State = HAL_DMA_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    return status;
-  }
-}
-
-/**
-  * @brief  Aborts the DMA Transfer in Interrupt mode.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                 the configuration information for the specified DMA Channel.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if(HAL_DMA_STATE_BUSY != hdma->State)
-  {
-    /* no transfer ongoing */
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Disable DMA IT */
-    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
-    /* Disable the channel */
-    __HAL_DMA_DISABLE(hdma);
-
-    /* Clear all flags */
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
-
-    /* Change the DMA state */
-    hdma->State = HAL_DMA_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    /* Call User Abort callback */
-    if(hdma->XferAbortCallback != NULL)
-    {
-      hdma->XferAbortCallback(hdma);
-    }
-  }
-  return status;
-}
-
-/**
-  * @brief  Polling for transfer complete.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                  the configuration information for the specified DMA Channel.
-  * @param  CompleteLevel Specifies the DMA level complete.
-  * @param  Timeout       Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
-{
-  uint32_t temp;
-  uint32_t tickstart;
-
-  if(HAL_DMA_STATE_BUSY != hdma->State)
-  {
-    /* no transfer ongoing */
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-    __HAL_UNLOCK(hdma);
-    return HAL_ERROR;
-  }
-
-  /* Polling mode not supported in circular mode */
-  if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC))
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
-    return HAL_ERROR;
-  }
-
-  /* Get the level transfer complete flag */
-  if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
-  {
-    /* Transfer Complete flag */
-    temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU);
-  }
-  else
-  {
-    /* Half Transfer Complete flag */
-    temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU);
-  }
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(0U == (hdma->DmaBaseAddress->ISR & temp))
-  {
-    if((0U != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1cU)))))
-    {
-      /* When a DMA transfer error occurs */
-      /* A hardware clear of its EN bits is performed */
-      /* Clear all flags */
-      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
-
-      /* Update error code */
-      hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
-      /* Change the DMA state */
-      hdma->State= HAL_DMA_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      return HAL_ERROR;
-    }
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if(((HAL_GetTick() - tickstart) > Timeout) ||  (Timeout == 0U))
-      {
-        /* Update error code */
-        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-
-        return HAL_ERROR;
-      }
-    }
-  }
-
-  if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
-  {
-    /* Clear the transfer complete flag */
-    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1cU));
-
-    /* The selected Channelx EN bit is cleared (DMA is disabled and
-    all transfers are complete) */
-    hdma->State = HAL_DMA_STATE_READY;
-  }
-  else
-  {
-    /* Clear the half transfer complete flag */
-    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU));
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdma);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle DMA interrupt request.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval None
-  */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
-  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
-  uint32_t source_it = hdma->Instance->CCR;
-
-  /* Half Transfer Complete Interrupt management ******************************/
-  if ((0U != (flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_HT)))
-  {
-      /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-      if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-      {
-        /* Disable the half transfer interrupt */
-        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
-      }
-      /* Clear the half transfer complete flag */
-      hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1cU);
-
-      /* DMA peripheral state is not updated in Half Transfer */
-      /* but in Transfer Complete case */
-
-     if(hdma->XferHalfCpltCallback != NULL)
-      {
-        /* Half transfer callback */
-        hdma->XferHalfCpltCallback(hdma);
-      }
-  }
-
-  /* Transfer Complete Interrupt management ***********************************/
-  else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC)))
-  {
-    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-    {
-      /* Disable the transfer complete and error interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_READY;
-    }
-    /* Clear the transfer complete flag */
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU));
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    if(hdma->XferCpltCallback != NULL)
-    {
-      /* Transfer complete callback */
-      hdma->XferCpltCallback(hdma);
-    }
-  }
-
-  /* Transfer Error Interrupt management **************************************/
-  else if ((0U != (flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TE)))
-  {
-    /* When a DMA transfer error occurs */
-    /* A hardware clear of its EN bits is performed */
-    /* Disable ALL DMA IT */
-    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
-    /* Clear all flags */
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
-
-    /* Update error code */
-    hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
-    /* Change the DMA state */
-    hdma->State = HAL_DMA_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    if (hdma->XferErrorCallback != NULL)
-    {
-      /* Transfer error callback */
-      hdma->XferErrorCallback(hdma);
-    }
-  }
-  else
-  {
-    /* Nothing To Do */
-  }
-  return;
-}
-
-/**
-  * @brief  Register callbacks
-  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
-  *                               the configuration information for the specified DMA Channel.
-  * @param  CallbackID           User Callback identifer
-  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
-  * @param  pCallback            pointer to private callbacsk function which has pointer to
-  *                               a DMA_HandleTypeDef structure as parameter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    switch (CallbackID)
-    {
-     case  HAL_DMA_XFER_CPLT_CB_ID:
-           hdma->XferCpltCallback = pCallback;
-           break;
-
-     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
-           hdma->XferHalfCpltCallback = pCallback;
-           break;
-
-     case  HAL_DMA_XFER_ERROR_CB_ID:
-           hdma->XferErrorCallback = pCallback;
-           break;
-
-     case  HAL_DMA_XFER_ABORT_CB_ID:
-           hdma->XferAbortCallback = pCallback;
-           break;
-
-     default:
-           status = HAL_ERROR;
-           break;
-    }
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return status;
-}
-
-/**
-  * @brief  UnRegister callbacks
-  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
-  *                               the configuration information for the specified DMA Channel.
-  * @param  CallbackID           User Callback identifer
-  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-    /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    switch (CallbackID)
-    {
-     case  HAL_DMA_XFER_CPLT_CB_ID:
-           hdma->XferCpltCallback = NULL;
-           break;
-
-     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
-           hdma->XferHalfCpltCallback = NULL;
-           break;
-
-     case  HAL_DMA_XFER_ERROR_CB_ID:
-           hdma->XferErrorCallback = NULL;
-           break;
-
-     case  HAL_DMA_XFER_ABORT_CB_ID:
-           hdma->XferAbortCallback = NULL;
-           break;
-
-    case   HAL_DMA_XFER_ALL_CB_ID:
-           hdma->XferCpltCallback = NULL;
-           hdma->XferHalfCpltCallback = NULL;
-           hdma->XferErrorCallback = NULL;
-           hdma->XferAbortCallback = NULL;
-           break;
-
-    default:
-           status = HAL_ERROR;
-           break;
-    }
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
- *  @brief    Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
-            ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DMA state
-      (+) Get error code
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the DMA handle state.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval HAL state
-  */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
-{
-  /* Return DMA handle state */
-  return hdma->State;
-}
-
-/**
-  * @brief  Return the DMA error code.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA Channel.
-  * @retval DMA Error Code
-  */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
-{
-  return hdma->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Sets the DMA Transfer parameter.
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Channel.
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  /* Clear all flags */
-  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
-
-  /* Configure DMA Channel data length */
-  hdma->Instance->CNDTR = DataLength;
-
-  /* Memory to Peripheral */
-  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
-  {
-    /* Configure DMA Channel destination address */
-    hdma->Instance->CPAR = DstAddress;
-
-    /* Configure DMA Channel source address */
-    hdma->Instance->CMAR = SrcAddress;
-  }
-  /* Peripheral to Memory */
-  else
-  {
-    /* Configure DMA Channel source address */
-    hdma->Instance->CPAR = SrcAddress;
-
-    /* Configure DMA Channel destination address */
-    hdma->Instance->CMAR = DstAddress;
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c
deleted file mode 100644
index 11a51ffb58..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c
+++ /dev/null
@@ -1,549 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_exti.c
-  * @author  MCD Application Team
-  * @brief   EXTI HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### EXTI Peripheral features #####
-  ==============================================================================
-  [..]
-    (+) Each Exti line can be configured within this driver.
-
-    (+) Exti line can be configured in 3 different modes
-        (++) Interrupt
-        (++) Event
-        (++) Both of them
-
-    (+) Configurable Exti lines can be configured with 3 different triggers
-        (++) Rising
-        (++) Falling
-        (++) Both of them
-
-    (+) When set in interrupt mode, configurable Exti lines have two different
-        interrupts pending registers which allow to distinguish which transition
-        occurs:
-        (++) Rising edge pending interrupt
-        (++) Falling
-
-    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
-        be selected through multiplexer.
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-
-    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
-        (++) Choose the interrupt line number by setting "Line" member from
-             EXTI_ConfigTypeDef structure.
-        (++) Configure the interrupt and/or event mode using "Mode" member from
-             EXTI_ConfigTypeDef structure.
-        (++) For configurable lines, configure rising and/or falling trigger
-             "Trigger" member from EXTI_ConfigTypeDef structure.
-        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
-             member from GPIO_InitTypeDef structure.
-
-    (#) Get current Exti configuration of a dedicated line using
-        HAL_EXTI_GetConfigLine().
-        (++) Provide exiting handle as parameter.
-        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
-
-    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
-        (++) Provide exiting handle as parameter.
-
-    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
-        (++) Provide exiting handle as first parameter.
-        (++) Provide which callback will be registered using one value from
-             EXTI_CallbackIDTypeDef.
-        (++) Provide callback function pointer.
-
-    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
-
-    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
-
-    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup EXTI
-  * @{
-  */
-/** MISRA C:2012 deviation rule has been granted for following rule:
-  * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
-  * of bounds [0,3] in following API :
-  * HAL_EXTI_SetConfigLine
-  * HAL_EXTI_GetConfigLine
-  * HAL_EXTI_ClearConfigLine
-  */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup EXTI_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup EXTI_Exported_Functions_Group1
-  *  @brief    Configuration functions
-  *
-@verbatim
- ===============================================================================
-              ##### Configuration functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set configuration of a dedicated Exti line.
-  * @param  hexti Exti handle.
-  * @param  pExtiConfig Pointer on EXTI configuration to be set.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
-{
-  uint32_t regval;
-  uint32_t linepos;
-  uint32_t maskline;
-
-  /* Check null pointer */
-  if ((hexti == NULL) || (pExtiConfig == NULL))
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check parameters */
-  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
-  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
-
-  /* Assign line number to handle */
-  hexti->Line = pExtiConfig->Line;
-
-  /* Compute line mask */
-  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
-  maskline = (1uL << linepos);
-
-  /* Configure triggers for configurable lines */
-  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
-  {
-    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
-
-    /* Configure rising trigger */
-    /* Mask or set line */
-    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
-    {
-      EXTI->RTSR |= maskline;
-    }
-    else
-    {
-      EXTI->RTSR &= ~maskline;
-    }
-
-    /* Configure falling trigger */
-    /* Mask or set line */
-    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
-    {
-      EXTI->FTSR |= maskline;
-    }
-    else
-    {
-      EXTI->FTSR &= ~maskline;
-    }
-
-
-    /* Configure gpio port selection in case of gpio exti line */
-    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
-    {
-      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
-      assert_param(IS_EXTI_GPIO_PIN(linepos));
-
-      regval = SYSCFG->EXTICR[linepos >> 2u];
-      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
-      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
-      SYSCFG->EXTICR[linepos >> 2u] = regval;
-    }
-  }
-
-  /* Configure interrupt mode : read current mode */
-  /* Mask or set line */
-  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
-  {
-    EXTI->IMR |= maskline;
-  }
-  else
-  {
-    EXTI->IMR &= ~maskline;
-  }
-
-  /* Configure event mode : read current mode */
-  /* Mask or set line */
-  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
-  {
-    EXTI->EMR |= maskline;
-  }
-  else
-  {
-    EXTI->EMR &= ~maskline;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get configuration of a dedicated Exti line.
-  * @param  hexti Exti handle.
-  * @param  pExtiConfig Pointer on structure to store Exti configuration.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
-{
-  uint32_t regval;
-  uint32_t linepos;
-  uint32_t maskline;
-
-  /* Check null pointer */
-  if ((hexti == NULL) || (pExtiConfig == NULL))
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameter */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-
-  /* Store handle line number to configuration structure */
-  pExtiConfig->Line = hexti->Line;
-
-  /* Compute line mask */
-  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
-  maskline = (1uL << linepos);
-
-  /* 1] Get core mode : interrupt */
-
-  /* Check if selected line is enable */
-  if ((EXTI->IMR & maskline) != 0x00u)
-  {
-    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
-  }
-  else
-  {
-    pExtiConfig->Mode = EXTI_MODE_NONE;
-  }
-
-  /* Get event mode */
-  /* Check if selected line is enable */
-  if ((EXTI->EMR & maskline) != 0x00u)
-  {
-    pExtiConfig->Mode |= EXTI_MODE_EVENT;
-  }
-
-  /* Get default Trigger and GPIOSel configuration */
-  pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
-  pExtiConfig->GPIOSel = 0x00u;
-
-  /* 2] Get trigger for configurable lines : rising */
-  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
-  {
-    /* Check if configuration of selected line is enable */
-    if ((EXTI->RTSR & maskline) != 0x00u)
-    {
-      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
-    }
-
-    /* Get falling configuration */
-    /* Check if configuration of selected line is enable */
-    if ((EXTI->FTSR & maskline) != 0x00u)
-    {
-      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
-    }
-
-    /* Get Gpio port selection for gpio lines */
-    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
-    {
-      assert_param(IS_EXTI_GPIO_PIN(linepos));
-
-      regval = SYSCFG->EXTICR[linepos >> 2u];
-      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Clear whole configuration of a dedicated Exti line.
-  * @param  hexti Exti handle.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
-{
-  uint32_t regval;
-  uint32_t linepos;
-  uint32_t maskline;
-
-  /* Check null pointer */
-  if (hexti == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameter */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-
-  /* compute line mask */
-  linepos = (hexti->Line & EXTI_PIN_MASK);
-  maskline = (1uL << linepos);
-
-  /* 1] Clear interrupt mode */
-  EXTI->IMR = (EXTI->IMR & ~maskline);
-
-  /* 2] Clear event mode */
-  EXTI->EMR = (EXTI->EMR & ~maskline);
-
-  /* 3] Clear triggers in case of configurable lines */
-  if ((hexti->Line & EXTI_CONFIG) != 0x00u)
-  {
-    EXTI->RTSR = (EXTI->RTSR & ~maskline);
-    EXTI->FTSR = (EXTI->FTSR & ~maskline);
-
-    /* Get Gpio port selection for gpio lines */
-    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
-    {
-      assert_param(IS_EXTI_GPIO_PIN(linepos));
-
-      regval = SYSCFG->EXTICR[linepos >> 2u];
-      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
-      SYSCFG->EXTICR[linepos >> 2u] = regval;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Register callback for a dedicated Exti line.
-  * @param  hexti Exti handle.
-  * @param  CallbackID User callback identifier.
-  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
-  * @param  pPendingCbfn function pointer to be stored as callback.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  switch (CallbackID)
-  {
-    case  HAL_EXTI_COMMON_CB_ID:
-      hexti->PendingCallback = pPendingCbfn;
-      break;
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Store line number as handle private field.
-  * @param  hexti Exti handle.
-  * @param  ExtiLine Exti line number.
-  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
-{
-  /* Check the parameters */
-  assert_param(IS_EXTI_LINE(ExtiLine));
-
-  /* Check null pointer */
-  if (hexti == NULL)
-  {
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Store line number as handle private field */
-    hexti->Line = ExtiLine;
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup EXTI_Exported_Functions_Group2
-  *  @brief EXTI IO functions.
-  *
-@verbatim
- ===============================================================================
-                       ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Handle EXTI interrupt request.
-  * @param  hexti Exti handle.
-  * @retval none.
-  */
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
-{
-  uint32_t regval;
-  uint32_t maskline;
-
-  /* Compute line mask */
-  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
-  /* Get pending bit  */
-  regval = (EXTI->PR & maskline);
-  if (regval != 0x00u)
-  {
-    /* Clear pending bit */
-    EXTI->PR = maskline;
-
-    /* Call callback */
-    if (hexti->PendingCallback != NULL)
-    {
-      hexti->PendingCallback();
-    }
-  }
-}
-
-/**
-  * @brief  Get interrupt pending bit of a dedicated line.
-  * @param  hexti Exti handle.
-  * @param  Edge Specify which pending edge as to be checked.
-  *         This parameter can be one of the following values:
-  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
-  *         This parameter is kept for compatibility with other series.
-  * @retval 1 if interrupt is pending else 0.
-  */
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
-{
-  uint32_t regval;
-  uint32_t linepos;
-  uint32_t maskline;
-
-  /* Check parameters */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
-  assert_param(IS_EXTI_PENDING_EDGE(Edge));
-
-  /* Compute line mask */
-  linepos = (hexti->Line & EXTI_PIN_MASK);
-  maskline = (1uL << linepos);
-
-  /* return 1 if bit is set else 0 */
-  regval = ((EXTI->PR & maskline) >> linepos);
-  return regval;
-}
-
-/**
-  * @brief  Clear interrupt pending bit of a dedicated line.
-  * @param  hexti Exti handle.
-  * @param  Edge Specify which pending edge as to be clear.
-  *         This parameter can be one of the following values:
-  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
-  *         This parameter is kept for compatibility with other series.
-  * @retval None.
-  */
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
-{
-  uint32_t maskline;
-
-  /* Check parameters */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
-  assert_param(IS_EXTI_PENDING_EDGE(Edge));
-
-  /* Compute line mask */
-  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
-  /* Clear Pending bit */
-  EXTI->PR =  maskline;
-}
-
-/**
-  * @brief  Generate a software interrupt for a dedicated line.
-  * @param  hexti Exti handle.
-  * @retval None.
-  */
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
-{
-  uint32_t maskline;
-
-  /* Check parameters */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
-
-  /* Compute line mask */
-  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
-  /* Generate Software interrupt */
-  EXTI->SWIER = maskline;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_EXTI_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_firewall.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_firewall.c
deleted file mode 100644
index 8570d3011a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_firewall.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_firewall.c
-  * @author  MCD Application Team
-  * @brief   FIREWALL HAL module driver.
-  *          This file provides firmware functions to manage the Firewall
-  *          Peripheral initialization and enabling.
-  *
-  *
-  @verbatim
- ===============================================================================
-                        ##### How to use this driver ##### 
- ===============================================================================
-  [..]
-    The FIREWALL HAL driver can be used as follows:
-              
-    (#) Declare a FIREWALL_InitTypeDef initialization structure.
-  
-    (#) Resort to HAL_FIREWALL_Config() API to initialize the Firewall
-
-    (#) Enable the FIREWALL in calling HAL_FIREWALL_EnableFirewall() API
-    
-    (#) To ensure that any code executed outside the protected segment closes the
-        FIREWALL, the user must set the flag FIREWALL_PRE_ARM_SET in calling 
-        __HAL_FIREWALL_PREARM_ENABLE() macro if called within a protected code segment
-        or
-        HAL_FIREWALL_EnablePreArmFlag() API if called outside of protected code segment
-        after HAL_FIREWALL_Config() call.
-
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */
-#if !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) && !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_FIREWALL_MODULE_ENABLED
-
-/** @addtogroup FIREWALL
-  * @brief HAL FIREWALL module driver
-  * @{
-  */
-
-    
-
-/** @addtogroup FIREWALL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FIREWALL_Exported_Functions_Group1
-  * @brief    Initialization and Configuration Functions 
-  *
-@verbatim    
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides the functions allowing to initialize the Firewall.
-    Initialization is done by HAL_FIREWALL_Config(): 
-
-      (+) Enable the Firewall clock thru __HAL_RCC_FIREWALL_CLK_ENABLE() macro.
-           
-      (+) Set the protected code segment address start and length.
-          
-      (+) Set the protected non-volatile and/or volatile data segments 
-          address starts and lengths if applicable.          
-          
-      (+) Set the volatile data segment execution and sharing status.
-      
-      (+) Length must be set to 0 for an unprotected segment.      
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Initialize the Firewall according to the FIREWALL_InitTypeDef structure parameters.
-  * @param fw_init: Firewall initialization structure
-  * @note  The API returns HAL_ERROR if the Firewall is already enabled.     
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init)
-{
-  /* Check the Firewall initialization structure allocation */
-  if(fw_init == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Enable Firewall clock */
-  __HAL_RCC_FIREWALL_CLK_ENABLE();
-
-  /* Make sure that Firewall is not enabled already */
-  if (__HAL_FIREWALL_IS_ENABLED() != RESET)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check Firewall configuration addresses and lengths when segment is protected */
-  /* Code segment */
-  if (fw_init->CodeSegmentLength != 0U)
-  {
-    assert_param(IS_FIREWALL_CODE_SEGMENT_ADDRESS(fw_init->CodeSegmentStartAddress));
-    assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength));  
-    /* Make sure that NonVDataSegmentLength is properly set to prevent code segment access */
-    if (fw_init->NonVDataSegmentLength < 0x100)
-    {
-      return HAL_ERROR;
-    }
-  }
-  /* Non volatile data segment */
-  if (fw_init->NonVDataSegmentLength != 0U)
-  {
-    assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(fw_init->NonVDataSegmentStartAddress));
-    assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength));  
-  }
-  /* Volatile data segment */
-  if (fw_init->VDataSegmentLength != 0U)
-  {
-    assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(fw_init->VDataSegmentStartAddress));
-    assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength));  
-  }
-  
-  /* Check Firewall Configuration Register parameters */
-  assert_param(IS_FIREWALL_VOLATILEDATA_EXECUTE(fw_init->VolatileDataExecution));
-  assert_param(IS_FIREWALL_VOLATILEDATA_SHARE(fw_init->VolatileDataShared));
-  
-  
-   /* Configuration */
-  
-  /* Protected code segment start address configuration */
-  WRITE_REG(FIREWALL->CSSA, (FW_CSSA_ADD & fw_init->CodeSegmentStartAddress));
-	/* Protected code segment length configuration */
-  WRITE_REG(FIREWALL->CSL, (FW_CSL_LENG & fw_init->CodeSegmentLength));
-  
-  /* Protected non volatile data segment start address configuration */
-  WRITE_REG(FIREWALL->NVDSSA, (FW_NVDSSA_ADD & fw_init->NonVDataSegmentStartAddress));
-	/* Protected non volatile data segment length configuration */
-  WRITE_REG(FIREWALL->NVDSL, (FW_NVDSL_LENG & fw_init->NonVDataSegmentLength));
-  
-  /* Protected volatile data segment start address configuration */
-  WRITE_REG(FIREWALL->VDSSA, (FW_VDSSA_ADD & fw_init->VDataSegmentStartAddress));
-	/* Protected volatile data segment length configuration */
-  WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength));  
-  
-  /* Set Firewall Configuration Register VDE and VDS bits
-     (volatile data execution and shared configuration) */  
-  MODIFY_REG(FIREWALL->CR, FW_CR_VDS|FW_CR_VDE, fw_init->VolatileDataExecution|fw_init->VolatileDataShared);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Retrieve the Firewall configuration.
-  * @param fw_config: Firewall configuration, type is same as initialization structure
-  * @note This API can't be executed inside a code area protected by the Firewall
-  *       when the Firewall is enabled
-  * @note If NVDSL register is different from 0, that is, if the non volatile data segment 
-  *       is defined, this API can't be executed when the Firewall is enabled.      
-  * @note User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status            
-  * @retval None
-  */
-void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config)
-{
-
-  /* Enable Firewall clock, in case no Firewall configuration has been carried 
-     out up to this point */
-  __HAL_RCC_FIREWALL_CLK_ENABLE();
-
-  /* Retrieve code segment protection setting */
-  fw_config->CodeSegmentStartAddress = (READ_REG(FIREWALL->CSSA) & FW_CSSA_ADD);
-  fw_config->CodeSegmentLength = (READ_REG(FIREWALL->CSL) & FW_CSL_LENG);
-  
-  /* Retrieve non volatile data segment protection setting */
-  fw_config->NonVDataSegmentStartAddress = (READ_REG(FIREWALL->NVDSSA) & FW_NVDSSA_ADD);
-  fw_config->NonVDataSegmentLength = (READ_REG(FIREWALL->NVDSL) & FW_NVDSL_LENG);
-  
-  /* Retrieve volatile data segment protection setting */
-  fw_config->VDataSegmentStartAddress = (READ_REG(FIREWALL->VDSSA) & FW_VDSSA_ADD);
-  fw_config->VDataSegmentLength = (READ_REG(FIREWALL->VDSL) & FW_VDSL_LENG);     
-  
-  /* Retrieve volatile data execution setting */
-  fw_config->VolatileDataExecution = (READ_REG(FIREWALL->CR) & FW_CR_VDE);
-  
-  /* Retrieve volatile data shared setting */
-  fw_config->VolatileDataShared = (READ_REG(FIREWALL->CR) & FW_CR_VDS);
-  
-  return;
-}
-
-
-
-/**
-  * @brief Enable FIREWALL. 
-  * @note Firewall is enabled in clearing FWDIS bit of SYSCFG CFGR1 register.
-  *       Once enabled, the Firewall cannot be disabled by software. Only a 
-  *       system reset can set again FWDIS bit.           
-  * @retval None
-  */
-void HAL_FIREWALL_EnableFirewall(void)
-{
-  /* Clears FWDIS bit of SYSCFG CFGR1 register */
-  CLEAR_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN);
-  
-}
-
-/**
-  * @brief Enable FIREWALL pre arm. 
-  * @note When FPA bit is set, any code executed outside the protected segment 
-  *       will close the Firewall. 
-  * @note This API provides the same service as __HAL_FIREWALL_PREARM_ENABLE() macro
-  *       but can't be executed inside a code area protected by the Firewall. 
-  * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.   
-  * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, 
-  *          when the non volatile data segment is not defined),
-  *          **  this API can be executed when the Firewall is closed
-  *          **  when the Firewall is opened, user should resort to 
-  *              __HAL_FIREWALL_PREARM_ENABLE() macro instead
-  * @note When the Firewall is enabled and  NVDSL register is different from 0
-  *          (that is, when the non volatile data segment is defined)
-  *          **  FW_CR register can be accessed only when the Firewall is opened: 
-  *              user should resort to  __HAL_FIREWALL_PREARM_ENABLE() macro instead.               
-  * @retval None
-  */
-void HAL_FIREWALL_EnablePreArmFlag(void)
-{
-  /* Set FPA bit */
-  SET_BIT(FIREWALL->CR, FW_CR_FPA);
-}
-
-
-/**
-  * @brief Disable FIREWALL pre arm.
-  * @note When FPA bit is reset, any code executed outside the protected segment 
-  *       when the Firewall is opened will generate a system reset.
-  * @note This API provides the same service as __HAL_FIREWALL_PREARM_DISABLE() macro
-  *       but can't be executed inside a code area protected by the Firewall.
-  * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.   
-  * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, 
-  *          when the non volatile data segment is not defined),
-  *          **  this API can be executed when the Firewall is closed
-  *          **  when the Firewall is opened, user should resort to 
-  *              __HAL_FIREWALL_PREARM_DISABLE() macro instead
-  * @note When the Firewall is enabled and  NVDSL register is different from 0
-  *          (that is, when the non volatile data segment is defined)
-  *          **  FW_CR register can be accessed only when the Firewall is opened: 
-  *              user should resort to  __HAL_FIREWALL_PREARM_DISABLE() macro instead.               
-          
-  * @retval None
-  */
-void HAL_FIREWALL_DisablePreArmFlag(void)
-{
-  /* Clear FPA bit */
-  CLEAR_BIT(FIREWALL->CR, FW_CR_FPA);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FIREWALL_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-#endif /* #if !defined (STM32L010xB) && !defined (STM32L010x8) && !defined (STM32L010x6) && !defined (STM32L010x4) && !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c
deleted file mode 100644
index 346998a3d3..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c
+++ /dev/null
@@ -1,769 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_flash.c
-  * @author  MCD Application Team
-  * @brief   FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the internal FLASH memory:
-  *           + Program operations functions
-  *           + Memory Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                        ##### FLASH peripheral features #####
-  ==============================================================================
-  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
-       to the Flash memory. It implements the erase and program Flash memory operations 
-       and the read and write protection mechanisms.
-
-  [..] The Flash memory interface accelerates code execution with a system of instruction
-      prefetch. 
-
-  [..] The FLASH main features are:
-      (+) Flash memory read operations
-      (+) Flash memory program/erase operations
-      (+) Read / write protections
-      (+) Prefetch on I-Code
-      (+) Option Bytes programming
-
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]                             
-      This driver provides functions and macros to configure and program the FLASH 
-      memory of all STM32L0xx devices.
-    
-      (#) FLASH Memory I/O Programming functions: this group includes all needed
-          functions to erase and program the main memory:
-        (++) Lock and Unlock the FLASH interface
-        (++) Erase function: Erase page
-        (++) Program functions: Fast Word and Half Page(should be 
-        executed from internal SRAM).
-  
-      (#) DATA EEPROM Programming functions: this group includes all 
-          needed functions to erase and program the DATA EEPROM memory:
-        (++) Lock and Unlock the DATA EEPROM interface.
-        (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase 
-             Double Word (should be executed from internal SRAM).
-        (++) Program functions: Fast Program Byte, Fast Program Half-Word, 
-             FastProgramWord, Program Byte, Program Half-Word, 
-             Program Word and Program Double-Word (should be executed 
-             from internal SRAM).
-
-      (#) FLASH Option Bytes Programming functions: this group includes all needed
-          functions to manage the Option Bytes:
-        (++) Lock and Unlock the Option Bytes
-        (++) Set/Reset the write protection
-        (++) Set the Read protection Level
-        (++) Program the user Option Bytes
-        (++) Launch the Option Bytes loader
-        (++) Set/Get the Read protection Level.
-        (++) Set/Get the BOR level.
-        (++) Get the Write protection.
-        (++) Get the user option bytes.
-    
-      (#) Interrupts and flags management functions : this group 
-          includes all needed functions to:
-        (++) Handle FLASH interrupts
-        (++) Wait for last FLASH operation according to its status
-        (++) Get error flag status
-
-    (#) FLASH Interface configuration functions: this group includes 
-      the management of following features:
-      (++) Enable/Disable the RUN PowerDown mode.
-      (++) Enable/Disable the SLEEP PowerDown mode.  
-  
-    (#) FLASH Peripheral State methods: this group includes 
-      the management of following features:
-      (++) Wait for the FLASH operation
-      (++)  Get the specific FLASH error flag
-    
-  [..] In addition to these function, this driver includes a set of macros allowing
-       to handle the following operations:
-      
-      (+) Set/Get the latency
-      (+) Enable/Disable the prefetch buffer
-      (+) Enable/Disable the preread buffer
-      (+) Enable/Disable the Flash power-down
-      (+) Enable/Disable the FLASH interrupts
-      (+) Monitor the FLASH flags status
-          
-                 ##### Programming operation functions #####
-  ===============================================================================  
-     [..]
-     This subsection provides a set of functions allowing to manage the FLASH 
-     program operations.
-  
-    [..] The FLASH Memory Programming functions, includes the following functions:
-     (+) HAL_FLASH_Unlock(void);
-     (+) HAL_FLASH_Lock(void);
-     (+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-     (+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-    
-     [..] Any operation of erase or program should follow these steps:
-     (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and 
-         program memory access.
-     (#) Call the desired function to erase page or program data.
-     (#) Call the HAL_FLASH_Lock() to disable the flash program memory access 
-        (recommended to protect the FLASH memory against possible unwanted operation).
-  
-               ##### Option Bytes Programming functions ##### 
-   ==============================================================================  
-  
-     [..] The FLASH_Option Bytes Programming_functions, includes the following functions:
-     (+) HAL_FLASH_OB_Unlock(void);
-     (+) HAL_FLASH_OB_Lock(void);
-     (+) HAL_FLASH_OB_Launch(void);
-     (+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-     (+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-    
-     [..] Any operation of erase or program should follow these steps:
-     (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control 
-         register access.
-     (#) Call the following functions to program the desired option bytes.
-         (++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);      
-     (#) Once all needed option bytes to be programmed are correctly written, call the
-         HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
-     (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended
-         to protect the option Bytes against possible unwanted operations).
-  
-    [..] Proprietary code Read Out Protection (PcROP):    
-    (#) The PcROP sector is selected by using the same option bytes as the Write
-        protection. As a result, these 2 options are exclusive each other.
-    (#) To activate PCROP mode for Flash sectors(s), you need to follow the sequence below:
-        (++) Use this function HAL_FLASHEx_AdvOBProgram with PCROPState = OB_PCROP_STATE_ENABLE.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @defgroup FLASH FLASH
-  * @brief FLASH HAL module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private macro ---------------------------- ---------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
-  * @{
-  */
- 
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
-  * @{
-  */
-/* Variables used for Erase pages under interruption*/
-FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private Functions
-  * @{
-  */
-static  void   FLASH_SetErrorCode(void);
-extern void    FLASH_PageErase(uint32_t PageAddress);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
-  * @{
-  */
-  
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
-  *  @brief   Programming operation functions 
-  *
-@verbatim   
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Program word at a specified address
-  * @note   To correctly run this function, the HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASH_Lock() to disable the flash memory access
-  *         (recommended to protect the FLASH memory against possible unwanted operation).
-  *
-  * @param  TypeProgram   Indicate the way to program at a specified address.
-  *                       This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address       Specifie the address to be programmed.
-  * @param  Data          Specifie the data to be programmed
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /*Program word (32-bit) at a specified address.*/
-    *(__IO uint32_t *)Address = Data;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief   Program word at a specified address  with interrupt enabled.
-  *
-  * @param  TypeProgram  Indicate the way to program at a specified address.
-  *                      This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address      Specifie the address to be programmed.
-  * @param  Data         Specifie the data to be programmed
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-  /* Enable End of FLASH Operation and Error source interrupts */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-  
-  pFlash.Address = Address;
-  pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
-  /* Clean the error context */
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-  if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
-  {
-    /* Program word (32-bit) at a specified address. */
-    *(__IO uint32_t *)Address = Data;
-  }
-  return status;
-}
-
-/**
-  * @brief This function handles FLASH interrupt request.
-  * @retval None
-  */
-void HAL_FLASH_IRQHandler(void)
-{
-  uint32_t addresstmp = 0;
-  
-  /* Check FLASH operation error flags */
-
-  /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
-   *           (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
-   *           as expected. If the user run an application using the first
-   *           cut of the STM32L031xx device or the first cut of the STM32L041xx
-   *           device, the check on the FLASH_FLAG_OPTVERR bit should be ignored.
-   *
-   *           Note :The revId of the device can be retrieved via the HAL_GetREVID()
-   *           function.
-   *
-   */
-
-  if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)    || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)      || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) )
-  {
-    if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
-    {
-      /* Return the faulty sector */
-      addresstmp = pFlash.Page;
-      pFlash.Page = 0xFFFFFFFFU;
-    }
-    else
-    {
-      /* Return the faulty address */
-      addresstmp = pFlash.Address;
-    }
-    /* Save the Error code */
-    FLASH_SetErrorCode();
-    
-    /* FLASH error interrupt user callback */
-    HAL_FLASH_OperationErrorCallback(addresstmp);
-
-    /* Stop the procedure ongoing */
-    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-  }
-
-  /* Check FLASH End of Operation flag  */
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-    
-    /* Process can continue only if no error detected */
-    if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
-    {
-      if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
-      {
-        /* Nb of pages to erased can be decreased */
-        pFlash.NbPagesToErase--;
-
-        /* Check if there are still pages to erase */
-        if(pFlash.NbPagesToErase != 0U)
-        {
-          addresstmp = pFlash.Page;
-          /*Indicate user which sector has been erased */
-          HAL_FLASH_EndOfOperationCallback(addresstmp);
-
-          /*Increment sector number*/
-          addresstmp = pFlash.Page + FLASH_PAGE_SIZE;
-          pFlash.Page = addresstmp;
-
-          /* If the erase operation is completed, disable the ERASE Bit */
-          CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-
-          FLASH_PageErase(addresstmp);
-        }
-        else
-        {
-          /* No more pages to Erase, user callback can be called. */
-          /* Reset Sector and stop Erase pages procedure */
-          pFlash.Page = addresstmp = 0xFFFFFFFFU;
-          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-          /* FLASH EOP interrupt user callback */
-          HAL_FLASH_EndOfOperationCallback(addresstmp);
-        }
-      }
-      else
-      {
-          /* If the program operation is completed, disable the PROG Bit */
-          CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
-
-          /* Program ended. Return the selected address */
-          /* FLASH EOP interrupt user callback */
-          HAL_FLASH_EndOfOperationCallback(pFlash.Address);
-        
-          /* Reset Address and stop Program procedure */
-          pFlash.Address = 0xFFFFFFFFU;
-          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-      }
-    }
-  }
-  
-
-  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
-  {
-    /* Operation is completed, disable the PROG and ERASE */
-    CLEAR_BIT(FLASH->PECR, (FLASH_PECR_ERASE | FLASH_PECR_PROG));
-
-    /* Disable End of FLASH Operation and Error source interrupts */
-    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(&pFlash);
-  }
-}
-
-/**
-  * @brief  FLASH end of operation interrupt callback
-  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
-  *                 - Pages Erase: Address of the page which has been erased 
-  *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
-  *                 - Program: Address which was selected for data program
-  * @retval none
-  */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  FLASH operation error interrupt callback
-  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
-  *                 - Pages Erase: Address of the page which returned an error
-  *                 - Program: Address which was selected for data program
-  * @retval none
-  */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
- *  @brief   management functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the FLASH 
-    memory operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlock the FLASH control register access
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)
-{
-  uint32_t primask_bit;
-
-  /* Unlocking FLASH_PECR register access*/
-  if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
-  {
-    /* Disable interrupts to avoid any interruption during unlock sequence */
-    primask_bit = __get_PRIMASK();
-    __disable_irq();
-
-    WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);
-    WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);
-
-    /* Re-enable the interrupts: restore previous priority mask */
-    __set_PRIMASK(primask_bit);
-
-    if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))
-  {
-    /* Disable interrupts to avoid any interruption during unlock sequence */
-    primask_bit = __get_PRIMASK();
-    __disable_irq();
-
-    /* Unlocking the program memory access */
-    WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1);
-    WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2);  
-
-    /* Re-enable the interrupts: restore previous priority mask */
-    __set_PRIMASK(primask_bit);
-
-    if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Locks the FLASH control register access
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
-{
-  /* Set the PRGLOCK Bit to lock the FLASH Registers access */
-  SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK);
-  
-  /* Set the PELOCK Bit to lock the PECR Register access */
-  SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK);
-
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Unlock the FLASH Option Control Registers access.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
-{
-  uint32_t primask_bit;
-
-  if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK))
-  {
-    /* Disable interrupts to avoid any interruption during unlock sequence */
-    primask_bit = __get_PRIMASK();
-    __disable_irq();
-
-    /* Unlocking FLASH_PECR register access*/
-    if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
-    {  
-      /* Unlocking FLASH_PECR register access*/
-      WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);
-      WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);
-    }
-
-    /* Unlocking the option bytes block access */
-    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
-    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
-
-    /* Re-enable the interrupts: restore previous priority mask */
-    __set_PRIMASK(primask_bit);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }  
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Lock the FLASH Option Control Registers access.
-  * @retval HAL Status 
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
-{
-  /* Set the OPTLOCK Bit to lock the option bytes block access */
-  SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK);
-  
-  return HAL_OK;  
-}
-  
-/**
-  * @brief  Launch the option byte loading.
-  * @note   This function will reset automatically the MCU.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
-{
-  /* Set the OBL_Launch bit to launch the option byte loading */
-  SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH);
-  
-  /* Wait for last operation to be completed */
-  return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
-}
-
-/**
-  * @}
-  */  
-
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions 
- *  @brief    Peripheral errors functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection permit to get in run-time errors of  the FLASH peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Get the specific FLASH error flag.
-  * @retval FLASH_ErrorCode The returned value can be:
-  *            @ref FLASH_Error_Codes
-  */
-uint32_t HAL_FLASH_GetError(void)
-{
-   return pFlash.ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-
-/**
-  * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout  maximum flash operation timeout
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
-{
-  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
-     Even if the FLASH operation fails, the BUSY flag will be reset and an error
-     flag will be set */
-     
-  uint32_t tickstart = HAL_GetTick();
-     
-  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
-  { 
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Check FLASH End of Operation flag  */
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-  }
-  
-  if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)    || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)      || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) )
-  {
-    /*Save the error code*/
-
-    /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
-     *           (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
-     *           as expected. If the user run an application using the first
-     *           cut of the STM32L031xx device or the first cut of the STM32L041xx
-     *           device, this error should be ignored. The revId of the device
-     *           can be retrieved via the HAL_GetREVID() function.
-     *
-     */
-    FLASH_SetErrorCode();
-    return HAL_ERROR;
-  }
-
-  /* There is no error flag set */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Set the specific FLASH error flag.
-  * @retval None
-  */
-static void FLASH_SetErrorCode(void)
-{
-  uint32_t flags = 0;
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
-    flags |= FLASH_FLAG_WRPERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
-    flags |= FLASH_FLAG_PGAERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
-  { 
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE;
-    flags |= FLASH_FLAG_SIZERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
-  {
-    /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
-     *           (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
-     *           as expected. If the user run an application using the first
-     *           cut of the STM32L031xx device or the first cut of the STM32L041xx
-     *           device, this error should be ignored. The revId of the device
-     *           can be retrieved via the HAL_GetREVID() function.
-     *
-     */
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
-    flags |= FLASH_FLAG_OPTVERR;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
-    flags |= FLASH_FLAG_RDERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR))
-  { 
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR;
-    flags |= HAL_FLASH_ERROR_FWWERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR))
-  { 
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO;
-    flags |= FLASH_FLAG_NOTZEROERR;
-  }
-
-  /* Clear FLASH error pending bits */
-  __HAL_FLASH_CLEAR_FLAG(flags);
-}  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c
deleted file mode 100644
index 690ca0c5e6..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c
+++ /dev/null
@@ -1,1274 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_flash_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended FLASH HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the internal FLASH memory:
-  *            + FLASH Interface configuration
-  *            + FLASH Memory Erasing
-  *            + DATA EEPROM Programming/Erasing
-  *            + Option Bytes Programming
-  *            + Interrupts management
-  *    
-  @verbatim
-  ==============================================================================
-               ##### Flash peripheral Extended features  #####
-  ==============================================================================
-           
-  [..] Comparing to other products, the FLASH interface for STM32L0xx
-       devices contains the following additional features        
-       (+) Erase functions
-       (+) DATA_EEPROM memory management
-       (+) BOOT option bit configuration       
-       (+) PCROP protection for all sectors
-   
-                      ##### How to use this driver #####
-  ==============================================================================
-  [..] This driver provides functions to configure and program the FLASH memory 
-       of all STM32L0xx. It includes:
-       (+) Full DATA_EEPROM erase and program management
-       (+) Boot activation
-       (+) PCROP protection configuration and control for all pages
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @addtogroup FLASH
-  * @{
-  */
-/** @addtogroup FLASH_Private_Variables
- * @{
- */
-/* Variables used for Erase pages under interruption*/
-extern FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx FLASHEx
-  * @brief FLASH HAL Extension module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
- * @{
- */
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
-  * @{
-  */
-/**
-  * @}
-  */ 
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
- * @{
- */
-void                      FLASH_PageErase(uint32_t PageAddress);
-#if defined(FLASH_OPTR_BFB2)
-static HAL_StatusTypeDef  FLASH_OB_BootConfig(uint8_t OB_BOOT);
-#endif /* FLASH_OPTR_BFB2 */
-static HAL_StatusTypeDef  FLASH_OB_RDPConfig(uint8_t OB_RDP);
-static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
-static HAL_StatusTypeDef  FLASH_OB_BORConfig(uint8_t OB_BOR);
-static uint8_t            FLASH_OB_GetRDP(void);
-static uint8_t            FLASH_OB_GetUser(void);
-static uint8_t            FLASH_OB_GetBOR(void);
-static uint8_t            FLASH_OB_GetBOOTBit1(void);
-static HAL_StatusTypeDef  FLASH_OB_BOOTBit1Config(uint8_t OB_BootBit1);
-#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)  
-static HAL_StatusTypeDef  FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t Sector2, uint32_t NewState);
-#else
-static HAL_StatusTypeDef  FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t NewState);
-#endif
-static uint32_t           FLASH_OB_GetWRP(void);
-#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)  
-static uint32_t           FLASH_OB_GetWRP2(void);
-#endif
-
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
-  * @{
-  */
-
-/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
- *  @brief   FLASH Memory Erasing functions
- *
-@verbatim   
-  ==============================================================================
-                ##### FLASH Erasing Programming functions ##### 
-  ==============================================================================
-
-    [..] The FLASH Memory Erasing functions, includes the following functions:
-    (+) HAL_FLASHEx_Erase: return only when erase has been done
-    (+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback 
-        is called with parameter 0xFFFFFFFF
-
-    [..] Any operation of erase should follow these steps:
-    (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and 
-        program memory access.
-    (#) Call the desired function to erase page.
-    (#) Call the HAL_FLASH_Lock() to disable the flash program memory access 
-       (recommended to protect the FLASH memory against possible unwanted operation).
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Erase the specified FLASH memory Pages 
-  * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access 
-  *         (recommended to protect the FLASH memory against possible unwanted operation)
-  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  * 
-  * @param[out]  PageError pointer to variable  that
-  *         contains the configuration information on faulty page in case of error
-  *         (0xFFFFFFFF means that all the pages have been correctly erased)
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  uint32_t address = 0U;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    /*Initialization of PageError variable*/
-    *PageError = 0xFFFFFFFFU;
-
-    /* Check the parameters */
-    assert_param(IS_NBPAGES(pEraseInit->NbPages));
-    assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-    assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
-    assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U));
-
-    /* Erase page by page to be done*/
-    for(address = pEraseInit->PageAddress; 
-        address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
-        address += FLASH_PAGE_SIZE)
-    {
-      FLASH_PageErase(address);
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-      /* If the erase operation is completed, disable the ERASE Bit */
-      CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
-      CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-
-      if (status != HAL_OK) 
-      {
-        /* In case of error, stop erase procedure and return the faulty address */
-        *PageError = address;
-        break;
-      }
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief  Perform a page erase of the specified FLASH memory pages  with interrupt enabled
-  * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access 
-  *         (recommended to protect the FLASH memory against possible unwanted operation)
-  *          End of erase is done when @ref HAL_FLASH_EndOfOperationCallback is called with parameter
-  *          0xFFFFFFFF
-  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-
-  /* If procedure already ongoing, reject the next one */
-  if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_NBPAGES(pEraseInit->NbPages));
-  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1));
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if (status == HAL_OK)
-  {
-    /* Enable End of FLASH Operation and Error source interrupts */
-    __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-    
-    pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
-    pFlash.NbPagesToErase = pEraseInit->NbPages;
-    pFlash.Page = pEraseInit->PageAddress;
-
-    /*Erase 1st page and wait for IT*/
-    FLASH_PageErase(pEraseInit->PageAddress);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(&pFlash);
-  }
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
- *  @brief   Option Bytes Programming functions
- *
-@verbatim   
-  ==============================================================================
-                ##### Option Bytes Programming functions ##### 
-  ==============================================================================  
-
-    [..] Any operation of erase or program should follow these steps:
-    (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control 
-        register access.
-    (#) Call following function to program the desired option bytes.
-        (++) HAL_FLASHEx_OBProgram:
-         - To Enable/Disable the desired sector write protection.
-         - To set the desired read Protection Level.
-         - To configure the user option Bytes: IWDG, STOP and the Standby.
-         - To Set the BOR level.
-    (#) Once all needed option bytes to be programmed are correctly written, call the
-        HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
-    (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended
-        to protect the option Bytes against possible unwanted operations).
-
-    [..] Proprietary code Read Out Protection (PcROP):
-    (#) The PcROP sector is selected by using the same option bytes as the Write
-        protection (nWRPi bits). As a result, these 2 options are exclusive each other.
-    (#) In order to activate the PcROP (change the function of the nWRPi option bits), 
-        the WPRMOD option bit must be activated.
-    (#) The active value of nWRPi bits is inverted when PCROP mode is active, this
-        means: if WPRMOD = 1 and nWRPi = 1 (default value), then the user sector "i"
-        is read/write protected.
-    (#) To activate PCROP mode for Flash sector(s), you need to call the following function:
-        (++) HAL_FLASHEx_AdvOBProgram in selecting sectors to be read/write protected
-        (++) HAL_FLASHEx_OB_SelectPCROP to enable the read/write protection
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Program option bytes
-  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-
-  /*Write protection configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
-  {
-    assert_param(IS_WRPSTATE(pOBInit->WRPState));
-#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)  
-    status = FLASH_OB_ProtectedSectorsConfig(pOBInit->WRPSector, pOBInit->WRPSector2, pOBInit->WRPState);
-#else
-    status = FLASH_OB_ProtectedSectorsConfig(pOBInit->WRPSector, pOBInit->WRPState);
-#endif
-    if (status != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&pFlash);
-      return status;
-    }
-  }
-  
-  /* Read protection configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
-  {
-    status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
-    if (status != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&pFlash);
-      return status;
-    }
-  }
-  
-  /* USER  configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
-  {
-    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, 
-                                 pOBInit->USERConfig & OB_STOP_NORST,
-                                 pOBInit->USERConfig & OB_STDBY_NORST);
-    if (status != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&pFlash);
-      return status;
-    }
-  }
-
-  /* BOR Level  configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
-  {
-    status = FLASH_OB_BORConfig(pOBInit->BORLevel);
-    if (status != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&pFlash);
-      return status;
-    }
-  }
-
-  /* Program BOOT Bit1 config option byte */
-  if ((pOBInit->OptionType & OPTIONBYTE_BOOT_BIT1) == OPTIONBYTE_BOOT_BIT1)
-  {
-    status = FLASH_OB_BOOTBit1Config(pOBInit->BOOTBit1Config);
-  }
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief   Get the Option byte configuration
-  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval None
-  */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
-
-  /* Get WRP sector */
-  pOBInit->WRPSector = FLASH_OB_GetWRP();
-
-#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)  
-  pOBInit->WRPSector2 = FLASH_OB_GetWRP2();
-#endif
-
-  /*Get RDP Level*/
-  pOBInit->RDPLevel   = FLASH_OB_GetRDP();
-
-  /*Get USER*/
-  pOBInit->USERConfig = FLASH_OB_GetUser();
-
-  /*Get BOR Level*/
-  pOBInit->BORLevel   = FLASH_OB_GetBOR();
-
-  /* Get BOOT bit 1 config OB */
-  pOBInit->BOOTBit1Config = FLASH_OB_GetBOOTBit1();
-}
-
-#if defined(FLASH_OPTR_WPRMOD) || defined(FLASH_OPTR_BFB2)
-    
-/**
-  * @brief  Program option bytes
-  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Check the parameters */
-  assert_param(IS_OBEX(pAdvOBInit->OptionType));
-
-#if defined(FLASH_OPTR_WPRMOD)
-    
-  /* Program PCROP option byte*/
-  if ((pAdvOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
-  {
-    /* Check the parameters */
-    assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
-#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)  
-    status = FLASH_OB_ProtectedSectorsConfig(pAdvOBInit->PCROPSector, pAdvOBInit->PCROPSector2, pAdvOBInit->PCROPState);
-#else
-    status = FLASH_OB_ProtectedSectorsConfig(pAdvOBInit->PCROPSector, pAdvOBInit->PCROPState);
-#endif
-  }
-  
-#endif /* FLASH_OPTR_WPRMOD */
-
-#if defined(FLASH_OPTR_BFB2)
-    
-  /* Program BOOT config option byte */
-  if ((pAdvOBInit->OptionType & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)
-  {
-    status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
-  }
-  
-#endif /* FLASH_OPTR_BFB2 */
-
-  return status;
-}
-
-/**
-  * @brief  Get the OBEX byte configuration
-  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval None
-  */
-void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
-{
-  pAdvOBInit->OptionType = 0;
-  
-#if defined(FLASH_OPTR_WPRMOD)
-      
-  pAdvOBInit->OptionType |= OPTIONBYTE_PCROP;
-
-
-  /* Get PCROP state */
-  pAdvOBInit->PCROPState = (FLASH->OPTR & FLASH_OPTR_WPRMOD) >> FLASH_OPTR_WPRMOD_Pos;
-  /* Get PCROP protected sector */
-  pAdvOBInit->PCROPSector = FLASH->WRPR;
-
-#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)  
-  /* Get PCROP protected sector */
-  pAdvOBInit->PCROPSector2 = FLASH->WRPR2;
-#endif
-#endif /* FLASH_OPTR_WPRMOD */
-
-#if defined(FLASH_OPTR_BFB2)
-      
-  pAdvOBInit->OptionType |= OPTIONBYTE_BOOTCONFIG;
-
-  /* Get Boot config OB */
-  pAdvOBInit->BootConfig = (FLASH->OPTR & FLASH_OPTR_BFB2) >> 16U;
-
-#endif /* FLASH_OPTR_BFB2 */
-}
-
-#endif /* FLASH_OPTR_WPRMOD || FLASH_OPTR_BFB2 */
-
-#if defined(FLASH_OPTR_WPRMOD)
-
-/**
-  * @brief  Select the Protection Mode (WPRMOD).
-  * @note   Once WPRMOD bit is active, unprotection of a protected sector is not possible 
-  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint16_t tmp1 = 0;
-  uint32_t tmp2 = 0;
-  uint8_t optiontmp = 0;
-  uint16_t optiontmp2 = 0;
-  
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  /* Mask RDP Byte */
-  optiontmp =  (uint8_t)(*(__IO uint8_t *)(OB_BASE)); 
-  
-  /* Update Option Byte */
-  optiontmp2 = (uint16_t)(OB_PCROP_SELECTED | optiontmp); 
-  
-  /* calculate the option byte to write */
-  tmp1 = (uint16_t)(~(optiontmp2 ));
-  tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2));
-  
-  if(status == HAL_OK)
-  {         
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* program PCRop */
-    OB->RDP = tmp2;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-  
-  /* Return the Read protection operation Status */
-  return status;            
-}
-
-/**
-  * @brief  Deselect the Protection Mode (WPRMOD).
-  * @note   Once WPRMOD bit is active, unprotection of a protected sector is not possible 
-  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint16_t tmp1 = 0;
-  uint32_t tmp2 = 0;
-  uint8_t optiontmp = 0;
-  uint16_t optiontmp2 = 0;
-  
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  /* Mask RDP Byte */
-  optiontmp =  (uint8_t)(*(__IO uint8_t *)(OB_BASE)); 
-  
-  /* Update Option Byte */
-  optiontmp2 = (uint16_t)(OB_PCROP_DESELECTED | optiontmp); 
-  
-  /* calculate the option byte to write */
-  tmp1 = (uint16_t)(~(optiontmp2 ));
-  tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2));
-  
-  if(status == HAL_OK)
-  {         
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* program PCRop */
-    OB->RDP = tmp2;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-  
-  /* Return the Read protection operation Status */
-  return status;            
-}
-
-#endif /* FLASH_OPTR_WPRMOD */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Exported_Functions_Group3 DATA EEPROM Programming functions
- *  @brief   DATA EEPROM Programming functions
- *
-@verbatim   
- ===============================================================================
-                     ##### DATA EEPROM Programming functions ##### 
- ===============================================================================  
- 
-    [..] Any operation of erase or program should follow these steps:
-    (#) Call the HAL_FLASHEx_DATAEEPROM_Unlock() function to enable the data EEPROM access
-        and Flash program erase control register access.
-    (#) Call the desired function to erase or program data.
-    (#) Call the HAL_FLASHEx_DATAEEPROM_Lock() to disable the data EEPROM access
-        and Flash program erase control register access(recommended
-        to protect the DATA_EEPROM against possible unwanted operation).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlocks the data memory and FLASH_PECR register access.
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void)
-{
-  uint32_t primask_bit;
-
-  if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)
-  {  
-    /* Disable interrupts to avoid any interruption during unlock sequence */
-    primask_bit = __get_PRIMASK();
-    __disable_irq();
-
-    /* Unlocking the Data memory and FLASH_PECR register access*/
-    FLASH->PEKEYR = FLASH_PEKEY1;
-    FLASH->PEKEYR = FLASH_PEKEY2;
-
-    /* Re-enable the interrupts: restore previous priority mask */
-    __set_PRIMASK(primask_bit);
-
-    if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Locks the Data memory and FLASH_PECR register access.
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void)
-{
-  /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */
-  SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Erase a word in data memory.
-  * @param  Address specifies the address to be erased.
-  * @note   To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASHEx_DATAEEPROM_Lock() to the data EEPROM access
-  *         and Flash program erase control register access(recommended to protect 
-  *         the DATA_EEPROM against possible unwanted operation).
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-      /* Write 00000000h to valid address in the data memory */
-      *(__IO uint32_t *) Address = 0x00000000U;
-
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-   
-  /* Return the erase status */
-  return status;
-}  
-
-/**
-  * @brief  Program word at a specified address
-  * @note   To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASHEx_DATAEEPROM_Unlock() to he data EEPROM access
-  *         and Flash program erase control register access(recommended to protect 
-  *         the DATA_EEPROM against possible unwanted operation).
-  * @note   The function @ref HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram() can be called before 
-  *         this function to configure the Fixed Time Programming.
-  * @param  TypeProgram  Indicate the way to program at a specified address.
-  *         This parameter can be a value of @ref FLASHEx_Type_Program_Data
-  * @param  Address  specifie the address to be programmed.
-  * @param  Data     specifie the data to be programmed
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-
-HAL_StatusTypeDef   HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_TYPEPROGRAMDATA(TypeProgram));
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    if(TypeProgram == FLASH_TYPEPROGRAMDATA_WORD)
-    {
-      /* Program word (32-bit) at a specified address.*/
-      *(__IO uint32_t *)Address = Data;
-    }
-    else if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD)
-    {
-      /* Program halfword (16-bit) at a specified address.*/
-      *(__IO uint16_t *)Address = (uint16_t) Data;
-    }
-    else if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE)
-    {
-      /* Program byte (8-bit) at a specified address.*/
-      *(__IO uint8_t *)Address = (uint8_t) Data;
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-
-    if (status != HAL_OK)
-    {
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief  Enable DATA EEPROM fixed Time programming (2*Tprog).
-  * @retval None
-  */
-void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void)
-{
-  SET_BIT(FLASH->PECR, FLASH_PECR_FIX);
-}
-
-/**
-  * @brief  Disables DATA EEPROM fixed Time programming (2*Tprog).
-  * @retval None
-  */
-void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void)
-{
-  CLEAR_BIT(FLASH->PECR, FLASH_PECR_FIX);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASHEx_Private_Functions
- * @{
- */
-
-/*
-==============================================================================
-              OPTIONS BYTES
-==============================================================================
-*/
-/**
-  * @brief  Enables or disables the read out protection.
-  * @note   To correctly run this function, the @ref HAL_FLASH_OB_Unlock() function
-  *         must be called before.
-  * @param  OB_RDP specifies the read protection level. 
-  *   This parameter can be:
-  *     @arg @ref OB_RDP_LEVEL_0 No protection
-  *     @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
-  *     @arg @ref OB_RDP_LEVEL_2 Chip protection
-  * 
-  *  !!!Warning!!! When enabling OB_RDP_LEVEL_2 it's no more possible to go back to level 1 or 0
-  *   
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_OB_RDP(OB_RDP));
-  
-  tmp1 = (uint32_t)(OB->RDP & FLASH_OPTR_RDPROT);
-  
-#if defined(FLASH_OPTR_WPRMOD)
-    /* Mask WPRMOD bit */
-    tmp3 = (uint32_t)(OB->RDP & FLASH_OPTR_WPRMOD);
-#endif
-
-    /* calculate the option byte to write */
-    tmp1 = (~((uint32_t)(OB_RDP | tmp3)));
-    tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)(OB_RDP | tmp3)));
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-    if(status == HAL_OK)
-    {
-      /* Clean the error context */
-      pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-      /* program read protection level */
-      OB->RDP = tmp2;
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    }
-
-  /* Return the Read protection operation Status */
-  return status;
-}
-
-/**
-  * @brief  Programs the FLASH brownout reset threshold level Option Byte.
-  * @param  OB_BOR Selects the brownout reset threshold level.
-  *   This parameter can be one of the following values:
-  *     @arg @ref OB_BOR_OFF BOR is disabled at power down, the reset is asserted when the VDD 
-  *                      power supply reaches the PDR(Power Down Reset) threshold (1.5V)
-  *     @arg @ref OB_BOR_LEVEL1 BOR Reset threshold levels for 1.7V - 1.8V VDD power supply
-  *     @arg @ref OB_BOR_LEVEL2 BOR Reset threshold levels for 1.9V - 2.0V VDD power supply
-  *     @arg @ref OB_BOR_LEVEL3 BOR Reset threshold levels for 2.3V - 2.4V VDD power supply
-  *     @arg @ref OB_BOR_LEVEL4 BOR Reset threshold levels for 2.55V - 2.65V VDD power supply
-  *     @arg @ref OB_BOR_LEVEL5 BOR Reset threshold levels for 2.8V - 2.9V VDD power supply
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp = 0, tmp1 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_OB_BOR_LEVEL(OB_BOR));
-
-  /* Get the User Option byte register */
-  tmp1 = OB->USER & ((~FLASH_OPTR_BOR_LEV) >> 16U);
-
-  /* Calculate the option byte to write - [0xFF | nUSER | 0x00 | USER]*/
-  tmp = (uint32_t)~((OB_BOR | tmp1)) << 16U;
-  tmp |= (OB_BOR | tmp1);
-    
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {  
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* Write the BOR Option Byte */            
-    OB->USER = tmp;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-  
-  /* Return the Option Byte BOR programming Status */
-  return status;
-}
-
-/**
-  * @brief  Sets or resets the BOOT bit1 option bit.
-  * @param  OB_BootBit1 Set or Reset the BOOT bit1 option bit.
-  *          This parameter can be one of the following values:
-  *             @arg @ref OB_BOOT_BIT1_RESET BOOT1 option bit reset
-  *             @arg @ref OB_BOOT_BIT1_SET BOOT1 option bit set
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef  FLASH_OB_BOOTBit1Config(uint8_t OB_BootBit1)
-{
-  HAL_StatusTypeDef status = HAL_OK; 
-  uint32_t tmp = 0, tmp1 = 0, OB_Bits = ((uint32_t) OB_BootBit1) << 15;
-
-  /* Check the parameters */
-  assert_param(IS_OB_BOOT1(OB_BootBit1));
-
-  /* Get the User Option byte register */
-  tmp1 = OB->USER & ((~FLASH_OPTR_BOOT1) >> 16U);
-
-  /* Calculate the user option byte to write */ 
-  tmp = (~(OB_Bits | tmp1)) << 16U;
-  tmp |= OB_Bits | tmp1;
-    
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {  
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-    /* Program OB */
-    OB->USER = tmp; 
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Returns the FLASH User Option Bytes values.
-  * @retval The FLASH User Option Bytes.
-  */
-static uint8_t FLASH_OB_GetUser(void)
-{
-  /* Return the User Option Byte */
-  return (uint8_t)((FLASH->OPTR & FLASH_OPTR_USER) >> 16U);
-}
-
-/**
-  * @brief  Returns the FLASH Read Protection level.
-  * @retval FLASH RDP level
-  *         This parameter can be one of the following values:
-  *            @arg @ref OB_RDP_LEVEL_0 No protection
-  *            @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
-  *            @arg @ref OB_RDP_LEVEL_2 Full chip protection
-  */
-static uint8_t FLASH_OB_GetRDP(void)
-{
-  uint8_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDPROT);
-
-  if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
-  {
-    return (OB_RDP_LEVEL_1);
-  }
-  else
-  {
-    return rdp_level;
-  }
-}
-
-/**
-  * @brief  Returns the FLASH BOR level.
-  * @retval The BOR level Option Bytes.
-  */
-static uint8_t FLASH_OB_GetBOR(void)
-{
-  /* Return the BOR level */
-  return (uint8_t)((FLASH->OPTR & (uint32_t)FLASH_OPTR_BOR_LEV) >> 16U);
-}
-
-/**
-  * @brief  Returns the FLASH BOOT bit1 value.
-  * @retval The BOOT bit 1 value Option Bytes.
-  */
-static uint8_t FLASH_OB_GetBOOTBit1(void)
-{
-  /* Return the BOR level */
-  return (FLASH->OPTR & FLASH_OPTR_BOOT1) >> FLASH_OPTR_BOOT1_Pos;
-
-}
-
-/**
-  * @brief  Returns the FLASH Write Protection Option Bytes value.
-  * @retval The FLASH Write Protection Option Bytes value.
-  */
-static uint32_t FLASH_OB_GetWRP(void)
-{
-  /* Return the FLASH write protection Register value */
-  return (uint32_t)(FLASH->WRPR);
-}
-
-#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)  
-/**
-  * @brief  Returns the FLASH Write Protection Option Bytes value.
-  * @retval The FLASH Write Protection Option Bytes value.
-  */
-static uint32_t FLASH_OB_GetWRP2(void)
-{
-  /* Return the FLASH write protection Register value */
-  return (uint32_t)(FLASH->WRPR2);
-}
-#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
-
-#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
-/**
-  * @brief  Write Option Byte of the desired pages of the Flash.
-  * @param  Sector specifies the sectors to be write protected.
-  * @param  Sector2 specifies the sectors to be write protected (only stm32l07xxx and stm32l08xxx devices)
-  * @param  NewState new state of the specified FLASH Pages Write protection.
-  *   This parameter can be: 
-  *        @arg @ref OB_WRPSTATE_ENABLE
-  *        @arg @ref OB_WRPSTATE_DISABLE
-  * @retval HAL_StatusTypeDef
-  */
-static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t Sector2, uint32_t NewState)
-#else
-/**
-  * @brief  Write Option Byte of the desired pages of the Flash.
-  * @param  Sector specifies the sectors to be write protected.
-  * @param  NewState new state of the specified FLASH Pages Write protection.
-  *   This parameter can be: 
-  *        @arg @ref OB_WRPSTATE_ENABLE
-  *        @arg @ref OB_WRPSTATE_DISABLE
-  * @retval HAL_StatusTypeDef
-  */
-static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t NewState)
-#endif
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t WRP_Data = 0;
-  uint32_t OB_WRP = Sector;
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
- 
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* Update WRP only if at least 1 selected sector */
-    if (OB_WRP != 0x00000000U)
-    {
-      if ((OB_WRP & WRP_MASK_LOW) != 0x00000000U)
-      {
-        if (NewState != OB_WRPSTATE_DISABLE)
-        {
-          WRP_Data = (uint16_t)(((OB_WRP & WRP_MASK_LOW) | OB->WRP01));
-          OB->WRP01 = (uint32_t)(~(WRP_Data) << 16U) | (WRP_Data);
-        }             
-        else
-        {
-          WRP_Data = (uint16_t)(~OB_WRP & (WRP_MASK_LOW & OB->WRP01));
-          OB->WRP01 =  (uint32_t)((~WRP_Data) << 16U) | (WRP_Data);
-        }
-      }
-    }
-#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)  
-    /* Update WRP only if at least 1 selected sector */
-    if (OB_WRP != 0x00000000U)
-    {
-      if ((OB_WRP & WRP_MASK_HIGH) != 0x00000000U)
-      {
-        if (NewState != OB_WRPSTATE_DISABLE)
-        {
-          WRP_Data = (uint16_t)((((OB_WRP & WRP_MASK_HIGH) >> 16U | OB->WRP23))); 
-          OB->WRP23 = (uint32_t)(~(WRP_Data) << 16U) | (WRP_Data);
-        }             
-        else
-        {
-          WRP_Data = (uint16_t)((((~OB_WRP & WRP_MASK_HIGH) >> 16U & OB->WRP23))); 
-          OB->WRP23 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data);
-        } 
-      }
-    }
-
-    OB_WRP = Sector2;
-    /* Update WRP only if at least 1 selected sector */
-    if (OB_WRP != 0x00000000U)
-    {
-      if ((OB_WRP & WRP_MASK_LOW) != 0x00000000U)
-      {
-        if (NewState != OB_WRPSTATE_DISABLE)
-        {
-          WRP_Data = (uint16_t)(((OB_WRP & WRP_MASK_LOW) | OB->WRP45));
-          OB->WRP45 =(uint32_t)(~(WRP_Data) << 16U) | (WRP_Data);
-        }             
-        else
-        {
-          WRP_Data = (uint16_t)(~OB_WRP & (WRP_MASK_LOW & OB->WRP45));
-          OB->WRP45 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data);
-        }
-      }
-    }
-#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
-  }
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  /* Return the write protection operation Status */
-  return status;      
-}
-
-/**
-  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-  * @param  OB_IWDG Selects the WDG mode.
-  *   This parameter can be one of the following values:
-  *     @arg @ref OB_IWDG_SW Software WDG selected
-  *     @arg @ref OB_IWDG_HW Hardware WDG selected
-  * @param  OB_STOP Reset event when entering STOP mode.
-  *   This parameter can be one of the following values:
-  *     @arg @ref OB_STOP_NORST No reset generated when entering in STOP
-  *     @arg @ref OB_STOP_RST Reset generated when entering in STOP
-  * @param  OB_STDBY Reset event when entering Standby mode.
-  *   This parameter can be one of the following values:
-  *     @arg @ref OB_STDBY_NORST No reset generated when entering in STANDBY
-  *     @arg @ref OB_STDBY_RST Reset generated when entering in STANDBY
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
-{
-  HAL_StatusTypeDef status = HAL_OK; 
-  uint32_t tmp = 0, tmp1 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
-  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
-  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
-  /* Get the User Option byte register */
-  tmp1 = OB->USER & ((~FLASH_OPTR_USER) >> 16U);
-
-  /* Calculate the user option byte to write */ 
-  tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16U);
-  tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {  
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* Write the User Option Byte */
-    OB->USER = tmp;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-#if defined(FLASH_OPTR_BFB2)
-/**
-  * @brief  Configures to boot from Bank1 or Bank2.
-  * @param  OB_BOOT select the FLASH Bank to boot from.
-  *   This parameter can be one of the following values:
-  *          This parameter can be one of the following values:
-  *             @arg @ref OB_BOOT_BANK1 BFB2 option bit reset
-  *             @arg @ref OB_BOOT_BANK2 BFB2 option bit set
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT)
-{
-  HAL_StatusTypeDef status = HAL_OK; 
-  uint32_t tmp = 0U, tmp1 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_OB_BOOT_BANK(OB_BOOT));
-
-  /* Get the User Option byte register  and BOR Level*/
-  tmp1 = OB->USER & ((~FLASH_OPTR_BFB2) >> 16U);
-
-  /* Calculate the option byte to write */
-  tmp = (uint32_t)~(OB_BOOT | tmp1) << 16U;
-  tmp |= (OB_BOOT | tmp1);
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {  
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* Write the BOOT Option Byte */
-    OB->USER = tmp;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-#endif /* FLASH_OPTR_BFB2 */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */
-
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-
-/**
-  * @brief  Erases a specified page in program memory.
-  * @param  PageAddress The page address in program memory to be erased.
-  * @note   A Page is erased in the Program memory only if the address to load 
-  *         is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
-  * @retval None
-  */
-void FLASH_PageErase(uint32_t PageAddress)
-{
-  /* Clean the error context */
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-  /* Set the ERASE bit */
-  SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-
-  /* Set PROG bit */
-  SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
-
-  /* Write 00000000h to the first word of the program page to erase */
-  *(__IO uint32_t *)(uint32_t)(PageAddress & ~(FLASH_PAGE_SIZE - 1)) = 0x00000000;
-}
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c
deleted file mode 100644
index f511eebfb1..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c
+++ /dev/null
@@ -1,521 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_flash_ramfunc.c
-  * @author  MCD Application Team
-  * @brief   FLASH RAMFUNC driver.
-  *          This file provides a Flash firmware functions which should be 
-  *          executed from internal SRAM
-  *
-  *  @verbatim
-
-    *** ARM Compiler ***
-    --------------------
-    [..] RAM functions are defined using the toolchain options. 
-         Functions that are be executed in RAM should reside in a separate
-         source module. Using the 'Options for File' dialog you can simply change
-         the 'Code / Const' area of a module to a memory space in physical RAM.
-         Available memory areas are declared in the 'Target' tab of the 
-         Options for Target' dialog.
-
-    *** ICCARM Compiler ***
-    -----------------------
-    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
-
-    *** GNU Compiler ***
-    --------------------
-    [..] RAM functions are defined using a specific toolchain attribute
-         "__attribute__((section(".RamFunc")))".
-
-@endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @addtogroup FLASH
-  * @{
-  */
-/** @addtogroup FLASH_Private_Variables
- * @{
- */
-extern FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
-  * @brief FLASH functions executed from RAM
-  * @{
-  */ 
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions
- * @{
- */
-
-static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout);
-static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void);
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
- 
-/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions
- *
-@verbatim  
- ===============================================================================
-                      ##### ramfunc functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions that should be executed from RAM 
-    transfers.
-
-@endverbatim
-  * @{
-  */ 
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions 
-  * @{
-  */  
-
-/**
-  * @brief  Enable  the power down mode during RUN mode.
-  * @note  This function can be used only when the user code is running from Internal SRAM.
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
-{
-  /* Enable the Power Down in Run mode*/
-  __HAL_FLASH_POWER_DOWN_ENABLE();
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the power down mode during RUN mode.
-  * @note  This function can be used only when the user code is running from Internal SRAM.
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
-{
-  /* Disable the Power Down in Run mode*/
-  __HAL_FLASH_POWER_DOWN_DISABLE();
-
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions 
- *
-@verbatim  
-@endverbatim
-  * @{
-  */
-
-#if defined(FLASH_PECR_PARALLBANK)
-/**
-  * @brief  Erases a specified 2 pages in program memory in parallel.
-  * @note   This function can be used only for STM32L07xxx/STM32L08xxx  devices.
-  *         To correctly run this function, the @ref HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access 
-  *        (recommended to protect the FLASH memory against possible unwanted operation).
-  * @param  Page_Address1: The page address in program memory to be erased in 
-  *         the first Bank (BANK1). This parameter should be between FLASH_BASE
-  *         and FLASH_BANK1_END.
-  * @param  Page_Address2: The page address in program memory to be erased in 
-  *         the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE
-  *         and FLASH_BANK2_END.
-  * @note   A Page is erased in the Program memory only if the address to load 
-  *         is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Proceed to erase the page */
-    SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
-    SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-    SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
-  
-    /* Write 00000000h to the first word of the first program page to erase */
-    *(__IO uint32_t *)Page_Address1 = 0x00000000U;
-    /* Write 00000000h to the first word of the second program page to erase */    
-    *(__IO uint32_t *)Page_Address2 = 0x00000000U;
- 
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-    /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
-  }     
-  /* Return the Erase Status */
-  return status;
-}
-
-/**
-  * @brief  Program 2 half pages in program memory in parallel (half page size is 16 Words).
-  * @note   This function can be used only for STM32L07xxx/STM32L08xxx  devices.
-  * @param  Address1: specifies the first address to be written in the first bank 
-  *        (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
-  * @param  pBuffer1: pointer to the buffer  containing the data to be  written 
-  *         to the first half page in the first bank.
-  * @param  Address2: specifies the second address to be written in the second bank
-  *        (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
-  * @param  pBuffer2: pointer to the buffer containing the data to be  written 
-  *         to the second half page in the second bank.
-  * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access  
-  *         (recommended to protect the FLASH memory against possible unwanted operation).
-  * @note   Half page write is possible only from SRAM.
-  * @note   A half page is written to the program memory only if the first 
-  *         address to load is the start address of a half page (multiple of 64 
-  *         bytes) and the 15 remaining words to load are in the same half page.
-  * @note   During the Program memory half page write all read operations are 
-  *         forbidden (this includes DMA read operations and debugger read 
-  *         operations such as breakpoints, periodic updates, etc.).
-  * @note   If a PGAERR is set during a Program memory half page write, the 
-  *         complete write operation is aborted. Software should then reset the 
-  *         FPRG and PROG/DATA bits and restart the write operation from the 
-  *         beginning.
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
-{
-  uint32_t count = 0U; 
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Proceed to program the new half page */
-    SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
-    SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
-    SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
-
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    if(status == HAL_OK)
-    {
-      /* Disable all IRQs */
-      __disable_irq();
-
-      /* Write the first half page directly with 16 different words */
-      while(count < 16U)
-      {
-        /* Address1 doesn't need to be increased */ 
-        *(__IO uint32_t*) Address1 = *pBuffer1;
-        pBuffer1++;
-        count ++;  
-      }
-
-      /* Write the second half page directly with 16 different words */
-      count = 0U;
-      while(count < 16U)
-      {
-        /* Address2 doesn't need to be increased */ 
-        *(__IO uint32_t*) Address2 = *pBuffer2;
-        pBuffer2++;
-        count ++;  
-      }
-
-      /* Enable IRQs */
-      __enable_irq();
-
-      /* Wait for last operation to be completed */
-      status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    }
-
-    /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
-  }
-
-  /* Return the Write Status */
-  return status;
-}
-#endif /* FLASH_PECR_PARALLBANK */
-
-/**
-  * @brief  Program a half page in program memory.
-  * @param  Address specifies the address to be written.
-  * @param  pBuffer pointer to the buffer  containing the data to be  written to 
-  *         the half page.
-  * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access  
-  *         (recommended to protect the FLASH memory against possible unwanted operation)
-  * @note   Half page write is possible only from SRAM.
-  * @note   A half page is written to the program memory only if the first 
-  *         address to load is the start address of a half page (multiple of 64 
-  *         bytes) and the 15 remaining words to load are in the same half page.
-  * @note   During the Program memory half page write all read operations are 
-  *         forbidden (this includes DMA read operations and debugger read 
-  *         operations such as breakpoints, periodic updates, etc.).
-  * @note   If a PGAERR is set during a Program memory half page write, the 
-  *         complete write operation is aborted. Software should then reset the 
-  *         FPRG and PROG/DATA bits and restart the write operation from the 
-  *         beginning.
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
-{
-  uint32_t count = 0U; 
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Proceed to program the new half page */
-    SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
-    SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
-    
-    /* Disable all IRQs */
-    __disable_irq();
-
-    /* Write one half page directly with 16 different words */
-    while(count < 16U)
-    {
-      /* Address doesn't need to be increased */ 
-      *(__IO uint32_t*) Address = *pBuffer;
-      pBuffer++;
-      count ++;  
-    }
-
-    /* Enable IRQs */
-    __enable_irq();
-
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
- 
-    /* If the write operation is completed, disable the PROG and FPRG bits */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
-  }
-
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions 
- *  @brief    Peripheral errors functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral errors functions #####
- ===============================================================================  
-    [..]
-    This subsection permit to get in run-time errors of  the FLASH peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Get the specific FLASH errors flag.
-  * @param  Error pointer is the error value. It can be a mixed of:
-  *            @arg @ref HAL_FLASH_ERROR_RD      FLASH Read Protection error flag (PCROP)
-  *            @arg @ref HAL_FLASH_ERROR_SIZE    FLASH Programming Parallelism error flag  
-  *            @arg @ref HAL_FLASH_ERROR_PGA     FLASH Programming Alignment error flag
-  *            @arg @ref HAL_FLASH_ERROR_WRP     FLASH Write protected error flag
-  *            @arg @ref HAL_FLASH_ERROR_OPTV    FLASH Option valid error flag 
-  *            @arg @ref HAL_FLASH_ERROR_FWWERR  FLASH Write or Erase operation aborted
-  *            @arg @ref HAL_FLASH_ERROR_NOTZERO FLASH Write operation is done in a not-erased region
-  * @retval HAL Status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t * Error)
-{ 
-  *Error = pFlash.ErrorCode;
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_RAMFUNC_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  Set the specific FLASH error flag.
-  * @retval HAL Status
-  */
-static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void)
-{
-  uint32_t flags = 0;
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
-    flags |= FLASH_FLAG_WRPERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
-    flags |= FLASH_FLAG_PGAERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
-  { 
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE;
-    flags |= FLASH_FLAG_SIZERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
-  {
-    /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
-     *           (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
-     *           as expected. If the user run an application using the first
-     *           cut of the STM32L031xx device or the first cut of the STM32L041xx
-     *           device, this error should be ignored. The revId of the device
-     *           can be retrieved via the HAL_GetREVID() function.
-     *
-     */
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
-    flags |= FLASH_FLAG_OPTVERR;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
-    flags |= FLASH_FLAG_RDERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR))
-  { 
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR;
-    flags |= HAL_FLASH_ERROR_FWWERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR))
-  { 
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO;
-    flags |= FLASH_FLAG_NOTZEROERR;
-  }
-
-  /* Clear FLASH error pending bits */
-  __HAL_FLASH_CLEAR_FLAG(flags);
-
-  return HAL_OK;
-}  
-
-/**
-  * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout maximum flash operationtimeout
-  * @retval HAL status
-  */
-static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout)
-{ 
-    /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
-       Even if the FLASH operation fails, the BUSY flag will be reset and an error
-       flag will be set */
-       
-    while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U)) 
-    { 
-      Timeout--;
-    }
-    
-    if(Timeout == 0x00U)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-  /* Check FLASH End of Operation flag  */
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-  }
-  
-  if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)    || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)      || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) )
-  {
-    /*Save the error code*/
-
-    /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
-     *           (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
-     *           as expected. If the user run an application using the first
-     *           cut of the STM32L031xx device or the first cut of the STM32L041xx
-     *           device, this error should be ignored. The revId of the device
-     *           can be retrieved via the HAL_GetREVID() function.
-     *
-     */
-    FLASHRAM_SetErrorCode();
-    return HAL_ERROR;
-  }
-
-  /* There is no error flag set */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-     
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c
deleted file mode 100644
index f07472bbb7..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c
+++ /dev/null
@@ -1,532 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_gpio.c
-  * @author  MCD Application Team
-  * @brief   GPIO HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### GPIO Peripheral features #####
-  ==============================================================================
-  [..]
-    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
-  configured by software in several modes:
-        (++) Input mode
-        (++) Analog mode
-        (++) Output mode
-        (++) Alternate function mode
-        (++) External interrupt/event lines
-
-    (+) During and just after reset, the alternate functions and external interrupt
-  lines are not active and the I/O ports are configured in input floating mode.
-
-    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
-  activated or not.
-
-    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
-  type and the IO speed can be selected depending on the VDD value.
-
-    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
-        multiplexer that allows only one peripheral alternate function (AF) connected
-  to an IO pin at a time. In this way, there can be no conflict between peripherals
-  sharing the same IO pin.
-
-    (+) All ports have external interrupt/event capability. To use external interrupt
-  lines, the port must be configured in input mode. All available GPIO pins are
-  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
-    (+) The external interrupt/event controller consists of up to 28 edge detectors
-  (16 lines are connected to GPIO) for generating event/interrupt requests (each
-  input line can be independently configured to select the type (interrupt or event)
-  and the corresponding trigger event (rising or falling or both). Each line can
-  also be masked independently.
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    (#) Enable the GPIO IOPORT clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
-
-    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
-        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
-        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
-             structure.
-        (++) In case of Output or alternate function mode selection: the speed is
-             configured through "Speed" member from GPIO_InitTypeDef structure.
-        (++) In alternate mode is selection, the alternate function connected to the IO
-             is configured through "Alternate" member from GPIO_InitTypeDef structure.
-        (++) Analog mode is required when a pin is to be used as ADC channel
-             or DAC output.
-        (++) In case of external interrupt/event selection the "Mode" member from
-             GPIO_InitTypeDef structure select the type (interrupt or event) and
-             the corresponding trigger event (rising or falling or both).
-
-    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
-        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
-        HAL_NVIC_EnableIRQ().
-
-   (#) HAL_GPIO_DeInit allows to set register values to their reset value. This function
-       is also to be used when unconfiguring pin which was used as an external interrupt
-       or in event mode. That is the only way to reset the corresponding bit in
-       EXTI & SYSCFG registers.
-
-    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
-
-    (#) To set/reset the level of a pin configured in output mode use
-        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-
-    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-
-    (#) During and just after reset, the alternate functions are not
-        active and the GPIO pins are configured in input floating mode (except JTAG
-        pins).
-
-    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
-        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
-        priority over the GPIO function.
-
-    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
-        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
-        The HSE has priority over the GPIO function.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/** @addtogroup GPIO
-  * @brief GPIO HAL module driver
-  * @{
-  */
-
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup GPIO_Private
-  * @{
-  */
-#define GPIO_NUMBER           (16U)
-/**
-  * @}
-  */
-/** @addtogroup GPIO_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group1
- *  @brief    Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
-  * @param  GPIOx where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family devices.
-  *                Note that GPIOE is not available on all devices.
-  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
-  *                    the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
-  uint32_t position = 0x00U;
-  uint32_t iocurrent = 0x00U;
-  uint32_t temp = 0x00U;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-  assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, (GPIO_Init->Pin)));
-
-  /* Configure the port pins */
-  while (((GPIO_Init->Pin) >> position) != 0)
-  {
-    /* Get the IO position */
-    iocurrent = (GPIO_Init->Pin) & (1U << position);
-
-    if (iocurrent)
-    {
-      /*--------------------- GPIO Mode Configuration ------------------------*/
-      /* In case of Output or Alternate function mode selection */
-      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
-          ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
-      {
-        /* Check the Speed parameter */
-        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
-        /* Configure the IO Speed */
-        temp = GPIOx->OSPEEDR;
-        temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U));
-        temp |= (GPIO_Init->Speed << (position * 2U));
-        GPIOx->OSPEEDR = temp;
-
-        /* Configure the IO Output Type */
-        temp = GPIOx->OTYPER;
-        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
-        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
-        GPIOx->OTYPER = temp;
-      }
-
-      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
-      {
-        /* Check the Pull parameter */
-        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
-        /* Activate the Pull-up or Pull down resistor for the current IO */
-        temp = GPIOx->PUPDR;
-        temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
-        temp |= ((GPIO_Init->Pull) << (position * 2U));
-        GPIOx->PUPDR = temp;
-      }
-
-      /* In case of Alternate function mode selection */
-      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
-      {
-        /* Check the Alternate function parameters */
-        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
-        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
-        /* Configure Alternate function mapped with the current IO */
-        temp = GPIOx->AFR[position >> 3U];
-        temp &= ~(0xFUL << ((uint32_t)(position & 0x07UL) * 4U));
-        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
-        GPIOx->AFR[position >> 3U] = temp;
-      }
-
-      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
-      temp = GPIOx->MODER;
-      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
-      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
-      GPIOx->MODER = temp;
-
-      /*--------------------- EXTI Mode Configuration ------------------------*/
-      /* Configure the External Interrupt or event for the current IO */
-      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
-      {
-        /* Enable SYSCFG Clock */
-        __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-        temp = SYSCFG->EXTICR[position >> 2U];
-        CLEAR_BIT(temp, (0x0FUL) << (4U * (position & 0x03U)));
-        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03U)));
-        SYSCFG->EXTICR[position >> 2U] = temp;
-
-        /* Clear EXTI line configuration */
-        temp = EXTI->IMR;
-        temp &= ~((uint32_t)iocurrent);
-        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->IMR = temp;
-
-        temp = EXTI->EMR;
-        temp &= ~((uint32_t)iocurrent);
-        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->EMR = temp;
-
-        /* Clear Rising Falling edge configuration */
-        temp = EXTI->RTSR;
-        temp &= ~((uint32_t)iocurrent);
-        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->RTSR = temp;
-
-        temp = EXTI->FTSR;
-        temp &= ~((uint32_t)iocurrent);
-        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->FTSR = temp;
-      }
-    }
-    position++;
-  }
-}
-
-/**
-  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family devices.
-  *                Note that GPIOE is not available on all devices.
-  * @param  GPIO_Pin specifies the port bit to be written.
-  *                   This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  *                   All port bits are not necessarily available on all GPIOs.
-  * @retval None
-  */
-void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
-{
-  uint32_t position = 0x00U;
-  uint32_t iocurrent = 0x00U;
-  uint32_t tmp = 0x00U;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
-
-  /* Configure the port pins */
-  while ((GPIO_Pin >> position) != 0)
-  {
-    /* Get the IO position */
-    iocurrent = (GPIO_Pin) & (1U << position);
-
-    if (iocurrent)
-    {
-      /*------------------------- EXTI Mode Configuration --------------------*/
-      /* Clear the External Interrupt or Event for the current IO */
-
-      tmp = SYSCFG->EXTICR[position >> 2U];
-      tmp &= ((0x0FUL) << (4U * (position & 0x03U)));
-      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
-      {
-        /* Clear EXTI line configuration */
-        EXTI->IMR &= ~((uint32_t)iocurrent);
-        EXTI->EMR &= ~((uint32_t)iocurrent);
-
-        /* Clear Rising Falling edge configuration */
-        EXTI->RTSR &= ~((uint32_t)iocurrent);
-        EXTI->FTSR &= ~((uint32_t)iocurrent);
-        
-        tmp = (0x0FUL) << (4U * (position & 0x03U));
-        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
-      }
-
-      /*------------------------- GPIO Mode Configuration --------------------*/
-      /* Configure IO Direction in Input Floting Mode */
-      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
-
-      /* Configure the default Alternate Function in current IO */
-      GPIOx->AFR[position >> 3U] &= ~(0xFUL << ((uint32_t)(position & 0x07UL) * 4U));
-
-      /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
-      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
-
-      /* Configure the default value IO Output Type */
-      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position);
-
-      /* Configure the default value for IO Speed */
-      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U));
-    }
-    position++;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group2
- *  @brief   GPIO Read and Write
- *
-@verbatim
- ===============================================================================
-                       ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads the specified input port pin.
-  * @param  GPIOx where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices.
-  *                Note that GPIOE is not available on all devices.
-  * @param  GPIO_Pin specifies the port bit to read.
-  *                   This parameter can be GPIO_PIN_x where x can be (0..15).
-  *                   All port bits are not necessarily available on all GPIOs.
-  * @retval The input port pin value.
-  */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
-  GPIO_PinState bitstatus;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
-
-  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
-  {
-    bitstatus = GPIO_PIN_SET;
-  }
-  else
-  {
-    bitstatus = GPIO_PIN_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Sets or clears the selected data port bit.
-  *
-  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
-  *         accesses. In this way, there is no risk of an IRQ occurring between
-  *         the read and the modify access.
-  *
-  * @param  GPIOx where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices.
-  *                Note that GPIOE is not available on all devices.
-  * @param  GPIO_Pin specifies the port bit to be written.
-  *                   This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  *                   All port bits are not necessarily available on all GPIOs.
-  * @param  PinState specifies the value to be written to the selected bit.
-  *                   This parameter can be one of the GPIO_PinState enum values:
-  *                        GPIO_PIN_RESET: to clear the port pin
-  *                        GPIO_PIN_SET: to set the port pin
-  * @retval None
-  */
-void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
-  assert_param(IS_GPIO_PIN_ACTION(PinState));
-
-  if (PinState != GPIO_PIN_RESET)
-  {
-    GPIOx->BSRR = GPIO_Pin;
-  }
-  else
-  {
-    GPIOx->BRR = GPIO_Pin ;
-  }
-}
-
-/**
-  * @brief  Toggles the specified GPIO pins.
-  * @param  GPIOx Where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices.
-  *                Note that GPIOE is not available on all devices.
-  *                All port bits are not necessarily available on all GPIOs.
-  * @param  GPIO_Pin Specifies the pins to be toggled.
-  * @retval None
-  */
-void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
-  uint32_t odr;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
-
-  /* get current Ouput Data Register value */
-  odr = GPIOx->ODR;
-
-  /* Set selected pins that were at low level, and reset ones that were high */
-  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
-}
-
-/**
-* @brief  Locks GPIO Pins configuration registers.
-* @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
-*         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
-* @note   The configuration of the locked GPIO pins can no longer be modified
-*         until the next reset.
-* @param  GPIOx where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family.
-*                Note that GPIOE is not available on all devices.
-* @param  GPIO_Pin specifies the port bit to be locked.
-*         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-*         All port bits are not necessarily available on all GPIOs.
-* @retval None
-*/
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
-  __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
-
-  /* Apply lock key write sequence */
-  tmp |= GPIO_Pin;
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
-  GPIOx->LCKR = GPIO_Pin;
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Read LCKK register. This read is mandatory to complete key lock sequence */
-  tmp = GPIOx->LCKR;
-
-  /* read again in order to confirm lock is active */
-  if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
-  {
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-/**
-  * @brief  This function handles EXTI interrupt request.
-  * @param  GPIO_Pin Specifies the pins connected to the EXTI line.
-  * @retval None
-  */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
-  /* EXTI line interrupt detected */
-  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
-  {
-    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
-    HAL_GPIO_EXTI_Callback(GPIO_Pin);
-  }
-}
-
-/**
-  * @brief  EXTI line detection callbacks.
-  * @param  GPIO_Pin Specifies the pins connected to the EXTI line.
-  * @retval None
-  */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(GPIO_Pin);
-
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_GPIO_EXTI_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c
deleted file mode 100644
index f644a74dfc..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c
+++ /dev/null
@@ -1,6794 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_i2c.c
-  * @author  MCD Application Team
-  * @brief   I2C HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and Errors functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The I2C HAL driver can be used as follows:
-
-    (#) Declare a I2C_HandleTypeDef handle structure, for example:
-        I2C_HandleTypeDef  hi2c;
-
-    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
-        (##) Enable the I2Cx interface clock
-        (##) I2C pins configuration
-            (+++) Enable the clock for the I2C GPIOs
-            (+++) Configure I2C pins as alternate function open-drain
-        (##) NVIC configuration if you need to use interrupt process
-            (+++) Configure the I2Cx interrupt priority
-            (+++) Enable the NVIC I2C IRQ Channel
-        (##) DMA Configuration if you need to use DMA process
-            (+++) Declare a DMA_HandleTypeDef handle structure for
-                  the transmit or receive channel
-            (+++) Enable the DMAx interface clock using
-            (+++) Configure the DMA handle parameters
-            (+++) Configure the DMA Tx or Rx channel
-            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
-                  the DMA Tx or Rx channel
-
-    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
-        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
-
-    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
-        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
-
-    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
-
-    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
-
-    *** Polling mode IO operation ***
-    =================================
-    [..]
-      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
-      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
-      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
-      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
-
-    *** Polling mode IO MEM operation ***
-    =====================================
-    [..]
-      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
-      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
-
-
-    *** Interrupt mode IO operation ***
-    ===================================
-    [..]
-      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
-      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
-      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
-      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
-      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
-      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
-      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
-      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
-           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
-      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
-      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
-      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
-           This action will inform Master to generate a Stop condition to discard the communication.
-
-
-    *** Interrupt mode or DMA mode IO sequential operation ***
-    ==========================================================
-    [..]
-      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
-          when a direction change during transfer
-    [..]
-      (+) A specific option field manage the different steps of a sequential transfer
-      (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
-      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
-           no sequential mode
-      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
-                            and data to transfer without a final stop condition
-      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
-                            start condition, address and data to transfer without a final stop condition,
-                            an then permit a call the same master sequential interface several times
-                            (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
-                            or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
-      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
-                            and with new data to transfer if the direction change or manage only the new data to
-                            transfer
-                            if no direction change and without a final stop condition in both cases
-      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
-                            and with new data to transfer if the direction change or manage only the new data to
-                            transfer
-                            if no direction change and with a final stop condition in both cases
-      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
-                            after several call of the same master sequential interface several times
-                            (link with option I2C_FIRST_AND_NEXT_FRAME).
-                            Usage can, transfer several bytes one by one using
-                              HAL_I2C_Master_Seq_Transmit_IT
-                              or HAL_I2C_Master_Seq_Receive_IT
-                              or HAL_I2C_Master_Seq_Transmit_DMA
-                              or HAL_I2C_Master_Seq_Receive_DMA
-                              with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
-                             Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
-                              Receive sequence permit to call the opposite interface Receive or Transmit
-                              without stopping the communication and so generate a restart condition.
-      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
-                            each call of the same master sequential
-                            interface.
-                            Usage can, transfer several bytes one by one with a restart with slave address between
-                            each bytes using
-                              HAL_I2C_Master_Seq_Transmit_IT
-                              or HAL_I2C_Master_Seq_Receive_IT
-                              or HAL_I2C_Master_Seq_Transmit_DMA
-                              or HAL_I2C_Master_Seq_Receive_DMA
-                              with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
-                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
-                            generation of STOP condition.
-
-      (+) Different sequential I2C interfaces are listed below:
-      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
-            HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
-      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
-            users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
-      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
-            HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
-      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
-      (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
-      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
-      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
-            HAL_I2C_DisableListen_IT()
-      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
-           add their own code to check the Address Match Code and the transmission direction request by master
-           (Write/Read).
-      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
-          add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
-      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
-            HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
-      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
-            users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
-      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
-            HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
-      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
-      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
-           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
-      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
-           This action will inform Master to generate a Stop condition to discard the communication.
-
-    *** Interrupt mode IO MEM operation ***
-    =======================================
-    [..]
-      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
-          HAL_I2C_Mem_Write_IT()
-      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
-      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
-          HAL_I2C_Mem_Read_IT()
-      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
-           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
-
-    *** DMA mode IO operation ***
-    ==============================
-    [..]
-      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
-          HAL_I2C_Master_Transmit_DMA()
-      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
-      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
-          HAL_I2C_Master_Receive_DMA()
-      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
-      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
-          HAL_I2C_Slave_Transmit_DMA()
-      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
-      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
-          HAL_I2C_Slave_Receive_DMA()
-      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
-           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
-      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
-      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
-      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
-           This action will inform Master to generate a Stop condition to discard the communication.
-
-    *** DMA mode IO MEM operation ***
-    =================================
-    [..]
-      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
-          HAL_I2C_Mem_Write_DMA()
-      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
-      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
-          HAL_I2C_Mem_Read_DMA()
-      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
-           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
-
-
-     *** I2C HAL driver macros list ***
-     ==================================
-     [..]
-       Below the list of most used macros in I2C HAL driver.
-
-      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
-      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
-      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
-      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
-      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
-      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
-      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
-
-     *** Callback registration ***
-     =============================================
-    [..]
-     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
-     allows the user to configure dynamically the driver callbacks.
-     Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
-     to register an interrupt callback.
-    [..]
-     Function HAL_I2C_RegisterCallback() allows to register following callbacks:
-       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
-       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
-       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
-       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
-       (+) ListenCpltCallback   : callback for end of listen mode.
-       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
-       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
-       (+) ErrorCallback        : callback for error detection.
-       (+) AbortCpltCallback    : callback for abort completion process.
-       (+) MspInitCallback      : callback for Msp Init.
-       (+) MspDeInitCallback    : callback for Msp DeInit.
-     This function takes as parameters the HAL peripheral handle, the Callback ID
-     and a pointer to the user callback function.
-    [..]
-     For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
-    [..]
-     Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
-     weak function.
-     HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
-     and the Callback ID.
-     This function allows to reset following callbacks:
-       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
-       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
-       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
-       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
-       (+) ListenCpltCallback   : callback for end of listen mode.
-       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
-       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
-       (+) ErrorCallback        : callback for error detection.
-       (+) AbortCpltCallback    : callback for abort completion process.
-       (+) MspInitCallback      : callback for Msp Init.
-       (+) MspDeInitCallback    : callback for Msp DeInit.
-    [..]
-     For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
-    [..]
-     By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
-     all callbacks are set to the corresponding weak functions:
-     examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
-     Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
-     these callbacks are null (not registered beforehand).
-     If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
-     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-    [..]
-     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
-     Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
-     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-     Then, the user first registers the MspInit/MspDeInit user callbacks
-     using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
-     or HAL_I2C_Init() function.
-    [..]
-     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
-     not defined, the callback registration feature is not available and all callbacks
-     are set to the corresponding weak functions.
-
-     [..]
-       (@) You can refer to the I2C HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2C I2C
-  * @brief I2C HAL module driver
-  * @{
-  */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup I2C_Private_Define I2C Private Define
-  * @{
-  */
-#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
-#define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
-#define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
-
-#define MAX_NBYTE_SIZE      255U
-#define SLAVE_ADDR_SHIFT     7U
-#define SLAVE_ADDR_MSK       0x06U
-
-/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
-                                                         (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
-                                              (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
-/*!< Mask State define, keep only RX and TX bits */
-#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))
-/*!< Default Value */
-#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
-                                              (uint32_t)HAL_I2C_MODE_MASTER))
-/*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
-                                              (uint32_t)HAL_I2C_MODE_MASTER))
-/*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
-                                              (uint32_t)HAL_I2C_MODE_SLAVE))
-/*!< Slave Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
-                                              (uint32_t)HAL_I2C_MODE_SLAVE))
-/*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
-#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
-                                              (uint32_t)HAL_I2C_MODE_MEM))
-/*!< Memory Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
-                                              (uint32_t)HAL_I2C_MODE_MEM))
-/*!< Memory Busy RX, combinaison of State LSB and Mode enum */
-
-
-/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /*!< Bit field can be combinated with
-                                                         @ref I2C_XFER_LISTEN_IT */
-#define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /*!< Bit field can be combinated with
-                                                         @ref I2C_XFER_LISTEN_IT */
-#define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
-                                                         and @ref I2C_XFER_RX_IT */
-
-#define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /*!< Bit definition to manage addition of global Error
-                                                         and NACK treatment */
-#define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /*!< Bit definition to manage only STOP evenement */
-#define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /*!< Bit definition to manage only Reload of NBYTE */
-
-/* Private define Sequential Transfer Options default/reset value */
-#define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-/* Private functions to handle DMA transfer */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAError(DMA_HandleTypeDef *hdma);
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
-
-/* Private functions to handle IT transfer */
-static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
-static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
-static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
-
-/* Private functions to handle IT transfer */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
-                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
-                                                uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
-                                               uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
-                                               uint32_t Tickstart);
-
-/* Private functions for I2C transfer IRQ handler */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
-                                           uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
-                                          uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
-                                            uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
-                                           uint32_t ITSources);
-
-/* Private functions to handle flags during polling transfer */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
-                                                    uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
-                                                        uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
-                                                        uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
-                                                        uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
-                                                 uint32_t Tickstart);
-
-/* Private functions to centralize the enable/disable of Interrupts */
-static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-
-/* Private function to treat different error callback */
-static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
-
-/* Private function to flush TXDR register */
-static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
-
-/* Private function to handle  start, restart or stop a transfer */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
-                               uint32_t Request);
-
-/* Private function to Convert Specific options */
-static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Functions I2C Exported Functions
-  * @{
-  */
-
-/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          deinitialize the I2Cx peripheral:
-
-      (+) User must Implement HAL_I2C_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_I2C_Init() to configure the selected device with
-          the selected configuration:
-        (++) Clock Timing
-        (++) Own Address 1
-        (++) Addressing mode (Master, Slave)
-        (++) Dual Addressing mode
-        (++) Own Address 2
-        (++) Own Address 2 Mask
-        (++) General call mode
-        (++) Nostretch mode
-
-      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
-          of the selected I2Cx peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the I2C according to the specified parameters
-  *         in the I2C_InitTypeDef and initialize the associated handle.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
-{
-  /* Check the I2C handle allocation */
-  if (hi2c == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
-  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
-  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
-  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
-  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
-  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
-  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
-
-  if (hi2c->State == HAL_I2C_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hi2c->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    /* Init the I2C Callback settings */
-    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
-    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
-    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
-    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
-    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
-    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
-    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
-    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
-    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
-    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
-
-    if (hi2c->MspInitCallback == NULL)
-    {
-      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
-    }
-
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
-    hi2c->MspInitCallback(hi2c);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
-    HAL_I2C_MspInit(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-
-  hi2c->State = HAL_I2C_STATE_BUSY;
-
-  /* Disable the selected I2C peripheral */
-  __HAL_I2C_DISABLE(hi2c);
-
-  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
-  /* Configure I2Cx: Frequency range */
-  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
-
-  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
-  /* Disable Own Address1 before set the Own Address1 configuration */
-  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
-
-  /* Configure I2Cx: Own Address1 and ack own address1 mode */
-  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-  {
-    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
-  }
-  else /* I2C_ADDRESSINGMODE_10BIT */
-  {
-    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
-  }
-
-  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
-  /* Configure I2Cx: Addressing Master mode */
-  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-  {
-    hi2c->Instance->CR2 = (I2C_CR2_ADD10);
-  }
-  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
-  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
-
-  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
-  /* Disable Own Address2 before set the Own Address2 configuration */
-  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
-
-  /* Configure I2Cx: Dual mode and Own Address2 */
-  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
-                          (hi2c->Init.OwnAddress2Masks << 8));
-
-  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
-  /* Configure I2Cx: Generalcall and NoStretch mode */
-  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
-
-  /* Enable the selected I2C peripheral */
-  __HAL_I2C_ENABLE(hi2c);
-
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the I2C peripheral.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Check the I2C handle allocation */
-  if (hi2c == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-
-  hi2c->State = HAL_I2C_STATE_BUSY;
-
-  /* Disable the I2C Peripheral Clock */
-  __HAL_I2C_DISABLE(hi2c);
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-  if (hi2c->MspDeInitCallback == NULL)
-  {
-    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
-  }
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  hi2c->MspDeInitCallback(hi2c);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_I2C_MspDeInit(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-  hi2c->State = HAL_I2C_STATE_RESET;
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Initialize the I2C MSP.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief DeInitialize the I2C MSP.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MspDeInit could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User I2C Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
-  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
-  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
-  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
-  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
-                                           pI2C_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
-  if (HAL_I2C_STATE_READY == hi2c->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
-        hi2c->MasterTxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
-        hi2c->MasterRxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
-        hi2c->SlaveTxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
-        hi2c->SlaveRxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
-        hi2c->ListenCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
-        hi2c->MemTxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
-        hi2c->MemRxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_ERROR_CB_ID :
-        hi2c->ErrorCallback = pCallback;
-        break;
-
-      case HAL_I2C_ABORT_CB_ID :
-        hi2c->AbortCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_MSPINIT_CB_ID :
-        hi2c->MspInitCallback = pCallback;
-        break;
-
-      case HAL_I2C_MSPDEINIT_CB_ID :
-        hi2c->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_I2C_STATE_RESET == hi2c->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2C_MSPINIT_CB_ID :
-        hi2c->MspInitCallback = pCallback;
-        break;
-
-      case HAL_I2C_MSPDEINIT_CB_ID :
-        hi2c->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-  return status;
-}
-
-/**
-  * @brief  Unregister an I2C Callback
-  *         I2C callback is redirected to the weak predefined callback
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
-  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
-  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
-  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
-  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
-  if (HAL_I2C_STATE_READY == hi2c->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
-        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
-        break;
-
-      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
-        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
-        break;
-
-      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
-        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
-        break;
-
-      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
-        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
-        break;
-
-      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
-        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
-        break;
-
-      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
-        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
-        break;
-
-      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
-        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
-        break;
-
-      case HAL_I2C_ERROR_CB_ID :
-        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
-        break;
-
-      case HAL_I2C_ABORT_CB_ID :
-        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
-        break;
-
-      case HAL_I2C_MSPINIT_CB_ID :
-        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_I2C_MSPDEINIT_CB_ID :
-        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_I2C_STATE_RESET == hi2c->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2C_MSPINIT_CB_ID :
-        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_I2C_MSPDEINIT_CB_ID :
-        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-  return status;
-}
-
-/**
-  * @brief  Register the Slave Address Match I2C Callback
-  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pCallback pointer to the Address Match Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
-  if (HAL_I2C_STATE_READY == hi2c->State)
-  {
-    hi2c->AddrCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-  return status;
-}
-
-/**
-  * @brief  UnRegister the Slave Address Match I2C Callback
-  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
-  if (HAL_I2C_STATE_READY == hi2c->State)
-  {
-    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-  return status;
-}
-
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
-  *  @brief   Data transfers functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2C data
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode.
-            The status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode : The communication is performed using Interrupts
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the
-            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) HAL_I2C_Master_Transmit()
-        (++) HAL_I2C_Master_Receive()
-        (++) HAL_I2C_Slave_Transmit()
-        (++) HAL_I2C_Slave_Receive()
-        (++) HAL_I2C_Mem_Write()
-        (++) HAL_I2C_Mem_Read()
-        (++) HAL_I2C_IsDeviceReady()
-
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) HAL_I2C_Master_Transmit_IT()
-        (++) HAL_I2C_Master_Receive_IT()
-        (++) HAL_I2C_Slave_Transmit_IT()
-        (++) HAL_I2C_Slave_Receive_IT()
-        (++) HAL_I2C_Mem_Write_IT()
-        (++) HAL_I2C_Mem_Read_IT()
-        (++) HAL_I2C_Master_Seq_Transmit_IT()
-        (++) HAL_I2C_Master_Seq_Receive_IT()
-        (++) HAL_I2C_Slave_Seq_Transmit_IT()
-        (++) HAL_I2C_Slave_Seq_Receive_IT()
-        (++) HAL_I2C_EnableListen_IT()
-        (++) HAL_I2C_DisableListen_IT()
-        (++) HAL_I2C_Master_Abort_IT()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) HAL_I2C_Master_Transmit_DMA()
-        (++) HAL_I2C_Master_Receive_DMA()
-        (++) HAL_I2C_Slave_Transmit_DMA()
-        (++) HAL_I2C_Slave_Receive_DMA()
-        (++) HAL_I2C_Mem_Write_DMA()
-        (++) HAL_I2C_Mem_Read_DMA()
-        (++) HAL_I2C_Master_Seq_Transmit_DMA()
-        (++) HAL_I2C_Master_Seq_Receive_DMA()
-        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
-        (++) HAL_I2C_Slave_Seq_Receive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2C_MasterTxCpltCallback()
-        (++) HAL_I2C_MasterRxCpltCallback()
-        (++) HAL_I2C_SlaveTxCpltCallback()
-        (++) HAL_I2C_SlaveRxCpltCallback()
-        (++) HAL_I2C_MemTxCpltCallback()
-        (++) HAL_I2C_MemRxCpltCallback()
-        (++) HAL_I2C_AddrCallback()
-        (++) HAL_I2C_ListenCpltCallback()
-        (++) HAL_I2C_ErrorCallback()
-        (++) HAL_I2C_AbortCpltCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits in master mode an amount of data in blocking mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                          uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr  = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferISR   = NULL;
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
-                         I2C_GENERATE_START_WRITE);
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
-                         I2C_GENERATE_START_WRITE);
-    }
-
-    while (hi2c->XferCount > 0U)
-    {
-      /* Wait until TXIS flag is set */
-      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        return HAL_ERROR;
-      }
-      /* Write data to TXDR */
-      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      hi2c->XferCount--;
-      hi2c->XferSize--;
-
-      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
-      {
-        /* Wait until TCR flag is set */
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        if (hi2c->XferCount > MAX_NBYTE_SIZE)
-        {
-          hi2c->XferSize = MAX_NBYTE_SIZE;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
-                             I2C_NO_STARTSTOP);
-        }
-        else
-        {
-          hi2c->XferSize = hi2c->XferCount;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
-                             I2C_NO_STARTSTOP);
-        }
-      }
-    }
-
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is set */
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode  = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives in master mode an amount of data in blocking mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                         uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr  = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferISR   = NULL;
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
-                         I2C_GENERATE_START_READ);
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
-                         I2C_GENERATE_START_READ);
-    }
-
-    while (hi2c->XferCount > 0U)
-    {
-      /* Wait until RXNE flag is set */
-      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        return HAL_ERROR;
-      }
-
-      /* Read data from RXDR */
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-
-      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
-      {
-        /* Wait until TCR flag is set */
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        if (hi2c->XferCount > MAX_NBYTE_SIZE)
-        {
-          hi2c->XferSize = MAX_NBYTE_SIZE;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
-                             I2C_NO_STARTSTOP);
-        }
-        else
-        {
-          hi2c->XferSize = hi2c->XferCount;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
-                             I2C_NO_STARTSTOP);
-        }
-      }
-    }
-
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is set */
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode  = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmits in slave mode an amount of data in blocking mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                         uint32_t Timeout)
-{
-  uint32_t tickstart;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr  = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferISR   = NULL;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Wait until ADDR flag is set */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_ERROR;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
-    /* If 10bit addressing mode is selected */
-    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-    {
-      /* Wait until ADDR flag is set */
-      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;
-        return HAL_ERROR;
-      }
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-    }
-
-    /* Wait until DIR flag is set Transmitter mode */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_ERROR;
-    }
-
-    while (hi2c->XferCount > 0U)
-    {
-      /* Wait until TXIS flag is set */
-      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;
-        return HAL_ERROR;
-      }
-
-      /* Write data to TXDR */
-      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      hi2c->XferCount--;
-    }
-
-    /* Wait until STOP flag is set */
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Normal use case for Transmitter mode */
-        /* A NACK is generated to confirm the end of transfer */
-        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-      }
-      else
-      {
-        return HAL_ERROR;
-      }
-    }
-
-    /* Clear STOP flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Wait until BUSY flag is reset */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_ERROR;
-    }
-
-    /* Disable Address Acknowledge */
-    hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode  = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in blocking mode
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                        uint32_t Timeout)
-{
-  uint32_t tickstart;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr  = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferISR   = NULL;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Wait until ADDR flag is set */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_ERROR;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
-    /* Wait until DIR flag is reset Receiver mode */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_ERROR;
-    }
-
-    while (hi2c->XferCount > 0U)
-    {
-      /* Wait until RXNE flag is set */
-      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-        /* Store Last receive data if any */
-        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-        {
-          /* Read data from RXDR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          hi2c->XferCount--;
-        }
-
-        return HAL_ERROR;
-      }
-
-      /* Read data from RXDR */
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      hi2c->XferCount--;
-    }
-
-    /* Wait until STOP flag is set */
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_ERROR;
-    }
-
-    /* Clear STOP flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Wait until BUSY flag is reset */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_ERROR;
-    }
-
-    /* Disable Address Acknowledge */
-    hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode  = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                             uint16_t Size)
-{
-  uint32_t xfermode;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
-
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
-      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                            uint16_t Size)
-{
-  uint32_t xfermode;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
-
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
-      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Slave_ISR_IT;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
-      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Slave_ISR_IT;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
-      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                              uint16_t Size)
-{
-  uint32_t xfermode;
-  HAL_StatusTypeDef dmaxferstatus;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_DMA;
-
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    if (hi2c->XferSize > 0U)
-    {
-      if (hi2c->hdmatx != NULL)
-      {
-        /* Set the I2C DMA transfer complete callback */
-        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
-        /* Set the DMA error callback */
-        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-        /* Set the unused DMA callbacks to NULL */
-        hi2c->hdmatx->XferHalfCpltCallback = NULL;
-        hi2c->hdmatx->XferAbortCallback = NULL;
-
-        /* Enable the DMA channel */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
-                                         hi2c->XferSize);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-
-      if (dmaxferstatus == HAL_OK)
-      {
-        /* Send Slave Address */
-        /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
-
-        /* Update XferCount value */
-        hi2c->XferCount -= hi2c->XferSize;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Note : The I2C interrupts must be enabled after unlocking current process
-                  to avoid the risk of I2C interrupt handle execution before current
-                  process unlock */
-        /* Enable ERR and NACK interrupts */
-        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
-        /* Enable DMA Request */
-        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Update Transfer ISR function pointer */
-      hi2c->XferISR = I2C_Master_ISR_IT;
-
-      /* Send Slave Address */
-      /* Set NBYTES to write and generate START condition */
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
-                         I2C_GENERATE_START_WRITE);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
-      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-      /* possible to enable all of these */
-      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
-        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                             uint16_t Size)
-{
-  uint32_t xfermode;
-  HAL_StatusTypeDef dmaxferstatus;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_DMA;
-
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    if (hi2c->XferSize > 0U)
-    {
-      if (hi2c->hdmarx != NULL)
-      {
-        /* Set the I2C DMA transfer complete callback */
-        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
-        /* Set the DMA error callback */
-        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-        /* Set the unused DMA callbacks to NULL */
-        hi2c->hdmarx->XferHalfCpltCallback = NULL;
-        hi2c->hdmarx->XferAbortCallback = NULL;
-
-        /* Enable the DMA channel */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
-                                         hi2c->XferSize);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-
-      if (dmaxferstatus == HAL_OK)
-      {
-        /* Send Slave Address */
-        /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
-        /* Update XferCount value */
-        hi2c->XferCount -= hi2c->XferSize;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Note : The I2C interrupts must be enabled after unlocking current process
-                  to avoid the risk of I2C interrupt handle execution before current
-                  process unlock */
-        /* Enable ERR and NACK interrupts */
-        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
-        /* Enable DMA Request */
-        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Update Transfer ISR function pointer */
-      hi2c->XferISR = I2C_Master_ISR_IT;
-
-      /* Send Slave Address */
-      /* Set NBYTES to read and generate START condition */
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
-                         I2C_GENERATE_START_READ);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
-      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-      /* possible to enable all of these */
-      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
-        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef dmaxferstatus;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Slave_ISR_DMA;
-
-    if (hi2c->hdmatx != NULL)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmatx->XferHalfCpltCallback = NULL;
-      hi2c->hdmatx->XferAbortCallback = NULL;
-
-      /* Enable the DMA channel */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
-                                       hi2c->XferSize);
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (dmaxferstatus == HAL_OK)
-    {
-      /* Enable Address Acknowledge */
-      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
-      /* Enable ERR, STOP, NACK, ADDR interrupts */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef dmaxferstatus;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Slave_ISR_DMA;
-
-    if (hi2c->hdmarx != NULL)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmarx->XferHalfCpltCallback = NULL;
-      hi2c->hdmarx->XferAbortCallback = NULL;
-
-      /* Enable the DMA channel */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
-                                       hi2c->XferSize);
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (dmaxferstatus == HAL_OK)
-    {
-      /* Enable Address Acknowledge */
-      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
-      /* Enable ERR, STOP, NACK, ADDR interrupts */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Write an amount of data in blocking mode to a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr  = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferISR   = NULL;
-
-    /* Send Slave Address and Memory Address */
-    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      return HAL_ERROR;
-    }
-
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-    }
-
-    do
-    {
-      /* Wait until TXIS flag is set */
-      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        return HAL_ERROR;
-      }
-
-      /* Write data to TXDR */
-      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      hi2c->XferCount--;
-      hi2c->XferSize--;
-
-      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
-      {
-        /* Wait until TCR flag is set */
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        if (hi2c->XferCount > MAX_NBYTE_SIZE)
-        {
-          hi2c->XferSize = MAX_NBYTE_SIZE;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
-                             I2C_NO_STARTSTOP);
-        }
-        else
-        {
-          hi2c->XferSize = hi2c->XferCount;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
-                             I2C_NO_STARTSTOP);
-        }
-      }
-
-    } while (hi2c->XferCount > 0U);
-
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode  = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Read an amount of data in blocking mode from a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                   uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr  = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferISR   = NULL;
-
-    /* Send Slave Address and Memory Address */
-    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      return HAL_ERROR;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
-                         I2C_GENERATE_START_READ);
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
-                         I2C_GENERATE_START_READ);
-    }
-
-    do
-    {
-      /* Wait until RXNE flag is set */
-      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
-      {
-        return HAL_ERROR;
-      }
-
-      /* Read data from RXDR */
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-
-      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
-      {
-        /* Wait until TCR flag is set */
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        if (hi2c->XferCount > MAX_NBYTE_SIZE)
-        {
-          hi2c->XferSize = MAX_NBYTE_SIZE;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
-                             I2C_NO_STARTSTOP);
-        }
-        else
-        {
-          hi2c->XferSize = hi2c->XferCount;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
-                             I2C_NO_STARTSTOP);
-        }
-      }
-    } while (hi2c->XferCount > 0U);
-
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode  = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart;
-  uint32_t xfermode;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
-
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Send Slave Address and Memory Address */
-    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
-        != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      return HAL_ERROR;
-    }
-
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
-      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                      uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart;
-  uint32_t xfermode;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
-
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Send Slave Address and Memory Address */
-    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      return HAL_ERROR;
-    }
-
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
-      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart;
-  uint32_t xfermode;
-  HAL_StatusTypeDef dmaxferstatus;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_DMA;
-
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Send Slave Address and Memory Address */
-    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
-        != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      return HAL_ERROR;
-    }
-
-
-    if (hi2c->hdmatx != NULL)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmatx->XferHalfCpltCallback = NULL;
-      hi2c->hdmatx->XferAbortCallback = NULL;
-
-      /* Enable the DMA channel */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
-                                       hi2c->XferSize);
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_READY;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (dmaxferstatus == HAL_OK)
-    {
-      /* Send Slave Address */
-      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
-      /* Update XferCount value */
-      hi2c->XferCount -= hi2c->XferSize;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
-      /* Enable ERR and NACK interrupts */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_READY;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be read
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart;
-  uint32_t xfermode;
-  HAL_StatusTypeDef dmaxferstatus;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_DMA;
-
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Send Slave Address and Memory Address */
-    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      return HAL_ERROR;
-    }
-
-    if (hi2c->hdmarx != NULL)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmarx->XferHalfCpltCallback = NULL;
-      hi2c->hdmarx->XferAbortCallback = NULL;
-
-      /* Enable the DMA channel */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
-                                       hi2c->XferSize);
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_READY;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (dmaxferstatus == HAL_OK)
-    {
-      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
-      /* Update XferCount value */
-      hi2c->XferCount -= hi2c->XferSize;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
-      /* Enable ERR and NACK interrupts */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_READY;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Checks if target device is ready for communication.
-  * @note   This function is used with Memory devices
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  Trials Number of trials
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
-                                        uint32_t Timeout)
-{
-  uint32_t tickstart;
-
-  __IO uint32_t I2C_Trials = 0UL;
-
-  FlagStatus tmp1;
-  FlagStatus tmp2;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    do
-    {
-      /* Generate Start */
-      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
-
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-      /* Wait until STOPF flag is set or a NACK flag is set*/
-      tickstart = HAL_GetTick();
-
-      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
-      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
-
-      while ((tmp1 == RESET) && (tmp2 == RESET))
-      {
-        if (Timeout != HAL_MAX_DELAY)
-        {
-          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-          {
-            /* Update I2C state */
-            hi2c->State = HAL_I2C_STATE_READY;
-
-            /* Update I2C error code */
-            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-
-            /* Process Unlocked */
-            __HAL_UNLOCK(hi2c);
-
-            return HAL_ERROR;
-          }
-        }
-
-        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
-        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
-      }
-
-      /* Check if the NACKF flag has not been set */
-      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
-      {
-        /* Wait until STOPF flag is reset */
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-        /* Device is ready */
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_OK;
-      }
-      else
-      {
-        /* Wait until STOPF flag is reset */
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        /* Clear STOP Flag, auto generated with autoend*/
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-      }
-
-      /* Check if the maximum allowed number of trials has been reached */
-      if (I2C_Trials == Trials)
-      {
-        /* Generate Stop */
-        hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
-        /* Wait until STOPF flag is reset */
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-      }
-
-      /* Increment Trials */
-      I2C_Trials++;
-    } while (I2C_Trials < Trials);
-
-    /* Update I2C state */
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Update I2C error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                                 uint16_t Size, uint32_t XferOptions)
-{
-  uint32_t xfermode;
-  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
-
-    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = hi2c->XferOptions;
-    }
-
-    /* If transfer direction not change and there is no request to start another frame,
-       do not generate Restart Condition */
-    /* Mean Previous state is same as current state */
-    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
-        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
-    {
-      xferrequest = I2C_NO_STARTSTOP;
-    }
-    else
-    {
-      /* Convert OTHER_xxx XferOptions if any */
-      I2C_ConvertOtherXferOptions(hi2c);
-
-      /* Update xfermode accordingly if no reload is necessary */
-      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
-      {
-        xfermode = hi2c->XferOptions;
-      }
-    }
-
-    /* Send Slave Address and set NBYTES to write */
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                                  uint16_t Size, uint32_t XferOptions)
-{
-  uint32_t xfermode;
-  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
-  HAL_StatusTypeDef dmaxferstatus;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferISR     = I2C_Master_ISR_DMA;
-
-    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = hi2c->XferOptions;
-    }
-
-    /* If transfer direction not change and there is no request to start another frame,
-       do not generate Restart Condition */
-    /* Mean Previous state is same as current state */
-    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
-        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
-    {
-      xferrequest = I2C_NO_STARTSTOP;
-    }
-    else
-    {
-      /* Convert OTHER_xxx XferOptions if any */
-      I2C_ConvertOtherXferOptions(hi2c);
-
-      /* Update xfermode accordingly if no reload is necessary */
-      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
-      {
-        xfermode = hi2c->XferOptions;
-      }
-    }
-
-    if (hi2c->XferSize > 0U)
-    {
-      if (hi2c->hdmatx != NULL)
-      {
-        /* Set the I2C DMA transfer complete callback */
-        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
-        /* Set the DMA error callback */
-        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-        /* Set the unused DMA callbacks to NULL */
-        hi2c->hdmatx->XferHalfCpltCallback = NULL;
-        hi2c->hdmatx->XferAbortCallback = NULL;
-
-        /* Enable the DMA channel */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
-                                         hi2c->XferSize);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-
-      if (dmaxferstatus == HAL_OK)
-      {
-        /* Send Slave Address and set NBYTES to write */
-        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
-
-        /* Update XferCount value */
-        hi2c->XferCount -= hi2c->XferSize;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Note : The I2C interrupts must be enabled after unlocking current process
-                  to avoid the risk of I2C interrupt handle execution before current
-                  process unlock */
-        /* Enable ERR and NACK interrupts */
-        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
-        /* Enable DMA Request */
-        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Update Transfer ISR function pointer */
-      hi2c->XferISR = I2C_Master_ISR_IT;
-
-      /* Send Slave Address */
-      /* Set NBYTES to write and generate START condition */
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
-                         I2C_GENERATE_START_WRITE);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
-      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-      /* possible to enable all of these */
-      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
-        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                                uint16_t Size, uint32_t XferOptions)
-{
-  uint32_t xfermode;
-  uint32_t xferrequest = I2C_GENERATE_START_READ;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
-
-    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = hi2c->XferOptions;
-    }
-
-    /* If transfer direction not change and there is no request to start another frame,
-       do not generate Restart Condition */
-    /* Mean Previous state is same as current state */
-    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
-        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
-    {
-      xferrequest = I2C_NO_STARTSTOP;
-    }
-    else
-    {
-      /* Convert OTHER_xxx XferOptions if any */
-      I2C_ConvertOtherXferOptions(hi2c);
-
-      /* Update xfermode accordingly if no reload is necessary */
-      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
-      {
-        xfermode = hi2c->XferOptions;
-      }
-    }
-
-    /* Send Slave Address and set NBYTES to read */
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                                 uint16_t Size, uint32_t XferOptions)
-{
-  uint32_t xfermode;
-  uint32_t xferrequest = I2C_GENERATE_START_READ;
-  HAL_StatusTypeDef dmaxferstatus;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferISR     = I2C_Master_ISR_DMA;
-
-    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = hi2c->XferOptions;
-    }
-
-    /* If transfer direction not change and there is no request to start another frame,
-       do not generate Restart Condition */
-    /* Mean Previous state is same as current state */
-    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
-        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
-    {
-      xferrequest = I2C_NO_STARTSTOP;
-    }
-    else
-    {
-      /* Convert OTHER_xxx XferOptions if any */
-      I2C_ConvertOtherXferOptions(hi2c);
-
-      /* Update xfermode accordingly if no reload is necessary */
-      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
-      {
-        xfermode = hi2c->XferOptions;
-      }
-    }
-
-    if (hi2c->XferSize > 0U)
-    {
-      if (hi2c->hdmarx != NULL)
-      {
-        /* Set the I2C DMA transfer complete callback */
-        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
-        /* Set the DMA error callback */
-        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-        /* Set the unused DMA callbacks to NULL */
-        hi2c->hdmarx->XferHalfCpltCallback = NULL;
-        hi2c->hdmarx->XferAbortCallback = NULL;
-
-        /* Enable the DMA channel */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
-                                         hi2c->XferSize);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-
-      if (dmaxferstatus == HAL_OK)
-      {
-        /* Send Slave Address and set NBYTES to read */
-        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
-
-        /* Update XferCount value */
-        hi2c->XferCount -= hi2c->XferSize;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Note : The I2C interrupts must be enabled after unlocking current process
-                  to avoid the risk of I2C interrupt handle execution before current
-                  process unlock */
-        /* Enable ERR and NACK interrupts */
-        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
-        /* Enable DMA Request */
-        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Update Transfer ISR function pointer */
-      hi2c->XferISR = I2C_Master_ISR_IT;
-
-      /* Send Slave Address */
-      /* Set NBYTES to read and generate START condition */
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
-                         I2C_GENERATE_START_READ);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
-      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-      /* possible to enable all of these */
-      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
-        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                                uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
-    /* and then toggle the HAL slave RX state to TX state */
-    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
-    {
-      /* Disable associated Interrupts */
-      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-      /* Abort DMA Xfer if any */
-      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
-      {
-        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
-        if (hi2c->hdmarx != NULL)
-        {
-          /* Set the I2C DMA Abort callback :
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
-          /* Abort DMA RX */
-          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
-          {
-            /* Call Directly XferAbortCallback function in case of error */
-            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
-          }
-        }
-      }
-    }
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferISR     = I2C_Slave_ISR_IT;
-
-    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
-    {
-      /* Clear ADDR flag after prepare the transfer parameters */
-      /* This action will generate an acknowledge to the Master */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-    /* REnable ADDR interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                                 uint32_t XferOptions)
-{
-  HAL_StatusTypeDef dmaxferstatus;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
-
-    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
-    /* and then toggle the HAL slave RX state to TX state */
-    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
-    {
-      /* Disable associated Interrupts */
-      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
-      {
-        /* Abort DMA Xfer if any */
-        if (hi2c->hdmarx != NULL)
-        {
-          hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
-          /* Set the I2C DMA Abort callback :
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
-          /* Abort DMA RX */
-          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
-          {
-            /* Call Directly XferAbortCallback function in case of error */
-            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
-          }
-        }
-      }
-    }
-    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
-    {
-      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
-      {
-        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
-        /* Abort DMA Xfer if any */
-        if (hi2c->hdmatx != NULL)
-        {
-          /* Set the I2C DMA Abort callback :
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
-          /* Abort DMA TX */
-          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
-          {
-            /* Call Directly XferAbortCallback function in case of error */
-            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
-          }
-        }
-      }
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferISR     = I2C_Slave_ISR_DMA;
-
-    if (hi2c->hdmatx != NULL)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmatx->XferHalfCpltCallback = NULL;
-      hi2c->hdmatx->XferAbortCallback = NULL;
-
-      /* Enable the DMA channel */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
-                                       hi2c->XferSize);
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (dmaxferstatus == HAL_OK)
-    {
-      /* Update XferCount value */
-      hi2c->XferCount -= hi2c->XferSize;
-
-      /* Reset XferSize */
-      hi2c->XferSize = 0;
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
-    {
-      /* Clear ADDR flag after prepare the transfer parameters */
-      /* This action will generate an acknowledge to the Master */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-    /* Enable ERR, STOP, NACK, ADDR interrupts */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                               uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
-    /* and then toggle the HAL slave TX state to RX state */
-    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
-    {
-      /* Disable associated Interrupts */
-      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
-      {
-        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
-        /* Abort DMA Xfer if any */
-        if (hi2c->hdmatx != NULL)
-        {
-          /* Set the I2C DMA Abort callback :
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
-          /* Abort DMA TX */
-          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
-          {
-            /* Call Directly XferAbortCallback function in case of error */
-            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
-          }
-        }
-      }
-    }
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferISR     = I2C_Slave_ISR_IT;
-
-    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
-    {
-      /* Clear ADDR flag after prepare the transfer parameters */
-      /* This action will generate an acknowledge to the Master */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-    /* REnable ADDR interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                                uint32_t XferOptions)
-{
-  HAL_StatusTypeDef dmaxferstatus;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
-      return  HAL_ERROR;
-    }
-
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
-    /* and then toggle the HAL slave TX state to RX state */
-    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
-    {
-      /* Disable associated Interrupts */
-      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
-      {
-        /* Abort DMA Xfer if any */
-        if (hi2c->hdmatx != NULL)
-        {
-          hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
-          /* Set the I2C DMA Abort callback :
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
-          /* Abort DMA TX */
-          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
-          {
-            /* Call Directly XferAbortCallback function in case of error */
-            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
-          }
-        }
-      }
-    }
-    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
-    {
-      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
-      {
-        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
-        /* Abort DMA Xfer if any */
-        if (hi2c->hdmarx != NULL)
-        {
-          /* Set the I2C DMA Abort callback :
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
-          /* Abort DMA RX */
-          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
-          {
-            /* Call Directly XferAbortCallback function in case of error */
-            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
-          }
-        }
-      }
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferISR     = I2C_Slave_ISR_DMA;
-
-    if (hi2c->hdmarx != NULL)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmarx->XferHalfCpltCallback = NULL;
-      hi2c->hdmarx->XferAbortCallback = NULL;
-
-      /* Enable the DMA channel */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
-                                       (uint32_t)pData, hi2c->XferSize);
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (dmaxferstatus == HAL_OK)
-    {
-      /* Update XferCount value */
-      hi2c->XferCount -= hi2c->XferSize;
-
-      /* Reset XferSize */
-      hi2c->XferSize = 0;
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
-    {
-      /* Clear ADDR flag after prepare the transfer parameters */
-      /* This action will generate an acknowledge to the Master */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-    /* REnable ADDR interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Enable the Address listen mode with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
-{
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    hi2c->State = HAL_I2C_STATE_LISTEN;
-    hi2c->XferISR = I2C_Slave_ISR_IT;
-
-    /* Enable the Address Match interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Disable the Address listen mode with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of tmp to prevent undefined behavior of volatile usage */
-  uint32_t tmp;
-
-  /* Disable Address listen mode only if a transfer is not ongoing */
-  if (hi2c->State == HAL_I2C_STATE_LISTEN)
-  {
-    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
-    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-    hi2c->XferISR = NULL;
-
-    /* Disable the Address Match interrupt */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
-{
-  if (hi2c->Mode == HAL_I2C_MODE_MASTER)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Disable Interrupts and Store Previous state */
-    if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
-    {
-      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
-    }
-    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
-    {
-      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-    }
-    else
-    {
-      /* Do nothing */
-    }
-
-    /* Set State at HAL_I2C_STATE_ABORT */
-    hi2c->State = HAL_I2C_STATE_ABORT;
-
-    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
-    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
-    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    /* Wrong usage of abort function */
-    /* This function should be used only in case of abort monitored by master device */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
-  * @{
-  */
-
-/**
-  * @brief  This function handles I2C event interrupt request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
-  /* Get current IT Flags and IT sources value */
-  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
-  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
-
-  /* I2C events treatment -------------------------------------*/
-  if (hi2c->XferISR != NULL)
-  {
-    hi2c->XferISR(hi2c, itflags, itsources);
-  }
-}
-
-/**
-  * @brief  This function handles I2C error interrupt request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
-  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
-  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
-  uint32_t tmperror;
-
-  /* I2C Bus error interrupt occurred ------------------------------------*/
-  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
-      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
-
-    /* Clear BERR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
-  }
-
-  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
-  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
-      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
-
-    /* Clear OVR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
-  }
-
-  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
-  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
-      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
-
-    /* Clear ARLO flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
-  }
-
-  /* Store current volatile hi2c->ErrorCode, misra rule */
-  tmperror = hi2c->ErrorCode;
-
-  /* Call the Error Callback in case of Error detected */
-  if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
-  {
-    I2C_ITError(hi2c, tmperror);
-  }
-}
-
-/**
-  * @brief  Master Tx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Master Rx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
-   */
-}
-
-/** @brief  Slave Tx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Rx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Address Match callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
-  * @param  AddrMatchCode Address Match Code
-  * @retval None
-  */
-__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-  UNUSED(TransferDirection);
-  UNUSED(AddrMatchCode);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_AddrCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Listen Complete callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Memory Tx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Memory Rx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  I2C error callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  I2C abort callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_AbortCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
-  *  @brief   Peripheral State, Mode and Error functions
-  *
-@verbatim
- ===============================================================================
-            ##### Peripheral State, Mode and Error functions #####
- ===============================================================================
-    [..]
-    This subsection permit to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the I2C handle state.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL state
-  */
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
-{
-  /* Return I2C handle state */
-  return hi2c->State;
-}
-
-/**
-  * @brief  Returns the I2C Master, Slave, Memory or no mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL mode
-  */
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->Mode;
-}
-
-/**
-  * @brief  Return the I2C error code.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *              the configuration information for the specified I2C.
-  * @retval I2C Error Code
-  */
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  ITFlags Interrupt flags to handle.
-  * @param  ITSources Interrupt sources enabled.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
-                                           uint32_t ITSources)
-{
-  uint16_t devaddress;
-  uint32_t tmpITFlags = ITFlags;
-
-  /* Process Locked */
-  __HAL_LOCK(hi2c);
-
-  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
-      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
-  {
-    /* Clear NACK Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Set corresponding Error Code */
-    /* No need to generate STOP, it is automatically done */
-    /* Error callback will be send during stop flag treatment */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
-    /* Flush TX register */
-    I2C_Flush_TXDR(hi2c);
-  }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
-           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
-  {
-    /* Remove RXNE flag on temporary variable as read done */
-    tmpITFlags &= ~I2C_FLAG_RXNE;
-
-    /* Read data from RXDR */
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    hi2c->XferSize--;
-    hi2c->XferCount--;
-  }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
-           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
-  {
-    /* Write data to TXDR */
-    hi2c->Instance->TXDR = *hi2c->pBuffPtr;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    hi2c->XferSize--;
-    hi2c->XferCount--;
-  }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
-           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
-  {
-    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
-    {
-      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
-
-      if (hi2c->XferCount > MAX_NBYTE_SIZE)
-      {
-        hi2c->XferSize = MAX_NBYTE_SIZE;
-        I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-      }
-      else
-      {
-        hi2c->XferSize = hi2c->XferCount;
-        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
-        {
-          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
-                             hi2c->XferOptions, I2C_NO_STARTSTOP);
-        }
-        else
-        {
-          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
-                             I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-        }
-      }
-    }
-    else
-    {
-      /* Call TxCpltCallback() if no stop mode is set */
-      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
-      {
-        /* Call I2C Master Sequential complete process */
-        I2C_ITMasterSeqCplt(hi2c);
-      }
-      else
-      {
-        /* Wrong size Status regarding TCR flag event */
-        /* Call the corresponding callback to inform upper layer of End of Transfer */
-        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
-      }
-    }
-  }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
-           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
-  {
-    if (hi2c->XferCount == 0U)
-    {
-      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
-      {
-        /* Generate a stop condition in case of no transfer option */
-        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
-        {
-          /* Generate Stop */
-          hi2c->Instance->CR2 |= I2C_CR2_STOP;
-        }
-        else
-        {
-          /* Call I2C Master Sequential complete process */
-          I2C_ITMasterSeqCplt(hi2c);
-        }
-      }
-    }
-    else
-    {
-      /* Wrong size Status regarding TC flag event */
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
-    }
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-
-  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
-      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
-  {
-    /* Call I2C Master complete process */
-    I2C_ITMasterCplt(hi2c, tmpITFlags);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  ITFlags Interrupt flags to handle.
-  * @param  ITSources Interrupt sources enabled.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
-                                          uint32_t ITSources)
-{
-  uint32_t tmpoptions = hi2c->XferOptions;
-  uint32_t tmpITFlags = ITFlags;
-
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
-  /* Check if STOPF is set */
-  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
-      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
-  {
-    /* Call I2C Slave complete process */
-    I2C_ITSlaveCplt(hi2c, tmpITFlags);
-  }
-
-  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
-      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
-  {
-    /* Check that I2C transfer finished */
-    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
-    /* Mean XferCount == 0*/
-    /* So clear Flag NACKF only */
-    if (hi2c->XferCount == 0U)
-    {
-      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
-        /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
-           Warning[Pa134]: left and right operands are identical */
-      {
-        /* Call I2C Listen complete process */
-        I2C_ITListenCplt(hi2c, tmpITFlags);
-      }
-      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
-      {
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        /* Flush TX register */
-        I2C_Flush_TXDR(hi2c);
-
-        /* Last Byte is Transmitted */
-        /* Call I2C Slave Sequential complete process */
-        I2C_ITSlaveSeqCplt(hi2c);
-      }
-      else
-      {
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-      }
-    }
-    else
-    {
-      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
-      /* Clear NACK Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-      /* Set ErrorCode corresponding to a Non-Acknowledge */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
-      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
-      {
-        /* Call the corresponding callback to inform upper layer of End of Transfer */
-        I2C_ITError(hi2c, hi2c->ErrorCode);
-      }
-    }
-  }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
-           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
-  {
-    if (hi2c->XferCount > 0U)
-    {
-      /* Read data from RXDR */
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-    }
-
-    if ((hi2c->XferCount == 0U) && \
-        (tmpoptions != I2C_NO_OPTION_FRAME))
-    {
-      /* Call I2C Slave Sequential complete process */
-      I2C_ITSlaveSeqCplt(hi2c);
-    }
-  }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
-           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
-  {
-    I2C_ITAddrCplt(hi2c, tmpITFlags);
-  }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
-           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
-  {
-    /* Write data to TXDR only if XferCount not reach "0" */
-    /* A TXIS flag can be set, during STOP treatment      */
-    /* Check if all Data have already been sent */
-    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
-    if (hi2c->XferCount > 0U)
-    {
-      /* Write data to TXDR */
-      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      hi2c->XferCount--;
-      hi2c->XferSize--;
-    }
-    else
-    {
-      if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
-      {
-        /* Last Byte is Transmitted */
-        /* Call I2C Slave Sequential complete process */
-        I2C_ITSlaveSeqCplt(hi2c);
-      }
-    }
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  ITFlags Interrupt flags to handle.
-  * @param  ITSources Interrupt sources enabled.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
-                                            uint32_t ITSources)
-{
-  uint16_t devaddress;
-  uint32_t xfermode;
-
-  /* Process Locked */
-  __HAL_LOCK(hi2c);
-
-  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
-      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
-  {
-    /* Clear NACK Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Set corresponding Error Code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
-    /* No need to generate STOP, it is automatically done */
-    /* But enable STOP interrupt, to treat it */
-    /* Error callback will be send during stop flag treatment */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-
-    /* Flush TX register */
-    I2C_Flush_TXDR(hi2c);
-  }
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
-           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
-  {
-    /* Disable TC interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
-
-    if (hi2c->XferCount != 0U)
-    {
-      /* Recover Slave address */
-      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
-
-      /* Prepare the new XferSize to transfer */
-      if (hi2c->XferCount > MAX_NBYTE_SIZE)
-      {
-        hi2c->XferSize = MAX_NBYTE_SIZE;
-        xfermode = I2C_RELOAD_MODE;
-      }
-      else
-      {
-        hi2c->XferSize = hi2c->XferCount;
-        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
-        {
-          xfermode = hi2c->XferOptions;
-        }
-        else
-        {
-          xfermode = I2C_AUTOEND_MODE;
-        }
-      }
-
-      /* Set the new XferSize in Nbytes register */
-      I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
-      /* Update XferCount value */
-      hi2c->XferCount -= hi2c->XferSize;
-
-      /* Enable DMA Request */
-      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
-      {
-        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-      }
-      else
-      {
-        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-      }
-    }
-    else
-    {
-      /* Call TxCpltCallback() if no stop mode is set */
-      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
-      {
-        /* Call I2C Master Sequential complete process */
-        I2C_ITMasterSeqCplt(hi2c);
-      }
-      else
-      {
-        /* Wrong size Status regarding TCR flag event */
-        /* Call the corresponding callback to inform upper layer of End of Transfer */
-        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
-      }
-    }
-  }
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
-           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
-  {
-    if (hi2c->XferCount == 0U)
-    {
-      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
-      {
-        /* Generate a stop condition in case of no transfer option */
-        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
-        {
-          /* Generate Stop */
-          hi2c->Instance->CR2 |= I2C_CR2_STOP;
-        }
-        else
-        {
-          /* Call I2C Master Sequential complete process */
-          I2C_ITMasterSeqCplt(hi2c);
-        }
-      }
-    }
-    else
-    {
-      /* Wrong size Status regarding TC flag event */
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
-    }
-  }
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
-           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
-  {
-    /* Call I2C Master complete process */
-    I2C_ITMasterCplt(hi2c, ITFlags);
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  ITFlags Interrupt flags to handle.
-  * @param  ITSources Interrupt sources enabled.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
-                                           uint32_t ITSources)
-{
-  uint32_t tmpoptions = hi2c->XferOptions;
-  uint32_t treatdmanack = 0U;
-  HAL_I2C_StateTypeDef tmpstate;
-
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
-  /* Check if STOPF is set */
-  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
-      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
-  {
-    /* Call I2C Slave complete process */
-    I2C_ITSlaveCplt(hi2c, ITFlags);
-  }
-
-  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
-      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
-  {
-    /* Check that I2C transfer finished */
-    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
-    /* Mean XferCount == 0 */
-    /* So clear Flag NACKF only */
-    if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
-        (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
-    {
-      /* Split check of hdmarx, for MISRA compliance */
-      if (hi2c->hdmarx != NULL)
-      {
-        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
-        {
-          if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
-          {
-            treatdmanack = 1U;
-          }
-        }
-      }
-
-      /* Split check of hdmatx, for MISRA compliance  */
-      if (hi2c->hdmatx != NULL)
-      {
-        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
-        {
-          if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
-          {
-            treatdmanack = 1U;
-          }
-        }
-      }
-
-      if (treatdmanack == 1U)
-      {
-        if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
-          /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
-             Warning[Pa134]: left and right operands are identical */
-        {
-          /* Call I2C Listen complete process */
-          I2C_ITListenCplt(hi2c, ITFlags);
-        }
-        else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
-        {
-          /* Clear NACK Flag */
-          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-          /* Flush TX register */
-          I2C_Flush_TXDR(hi2c);
-
-          /* Last Byte is Transmitted */
-          /* Call I2C Slave Sequential complete process */
-          I2C_ITSlaveSeqCplt(hi2c);
-        }
-        else
-        {
-          /* Clear NACK Flag */
-          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-        }
-      }
-      else
-      {
-        /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        /* Set ErrorCode corresponding to a Non-Acknowledge */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
-        /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
-        tmpstate = hi2c->State;
-
-        if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
-        {
-          if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
-          {
-            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-          }
-          else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
-          {
-            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
-          }
-          else
-          {
-            /* Do nothing */
-          }
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-          I2C_ITError(hi2c, hi2c->ErrorCode);
-        }
-      }
-    }
-    else
-    {
-      /* Only Clear NACK Flag, no DMA treatment is pending */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-    }
-  }
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
-           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
-  {
-    I2C_ITAddrCplt(hi2c, ITFlags);
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for write request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
-                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
-                                                uint32_t Tickstart)
-{
-  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
-
-  /* Wait until TXIS flag is set */
-  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-  /* If Memory address size is 8Bit */
-  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
-  {
-    /* Send Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-  /* If Memory address size is 16Bit */
-  else
-  {
-    /* Send MSB of Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
-
-    /* Wait until TXIS flag is set */
-    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Send LSB of Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-
-  /* Wait until TCR flag is set */
-  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for read request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
-                                               uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
-                                               uint32_t Tickstart)
-{
-  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
-
-  /* Wait until TXIS flag is set */
-  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-  /* If Memory address size is 8Bit */
-  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
-  {
-    /* Send Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-  /* If Memory address size is 16Bit */
-  else
-  {
-    /* Send MSB of Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
-
-    /* Wait until TXIS flag is set */
-    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Send LSB of Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-
-  /* Wait until TC flag is set */
-  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  I2C Address complete process callback.
-  * @param  hi2c I2C handle.
-  * @param  ITFlags Interrupt flags to handle.
-  * @retval None
-  */
-static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
-  uint8_t transferdirection;
-  uint16_t slaveaddrcode;
-  uint16_t ownadd1code;
-  uint16_t ownadd2code;
-
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ITFlags);
-
-  /* In case of Listen state, need to inform upper layer of address match code event */
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
-  {
-    transferdirection = I2C_GET_DIR(hi2c);
-    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
-    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
-    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
-
-    /* If 10bits addressing mode is selected */
-    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-    {
-      if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
-      {
-        slaveaddrcode = ownadd1code;
-        hi2c->AddrEventCount++;
-        if (hi2c->AddrEventCount == 2U)
-        {
-          /* Reset Address Event counter */
-          hi2c->AddrEventCount = 0U;
-
-          /* Clear ADDR flag */
-          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          /* Call Slave Addr callback */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-          hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
-#else
-          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-        }
-      }
-      else
-      {
-        slaveaddrcode = ownadd2code;
-
-        /* Disable ADDR Interrupts */
-        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Call Slave Addr callback */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-        hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
-#else
-        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-      }
-    }
-    /* else 7 bits addressing mode is selected */
-    else
-    {
-      /* Disable ADDR Interrupts */
-      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Call Slave Addr callback */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
-#else
-      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-  }
-  /* Else clear address flag only */
-  else
-  {
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-  }
-}
-
-/**
-  * @brief  I2C Master sequential complete process.
-  * @param  hi2c I2C handle.
-  * @retval None
-  */
-static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
-{
-  /* Reset I2C handle mode */
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  /* No Generate Stop, to permit restart mode */
-  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
-  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
-  {
-    hi2c->State         = HAL_I2C_STATE_READY;
-    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
-    hi2c->XferISR       = NULL;
-
-    /* Disable Interrupts */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->MasterTxCpltCallback(hi2c);
-#else
-    HAL_I2C_MasterTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
-  else
-  {
-    hi2c->State         = HAL_I2C_STATE_READY;
-    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-    hi2c->XferISR       = NULL;
-
-    /* Disable Interrupts */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->MasterRxCpltCallback(hi2c);
-#else
-    HAL_I2C_MasterRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  I2C Slave sequential complete process.
-  * @param  hi2c I2C handle.
-  * @retval None
-  */
-static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
-{
-  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
-
-  /* Reset I2C handle mode */
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  /* If a DMA is ongoing, Update handle size context */
-  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
-  {
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-  }
-  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
-  {
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-  }
-  else
-  {
-    /* Do nothing */
-  }
-
-  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
-  {
-    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
-    hi2c->State         = HAL_I2C_STATE_LISTEN;
-    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-
-    /* Disable Interrupts */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->SlaveTxCpltCallback(hi2c);
-#else
-    HAL_I2C_SlaveTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-
-  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
-  {
-    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
-    hi2c->State         = HAL_I2C_STATE_LISTEN;
-    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
-
-    /* Disable Interrupts */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->SlaveRxCpltCallback(hi2c);
-#else
-    HAL_I2C_SlaveRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-}
-
-/**
-  * @brief  I2C Master complete process.
-  * @param  hi2c I2C handle.
-  * @param  ITFlags Interrupt flags to handle.
-  * @retval None
-  */
-static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
-  uint32_t tmperror;
-  uint32_t tmpITFlags = ITFlags;
-  __IO uint32_t tmpreg;
-
-  /* Clear STOP Flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-  /* Disable Interrupts and Store Previous state */
-  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
-  {
-    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
-  }
-  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
-  {
-    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-  }
-  else
-  {
-    /* Do nothing */
-  }
-
-  /* Clear Configuration Register 2 */
-  I2C_RESET_CR2(hi2c);
-
-  /* Reset handle parameters */
-  hi2c->XferISR       = NULL;
-  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
-
-  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
-  {
-    /* Clear NACK Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Set acknowledge error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-  }
-
-  /* Fetch Last receive data if any */
-  if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
-  {
-    /* Read data from RXDR */
-    tmpreg = (uint8_t)hi2c->Instance->RXDR;
-    UNUSED(tmpreg);
-  }
-
-  /* Flush TX register */
-  I2C_Flush_TXDR(hi2c);
-
-  /* Store current volatile hi2c->ErrorCode, misra rule */
-  tmperror = hi2c->ErrorCode;
-
-  /* Call the corresponding callback to inform upper layer of End of Transfer */
-  if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
-  {
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    I2C_ITError(hi2c, hi2c->ErrorCode);
-  }
-  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
-  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->PreviousState = I2C_STATE_NONE;
-
-    if (hi2c->Mode == HAL_I2C_MODE_MEM)
-    {
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->MemTxCpltCallback(hi2c);
-#else
-      HAL_I2C_MemTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-    else
-    {
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->MasterTxCpltCallback(hi2c);
-#else
-      HAL_I2C_MasterTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-  }
-  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
-  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->PreviousState = I2C_STATE_NONE;
-
-    if (hi2c->Mode == HAL_I2C_MODE_MEM)
-    {
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->MemRxCpltCallback(hi2c);
-#else
-      HAL_I2C_MemRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-    else
-    {
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->MasterRxCpltCallback(hi2c);
-#else
-      HAL_I2C_MasterRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-}
-
-/**
-  * @brief  I2C Slave complete process.
-  * @param  hi2c I2C handle.
-  * @param  ITFlags Interrupt flags to handle.
-  * @retval None
-  */
-static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
-  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
-  uint32_t tmpITFlags = ITFlags;
-  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
-
-  /* Clear STOP Flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-  /* Disable Interrupts and Store Previous state */
-  if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
-  {
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
-    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-  }
-  else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
-  {
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
-    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
-  }
-  else
-  {
-    /* Do nothing */
-  }
-
-  /* Disable Address Acknowledge */
-  hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-  /* Clear Configuration Register 2 */
-  I2C_RESET_CR2(hi2c);
-
-  /* Flush TX register */
-  I2C_Flush_TXDR(hi2c);
-
-  /* If a DMA is ongoing, Update handle size context */
-  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
-  {
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
-    if (hi2c->hdmatx != NULL)
-    {
-      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
-    }
-  }
-  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
-  {
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
-    if (hi2c->hdmarx != NULL)
-    {
-      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
-    }
-  }
-  else
-  {
-    /* Do nothing */
-  }
-
-  /* Store Last receive data if any */
-  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
-  {
-    /* Remove RXNE flag on temporary variable as read done */
-    tmpITFlags &= ~I2C_FLAG_RXNE;
-
-    /* Read data from RXDR */
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    if ((hi2c->XferSize > 0U))
-    {
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-    }
-  }
-
-  /* All data are not transferred, so set error code accordingly */
-  if (hi2c->XferCount != 0U)
-  {
-    /* Set ErrorCode corresponding to a Non-Acknowledge */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-  }
-
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-  hi2c->XferISR = NULL;
-
-  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    I2C_ITError(hi2c, hi2c->ErrorCode);
-
-    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-    if (hi2c->State == HAL_I2C_STATE_LISTEN)
-    {
-      /* Call I2C Listen complete process */
-      I2C_ITListenCplt(hi2c, tmpITFlags);
-    }
-  }
-  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
-  {
-    /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
-    I2C_ITSlaveSeqCplt(hi2c);
-
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->PreviousState = I2C_STATE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->ListenCpltCallback(hi2c);
-#else
-    HAL_I2C_ListenCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-  /* Call the corresponding callback to inform upper layer of End of Transfer */
-  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->PreviousState = I2C_STATE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->SlaveRxCpltCallback(hi2c);
-#else
-    HAL_I2C_SlaveRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->PreviousState = I2C_STATE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->SlaveTxCpltCallback(hi2c);
-#else
-    HAL_I2C_SlaveTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  I2C Listen complete process.
-  * @param  hi2c I2C handle.
-  * @param  ITFlags Interrupt flags to handle.
-  * @retval None
-  */
-static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
-  /* Reset handle parameters */
-  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-  hi2c->XferISR = NULL;
-
-  /* Store Last receive data if any */
-  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
-  {
-    /* Read data from RXDR */
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    if ((hi2c->XferSize > 0U))
-    {
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-
-      /* Set ErrorCode corresponding to a Non-Acknowledge */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-    }
-  }
-
-  /* Disable all Interrupts*/
-  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
-  /* Clear NACK Flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2c);
-
-  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-  hi2c->ListenCpltCallback(hi2c);
-#else
-  HAL_I2C_ListenCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  I2C interrupts error process.
-  * @param  hi2c I2C handle.
-  * @param  ErrorCode Error code to handle.
-  * @retval None
-  */
-static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
-{
-  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
-  uint32_t tmppreviousstate;
-
-  /* Reset handle parameters */
-  hi2c->Mode          = HAL_I2C_MODE_NONE;
-  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
-  hi2c->XferCount     = 0U;
-
-  /* Set new error code */
-  hi2c->ErrorCode |= ErrorCode;
-
-  /* Disable Interrupts */
-  if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
-      (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
-      (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
-  {
-    /* Disable all interrupts, except interrupts related to LISTEN state */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
-    /* keep HAL_I2C_STATE_LISTEN if set */
-    hi2c->State         = HAL_I2C_STATE_LISTEN;
-    hi2c->XferISR       = I2C_Slave_ISR_IT;
-  }
-  else
-  {
-    /* Disable all interrupts */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
-    /* If state is an abort treatment on going, don't change state */
-    /* This change will be do later */
-    if (hi2c->State != HAL_I2C_STATE_ABORT)
-    {
-      /* Set HAL_I2C_STATE_READY */
-      hi2c->State         = HAL_I2C_STATE_READY;
-    }
-    hi2c->XferISR       = NULL;
-  }
-
-  /* Abort DMA TX transfer if any */
-  tmppreviousstate = hi2c->PreviousState;
-  if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
-                                 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
-  {
-    if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
-    {
-      hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-    }
-
-    if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
-    {
-      /* Set the I2C DMA Abort callback :
-       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
-      {
-        /* Call Directly XferAbortCallback function in case of error */
-        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
-      }
-    }
-    else
-    {
-      I2C_TreatErrorCallback(hi2c);
-    }
-  }
-  /* Abort DMA RX transfer if any */
-  else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
-                                      (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
-  {
-    if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
-    {
-      hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-    }
-
-    if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
-    {
-      /* Set the I2C DMA Abort callback :
-        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
-      {
-        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
-        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
-      }
-    }
-    else
-    {
-      I2C_TreatErrorCallback(hi2c);
-    }
-  }
-  else
-  {
-    I2C_TreatErrorCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  I2C Error callback treatment.
-  * @param  hi2c I2C handle.
-  * @retval None
-  */
-static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
-{
-  if (hi2c->State == HAL_I2C_STATE_ABORT)
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->PreviousState = I2C_STATE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->AbortCpltCallback(hi2c);
-#else
-    HAL_I2C_AbortCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    hi2c->PreviousState = I2C_STATE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->ErrorCallback(hi2c);
-#else
-    HAL_I2C_ErrorCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  I2C Tx data register flush process.
-  * @param  hi2c I2C handle.
-  * @retval None
-  */
-static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
-{
-  /* If a pending TXIS flag is set */
-  /* Write a dummy data in TXDR to clear it */
-  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
-  {
-    hi2c->Instance->TXDR = 0x00U;
-  }
-
-  /* Flush TX register if not empty */
-  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
-  {
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
-  }
-}
-
-/**
-  * @brief  DMA I2C master transmit process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  /* Derogation MISRAC2012-Rule-11.5 */
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
-  /* If last transfer, enable STOP interrupt */
-  if (hi2c->XferCount == 0U)
-  {
-    /* Enable STOP interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-  }
-  /* else prepare a new DMA transfer and enable TCReload interrupt */
-  else
-  {
-    /* Update Buffer pointer */
-    hi2c->pBuffPtr += hi2c->XferSize;
-
-    /* Set the XferSize to transfer */
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-    }
-
-    /* Enable the DMA channel */
-    if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
-                         hi2c->XferSize) != HAL_OK)
-    {
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
-    }
-    else
-    {
-      /* Enable TC interrupts */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
-    }
-  }
-}
-
-/**
-  * @brief  DMA I2C slave transmit process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  /* Derogation MISRAC2012-Rule-11.5 */
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
-  uint32_t tmpoptions = hi2c->XferOptions;
-
-  if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
-  {
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
-    /* Last Byte is Transmitted */
-    /* Call I2C Slave Sequential complete process */
-    I2C_ITSlaveSeqCplt(hi2c);
-  }
-  else
-  {
-    /* No specific action, Master fully manage the generation of STOP condition */
-    /* Mean that this generation can arrive at any time, at the end or during DMA process */
-    /* So STOP condition should be manage through Interrupt treatment */
-  }
-}
-
-/**
-  * @brief DMA I2C master receive process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  /* Derogation MISRAC2012-Rule-11.5 */
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
-  /* If last transfer, enable STOP interrupt */
-  if (hi2c->XferCount == 0U)
-  {
-    /* Enable STOP interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-  }
-  /* else prepare a new DMA transfer and enable TCReload interrupt */
-  else
-  {
-    /* Update Buffer pointer */
-    hi2c->pBuffPtr += hi2c->XferSize;
-
-    /* Set the XferSize to transfer */
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-    }
-
-    /* Enable the DMA channel */
-    if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
-                         hi2c->XferSize) != HAL_OK)
-    {
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
-    }
-    else
-    {
-      /* Enable TC interrupts */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
-    }
-  }
-}
-
-/**
-  * @brief  DMA I2C slave receive process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  /* Derogation MISRAC2012-Rule-11.5 */
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
-  uint32_t tmpoptions = hi2c->XferOptions;
-
-  if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
-      (tmpoptions != I2C_NO_OPTION_FRAME))
-  {
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
-    /* Call I2C Slave Sequential complete process */
-    I2C_ITSlaveSeqCplt(hi2c);
-  }
-  else
-  {
-    /* No specific action, Master fully manage the generation of STOP condition */
-    /* Mean that this generation can arrive at any time, at the end or during DMA process */
-    /* So STOP condition should be manage through Interrupt treatment */
-  }
-}
-
-/**
-  * @brief  DMA I2C communication error callback.
-  * @param hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAError(DMA_HandleTypeDef *hdma)
-{
-  /* Derogation MISRAC2012-Rule-11.5 */
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
-
-  /* Disable Acknowledge */
-  hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-  /* Call the corresponding callback to inform upper layer of End of Transfer */
-  I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
-}
-
-/**
-  * @brief DMA I2C communication abort callback
-  *        (To be called at end of DMA Abort procedure).
-  * @param hdma DMA handle.
-  * @retval None
-  */
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
-{
-  /* Derogation MISRAC2012-Rule-11.5 */
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
-
-  /* Reset AbortCpltCallback */
-  if (hi2c->hdmatx != NULL)
-  {
-    hi2c->hdmatx->XferAbortCallback = NULL;
-  }
-  if (hi2c->hdmarx != NULL)
-  {
-    hi2c->hdmarx->XferAbortCallback = NULL;
-  }
-
-  I2C_TreatErrorCallback(hi2c);
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Flag Specifies the I2C flag to check.
-  * @param  Status The new Flag status (SET or RESET).
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
-                                                    uint32_t Timeout, uint32_t Tickstart)
-{
-  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
-                                                        uint32_t Tickstart)
-{
-  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
-                                                        uint32_t Tickstart)
-{
-  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
-                                                        uint32_t Tickstart)
-{
-  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check if a STOPF is detected */
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
-    {
-      /* Check if an RXNE is pending */
-      /* Store Last receive data if any */
-      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
-      {
-        /* Return HAL_OK */
-        /* The Reading of data from RXDR will be done in caller function */
-        return HAL_OK;
-      }
-      else
-      {
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-        /* Clear Configuration Register 2 */
-        I2C_RESET_CR2(hi2c);
-
-        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-
-    /* Check for the Timeout */
-    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
-  {
-    /* In case of Soft End condition, generate the STOP condition */
-    if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
-    {
-      /* Generate Stop */
-      hi2c->Instance->CR2 |= I2C_CR2_STOP;
-    }
-    /* Wait until STOP Flag is reset */
-    /* AutoEnd should be initiate after AF */
-    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
-    {
-      /* Check for the Timeout */
-      if (Timeout != HAL_MAX_DELAY)
-      {
-        if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-        {
-          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-          hi2c->State = HAL_I2C_STATE_READY;
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          return HAL_ERROR;
-        }
-      }
-    }
-
-    /* Clear NACKF Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Flush TX register */
-    I2C_Flush_TXDR(hi2c);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_ERROR;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
-  * @param  hi2c I2C handle.
-  * @param  DevAddress Specifies the slave address to be programmed.
-  * @param  Size Specifies the number of bytes to be programmed.
-  *   This parameter must be a value between 0 and 255.
-  * @param  Mode New state of the I2C START condition generation.
-  *   This parameter can be one of the following values:
-  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
-  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
-  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
-  * @param  Request New state of the I2C START condition generation.
-  *   This parameter can be one of the following values:
-  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
-  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
-  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
-  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
-  * @retval None
-  */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
-                               uint32_t Request)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_TRANSFER_MODE(Mode));
-  assert_param(IS_TRANSFER_REQUEST(Request));
-
-  /* update CR2 register */
-  MODIFY_REG(hi2c->Instance->CR2,
-             ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
-               (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
-               I2C_CR2_START | I2C_CR2_STOP)), \
-             (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
-                        (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
-                        (uint32_t)Mode | (uint32_t)Request));
-}
-
-/**
-  * @brief  Manage the enabling of Interrupts.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
-  * @retval None
-  */
-static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
-{
-  uint32_t tmpisr = 0U;
-
-  if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
-      (hi2c->XferISR == I2C_Slave_ISR_DMA))
-  {
-    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
-    {
-      /* Enable ERR, STOP, NACK and ADDR interrupts */
-      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-    }
-
-    if (InterruptRequest == I2C_XFER_ERROR_IT)
-    {
-      /* Enable ERR and NACK interrupts */
-      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
-    }
-
-    if (InterruptRequest == I2C_XFER_CPLT_IT)
-    {
-      /* Enable STOP interrupts */
-      tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
-    }
-
-    if (InterruptRequest == I2C_XFER_RELOAD_IT)
-    {
-      /* Enable TC interrupts */
-      tmpisr |= I2C_IT_TCI;
-    }
-  }
-  else
-  {
-    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
-    {
-      /* Enable ERR, STOP, NACK, and ADDR interrupts */
-      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-    }
-
-    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
-    {
-      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
-      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
-    }
-
-    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
-    {
-      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
-      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
-    }
-
-    if (InterruptRequest == I2C_XFER_CPLT_IT)
-    {
-      /* Enable STOP interrupts */
-      tmpisr |= I2C_IT_STOPI;
-    }
-  }
-
-  /* Enable interrupts only at the end */
-  /* to avoid the risk of I2C interrupt handle execution before */
-  /* all interrupts requested done */
-  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
-}
-
-/**
-  * @brief  Manage the disabling of Interrupts.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
-  * @retval None
-  */
-static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
-{
-  uint32_t tmpisr = 0U;
-
-  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
-  {
-    /* Disable TC and TXI interrupts */
-    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
-
-    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
-    {
-      /* Disable NACK and STOP interrupts */
-      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-    }
-  }
-
-  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
-  {
-    /* Disable TC and RXI interrupts */
-    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
-
-    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
-    {
-      /* Disable NACK and STOP interrupts */
-      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-    }
-  }
-
-  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
-  {
-    /* Disable ADDR, NACK and STOP interrupts */
-    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-  }
-
-  if (InterruptRequest == I2C_XFER_ERROR_IT)
-  {
-    /* Enable ERR and NACK interrupts */
-    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
-  }
-
-  if (InterruptRequest == I2C_XFER_CPLT_IT)
-  {
-    /* Enable STOP interrupts */
-    tmpisr |= I2C_IT_STOPI;
-  }
-
-  if (InterruptRequest == I2C_XFER_RELOAD_IT)
-  {
-    /* Enable TC interrupts */
-    tmpisr |= I2C_IT_TCI;
-  }
-
-  /* Disable interrupts only at the end */
-  /* to avoid a breaking situation like at "t" time */
-  /* all disable interrupts request are not done */
-  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
-}
-
-/**
-  * @brief  Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
-  * @param  hi2c I2C handle.
-  * @retval None
-  */
-static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
-{
-  /* if user set XferOptions to I2C_OTHER_FRAME            */
-  /* it request implicitly to generate a restart condition */
-  /* set XferOptions to I2C_FIRST_FRAME                    */
-  if (hi2c->XferOptions == I2C_OTHER_FRAME)
-  {
-    hi2c->XferOptions = I2C_FIRST_FRAME;
-  }
-  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
-  /* it request implicitly to generate a restart condition    */
-  /* then generate a stop condition at the end of transfer    */
-  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
-  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
-  {
-    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c
deleted file mode 100644
index b26e194882..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_i2c_ex.c
-  * @author  MCD Application Team
-  * @brief   I2C Extended HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of I2C Extended peripheral:
-  *           + Filter Mode Functions
-  *           + WakeUp Mode Functions
-  *           + FastModePlus Functions
-  *
-  @verbatim
-  ==============================================================================
-               ##### I2C peripheral Extended features  #####
-  ==============================================================================
-
-  [..] Comparing to other previous devices, the I2C interface for STM32L0xx
-       devices contains the following additional features
-
-       (+) Possibility to disable or enable Analog Noise Filter
-       (+) Use of a configured Digital Noise Filter
-       (+) Disable or enable wakeup from Stop mode(s)
-       (+) Disable or enable Fast Mode Plus
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
-    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
-    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
-    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
-          (++) HAL_I2CEx_EnableWakeUp()
-          (++) HAL_I2CEx_DisableWakeUp()
-    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
-          (++) HAL_I2CEx_EnableFastModePlus()
-          (++) HAL_I2CEx_DisableFastModePlus()
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2CEx I2CEx
-  * @brief I2C Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
-  * @{
-  */
-
-/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
-  * @brief    Filter Mode Functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Filter Mode Functions #####
- ===============================================================================
-    [..] This section provides functions allowing to:
-      (+) Configure Noise Filters
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure I2C Analog noise filter.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2Cx peripheral.
-  * @param  AnalogFilter New state of the Analog filter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-
-    /* Disable the selected I2C peripheral */
-    __HAL_I2C_DISABLE(hi2c);
-
-    /* Reset I2Cx ANOFF bit */
-    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
-
-    /* Set analog filter bit*/
-    hi2c->Instance->CR1 |= AnalogFilter;
-
-    __HAL_I2C_ENABLE(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Configure I2C Digital noise filter.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2Cx peripheral.
-  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-
-    /* Disable the selected I2C peripheral */
-    __HAL_I2C_DISABLE(hi2c);
-
-    /* Get the old register value */
-    tmpreg = hi2c->Instance->CR1;
-
-    /* Reset I2Cx DNF bits [11:8] */
-    tmpreg &= ~(I2C_CR1_DNF);
-
-    /* Set I2Cx DNF coefficient */
-    tmpreg |= DigitalFilter << 8U;
-
-    /* Store the new register value */
-    hi2c->Instance->CR1 = tmpreg;
-
-    __HAL_I2C_ENABLE(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @}
-  */
-
-/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
-  * @brief    WakeUp Mode Functions
-  *
-@verbatim
- ===============================================================================
-                      ##### WakeUp Mode Functions #####
- ===============================================================================
-    [..] This section provides functions allowing to:
-      (+) Configure Wake Up Feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enable I2C wakeup from Stop mode(s).
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2Cx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-
-    /* Disable the selected I2C peripheral */
-    __HAL_I2C_DISABLE(hi2c);
-
-    /* Enable wakeup from stop mode */
-    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
-
-    __HAL_I2C_ENABLE(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Disable I2C wakeup from Stop mode(s).
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2Cx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-
-    /* Disable the selected I2C peripheral */
-    __HAL_I2C_DISABLE(hi2c);
-
-    /* Enable wakeup from stop mode */
-    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
-
-    __HAL_I2C_ENABLE(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @}
-  */
-#if  (defined(SYSCFG_CFGR2_I2C_PB6_FMP) || defined(SYSCFG_CFGR2_I2C_PB7_FMP)) || (defined(SYSCFG_CFGR2_I2C_PB8_FMP) || defined(SYSCFG_CFGR2_I2C_PB9_FMP)) || (defined(SYSCFG_CFGR2_I2C1_FMP)) || defined(SYSCFG_CFGR2_I2C2_FMP) || defined(SYSCFG_CFGR2_I2C3_FMP)
-
-/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
-  * @brief    Fast Mode Plus Functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Fast Mode Plus Functions #####
- ===============================================================================
-    [..] This section provides functions allowing to:
-      (+) Configure Fast Mode Plus
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Enable the I2C fast mode plus driving capability.
-  * @param ConfigFastModePlus Selects the pin.
-  *   This parameter can be one of the @ref I2CEx_FastModePlus values
-  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
-  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
-  *        on each one of the following pins PB6, PB7, PB8 and PB9.
-  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
-  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
-  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
-  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
-  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
-  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
-  * @retval None
-  */
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  /* Check the parameter */
-  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-
-  /* Enable SYSCFG clock */
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-  /* Enable fast mode plus driving capability for selected pin */
-  SET_BIT(SYSCFG->CFGR2, (uint32_t)ConfigFastModePlus);
-}
-
-/**
-  * @brief Disable the I2C fast mode plus driving capability.
-  * @param ConfigFastModePlus Selects the pin.
-  *   This parameter can be one of the @ref I2CEx_FastModePlus values
-  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
-  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
-  *        on each one of the following pins PB6, PB7, PB8 and PB9.
-  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
-  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
-  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
-  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
-  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
-  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
-  * @retval None
-  */
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  /* Check the parameter */
-  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-
-  /* Enable SYSCFG clock */
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-  /* Disable fast mode plus driving capability for selected pin */
-  CLEAR_BIT(SYSCFG->CFGR2, (uint32_t)ConfigFastModePlus);
-}
-/**
-  * @}
-  */
-#endif /* Fast Mode Plus Availability */
-/**
-  * @}
-  */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c
deleted file mode 100644
index 39cad530dd..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c
+++ /dev/null
@@ -1,1861 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_i2s.c
-  * @author  MCD Application Team
-  * @brief   I2S HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and Errors functions
-  @verbatim
- ===============================================================================
-                  ##### How to use this driver #####
- ===============================================================================
- [..]
-    The I2S HAL driver can be used as follow:
-
-    (#) Declare a I2S_HandleTypeDef handle structure.
-    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
-        (##) Enable the SPIx interface clock.
-        (##) I2S pins configuration:
-            (+++) Enable the clock for the I2S GPIOs.
-            (+++) Configure these I2S pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
-             and HAL_I2S_Receive_IT() APIs).
-            (+++) Configure the I2Sx interrupt priority.
-            (+++) Enable the NVIC I2S IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
-             and HAL_I2S_Receive_DMA() APIs:
-            (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx Stream/Channel.
-            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
-                  DMA Tx/Rx Stream/Channel.
-
-   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
-       using HAL_I2S_Init() function.
-
-   -@- The specific I2S interrupts (Transmission complete interrupt,
-       RXNE interrupt and Error Interrupts) will be managed using the macros
-       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
-   -@- Make sure that either:
-        (+@) External clock source is configured after setting correctly
-             the define constant HSE_VALUE in the stm32l0xx_hal_conf.h file.
-
-    (#) Three mode of operations are available within this driver :
-
-   *** Polling mode IO operation ***
-   =================================
-   [..]
-     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
-     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
-
-   *** Interrupt mode IO operation ***
-   ===================================
-   [..]
-     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
-         add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
-   *** DMA mode IO operation ***
-   ==============================
-   [..]
-     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
-         add his own code by customization of function pointer HAL_I2S_ErrorCallback
-     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
-     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
-     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
-         In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
-         HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
-         In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
-         inside DR register and avoid using DeInit/Init process for the next transfer.
-
-   *** I2S HAL driver macros list ***
-   ===================================
-   [..]
-     Below the list of most used macros in I2S HAL driver.
-
-      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
-      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
-      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
-      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
-      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
-      (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
-
-    [..]
-      (@) You can refer to the I2S HAL driver header file for more useful macros
-
-   *** I2S HAL driver macros list ***
-   ===================================
-   [..]
-       Callback registration:
-
-      (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
-          allows the user to configure dynamically the driver callbacks.
-          Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
-
-          Function HAL_I2S_RegisterCallback() allows to register following callbacks:
-            (++) TxCpltCallback        : I2S Tx Completed callback
-            (++) RxCpltCallback        : I2S Rx Completed callback
-            (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
-            (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
-            (++) ErrorCallback         : I2S Error callback
-            (++) MspInitCallback       : I2S Msp Init callback
-            (++) MspDeInitCallback     : I2S Msp DeInit callback
-          This function takes as parameters the HAL peripheral handle, the Callback ID
-          and a pointer to the user callback function.
-
-
-      (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
-          weak function.
-          HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
-          and the Callback ID.
-          This function allows to reset following callbacks:
-            (++) TxCpltCallback        : I2S Tx Completed callback
-            (++) RxCpltCallback        : I2S Rx Completed callback
-            (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
-            (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
-            (++) ErrorCallback         : I2S Error callback
-            (++) MspInitCallback       : I2S Msp Init callback
-            (++) MspDeInitCallback     : I2S Msp DeInit callback
-
-       [..]
-       By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
-       all callbacks are set to the corresponding weak functions:
-       examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
-       Exception done for MspInit and MspDeInit functions that are
-       reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
-       these callbacks are null (not registered beforehand).
-       If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
-       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
-       [..]
-       Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
-       Exception done MspInit/MspDeInit functions that can be registered/unregistered
-       in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
-       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-       Then, the user first registers the MspInit/MspDeInit user callbacks
-       using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
-       or HAL_I2S_Init() function.
-
-       [..]
-       When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
-       not defined, the callback registering feature is not available
-       and weak (surcharged) callbacks are used.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-#ifdef HAL_I2S_MODULE_ENABLED
-
-#if defined(SPI_I2S_SUPPORT)
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2S I2S
-  * @brief I2S HAL module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define I2S_TIMEOUT_FLAG          100U         /*!< Timeout 100 ms            */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup I2S_Private_Functions I2S Private Functions
-  * @{
-  */
-static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
-static void               I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
-static void               I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
-                                                        uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup I2S_Exported_Functions I2S Exported Functions
-  * @{
-  */
-
-/** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          de-initialize the I2Sx peripheral in simplex mode:
-
-      (+) User must Implement HAL_I2S_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_I2S_Init() to configure the selected device with
-          the selected configuration:
-        (++) Mode
-        (++) Standard
-        (++) Data Format
-        (++) MCLK Output
-        (++) Audio frequency
-        (++) Polarity
-
-     (+) Call the function HAL_I2S_DeInit() to restore the default configuration
-          of the selected I2Sx peripheral.
-  @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the I2S according to the specified parameters
-  *         in the I2S_InitTypeDef and create the associated handle.
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
-{
-  uint32_t i2sdiv;
-  uint32_t i2sodd;
-  uint32_t packetlength;
-  uint32_t tmp;
-  uint32_t i2sclk;
-
-  /* Check the I2S handle allocation */
-  if (hi2s == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the I2S parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
-  assert_param(IS_I2S_MODE(hi2s->Init.Mode));
-  assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
-  assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
-  assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
-  assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
-  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
-
-  if (hi2s->State == HAL_I2S_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hi2s->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-    /* Init the I2S Callback settings */
-    hi2s->TxCpltCallback       = HAL_I2S_TxCpltCallback;          /* Legacy weak TxCpltCallback       */
-    hi2s->RxCpltCallback       = HAL_I2S_RxCpltCallback;          /* Legacy weak RxCpltCallback       */
-    hi2s->TxHalfCpltCallback   = HAL_I2S_TxHalfCpltCallback;      /* Legacy weak TxHalfCpltCallback   */
-    hi2s->RxHalfCpltCallback   = HAL_I2S_RxHalfCpltCallback;      /* Legacy weak RxHalfCpltCallback   */
-    hi2s->ErrorCallback        = HAL_I2S_ErrorCallback;           /* Legacy weak ErrorCallback        */
-
-    if (hi2s->MspInitCallback == NULL)
-    {
-      hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit  */
-    }
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    hi2s->MspInitCallback(hi2s);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
-    HAL_I2S_MspInit(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-  }
-
-  hi2s->State = HAL_I2S_STATE_BUSY;
-
-  /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
-  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-  CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
-                                      SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
-                                      SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
-  hi2s->Instance->I2SPR = 0x0002U;
-
-  /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
-  /* If the requested audio frequency is not the default, compute the prescaler */
-  if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
-  {
-    /* Check the frame length (For the Prescaler computing) ********************/
-    if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
-    {
-      /* Packet length is 16 bits */
-      packetlength = 16U;
-    }
-    else
-    {
-      /* Packet length is 32 bits */
-      packetlength = 32U;
-    }
-
-    /* I2S standard */
-    if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
-    {
-      /* In I2S standard packet length is multiplied by 2 */
-      packetlength = packetlength * 2U;
-    }
-
-    /* Get the source clock value: based on System Clock value */
-    i2sclk = HAL_RCC_GetSysClockFreq();
-
-    /* Compute the Real divider depending on the MCLK output state, with a floating point */
-    if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
-    {
-      /* MCLK output is enabled */
-      if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
-      {
-        tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
-      }
-      else
-      {
-        tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
-      }
-    }
-    else
-    {
-      /* MCLK output is disabled */
-      tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
-    }
-
-    /* Remove the flatting point */
-    tmp = tmp / 10U;
-
-    /* Check the parity of the divider */
-    i2sodd = (uint32_t)(tmp & (uint32_t)1U);
-
-    /* Compute the i2sdiv prescaler */
-    i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
-
-    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-    i2sodd = (uint32_t)(i2sodd << 8U);
-  }
-  else
-  {
-    /* Set the default values */
-    i2sdiv = 2U;
-    i2sodd = 0U;
-  }
-
-  /* Test if the divider is 1 or 0 or greater than 0xFF */
-  if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
-  {
-    /* Set the error code and execute error callback*/
-    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
-    return  HAL_ERROR;
-  }
-
-  /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
-
-  /* Write to SPIx I2SPR register the computed value */
-  hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
-
-  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-  /* And configure the I2S with the I2S_InitStruct values                      */
-  MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
-                                       SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
-                                       SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
-                                       SPI_I2SCFGR_I2SE  | SPI_I2SCFGR_I2SMOD), \
-             (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
-              hi2s->Init.Standard | hi2s->Init.DataFormat | \
-              hi2s->Init.CPOL));
-
-#if defined(SPI_I2SCFGR_ASTRTEN)
-  if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
-  {
-    /* Write to SPIx I2SCFGR */
-    SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
-  }
-#endif /* SPI_I2SCFGR_ASTRTEN */
-
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State     = HAL_I2S_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief DeInitializes the I2S peripheral
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Check the I2S handle allocation */
-  if (hi2s == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
-
-  hi2s->State = HAL_I2S_STATE_BUSY;
-
-  /* Disable the I2S Peripheral Clock */
-  __HAL_I2S_DISABLE(hi2s);
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  if (hi2s->MspDeInitCallback == NULL)
-  {
-    hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit  */
-  }
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  hi2s->MspDeInitCallback(hi2s);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_I2S_MspDeInit(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State     = HAL_I2S_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief I2S MSP Init
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief I2S MSP DeInit
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_MspDeInit could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  Register a User I2S Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2S.
-  * @param  CallbackID ID of the callback to be registered
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
-                                           pI2S_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hi2s);
-
-  if (HAL_I2S_STATE_READY == hi2s->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2S_TX_COMPLETE_CB_ID :
-        hi2s->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2S_RX_COMPLETE_CB_ID :
-        hi2s->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
-        hi2s->TxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
-        hi2s->RxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_I2S_ERROR_CB_ID :
-        hi2s->ErrorCallback = pCallback;
-        break;
-
-      case HAL_I2S_MSPINIT_CB_ID :
-        hi2s->MspInitCallback = pCallback;
-        break;
-
-      case HAL_I2S_MSPDEINIT_CB_ID :
-        hi2s->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_I2S_STATE_RESET == hi2s->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2S_MSPINIT_CB_ID :
-        hi2s->MspInitCallback = pCallback;
-        break;
-
-      case HAL_I2S_MSPDEINIT_CB_ID :
-        hi2s->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
-  return status;
-}
-
-/**
-  * @brief  Unregister an I2S Callback
-  *         I2S callback is redirected to the weak predefined callback
-  * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2S.
-  * @param  CallbackID ID of the callback to be unregistered
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hi2s);
-
-  if (HAL_I2S_STATE_READY == hi2s->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2S_TX_COMPLETE_CB_ID :
-        hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback;                /* Legacy weak TxCpltCallback       */
-        break;
-
-      case HAL_I2S_RX_COMPLETE_CB_ID :
-        hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback;                /* Legacy weak RxCpltCallback       */
-        break;
-
-      case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
-        hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback   */
-        break;
-
-      case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
-        hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback   */
-        break;
-
-      case HAL_I2S_ERROR_CB_ID :
-        hi2s->ErrorCallback = HAL_I2S_ErrorCallback;                  /* Legacy weak ErrorCallback        */
-        break;
-
-      case HAL_I2S_MSPINIT_CB_ID :
-        hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
-        break;
-
-      case HAL_I2S_MSPDEINIT_CB_ID :
-        hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_I2S_STATE_RESET == hi2s->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2S_MSPINIT_CB_ID :
-        hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
-        break;
-
-      case HAL_I2S_MSPDEINIT_CB_ID :
-        hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
-  return status;
-}
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
-  *  @brief Data transfers functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2S data
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode.
-            The status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode : The communication is performed using Interrupts
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the
-            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) HAL_I2S_Transmit()
-        (++) HAL_I2S_Receive()
-
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) HAL_I2S_Transmit_IT()
-        (++) HAL_I2S_Receive_IT()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) HAL_I2S_Transmit_DMA()
-        (++) HAL_I2S_Receive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2S_TxCpltCallback()
-        (++) HAL_I2S_RxCpltCallback()
-        (++) HAL_I2S_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmit an amount of data in blocking mode
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  pData a 16-bit pointer to data buffer.
-  * @param  Size number of data sample to be sent:
-  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *         configuration phase, the Size parameter means the number of 16-bit data length
-  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *         the Size parameter means the number of 24-bit or 32-bit data length.
-  * @param  Timeout Timeout duration
-  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *         between Master and Slave(example: audio streaming).
-  * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tmpreg_cfgr;
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
-  /* Set state and reset error code */
-  hi2s->State = HAL_I2S_STATE_BUSY_TX;
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->pTxBuffPtr = pData;
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
-  {
-    hi2s->TxXferSize = (Size << 1U);
-    hi2s->TxXferCount = (Size << 1U);
-  }
-  else
-  {
-    hi2s->TxXferSize = Size;
-    hi2s->TxXferCount = Size;
-  }
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR;
-
-  /* Check if the I2S is already enabled */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  /* Wait until TXE flag is set */
-  if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
-  {
-    /* Set the error code */
-    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-    hi2s->State = HAL_I2S_STATE_READY;
-    __HAL_UNLOCK(hi2s);
-    return HAL_ERROR;
-  }
-
-  while (hi2s->TxXferCount > 0U)
-  {
-    hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
-    hi2s->pTxBuffPtr++;
-    hi2s->TxXferCount--;
-
-    /* Wait until TXE flag is set */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
-    {
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-      hi2s->State = HAL_I2S_STATE_READY;
-      __HAL_UNLOCK(hi2s);
-      return HAL_ERROR;
-    }
-
-    /* Check if an underrun occurs */
-    if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
-    {
-      /* Clear underrun flag */
-      __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
-    }
-  }
-
-  /* Check if Slave mode is selected */
-  if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
-      || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
-  {
-    /* Wait until Busy flag is reset */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
-    {
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-      hi2s->State = HAL_I2S_STATE_READY;
-      __HAL_UNLOCK(hi2s);
-      return HAL_ERROR;
-    }
-  }
-
-  hi2s->State = HAL_I2S_STATE_READY;
-  __HAL_UNLOCK(hi2s);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receive an amount of data in blocking mode
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  pData a 16-bit pointer to data buffer.
-  * @param  Size number of data sample to be sent:
-  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *         configuration phase, the Size parameter means the number of 16-bit data length
-  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *         the Size parameter means the number of 24-bit or 32-bit data length.
-  * @param  Timeout Timeout duration
-  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *         between Master and Slave(example: audio streaming).
-  * @note   In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
-  *         in continuous way and as the I2S is not disabled at the end of the I2S transaction.
-  * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tmpreg_cfgr;
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
-  /* Set state and reset error code */
-  hi2s->State = HAL_I2S_STATE_BUSY_RX;
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->pRxBuffPtr = pData;
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
-  {
-    hi2s->RxXferSize = (Size << 1U);
-    hi2s->RxXferCount = (Size << 1U);
-  }
-  else
-  {
-    hi2s->RxXferSize = Size;
-    hi2s->RxXferCount = Size;
-  }
-
-  /* Check if the I2S is already enabled */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  /* Check if Master Receiver mode is selected */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-  {
-    /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
-    access to the SPI_SR register. */
-    __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-  }
-
-  /* Receive data */
-  while (hi2s->RxXferCount > 0U)
-  {
-    /* Wait until RXNE flag is set */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
-    {
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-      hi2s->State = HAL_I2S_STATE_READY;
-      __HAL_UNLOCK(hi2s);
-      return HAL_ERROR;
-    }
-
-    (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
-    hi2s->pRxBuffPtr++;
-    hi2s->RxXferCount--;
-
-    /* Check if an overrun occurs */
-    if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
-    {
-      /* Clear overrun flag */
-      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
-    }
-  }
-
-  hi2s->State = HAL_I2S_STATE_READY;
-  __HAL_UNLOCK(hi2s);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  pData a 16-bit pointer to data buffer.
-  * @param  Size number of data sample to be sent:
-  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *         configuration phase, the Size parameter means the number of 16-bit data length
-  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *         the Size parameter means the number of 24-bit or 32-bit data length.
-  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *         between Master and Slave(example: audio streaming).
-  * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t tmpreg_cfgr;
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
-  /* Set state and reset error code */
-  hi2s->State = HAL_I2S_STATE_BUSY_TX;
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->pTxBuffPtr = pData;
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
-  {
-    hi2s->TxXferSize = (Size << 1U);
-    hi2s->TxXferCount = (Size << 1U);
-  }
-  else
-  {
-    hi2s->TxXferSize = Size;
-    hi2s->TxXferCount = Size;
-  }
-
-  /* Enable TXE and ERR interrupt */
-  __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-  /* Check if the I2S is already enabled */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  __HAL_UNLOCK(hi2s);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  pData a 16-bit pointer to the Receive data buffer.
-  * @param  Size number of data sample to be sent:
-  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *         configuration phase, the Size parameter means the number of 16-bit data length
-  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *         the Size parameter means the number of 24-bit or 32-bit data length.
-  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *         between Master and Slave(example: audio streaming).
-  * @note   It is recommended to use DMA for the I2S receiver to avoid de-synchronization
-  * between Master and Slave otherwise the I2S interrupt should be optimized.
-  * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t tmpreg_cfgr;
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
-  /* Set state and reset error code */
-  hi2s->State = HAL_I2S_STATE_BUSY_RX;
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->pRxBuffPtr = pData;
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
-  {
-    hi2s->RxXferSize = (Size << 1U);
-    hi2s->RxXferCount = (Size << 1U);
-  }
-  else
-  {
-    hi2s->RxXferSize = Size;
-    hi2s->RxXferCount = Size;
-  }
-
-  /* Enable RXNE and ERR interrupt */
-  __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
-  /* Check if the I2S is already enabled */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  __HAL_UNLOCK(hi2s);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with DMA
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  pData a 16-bit pointer to the Transmit data buffer.
-  * @param  Size number of data sample to be sent:
-  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *         configuration phase, the Size parameter means the number of 16-bit data length
-  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *         the Size parameter means the number of 24-bit or 32-bit data length.
-  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *         between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t tmpreg_cfgr;
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
-  /* Set state and reset error code */
-  hi2s->State = HAL_I2S_STATE_BUSY_TX;
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->pTxBuffPtr = pData;
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
-  {
-    hi2s->TxXferSize = (Size << 1U);
-    hi2s->TxXferCount = (Size << 1U);
-  }
-  else
-  {
-    hi2s->TxXferSize = Size;
-    hi2s->TxXferCount = Size;
-  }
-
-  /* Set the I2S Tx DMA Half transfer complete callback */
-  hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
-
-  /* Set the I2S Tx DMA transfer complete callback */
-  hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
-
-  /* Set the DMA error callback */
-  hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
-
-  /* Enable the Tx DMA Stream/Channel */
-  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
-                                 (uint32_t)hi2s->pTxBuffPtr,
-                                 (uint32_t)&hi2s->Instance->DR,
-                                 hi2s->TxXferSize))
-  {
-    /* Update SPI error code */
-    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
-    hi2s->State = HAL_I2S_STATE_READY;
-
-    __HAL_UNLOCK(hi2s);
-    return HAL_ERROR;
-  }
-
-  /* Check if the I2S is already enabled */
-  if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  /* Check if the I2S Tx request is already enabled */
-  if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
-  {
-    /* Enable Tx DMA Request */
-    SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-  }
-
-  __HAL_UNLOCK(hi2s);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with DMA
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  pData a 16-bit pointer to the Receive data buffer.
-  * @param  Size number of data sample to be sent:
-  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *         configuration phase, the Size parameter means the number of 16-bit data length
-  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *         the Size parameter means the number of 24-bit or 32-bit data length.
-  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *         between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t tmpreg_cfgr;
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
-  /* Set state and reset error code */
-  hi2s->State = HAL_I2S_STATE_BUSY_RX;
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->pRxBuffPtr = pData;
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
-  {
-    hi2s->RxXferSize = (Size << 1U);
-    hi2s->RxXferCount = (Size << 1U);
-  }
-  else
-  {
-    hi2s->RxXferSize = Size;
-    hi2s->RxXferCount = Size;
-  }
-
-  /* Set the I2S Rx DMA Half transfer complete callback */
-  hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-
-  /* Set the I2S Rx DMA transfer complete callback */
-  hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-
-  /* Set the DMA error callback */
-  hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-
-  /* Check if Master Receiver mode is selected */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-  {
-    /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
-    access to the SPI_SR register. */
-    __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-  }
-
-  /* Enable the Rx DMA Stream/Channel */
-  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
-                                 hi2s->RxXferSize))
-  {
-    /* Update SPI error code */
-    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
-    hi2s->State = HAL_I2S_STATE_READY;
-
-    __HAL_UNLOCK(hi2s);
-    return HAL_ERROR;
-  }
-
-  /* Check if the I2S is already enabled */
-  if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  /* Check if the I2S Rx request is already enabled */
-  if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
-  {
-    /* Enable Rx DMA Request */
-    SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-  }
-
-  __HAL_UNLOCK(hi2s);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Pauses the audio DMA Stream/Channel playing from the Media.
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Disable the I2S DMA Tx request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-  }
-  else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Disable the I2S DMA Rx request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Resumes the audio DMA Stream/Channel playing from the Media.
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Enable the I2S DMA Tx request */
-    SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-  }
-  else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Enable the I2S DMA Rx request */
-    SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-  /* If the I2S peripheral is still not enabled, enable it */
-  if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the audio DMA Stream/Channel playing from the Media.
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
-     when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
-     */
-
-  if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
-  {
-    /* Abort the I2S DMA tx Stream/Channel */
-    if (hi2s->hdmatx != NULL)
-    {
-      /* Disable the I2S DMA tx Stream/Channel */
-      if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
-      {
-        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
-        errorcode = HAL_ERROR;
-      }
-    }
-
-    /* Wait until TXE flag is set */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
-    {
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-      hi2s->State = HAL_I2S_STATE_READY;
-      errorcode   = HAL_ERROR;
-    }
-
-    /* Wait until BSY flag is Reset */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
-    {
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-      hi2s->State = HAL_I2S_STATE_READY;
-      errorcode   = HAL_ERROR;
-    }
-
-    /* Disable I2S peripheral */
-    __HAL_I2S_DISABLE(hi2s);
-
-    /* Clear UDR flag */
-    __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
-    /* Disable the I2S Tx DMA requests */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-
-  }
-
-  else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
-  {
-    /* Abort the I2S DMA rx Stream/Channel */
-    if (hi2s->hdmarx != NULL)
-    {
-      /* Disable the I2S DMA rx Stream/Channel */
-      if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
-      {
-        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
-        errorcode = HAL_ERROR;
-      }
-    }
-
-    /* Disable I2S peripheral */
-    __HAL_I2S_DISABLE(hi2s);
-
-    /* Clear OVR flag */
-    __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
-    /* Disable the I2S Rx DMA request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-
-    if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
-    {
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
-
-      /* Set the I2S State ready */
-      hi2s->State = HAL_I2S_STATE_READY;
-      errorcode = HAL_ERROR;
-    }
-    else
-    {
-      /* Read DR to Flush RX Data */
-      READ_REG((hi2s->Instance)->DR);
-    }
-  }
-
-  hi2s->State = HAL_I2S_STATE_READY;
-
-  return errorcode;
-}
-
-/**
-  * @brief  This function handles I2S interrupt request.
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
-  uint32_t itsource = hi2s->Instance->CR2;
-  uint32_t itflag   = hi2s->Instance->SR;
-
-  /* I2S in mode Receiver ------------------------------------------------*/
-  if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
-      (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
-  {
-    I2S_Receive_IT(hi2s);
-    return;
-  }
-
-  /* I2S in mode Tramitter -----------------------------------------------*/
-  if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
-  {
-    I2S_Transmit_IT(hi2s);
-    return;
-  }
-
-  /* I2S interrupt error -------------------------------------------------*/
-  if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
-  {
-    /* I2S Overrun error interrupt occurred ---------------------------------*/
-    if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
-    {
-      /* Disable RXNE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
-      /* Set the error code and execute error callback*/
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
-    }
-
-    /* I2S Underrun error interrupt occurred --------------------------------*/
-    if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
-    {
-      /* Disable TXE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-      /* Set the error code and execute error callback*/
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
-    }
-
-    /* Set the I2S State ready */
-    hi2s->State = HAL_I2S_STATE_READY;
-
-    /* Call user error callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-    hi2s->ErrorCallback(hi2s);
-#else
-    HAL_I2S_ErrorCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  Tx Transfer Half completed callbacks
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Transfer completed callbacks
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer half completed callbacks
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callbacks
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  I2S error callbacks
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
-  *  @brief   Peripheral State functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the I2S state
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL state
-  */
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
-{
-  return hi2s->State;
-}
-
-/**
-  * @brief  Return the I2S error code
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval I2S Error Code
-  */
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
-{
-  return hi2s->ErrorCode;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Private_Functions I2S Private Functions
-  * @{
-  */
-/**
-  * @brief  DMA I2S transmit process complete callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* if DMA is configured in DMA_NORMAL Mode */
-  if (hdma->Init.Mode == DMA_NORMAL)
-  {
-    /* Disable Tx DMA Request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    hi2s->TxXferCount = 0U;
-    hi2s->State = HAL_I2S_STATE_READY;
-  }
-  /* Call user Tx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  hi2s->TxCpltCallback(hi2s);
-#else
-  HAL_I2S_TxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA I2S transmit process half complete callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Call user Tx half complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  hi2s->TxHalfCpltCallback(hi2s);
-#else
-  HAL_I2S_TxHalfCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA I2S receive process complete callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* if DMA is configured in DMA_NORMAL Mode */
-  if (hdma->Init.Mode == DMA_NORMAL)
-  {
-    /* Disable Rx DMA Request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-    hi2s->RxXferCount = 0U;
-    hi2s->State = HAL_I2S_STATE_READY;
-  }
-  /* Call user Rx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  hi2s->RxCpltCallback(hi2s);
-#else
-  HAL_I2S_RxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA I2S receive process half complete callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Call user Rx half complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  hi2s->RxHalfCpltCallback(hi2s);
-#else
-  HAL_I2S_RxHalfCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA I2S communication error callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMAError(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Disable Rx and Tx DMA Request */
-  CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
-  hi2s->TxXferCount = 0U;
-  hi2s->RxXferCount = 0U;
-
-  hi2s->State = HAL_I2S_STATE_READY;
-
-  /* Set the error code and execute error callback*/
-  SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
-  /* Call user error callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  hi2s->ErrorCallback(hi2s);
-#else
-  HAL_I2S_ErrorCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
-{
-  /* Transmit data */
-  hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
-  hi2s->pTxBuffPtr++;
-  hi2s->TxXferCount--;
-
-  if (hi2s->TxXferCount == 0U)
-  {
-    /* Disable TXE and ERR interrupt */
-    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-    hi2s->State = HAL_I2S_STATE_READY;
-    /* Call user Tx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-    hi2s->TxCpltCallback(hi2s);
-#else
-    HAL_I2S_TxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
-{
-  /* Receive data */
-  (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
-  hi2s->pRxBuffPtr++;
-  hi2s->RxXferCount--;
-
-  if (hi2s->RxXferCount == 0U)
-  {
-    /* Disable RXNE and ERR interrupt */
-    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
-    hi2s->State = HAL_I2S_STATE_READY;
-    /* Call user Rx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-    hi2s->RxCpltCallback(hi2s);
-#else
-    HAL_I2S_RxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  This function handles I2S Communication Timeout.
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  Flag Flag checked
-  * @param  State Value of the flag expected
-  * @param  Timeout Duration of the timeout
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
-                                                       uint32_t Timeout)
-{
-  uint32_t tickstart;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait until flag is set to status*/
-  while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
-      {
-        /* Set the I2S State ready */
-        hi2s->State = HAL_I2S_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2s);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c
deleted file mode 100644
index 2ee229e4fe..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c
+++ /dev/null
@@ -1,2992 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_irda.c
-  * @author  MCD Application Team
-  * @brief   IRDA HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the IrDA (Infrared Data Association) Peripheral
-  *          (IRDA)
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and Errors functions
-  *           + Peripheral Control functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The IRDA HAL driver can be used as follows:
-
-    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
-    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
-        in setting the associated USART or UART in IRDA mode:
-        (++) Enable the USARTx/UARTx interface clock.
-        (++) USARTx/UARTx pins configuration:
-            (+++) Enable the clock for the USARTx/UARTx GPIOs.
-            (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
-        (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
-             and HAL_IRDA_Receive_IT() APIs):
-            (+++) Configure the USARTx/UARTx interrupt priority.
-            (+++) Enable the NVIC USARTx/UARTx IRQ handle.
-            (+++) The specific IRDA interrupts (Transmission complete interrupt,
-                  RXNE interrupt and Error Interrupts) will be managed using the macros
-                  __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
-
-        (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
-             and HAL_IRDA_Receive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx channel.
-            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer
-                  complete interrupt on the DMA Tx/Rx channel.
-
-    (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
-        the normal or low power mode and the clock prescaler in the hirda handle Init structure.
-
-    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
-        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-             by calling the customized HAL_IRDA_MspInit() API.
-
-         -@@- The specific IRDA interrupts (Transmission complete interrupt,
-             RXNE interrupt and Error Interrupts) will be managed using the macros
-             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
-
-    (#) Three operation modes are available within this driver :
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
-       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..]
-       (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
-       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
-            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
-       (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
-       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
-            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
-       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..]
-       (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
-       (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
-            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
-       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
-            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
-       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
-       (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
-            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
-       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
-            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
-       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
-
-     *** IRDA HAL driver macros list ***
-     ====================================
-     [..]
-       Below the list of most used macros in IRDA HAL driver.
-
-       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
-       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
-       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
-       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
-       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
-       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
-       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
-
-     [..]
-       (@) You can refer to the IRDA HAL driver header file for more useful macros
-
-    ##### Callback registration #####
-    ==================================
-
-    [..]
-    The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
-    allows the user to configure dynamically the driver callbacks.
-
-    [..]
-    Use Function HAL_IRDA_RegisterCallback() to register a user callback.
-    Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-    (+) MspInitCallback           : IRDA MspInit.
-    (+) MspDeInitCallback         : IRDA MspDeInit.
-    This function takes as parameters the HAL peripheral handle, the Callback ID
-    and a pointer to the user callback function.
-
-    [..]
-    Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-    and the Callback ID.
-    This function allows to reset following callbacks:
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-    (+) MspInitCallback           : IRDA MspInit.
-    (+) MspDeInitCallback         : IRDA MspDeInit.
-
-    [..]
-    By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
-    Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
-    and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
-    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
-
-    [..]
-    Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
-    Exception done MspInit/MspDeInit that can be registered/unregistered
-    in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
-    MspInit/DeInit callbacks can be used during the Init/DeInit.
-    In that case first register the MspInit/MspDeInit user callbacks
-    using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
-    or HAL_IRDA_Init() function.
-
-    [..]
-    When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
-    not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup IRDA IRDA
-  * @brief HAL IRDA module driver
-  * @{
-  */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup IRDA_Private_Constants IRDA Private Constants
-  * @{
-  */
-#define IRDA_TEACK_REACK_TIMEOUT            1000U                                   /*!< IRDA TX or RX enable acknowledge time-out value  */
-
-#define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
-                                     | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))  /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
-
-#define USART_BRR_MIN    0x10U        /*!< USART BRR minimum authorized value */
-
-#define USART_BRR_MAX    0x0000FFFFU  /*!< USART BRR maximum authorized value */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup IRDA_Private_Macros IRDA Private Macros
-  * @{
-  */
-/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
-  * @param  __PCLK__ IRDA clock source.
-  * @param  __BAUD__ Baud rate set by the user.
-  * @retval Division result
-  */
-#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__)  (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup IRDA_Private_Functions
-  * @{
-  */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
-                                                     uint32_t Tickstart, uint32_t Timeout);
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
-static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
-static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
-  * @{
-  */
-
-/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
-  ==============================================================================
-              ##### Initialization and Configuration functions #####
-  ==============================================================================
-  [..]
-  This subsection provides a set of functions allowing to initialize the USARTx
-  in asynchronous IRDA mode.
-  (+) For the asynchronous mode only these parameters can be configured:
-      (++) Baud Rate
-      (++) Word Length
-      (++) Parity: If the parity is enabled, then the MSB bit of the data written
-           in the data register is transmitted but is changed by the parity bit.
-      (++) Power mode
-      (++) Prescaler setting
-      (++) Receiver/transmitter modes
-
-  [..]
-  The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
-  (details for the procedures are available in reference manual).
-
-@endverbatim
-
-  Depending on the frame length defined by the M1 and M0 bits (7-bit,
-  8-bit or 9-bit), the possible IRDA frame formats are listed in the
-  following table.
-
-    Table 1. IRDA frame format.
-    +-----------------------------------------------------------------------+
-    |  M1 bit |  M0 bit |  PCE bit  |             IRDA frame                |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
-    +-----------------------------------------------------------------------+
-
-  * @{
-  */
-
-/**
-  * @brief Initialize the IRDA mode according to the specified
-  *        parameters in the IRDA_InitTypeDef and initialize the associated handle.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
-{
-  /* Check the IRDA handle allocation */
-  if (hirda == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the USART/UART associated to the IRDA handle */
-  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-
-  if (hirda->gState == HAL_IRDA_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hirda->Lock = HAL_UNLOCKED;
-
-#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
-    IRDA_InitCallbacksToDefault(hirda);
-
-    if (hirda->MspInitCallback == NULL)
-    {
-      hirda->MspInitCallback = HAL_IRDA_MspInit;
-    }
-
-    /* Init the low level hardware */
-    hirda->MspInitCallback(hirda);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_IRDA_MspInit(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-  }
-
-  hirda->gState = HAL_IRDA_STATE_BUSY;
-
-  /* Disable the Peripheral to update the configuration registers */
-  __HAL_IRDA_DISABLE(hirda);
-
-  /* Set the IRDA Communication parameters */
-  if (IRDA_SetConfig(hirda) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  /* In IRDA mode, the following bits must be kept cleared:
-  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
-  - SCEN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
-  CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-
-  /* set the UART/USART in IRDA mode */
-  hirda->Instance->CR3 |= USART_CR3_IREN;
-
-  /* Enable the Peripheral */
-  __HAL_IRDA_ENABLE(hirda);
-
-  /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
-  return (IRDA_CheckIdleState(hirda));
-}
-
-/**
-  * @brief DeInitialize the IRDA peripheral.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
-{
-  /* Check the IRDA handle allocation */
-  if (hirda == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the USART/UART associated to the IRDA handle */
-  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-
-  hirda->gState = HAL_IRDA_STATE_BUSY;
-
-  /* DeInit the low level hardware */
-#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
-  if (hirda->MspDeInitCallback == NULL)
-  {
-    hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  hirda->MspDeInitCallback(hirda);
-#else
-  HAL_IRDA_MspDeInit(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-  /* Disable the Peripheral */
-  __HAL_IRDA_DISABLE(hirda);
-
-  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-  hirda->gState    = HAL_IRDA_STATE_RESET;
-  hirda->RxState   = HAL_IRDA_STATE_RESET;
-
-  /* Process Unlock */
-  __HAL_UNLOCK(hirda);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Initialize the IRDA MSP.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_IRDA_MspInit can be implemented in the user file
-   */
-}
-
-/**
-  * @brief DeInitialize the IRDA MSP.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_IRDA_MspDeInit can be implemented in the user file
-   */
-}
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User IRDA Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hirda irda handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
-                                            pIRDA_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hirda);
-
-  if (hirda->gState == HAL_IRDA_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
-        hirda->TxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_TX_COMPLETE_CB_ID :
-        hirda->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
-        hirda->RxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_RX_COMPLETE_CB_ID :
-        hirda->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_ERROR_CB_ID :
-        hirda->ErrorCallback = pCallback;
-        break;
-
-      case HAL_IRDA_ABORT_COMPLETE_CB_ID :
-        hirda->AbortCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        hirda->AbortTransmitCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
-        hirda->AbortReceiveCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_MSPINIT_CB_ID :
-        hirda->MspInitCallback = pCallback;
-        break;
-
-      case HAL_IRDA_MSPDEINIT_CB_ID :
-        hirda->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hirda->gState == HAL_IRDA_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_IRDA_MSPINIT_CB_ID :
-        hirda->MspInitCallback = pCallback;
-        break;
-
-      case HAL_IRDA_MSPDEINIT_CB_ID :
-        hirda->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hirda);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister an IRDA callback
-  *         IRDA callback is redirected to the weak predefined callback
-  * @param  hirda irda handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hirda);
-
-  if (HAL_IRDA_STATE_READY == hirda->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
-        hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback    */
-        break;
-
-      case HAL_IRDA_TX_COMPLETE_CB_ID :
-        hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback;                       /* Legacy weak TxCpltCallback         */
-        break;
-
-      case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
-        hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback     */
-        break;
-
-      case HAL_IRDA_RX_COMPLETE_CB_ID :
-        hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback;                       /* Legacy weak RxCpltCallback         */
-        break;
-
-      case HAL_IRDA_ERROR_CB_ID :
-        hirda->ErrorCallback = HAL_IRDA_ErrorCallback;                         /* Legacy weak ErrorCallback          */
-        break;
-
-      case HAL_IRDA_ABORT_COMPLETE_CB_ID :
-        hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback      */
-        break;
-
-      case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
-                                                                                  AbortTransmitCpltCallback          */
-        break;
-
-      case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
-        hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback;   /* Legacy weak
-                                                                                  AbortReceiveCpltCallback           */
-        break;
-
-      case HAL_IRDA_MSPINIT_CB_ID :
-        hirda->MspInitCallback = HAL_IRDA_MspInit;                             /* Legacy weak MspInitCallback        */
-        break;
-
-      case HAL_IRDA_MSPDEINIT_CB_ID :
-        hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;                         /* Legacy weak MspDeInitCallback      */
-        break;
-
-      default :
-        /* Update the error code */
-        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_IRDA_STATE_RESET == hirda->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_IRDA_MSPINIT_CB_ID :
-        hirda->MspInitCallback = HAL_IRDA_MspInit;
-        break;
-
-      case HAL_IRDA_MSPDEINIT_CB_ID :
-        hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hirda);
-
-  return status;
-}
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
-  *  @brief   IRDA Transmit and Receive functions
-  *
-@verbatim
- ===============================================================================
-                         ##### IO operation functions #####
- ===============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the IRDA data transfers.
-
-  [..]
-    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
-    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
-    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
-    While receiving data, transmission should be avoided as the data to be transmitted
-    could be corrupted.
-
-  [..]
-    (#) There are two modes of transfer:
-        (++) Blocking mode: the communication is performed in polling mode.
-             The HAL status of all data processing is returned by the same function
-             after finishing transfer.
-        (++) Non-Blocking mode: the communication is performed using Interrupts
-             or DMA, these API's return the HAL status.
-             The end of the data processing will be indicated through the
-             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
-             using DMA mode.
-             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
-             will be executed respectively at the end of the Transmit or Receive process
-             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
-
-    (#) Blocking mode APIs are :
-        (++) HAL_IRDA_Transmit()
-        (++) HAL_IRDA_Receive()
-
-    (#) Non Blocking mode APIs with Interrupt are :
-        (++) HAL_IRDA_Transmit_IT()
-        (++) HAL_IRDA_Receive_IT()
-        (++) HAL_IRDA_IRQHandler()
-
-    (#) Non Blocking mode functions with DMA are :
-        (++) HAL_IRDA_Transmit_DMA()
-        (++) HAL_IRDA_Receive_DMA()
-        (++) HAL_IRDA_DMAPause()
-        (++) HAL_IRDA_DMAResume()
-        (++) HAL_IRDA_DMAStop()
-
-    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
-        (++) HAL_IRDA_TxHalfCpltCallback()
-        (++) HAL_IRDA_TxCpltCallback()
-        (++) HAL_IRDA_RxHalfCpltCallback()
-        (++) HAL_IRDA_RxCpltCallback()
-        (++) HAL_IRDA_ErrorCallback()
-
-    (#) Non-Blocking mode transfers could be aborted using Abort API's :
-        (++) HAL_IRDA_Abort()
-        (++) HAL_IRDA_AbortTransmit()
-        (++) HAL_IRDA_AbortReceive()
-        (++) HAL_IRDA_Abort_IT()
-        (++) HAL_IRDA_AbortTransmit_IT()
-        (++) HAL_IRDA_AbortReceive_IT()
-
-    (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
-        (++) HAL_IRDA_AbortCpltCallback()
-        (++) HAL_IRDA_AbortTransmitCpltCallback()
-        (++) HAL_IRDA_AbortReceiveCpltCallback()
-
-    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
-        Errors are handled as follows :
-        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
-             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
-             in Interrupt mode reception .
-             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
-             to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
-             Transfer is kept ongoing on IRDA side.
-             If user wants to abort it, Abort services should be called by user.
-        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
-             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
-             Error code is set to allow user to identify error type, and
-             HAL_IRDA_ErrorCallback() user callback is executed.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Send an amount of data in blocking mode.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the sent data is handled as a set of u16. In this case, Size must reflect the number
-  *        of u16 available through pData.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size Amount of data elements (u8 or u16) to be sent.
-  * @param Timeout Specify timeout value.
-  * @retval HAL status
-  */
-/**
-  * @note   When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
-  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
-  */
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-  uint32_t tickstart;
-
-  /* Check that a Tx process is not already ongoing */
-  if (hirda->gState == HAL_IRDA_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be filled into TDR will be
-       handled through a u16 cast. */
-    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    hirda->TxXferSize = Size;
-    hirda->TxXferCount = Size;
-
-    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
-    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
-    }
-    else
-    {
-      pdata8bits  = pData;
-      pdata16bits = NULL;
-    }
-
-    while (hirda->TxXferCount > 0U)
-    {
-      hirda->TxXferCount--;
-
-      if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if (pdata8bits == NULL)
-      {
-        hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
-        pdata16bits++;
-      }
-      else
-      {
-        hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
-        pdata8bits++;
-      }
-    }
-
-    if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* At end of Tx process, restore hirda->gState to Ready */
-    hirda->gState = HAL_IRDA_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the received data is handled as a set of u16. In this case, Size must reflect the number
-  *        of u16 available through pData.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size Amount of data elements (u8 or u16) to be received.
-  * @param Timeout Specify timeout value.
-  * @retval HAL status
-  */
-/**
-  * @note   When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
-  *         (as received data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
-  */
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-  uint16_t uhMask;
-  uint32_t tickstart;
-
-  /* Check that a Rx process is not already ongoing */
-  if (hirda->RxState == HAL_IRDA_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be received from RDR will be
-       handled through a u16 cast. */
-    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    hirda->RxXferSize = Size;
-    hirda->RxXferCount = Size;
-
-    /* Computation of the mask to apply to RDR register
-       of the UART associated to the IRDA */
-    IRDA_MASK_COMPUTATION(hirda);
-    uhMask = hirda->Mask;
-
-    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
-    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
-    }
-    else
-    {
-      pdata8bits  = pData;
-      pdata16bits = NULL;
-    }
-
-    /* Check data remaining to be received */
-    while (hirda->RxXferCount > 0U)
-    {
-      hirda->RxXferCount--;
-
-      if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if (pdata8bits == NULL)
-      {
-        *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask);
-        pdata16bits++;
-      }
-      else
-      {
-        *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
-        pdata8bits++;
-      }
-    }
-
-    /* At end of Rx process, restore hirda->RxState to Ready */
-    hirda->RxState = HAL_IRDA_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in interrupt mode.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the sent data is handled as a set of u16. In this case, Size must reflect the number
-  *        of u16 available through pData.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size Amount of data elements (u8 or u16) to be sent.
-  * @retval HAL status
-  */
-/**
-  * @note   When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
-  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
-  */
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Tx process is not already ongoing */
-  if (hirda->gState == HAL_IRDA_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be filled into TDR will be
-       handled through a u16 cast. */
-    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->pTxBuffPtr = pData;
-    hirda->TxXferSize = Size;
-    hirda->TxXferCount = Size;
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    /* Enable the IRDA Transmit Data Register Empty Interrupt */
-    SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in interrupt mode.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the received data is handled as a set of u16. In this case, Size must reflect the number
-  *        of u16 available through pData.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-/**
-  * @note   When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
-  *         (as received data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
-  */
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if (hirda->RxState == HAL_IRDA_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be received from RDR will be
-       handled through a u16 cast. */
-    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->pRxBuffPtr = pData;
-    hirda->RxXferSize = Size;
-    hirda->RxXferCount = Size;
-
-    /* Computation of the mask to apply to the RDR register
-       of the UART associated to the IRDA */
-    IRDA_MASK_COMPUTATION(hirda);
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
-    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-
-    /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in DMA mode.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the sent data is handled as a set of u16. In this case, Size must reflect the number
-  *        of u16 available through pData.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @param pData pointer to data buffer (u8 or u16 data elements).
-  * @param Size Amount of data elements (u8 or u16) to be sent.
-  * @retval HAL status
-  */
-/**
-  * @note   When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
-  *         (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
-  */
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Tx process is not already ongoing */
-  if (hirda->gState == HAL_IRDA_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data copy into TDR will be
-       handled by DMA from a u16 frontier. */
-    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->pTxBuffPtr = pData;
-    hirda->TxXferSize = Size;
-    hirda->TxXferCount = Size;
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
-    /* Set the IRDA DMA transfer complete callback */
-    hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
-
-    /* Set the IRDA DMA half transfer complete callback */
-    hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
-
-    /* Set the DMA error callback */
-    hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
-
-    /* Set the DMA abort callback */
-    hirda->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the IRDA transmit DMA channel */
-    if (HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size) == HAL_OK)
-    {
-      /* Clear the TC flag in the ICR register */
-      __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hirda);
-
-      /* Enable the DMA transfer for transmit request by setting the DMAT bit
-         in the USART CR3 register */
-      SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-      return HAL_OK;
-    }
-    else
-    {
-      /* Set error code to DMA */
-      hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hirda);
-
-      /* Restore hirda->gState to ready */
-      hirda->gState = HAL_IRDA_STATE_READY;
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in DMA mode.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the received data is handled as a set of u16. In this case, Size must reflect the number
-  *        of u16 available through pData.
-  * @note   When the IRDA parity is enabled (PCE = 1), the received data contains
-  *         the parity bit (MSB position).
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-/**
-  * @note   When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
-  *         (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
-  */
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if (hirda->RxState == HAL_IRDA_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data copy from RDR will be
-       handled by DMA from a u16 frontier. */
-    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->pRxBuffPtr = pData;
-    hirda->RxXferSize = Size;
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
-    /* Set the IRDA DMA transfer complete callback */
-    hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
-
-    /* Set the IRDA DMA half transfer complete callback */
-    hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
-
-    /* Set the DMA error callback */
-    hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
-
-    /* Set the DMA abort callback */
-    hirda->hdmarx->XferAbortCallback = NULL;
-
-    /* Enable the DMA channel */
-    if (HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size) == HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hirda);
-
-      /* Enable the UART Parity Error Interrupt */
-      SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-
-      /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-      SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-      /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-         in the USART CR3 register */
-      SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-      return HAL_OK;
-    }
-    else
-    {
-      /* Set error code to DMA */
-      hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hirda);
-
-      /* Restore hirda->RxState to ready */
-      hirda->RxState = HAL_IRDA_STATE_READY;
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-
-/**
-  * @brief Pause the DMA Transfer.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
-{
-  /* Process Locked */
-  __HAL_LOCK(hirda);
-
-  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
-  {
-    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-    {
-      /* Disable the IRDA DMA Tx request */
-      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-    }
-  }
-  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
-  {
-    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-    {
-      /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-      /* Disable the IRDA DMA Rx request */
-      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hirda);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Resume the DMA Transfer.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
-{
-  /* Process Locked */
-  __HAL_LOCK(hirda);
-
-  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
-  {
-    /* Enable the IRDA DMA Tx request */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-  }
-  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
-  {
-    /* Clear the Overrun flag before resuming the Rx transfer*/
-    __HAL_IRDA_CLEAR_OREFLAG(hirda);
-
-    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the IRDA DMA Rx request */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hirda);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stop the DMA Transfer.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
-{
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
-     HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
-     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
-     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
-     the stream and the corresponding call back is executed. */
-
-  /* Stop IRDA DMA Tx request if ongoing */
-  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
-  {
-    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-    {
-      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-      /* Abort the IRDA DMA Tx channel */
-      if (hirda->hdmatx != NULL)
-      {
-        if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
-        {
-          if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-          {
-            /* Set error code to DMA */
-            hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
-
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-
-      IRDA_EndTxTransfer(hirda);
-    }
-  }
-
-  /* Stop IRDA DMA Rx request if ongoing */
-  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
-  {
-    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-    {
-      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-      /* Abort the IRDA DMA Rx channel */
-      if (hirda->hdmarx != NULL)
-      {
-        if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
-        {
-          if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-          {
-            /* Set error code to DMA */
-            hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
-
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-
-      IRDA_EndRxTransfer(hirda);
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfers (blocking mode).
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable IRDA Interrupts (Tx and Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the IRDA DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if (hirda->hdmatx != NULL)
-    {
-      /* Set the IRDA DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hirda->hdmatx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Disable the IRDA DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if (hirda->hdmarx != NULL)
-    {
-      /* Set the IRDA DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hirda->hdmarx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Tx and Rx transfer counters */
-  hirda->TxXferCount = 0U;
-  hirda->RxXferCount = 0U;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
-  /* Restore hirda->gState and hirda->RxState to Ready */
-  hirda->gState  = HAL_IRDA_STATE_READY;
-  hirda->RxState = HAL_IRDA_STATE_READY;
-
-  /* Reset Handle ErrorCode to No Error */
-  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (blocking mode).
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable IRDA Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Disable the IRDA DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if (hirda->hdmatx != NULL)
-    {
-      /* Set the IRDA DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hirda->hdmatx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Tx transfer counter */
-  hirda->TxXferCount = 0U;
-
-  /* Restore hirda->gState to Ready */
-  hirda->gState = HAL_IRDA_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (blocking mode).
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable IRDA Interrupts (Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the IRDA DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if (hirda->hdmarx != NULL)
-    {
-      /* Set the IRDA DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hirda->hdmarx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Rx transfer counter */
-  hirda->RxXferCount = 0U;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
-  /* Restore hirda->RxState to Ready */
-  hirda->RxState = HAL_IRDA_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfers (Interrupt mode).
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable IRDA Interrupts (Tx and Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
-{
-  uint32_t abortcplt = 1U;
-
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-  /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
-     before any call to DMA Abort functions */
-  /* DMA Tx Handle is valid */
-  if (hirda->hdmatx != NULL)
-  {
-    /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-    {
-      hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
-    }
-    else
-    {
-      hirda->hdmatx->XferAbortCallback = NULL;
-    }
-  }
-  /* DMA Rx Handle is valid */
-  if (hirda->hdmarx != NULL)
-  {
-    /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-    {
-      hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
-    }
-    else
-    {
-      hirda->hdmarx->XferAbortCallback = NULL;
-    }
-  }
-
-  /* Disable the IRDA DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-  {
-    /* Disable DMA Tx at UART level */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
-    if (hirda->hdmatx != NULL)
-    {
-      /* IRDA Tx DMA Abort callback has already been initialised :
-         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
-      {
-        hirda->hdmatx->XferAbortCallback = NULL;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-
-  /* Disable the IRDA DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
-    if (hirda->hdmarx != NULL)
-    {
-      /* IRDA Rx DMA Abort callback has already been initialised :
-         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
-      {
-        hirda->hdmarx->XferAbortCallback = NULL;
-        abortcplt = 1U;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-
-  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
-  if (abortcplt == 1U)
-  {
-    /* Reset Tx and Rx transfer counters */
-    hirda->TxXferCount = 0U;
-    hirda->RxXferCount = 0U;
-
-    /* Reset errorCode */
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
-    /* Clear the Error flags in the ICR register */
-    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
-    /* Restore hirda->gState and hirda->RxState to Ready */
-    hirda->gState  = HAL_IRDA_STATE_READY;
-    hirda->RxState = HAL_IRDA_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort complete callback */
-    hirda->AbortCpltCallback(hirda);
-#else
-    /* Call legacy weak Abort complete callback */
-    HAL_IRDA_AbortCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable IRDA Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Disable the IRDA DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
-    if (hirda->hdmatx != NULL)
-    {
-      /* Set the IRDA DMA Abort callback :
-         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-      hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
-      {
-        /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
-        hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
-      }
-    }
-    else
-    {
-      /* Reset Tx transfer counter */
-      hirda->TxXferCount = 0U;
-
-      /* Restore hirda->gState to Ready */
-      hirda->gState = HAL_IRDA_STATE_READY;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Transmit Complete Callback */
-      hirda->AbortTransmitCpltCallback(hirda);
-#else
-      /* Call legacy weak Abort Transmit Complete Callback */
-      HAL_IRDA_AbortTransmitCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-    }
-  }
-  else
-  {
-    /* Reset Tx transfer counter */
-    hirda->TxXferCount = 0U;
-
-    /* Restore hirda->gState to Ready */
-    hirda->gState = HAL_IRDA_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Transmit Complete Callback */
-    hirda->AbortTransmitCpltCallback(hirda);
-#else
-    /* Call legacy weak Abort Transmit Complete Callback */
-    HAL_IRDA_AbortTransmitCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (Interrupt mode).
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable IRDA Interrupts (Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the IRDA DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
-    if (hirda->hdmarx != NULL)
-    {
-      /* Set the IRDA DMA Abort callback :
-         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-      hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
-      {
-        /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
-        hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
-      }
-    }
-    else
-    {
-      /* Reset Rx transfer counter */
-      hirda->RxXferCount = 0U;
-
-      /* Clear the Error flags in the ICR register */
-      __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
-      /* Restore hirda->RxState to Ready */
-      hirda->RxState = HAL_IRDA_STATE_READY;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Receive Complete Callback */
-      hirda->AbortReceiveCpltCallback(hirda);
-#else
-      /* Call legacy weak Abort Receive Complete Callback */
-      HAL_IRDA_AbortReceiveCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-    }
-  }
-  else
-  {
-    /* Reset Rx transfer counter */
-    hirda->RxXferCount = 0U;
-
-    /* Clear the Error flags in the ICR register */
-    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
-    /* Restore hirda->RxState to Ready */
-    hirda->RxState = HAL_IRDA_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Receive Complete Callback */
-    hirda->AbortReceiveCpltCallback(hirda);
-#else
-    /* Call legacy weak Abort Receive Complete Callback */
-    HAL_IRDA_AbortReceiveCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Handle IRDA interrupt request.
-  * @param hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
-{
-  uint32_t isrflags   = READ_REG(hirda->Instance->ISR);
-  uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
-  uint32_t cr3its;
-  uint32_t errorflags;
-  uint32_t errorcode;
-
-  /* If no error occurs */
-  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
-  if (errorflags == 0U)
-  {
-    /* IRDA in mode Receiver ---------------------------------------------------*/
-    if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U))
-    {
-      IRDA_Receive_IT(hirda);
-      return;
-    }
-  }
-
-  /* If some errors occur */
-  cr3its = READ_REG(hirda->Instance->CR3);
-  if ((errorflags != 0U)
-      && (((cr3its & USART_CR3_EIE) != 0U)
-          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
-  {
-    /* IRDA parity error interrupt occurred -------------------------------------*/
-    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
-    {
-      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
-
-      hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
-    }
-
-    /* IRDA frame error interrupt occurred --------------------------------------*/
-    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
-    {
-      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
-
-      hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
-    }
-
-    /* IRDA noise error interrupt occurred --------------------------------------*/
-    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
-    {
-      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
-
-      hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
-    }
-
-    /* IRDA Over-Run interrupt occurred -----------------------------------------*/
-    if (((isrflags & USART_ISR_ORE) != 0U) &&
-        (((cr1its & USART_CR1_RXNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U)))
-    {
-      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
-
-      hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
-    }
-
-    /* Call IRDA Error Call back function if need be --------------------------*/
-    if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
-    {
-      /* IRDA in mode Receiver ---------------------------------------------------*/
-      if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U))
-      {
-        IRDA_Receive_IT(hirda);
-      }
-
-      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
-         consider error as blocking */
-      errorcode = hirda->ErrorCode;
-      if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ||
-          ((errorcode & HAL_IRDA_ERROR_ORE) != 0U))
-      {
-        /* Blocking error : transfer is aborted
-           Set the IRDA state ready to be able to start again the process,
-           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
-        IRDA_EndRxTransfer(hirda);
-
-        /* Disable the IRDA DMA Rx request if enabled */
-        if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-        {
-          CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-          /* Abort the IRDA DMA Rx channel */
-          if (hirda->hdmarx != NULL)
-          {
-            /* Set the IRDA DMA Abort callback :
-               will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
-            hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
-
-            /* Abort DMA RX */
-            if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
-            {
-              /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
-              hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
-            }
-          }
-          else
-          {
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-            /* Call registered user error callback */
-            hirda->ErrorCallback(hirda);
-#else
-            /* Call legacy weak user error callback */
-            HAL_IRDA_ErrorCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-          }
-        }
-        else
-        {
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-          /* Call registered user error callback */
-          hirda->ErrorCallback(hirda);
-#else
-          /* Call legacy weak user error callback */
-          HAL_IRDA_ErrorCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-        }
-      }
-      else
-      {
-        /* Non Blocking error : transfer could go on.
-           Error is notified to user through user error callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-        /* Call registered user error callback */
-        hirda->ErrorCallback(hirda);
-#else
-        /* Call legacy weak user error callback */
-        HAL_IRDA_ErrorCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-      }
-    }
-    return;
-
-  } /* End if some error occurs */
-
-  /* IRDA in mode Transmitter ------------------------------------------------*/
-  if (((isrflags & USART_ISR_TXE) != 0U) && ((cr1its & USART_CR1_TXEIE) != 0U))
-  {
-    IRDA_Transmit_IT(hirda);
-    return;
-  }
-
-  /* IRDA in mode Transmitter (transmission end) -----------------------------*/
-  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
-  {
-    IRDA_EndTransmit_IT(hirda);
-    return;
-  }
-
-}
-
-/**
-  * @brief  Tx Transfer completed callback.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_TxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callback.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callback.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_RxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer complete callback.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  IRDA error callback.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_ErrorCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  IRDA Abort Complete callback.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  IRDA Abort Complete callback.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  IRDA Abort Receive Complete callback.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
-  *  @brief   IRDA State and Errors functions
-  *
-@verbatim
-  ==============================================================================
-            ##### Peripheral State and Error functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to return the State of IrDA
-    communication process and also return Peripheral Errors occurred during communication process
-     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
-         of the IRDA peripheral handle.
-     (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
-         communication.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Return the IRDA handle state.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL state
-  */
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
-{
-  /* Return IRDA handle state */
-  uint32_t temp1;
-  uint32_t temp2;
-  temp1 = (uint32_t)hirda->gState;
-  temp2 = (uint32_t)hirda->RxState;
-
-  return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
-}
-
-/**
-  * @brief Return the IRDA handle error code.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval IRDA Error Code
-  */
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
-{
-  return hirda->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Private_Functions IRDA Private Functions
-  * @{
-  */
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Initialize the callbacks to their default values.
-  * @param  hirda IRDA handle.
-  * @retval none
-  */
-void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
-{
-  /* Init the IRDA Callback settings */
-  hirda->TxHalfCpltCallback        = HAL_IRDA_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
-  hirda->TxCpltCallback            = HAL_IRDA_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
-  hirda->RxHalfCpltCallback        = HAL_IRDA_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
-  hirda->RxCpltCallback            = HAL_IRDA_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
-  hirda->ErrorCallback             = HAL_IRDA_ErrorCallback;             /* Legacy weak ErrorCallback             */
-  hirda->AbortCpltCallback         = HAL_IRDA_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
-  hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
-  hirda->AbortReceiveCpltCallback  = HAL_IRDA_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
-
-}
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/**
-  * @brief Configure the IRDA peripheral.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
-{
-  uint32_t tmpreg;
-  IRDA_ClockSourceTypeDef clocksource;
-  HAL_StatusTypeDef ret = HAL_OK;
-  uint32_t pclk;
-
-  /* Check the communication parameters */
-  assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
-  assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
-  assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
-  assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
-  assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
-  assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  /* Configure the IRDA Word Length, Parity and transfer Mode:
-     Set the M bits according to hirda->Init.WordLength value
-     Set PCE and PS bits according to hirda->Init.Parity value
-     Set TE and RE bits according to hirda->Init.Mode value */
-  tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
-
-  MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/
-  MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
-
-
-  /*-------------------------- USART GTPR Configuration ----------------------*/
-  MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
-
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  IRDA_GETCLOCKSOURCE(hirda, clocksource);
-  tmpreg =   0U;
-  switch (clocksource)
-  {
-    case IRDA_CLOCKSOURCE_PCLK1:
-      pclk = HAL_RCC_GetPCLK1Freq();
-      tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
-      break;
-    case IRDA_CLOCKSOURCE_PCLK2:
-      pclk = HAL_RCC_GetPCLK2Freq();
-      tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
-      break;
-    case IRDA_CLOCKSOURCE_HSI:
-      tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate));
-      break;
-    case IRDA_CLOCKSOURCE_SYSCLK:
-      pclk = HAL_RCC_GetSysClockFreq();
-      tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
-      break;
-    case IRDA_CLOCKSOURCE_LSE:
-      tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate));
-      break;
-    default:
-      ret = HAL_ERROR;
-      break;
-  }
-
-  /* USARTDIV must be greater than or equal to 0d16 */
-  if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
-  {
-    hirda->Instance->BRR = tmpreg;
-  }
-  else
-  {
-    ret = HAL_ERROR;
-  }
-
-  return ret;
-}
-
-/**
-  * @brief Check the IRDA Idle State.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
-{
-  uint32_t tickstart;
-
-  /* Initialize the IRDA ErrorCode */
-  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
-  /* Init tickstart for timeout management */
-  tickstart = HAL_GetTick();
-
-  /* Check if the Transmitter is enabled */
-  if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
-  {
-    /* Wait until TEACK flag is set */
-    if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
-    {
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
-    }
-  }
-  /* Check if the Receiver is enabled */
-  if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
-  {
-    /* Wait until REACK flag is set */
-    if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
-    {
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Initialize the IRDA state*/
-  hirda->gState  = HAL_IRDA_STATE_READY;
-  hirda->RxState = HAL_IRDA_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hirda);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle IRDA Communication Timeout.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @param  Flag Specifies the IRDA flag to check.
-  * @param  Status Flag status (SET or RESET)
-  * @param  Tickstart Tick start value
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
-                                                     uint32_t Tickstart, uint32_t Timeout)
-{
-  /* Wait until flag is set */
-  while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-      {
-        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
-           interrupts for the interrupt process */
-        CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
-        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-        hirda->gState  = HAL_IRDA_STATE_READY;
-        hirda->RxState = HAL_IRDA_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hirda);
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* At end of Tx process, restore hirda->gState to Ready */
-  hirda->gState = HAL_IRDA_STATE_READY;
-}
-
-
-/**
-  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-  /* At end of Rx process, restore hirda->RxState to Ready */
-  hirda->RxState = HAL_IRDA_STATE_READY;
-}
-
-
-/**
-  * @brief  DMA IRDA transmit process complete callback.
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
-
-  /* DMA Normal mode */
-  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
-  {
-    hirda->TxXferCount = 0U;
-
-    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
-       in the IRDA CR3 register */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Enable the IRDA Transmit Complete Interrupt */
-    SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-  }
-  /* DMA Circular mode */
-  else
-  {
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-    /* Call registered Tx complete callback */
-    hirda->TxCpltCallback(hirda);
-#else
-    /* Call legacy weak Tx complete callback */
-    HAL_IRDA_TxCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-  }
-
-}
-
-/**
-  * @brief  DMA IRDA transmit process half complete callback.
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Tx Half complete callback */
-  hirda->TxHalfCpltCallback(hirda);
-#else
-  /* Call legacy weak Tx complete callback */
-  HAL_IRDA_TxHalfCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA IRDA receive process complete callback.
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
-
-  /* DMA Normal mode */
-  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
-  {
-    hirda->RxXferCount = 0U;
-
-    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
-       in the IRDA CR3 register */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    /* At end of Rx process, restore hirda->RxState to Ready */
-    hirda->RxState = HAL_IRDA_STATE_READY;
-  }
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Rx complete callback */
-  hirda->RxCpltCallback(hirda);
-#else
-  /* Call legacy weak Rx complete callback */
-  HAL_IRDA_RxCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief DMA IRDA receive process half complete callback.
-  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /*Call registered Rx Half complete callback*/
-  hirda->RxHalfCpltCallback(hirda);
-#else
-  /* Call legacy weak Rx Half complete callback */
-  HAL_IRDA_RxHalfCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief DMA IRDA communication error callback.
-  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
-
-  /* Stop IRDA DMA Tx request if ongoing */
-  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
-  {
-    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-    {
-      hirda->TxXferCount = 0U;
-      IRDA_EndTxTransfer(hirda);
-    }
-  }
-
-  /* Stop IRDA DMA Rx request if ongoing */
-  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
-  {
-    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-    {
-      hirda->RxXferCount = 0U;
-      IRDA_EndRxTransfer(hirda);
-    }
-  }
-
-  hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered user error callback */
-  hirda->ErrorCallback(hirda);
-#else
-  /* Call legacy weak user error callback */
-  HAL_IRDA_ErrorCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
-  hirda->RxXferCount = 0U;
-  hirda->TxXferCount = 0U;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered user error callback */
-  hirda->ErrorCallback(hirda);
-#else
-  /* Call legacy weak user error callback */
-  HAL_IRDA_ErrorCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA IRDA Tx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Rx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
-
-  hirda->hdmatx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (hirda->hdmarx != NULL)
-  {
-    if (hirda->hdmarx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  hirda->TxXferCount = 0U;
-  hirda->RxXferCount = 0U;
-
-  /* Reset errorCode */
-  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
-  /* Restore hirda->gState and hirda->RxState to Ready */
-  hirda->gState  = HAL_IRDA_STATE_READY;
-  hirda->RxState = HAL_IRDA_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  hirda->AbortCpltCallback(hirda);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_IRDA_AbortCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-
-/**
-  * @brief  DMA IRDA Rx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Tx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
-
-  hirda->hdmarx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (hirda->hdmatx != NULL)
-  {
-    if (hirda->hdmatx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  hirda->TxXferCount = 0U;
-  hirda->RxXferCount = 0U;
-
-  /* Reset errorCode */
-  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
-  /* Restore hirda->gState and hirda->RxState to Ready */
-  hirda->gState  = HAL_IRDA_STATE_READY;
-  hirda->RxState = HAL_IRDA_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  hirda->AbortCpltCallback(hirda);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_IRDA_AbortCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-
-/**
-  * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
-  *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
-  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
-  *         and leads to user Tx Abort Complete callback execution).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
-
-  hirda->TxXferCount = 0U;
-
-  /* Restore hirda->gState to Ready */
-  hirda->gState = HAL_IRDA_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Transmit Complete Callback */
-  hirda->AbortTransmitCpltCallback(hirda);
-#else
-  /* Call legacy weak Abort Transmit Complete Callback */
-  HAL_IRDA_AbortTransmitCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
-  *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
-  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
-  *         and leads to user Rx Abort Complete callback execution).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  hirda->RxXferCount = 0U;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
-  /* Restore hirda->RxState to Ready */
-  hirda->RxState = HAL_IRDA_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Receive Complete Callback */
-  hirda->AbortReceiveCpltCallback(hirda);
-#else
-  /* Call legacy weak Abort Receive Complete Callback */
-  HAL_IRDA_AbortReceiveCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  Send an amount of data in interrupt mode.
-  * @note   Function is called under interruption only, once
-  *         interruptions have been enabled by HAL_IRDA_Transmit_IT().
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
-{
-  uint16_t *tmp;
-
-  /* Check that a Tx process is ongoing */
-  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
-  {
-    if (hirda->TxXferCount == 0U)
-    {
-      /* Disable the IRDA Transmit Data Register Empty Interrupt */
-      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
-
-      /* Enable the IRDA Transmit Complete Interrupt */
-      SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-    }
-    else
-    {
-      if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
-      {
-        tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
-        hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
-        hirda->pTxBuffPtr += 2U;
-      }
-      else
-      {
-        hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU);
-        hirda->pTxBuffPtr++;
-      }
-      hirda->TxXferCount--;
-    }
-  }
-}
-
-/**
-  * @brief  Wrap up transmission in non-blocking mode.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable the IRDA Transmit Complete Interrupt */
-  CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-
-  /* Tx process is ended, restore hirda->gState to Ready */
-  hirda->gState = HAL_IRDA_STATE_READY;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Tx complete callback */
-  hirda->TxCpltCallback(hirda);
-#else
-  /* Call legacy weak Tx complete callback */
-  HAL_IRDA_TxCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  Receive an amount of data in interrupt mode.
-  * @note   Function is called under interruption only, once
-  *         interruptions have been enabled by HAL_IRDA_Receive_IT()
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *               the configuration information for the specified IRDA module.
-  * @retval None
-  */
-static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
-{
-  uint16_t *tmp;
-  uint16_t  uhMask = hirda->Mask;
-  uint16_t  uhdata;
-
-  /* Check that a Rx process is ongoing */
-  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
-  {
-    uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
-    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
-    {
-      tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */
-      *tmp = (uint16_t)(uhdata & uhMask);
-      hirda->pRxBuffPtr  += 2U;
-    }
-    else
-    {
-      *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
-      hirda->pRxBuffPtr++;
-    }
-
-    hirda->RxXferCount--;
-    if (hirda->RxXferCount == 0U)
-    {
-      /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
-      CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
-      /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-      /* Rx process is completed, restore hirda->RxState to Ready */
-      hirda->RxState = HAL_IRDA_STATE_READY;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-      /* Call registered Rx complete callback */
-      hirda->RxCpltCallback(hirda);
-#else
-      /* Call legacy weak Rx complete callback */
-      HAL_IRDA_RxCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-    }
-  }
-  else
-  {
-    /* Clear RXNE interrupt flag */
-    __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_IRDA_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c
deleted file mode 100644
index 7179ec5314..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_iwdg.c
-  * @author  MCD Application Team
-  * @brief   IWDG HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Independent Watchdog (IWDG) peripheral:
-  *           + Initialization and Start functions
-  *           + IO operation functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### IWDG Generic features #####
-  ==============================================================================
-  [..]
-    (+) The IWDG can be started by either software or hardware (configurable
-        through option byte).
-
-    (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
-        active even if the main clock fails.
-
-    (+) Once the IWDG is started, the LSI is forced ON and both cannot be
-        disabled. The counter starts counting down from the reset value (0xFFF).
-        When it reaches the end of count value (0x000) a reset signal is
-        generated (IWDG reset).
-
-    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
-        the IWDG_RLR value is reloaded into the counter and the watchdog reset
-        is prevented.
-
-    (+) The IWDG is implemented in the VDD voltage domain that is still functional
-        in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
-        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
-        reset occurs.
-
-    (+) Debug mode: When the microcontroller enters debug mode (core halted),
-        the IWDG counter either continues to work normally or stops, depending
-        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
-        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
-
-    [..] Min-max timeout value @37KHz (LSI): ~144us / ~37.8s
-         The IWDG timeout may vary due to LSI clock frequency dispersion.
-         STM32L0xx devices provide the capability to measure the LSI clock
-         frequency (LSI clock is internally connected to TIM16 CH1 input capture).
-         The measured value can be used to have an IWDG timeout with an
-         acceptable accuracy.
-
-    [..] Default timeout value (necessary for IWDG_SR status register update):
-         Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
-         This frequency being subject to variations as mentioned above, the
-         default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
-         below) may become too short or too long.
-         In such cases, this default timeout value can be tuned by redefining
-         the constant LSI_VALUE at user-application level (based, for instance,
-         on the measured LSI clock frequency as explained above).
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    (#) Use IWDG using HAL_IWDG_Init() function to :
-      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
-           clock is forced ON and IWDG counter starts counting down.
-      (++) Enable write access to configuration registers:
-          IWDG_PR, IWDG_RLR and IWDG_WINR.
-      (++) Configure the IWDG prescaler and counter reload value. This reload
-           value will be loaded in the IWDG counter each time the watchdog is
-           reloaded, then the IWDG will start counting down from this value.
-      (++) Depending on window parameter:
-        (+++) If Window Init parameter is same as Window register value,
-             nothing more is done but reload counter value in order to exit
-             function with exact time base.
-        (+++) Else modify Window register. This will automatically reload
-             watchdog counter.
-      (++) Wait for status flags to be reset.
-
-    (#) Then the application program must refresh the IWDG counter at regular
-        intervals during normal operation to prevent an MCU reset, using
-        HAL_IWDG_Refresh() function.
-
-     *** IWDG HAL driver macros list ***
-     ====================================
-     [..]
-       Below the list of most used macros in IWDG HAL driver:
-      (+) __HAL_IWDG_START: Enable the IWDG peripheral
-      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
-          the reload register
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
-/** @addtogroup IWDG
-  * @brief IWDG HAL module driver.
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup IWDG_Private_Defines IWDG Private Defines
-  * @{
-  */
-/* Status register needs up to 5 LSI clock periods divided by the clock
-   prescaler to be updated. The number of LSI clock periods is upper-rounded to
-   6 for the timeout value calculation.
-   The timeout value is calculated using the highest prescaler (256) and
-   the LSI_VALUE constant. The value of this constant can be changed by the user
-   to take into account possible LSI clock period variations.
-   The timeout value is multiplied by 1000 to be converted in milliseconds.
-   LSI startup time is also considered here by adding LSI_STARTUP_TIMEOUT
-   converted in milliseconds. */
-#define HAL_IWDG_DEFAULT_TIMEOUT        (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
-#define IWDG_KERNEL_UPDATE_FLAGS        (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup IWDG_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup IWDG_Exported_Functions_Group1
-  *  @brief    Initialization and Start functions.
-  *
-@verbatim
- ===============================================================================
-          ##### Initialization and Start functions #####
- ===============================================================================
- [..]  This section provides functions allowing to:
-      (+) Initialize the IWDG according to the specified parameters in the
-          IWDG_InitTypeDef of associated handle.
-      (+) Manage Window option.
-      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
-          is reloaded in order to exit function with correct time base.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the IWDG according to the specified parameters in the
-  *         IWDG_InitTypeDef and start watchdog. Before exiting function,
-  *         watchdog is refreshed in order to have correct time base.
-  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
-{
-  uint32_t tickstart;
-
-  /* Check the IWDG handle allocation */
-  if (hiwdg == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
-  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
-  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
-  assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
-
-  /* Enable IWDG. LSI is turned on automatically */
-  __HAL_IWDG_START(hiwdg);
-
-  /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
-  0x5555 in KR */
-  IWDG_ENABLE_WRITE_ACCESS(hiwdg);
-
-  /* Write to IWDG registers the Prescaler & Reload values to work with */
-  hiwdg->Instance->PR = hiwdg->Init.Prescaler;
-  hiwdg->Instance->RLR = hiwdg->Init.Reload;
-
-  /* Check pending flag, if previous update not done, return timeout */
-  tickstart = HAL_GetTick();
-
-  /* Wait for register to be updated */
-  while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
-  {
-    if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
-    {
-      if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* If window parameter is different than current value, modify window
-  register */
-  if (hiwdg->Instance->WINR != hiwdg->Init.Window)
-  {
-    /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
-    even if window feature is disabled, Watchdog will be reloaded by writing
-    windows register */
-    hiwdg->Instance->WINR = hiwdg->Init.Window;
-  }
-  else
-  {
-    /* Reload IWDG counter with value defined in the reload register */
-    __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup IWDG_Exported_Functions_Group2
-  *  @brief   IO operation functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
- [..]  This section provides functions allowing to:
-      (+) Refresh the IWDG.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Refresh the IWDG.
-  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
-{
-  /* Reload IWDG counter with value defined in the reload register */
-  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_IWDG_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lcd.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lcd.c
deleted file mode 100644
index 62c405dd5d..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lcd.c
+++ /dev/null
@@ -1,609 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_lcd.c
-  * @author  MCD Application Team
-  * @brief   LCD Controller HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the LCD Controller (LCD) peripheral:
-  *           + Initialization/de-initialization methods
-  *           + I/O operation methods
-  *           + Peripheral State methods
-  *           
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================   
-      [..] The LCD HAL driver can be used as follow:
-    
-      (#) Declare a LCD_HandleTypeDef handle structure.
-
-      (#) Prepare the initialization of the LCD low level resources by implementing your HAL_LCD_MspInit() API:
-          (##) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, use the RCC function 
-               HAL_RCCEx_PeriphCLKConfig, indicating here RCC_PERIPHCLK_LCD and the selected clock 
-               source (HSE, LSI or LSE)
-          (##) The frequency generator allows you to achieve various LCD frame rates starting from an 
-               LCD input clock frequency (LCDCLK) which can vary from 32 kHz up to 1 MHz.
-          (##) LCD pins configuration:
-              - Enable the clock for the LCD GPIOs
-              - Configure these LCD pins as alternate function no-pull.
-          (##) Enable the LCD interface clock.
-
-      (#) Set the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias, Voltage Source, 
-          Dead Time, Pulse On Duration and Contrast in the hlcd Init structure.
-
-      (#) Initialize the LCD registers by calling the HAL_LCD_Init() API.
-          (##) The HAL_LCD_Init() API configures the low level Hardware (GPIO, CLOCK, ...etc)
-               by calling the user customized HAL_LCD_MspInit() API.
-      (#) After calling the HAL_LCD_Init() the LCD RAM memory is cleared
-
-      (#) Optionally you can update the LCD configuration using these macros:
-           (##) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros
-           (##) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro
-           (##) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro  
-           (##) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro
-           (##) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro  
-
-      (#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called
-          several times to update the different LCD RAM registers before calling 
-          HAL_LCD_UpdateDisplayRequest() API.
-
-      (#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory.
-
-      (#) When the LCD RAM memory is updated, enable the update display request calling
-          the HAL_LCD_UpdateDisplayRequest() API.
-
-      [..] LCD and low power modes: The LCD remain active during STOP mode.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_LCD_MODULE_ENABLED
-
-/** @addtogroup LCD
-  * @brief LCD HAL module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup LCD_Private
-  * @{
-  */
-#define LCD_TIMEOUT_VALUE             1000U
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup LCD_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup LCD_Exported_Functions_Group1
-  *  @brief    Initialization and Configuration functions 
-  *
-@verbatim    
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================  
-    [..]
-
-@endverbatim
-  * @{
-  */
- 
-/**
-  * @brief  DeInitializes the LCD peripheral. 
-  * @param  hlcd LCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd)
-{
-  /* Check the LCD handle allocation */
-  if(hlcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
-
-  /* Check the LCD peripheral state */
-  if(hlcd->State == HAL_LCD_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-
-  hlcd->State = HAL_LCD_STATE_BUSY;
-  
-  /* Disable the peripheral */
-  __HAL_LCD_DISABLE(hlcd);
-
-  /*Disable Highdrive by default*/
-  __HAL_LCD_HIGHDRIVER_DISABLE(hlcd);
-
-  /* DeInit the low level hardware */
-  HAL_LCD_MspDeInit(hlcd);
-  
-  hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
-  hlcd->State = HAL_LCD_STATE_RESET;
-    
-  /* Release Lock */
-  __HAL_UNLOCK(hlcd);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Initializes the LCD peripheral according to the specified parameters 
-  *         in the LCD_InitStruct.
-  * @note   This function can be used only when the LCD is disabled.
-  *         The LCD HighDrive can be enabled/disabled using related macros up to user.
-  * @param  hlcd LCD handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd)
-{
-  uint32_t tickstart = 0x00U;
-  uint8_t counter = 0U;
-    
-  /* Check the LCD handle allocation */
-  if(hlcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check function parameters */
-  assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
-  assert_param(IS_LCD_PRESCALER(hlcd->Init.Prescaler));
-  assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider));
-  assert_param(IS_LCD_DUTY(hlcd->Init.Duty));
-  assert_param(IS_LCD_BIAS(hlcd->Init.Bias));  
-  assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource));
-  assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration));
-  assert_param(IS_LCD_HIGHDRIVE(hlcd->Init.HighDrive));
-  assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime));
-  assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast)); 
-  assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency)); 
-  assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode)); 
-  assert_param(IS_LCD_MUXSEGMENT(hlcd->Init.MuxSegment));
-  
-  if(hlcd->State == HAL_LCD_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    __HAL_UNLOCK(hlcd);
-
-    /* Initialize the low level hardware (MSP) */
-    HAL_LCD_MspInit(hlcd);
-  }
-  
-  hlcd->State = HAL_LCD_STATE_BUSY;
-  
-  /* Disable the peripheral */
-  __HAL_LCD_DISABLE(hlcd);
-  
-  /* Clear the LCD_RAM registers and enable the display request by setting the UDR bit
-     in the LCD_SR register */
-  for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
-  {
-    hlcd->Instance->RAM[counter] = 0U;
-  }
-  /* Enable the display request */
-  SET_BIT(hlcd->Instance->SR, LCD_SR_UDR);
-  
-  /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency: 
-  Set PS[3:0] bits according to hlcd->Init.Prescaler value 
-     Set DIV[3:0] bits according to hlcd->Init.Divider value
-     Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value
-     Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value
-     Set DEAD[2:0] bits according to hlcd->Init.DeadTime value
-     Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value 
-     Set CC[2:0] bits according to hlcd->Init.Contrast value
-     Set HD[0] bit according to hlcd->Init.HighDrive value*/
-
-  MODIFY_REG(hlcd->Instance->FCR, \
-             (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \
-             LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC), \
-             (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \
-             hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive));
-
-  /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register 
-     This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK
-     domain. It is cleared by hardware when writing to the LCD_FCR register.*/
-  LCD_WaitForSynchro(hlcd);
-  
-  /* Configure the LCD Duty, Bias, Voltage Source, Dead Time:
-     Set DUTY[2:0] bits according to hlcd->Init.Duty value 
-     Set BIAS[1:0] bits according to hlcd->Init.Bias value
-     Set VSEL bit according to hlcd->Init.VoltageSource value
-     Set MUX_SEG bit according to hlcd->Init.MuxSegment value */
-  MODIFY_REG(hlcd->Instance->CR, \
-             (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \
-             (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment));
-  
-  /* Enable the peripheral */
-  __HAL_LCD_ENABLE(hlcd);
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-      
-  /* Wait Until the LCD is enabled */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-    { 
-      hlcd->ErrorCode = HAL_LCD_ERROR_ENS;
-      return HAL_TIMEOUT;
-    } 
-  }
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-  
-  /*!< Wait Until the LCD Booster is ready */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-    {   
-      hlcd->ErrorCode = HAL_LCD_ERROR_RDY;
-      return HAL_TIMEOUT;
-    } 
-  }
- 
-  /* Initialize the LCD state */
-  hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
-  hlcd->State= HAL_LCD_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  LCD MSP DeInit.
-  * @param  hlcd LCD handle
-  * @retval None
-  */
- __weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlcd);
-
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_LCD_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  LCD MSP Init.
-  * @param  hlcd LCD handle
-  * @retval None
-  */
- __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlcd);
-
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_LCD_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup LCD_Exported_Functions_Group2
-  *  @brief LCD RAM functions 
-  *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================  
- [..] Using its double buffer memory the LCD controller ensures the coherency of the 
- displayed information without having to use interrupts to control LCD_RAM 
- modification.
- The application software can access the first buffer level (LCD_RAM) through 
- the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API,
- it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API.
- This UDR flag (update display request) requests the updated information to be 
- moved into the second buffer level (LCD_DISPLAY).
- This operation is done synchronously with the frame (at the beginning of the 
- next frame), until the update is completed, the LCD_RAM is write protected and 
- the UDR flag stays high.
- Once the update is completed another flag (UDD - Update Display Done) is set and
- generates an interrupt if the UDDIE bit in the LCD_FCR register is set.
- The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one 
- even frame.
- The update will not occur (UDR = 1 and UDD = 0) until the display is 
- enabled (LCDEN = 1).
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Writes a word in the specific LCD RAM.
-  * @param  hlcd LCD handle
-  * @param  RAMRegisterIndex specifies the LCD RAM Register.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_RAM_REGISTER0: LCD RAM Register 0
-  *     @arg LCD_RAM_REGISTER1: LCD RAM Register 1
-  *     @arg LCD_RAM_REGISTER2: LCD RAM Register 2
-  *     @arg LCD_RAM_REGISTER3: LCD RAM Register 3
-  *     @arg LCD_RAM_REGISTER4: LCD RAM Register 4
-  *     @arg LCD_RAM_REGISTER5: LCD RAM Register 5
-  *     @arg LCD_RAM_REGISTER6: LCD RAM Register 6 
-  *     @arg LCD_RAM_REGISTER7: LCD RAM Register 7  
-  *     @arg LCD_RAM_REGISTER8: LCD RAM Register 8
-  *     @arg LCD_RAM_REGISTER9: LCD RAM Register 9
-  *     @arg LCD_RAM_REGISTER10: LCD RAM Register 10
-  *     @arg LCD_RAM_REGISTER11: LCD RAM Register 11
-  *     @arg LCD_RAM_REGISTER12: LCD RAM Register 12 
-  *     @arg LCD_RAM_REGISTER13: LCD RAM Register 13 
-  *     @arg LCD_RAM_REGISTER14: LCD RAM Register 14 
-  *     @arg LCD_RAM_REGISTER15: LCD RAM Register 15
-  * @param  RAMRegisterMask specifies the LCD RAM Register Data Mask.
-  * @param  Data specifies LCD Data Value to be written.
-  * @note   For LCD glass COM*SEG as 8*40 for example, the LCD common terminals COM[0,7]
-  *         are mapped on 32bits LCD_RAM_REGISTER[0,14] according to rules: COM(n) spread
-  *  	    on LCD_RAM_REGISTER(2*n) and  LCD_RAM_REGISTER(2*n+1).The segment terminals 
-  *		    SEG[0,39] of COM(n) correspond to LSB bits of related LCD_RAM_REGISTER(2*n)[0,31]
-  *		    and LCD_RAM_REGISTER(2*n+1)[0,7] 
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
-{
-  uint32_t tickstart = 0x00U; 
-  
-  if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
-  {
-    /* Check the parameters */
-    assert_param(IS_LCD_RAM_REGISTER(RAMRegisterIndex));
-    
-    if(hlcd->State == HAL_LCD_STATE_READY)
-    {
-      /* Process Locked */
-      __HAL_LOCK(hlcd);
-      hlcd->State = HAL_LCD_STATE_BUSY;
-      
-      /* Get timeout */
-      tickstart = HAL_GetTick();
-      
-      /*!< Wait Until the LCD is ready */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
-      {
-        if((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
-        { 
-          hlcd->ErrorCode = HAL_LCD_ERROR_UDR;      
-          /* Process Unlocked */
-          __HAL_UNLOCK(hlcd);
-          return HAL_TIMEOUT;
-        } 
-      }
-    }
-/* Copy the new Data bytes to LCD RAM register */
-    MODIFY_REG(hlcd->Instance->RAM[RAMRegisterIndex], ~(RAMRegisterMask), Data);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief Clears the LCD RAM registers.
-  * @param hlcd: LCD handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd)
-{
-  uint32_t tickstart = 0x00U; 
-  uint32_t counter = 0U;
-
-  if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hlcd);
-    
-    hlcd->State = HAL_LCD_STATE_BUSY;
-    
-    /* Get timeout */
-    tickstart = HAL_GetTick();
-    
-    /*!< Wait Until the LCD is ready */
-    while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
-    {
-      if( (HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
-      { 
-        hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hlcd);
-
-        return HAL_TIMEOUT;
-      } 
-    }
-    /* Clear the LCD_RAM registers */
-    for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
-    {
-      hlcd->Instance->RAM[counter] = 0U;
-    }
-    
-    /* Update the LCD display */
-    HAL_LCD_UpdateDisplayRequest(hlcd);     
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Enables the Update Display Request.
-  * @param  hlcd LCD handle
-  * @note   Each time software modifies the LCD_RAM it must set the UDR bit to 
-  *         transfer the updated data to the second level buffer. 
-  *         The UDR bit stays set until the end of the update and during this 
-  *         time the LCD_RAM is write protected. 
-  * @note   When the display is disabled, the update is performed for all 
-  *         LCD_DISPLAY locations.
-  *         When the display is enabled, the update is performed only for locations 
-  *         for which commons are active (depending on DUTY). For example if 
-  *         DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.    
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd)
-{
-  uint32_t tickstart = 0x00U;
-  
-  /* Clear the Update Display Done flag before starting the update display request */
-  __HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD);
-  
-  /* Enable the display request */
-  hlcd->Instance->SR |= LCD_SR_UDR;
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-  
-  /*!< Wait Until the LCD display is done */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-    { 
-      hlcd->ErrorCode = HAL_LCD_ERROR_UDD;
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hlcd);
-  
-      return HAL_TIMEOUT;
-    }
-  }
-
-  hlcd->State = HAL_LCD_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hlcd);
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup LCD_Exported_Functions_Group3
-  *  @brief   LCD State functions 
-  *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-     This subsection provides a set of functions allowing to control the LCD:
-      (+) HAL_LCD_GetState() API can be helpful to check in run-time the state of the LCD peripheral State. 
-      (+) HAL_LCD_GetError() API to return the LCD error code. 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Returns the LCD state.
-  * @param hlcd: LCD handle
-  * @retval HAL state
-  */
-HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd)
-{
-  return hlcd->State;
-}
-
-/**
-  * @brief Return the LCD error code
-  * @param hlcd: LCD handle
-  * @retval LCD Error Code
-  */
-uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd)
-{
-  return hlcd->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup LCD_Private
-  * @{
-  */
-
-/**
-  * @brief  Waits until the LCD FCR register is synchronized in the LCDCLK domain.
-  *   This function must be called after any write operation to LCD_FCR register.
-  * @param  hlcd LCD handle
-  * @retval None
-  */
-HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd)
-{
-  uint32_t tickstart = 0x00U; 
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-
-  /* Loop until FCRSF flag is set */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET)
-  {
-    if((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
-    {       
-      hlcd->ErrorCode = HAL_LCD_ERROR_FCRSF;
-      return HAL_TIMEOUT;
-    } 
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_LCD_MODULE_ENABLED */
-/**
-  * @}
-  */
-#endif /* #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c
deleted file mode 100644
index d6bbc98931..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c
+++ /dev/null
@@ -1,2457 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_lptim.c
-  * @author  MCD Application Team
-  * @brief   LPTIM HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Low Power Timer (LPTIM) peripheral:
-  *           + Initialization and de-initialization functions.
-  *           + Start/Stop operation functions in polling mode.
-  *           + Start/Stop operation functions in interrupt mode.
-  *           + Reading operation functions.
-  *           + Peripheral State functions.
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The LPTIM HAL driver can be used as follows:
-
-      (#)Initialize the LPTIM low level resources by implementing the
-        HAL_LPTIM_MspInit():
-         (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
-         (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
-             (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
-             (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
-             (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
-
-      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
-         configures mainly:
-         (++) The instance: LPTIM1.
-         (++) Clock: the counter clock.
-             (+++) Source   : it can be either the ULPTIM input (IN1) or one of
-                              the internal clock; (APB, LSE, LSI or MSI).
-             (+++) Prescaler: select the clock divider.
-         (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
-               as counter clock source.
-             (+++) Polarity:   polarity of the active edge for the counter unit
-                               if the ULPTIM input is selected.
-             (+++) SampleTime: clock sampling time to configure the clock glitch
-                               filter.
-         (++) Trigger: How the counter start.
-             (+++) Source: trigger can be software or one of the hardware triggers.
-             (+++) ActiveEdge : only for hardware trigger.
-             (+++) SampleTime : trigger sampling time to configure the trigger
-                                glitch filter.
-         (++) OutputPolarity : 2 opposite polarities are possible.
-         (++) UpdateMode: specifies whether the update of the autoreload and
-              the compare values is done immediately or after the end of current
-              period.
-
-      (#)Six modes are available:
-
-         (++) PWM Mode: To generate a PWM signal with specified period and pulse,
-         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
-         mode.
-
-         (++) One Pulse Mode: To generate pulse with specified width in response
-         to a stimulus, call HAL_LPTIM_OnePulse_Start() or
-         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
-
-         (++) Set once Mode: In this mode, the output changes the level (from
-         low level to high level if the output polarity is configured high, else
-         the opposite) when a compare match occurs. To start this mode, call
-         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
-         interruption mode.
-
-         (++) Encoder Mode: To use the encoder interface call
-         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
-         interruption mode. Only available for LPTIM1 instance.
-
-         (++) Time out Mode: an active edge on one selected trigger input rests
-         the counter. The first trigger event will start the timer, any
-         successive trigger event will reset the counter and the timer will
-         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
-         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
-
-         (++) Counter Mode: counter can be used to count external events on
-         the LPTIM Input1 or it can be used to count internal clock cycles.
-         To start this mode, call HAL_LPTIM_Counter_Start() or
-         HAL_LPTIM_Counter_Start_IT() for interruption mode.
-
-
-      (#) User can stop any process by calling the corresponding API:
-          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
-          already started in interruption mode.
-
-      (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
-
-    *** Callback registration ***
-  =============================================
-  [..]
-  The compilation define  USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
-  allows the user to configure dynamically the driver callbacks.
-  [..]
-  Use Function HAL_LPTIM_RegisterCallback() to register a callback.
-  HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
-  the Callback ID and a pointer to the user callback function.
-  [..]
-  Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
-  default weak function.
-  HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
-  and the Callback ID.
-  [..]
-  These functions allow to register/unregister following callbacks:
-
-    (+) MspInitCallback         : LPTIM Base Msp Init Callback.
-    (+) MspDeInitCallback       : LPTIM Base Msp DeInit Callback.
-    (+) CompareMatchCallback    : Compare match Callback.
-    (+) AutoReloadMatchCallback : Auto-reload match Callback.
-    (+) TriggerCallback         : External trigger event detection Callback.
-    (+) CompareWriteCallback    : Compare register write complete Callback.
-    (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
-    (+) DirectionUpCallback     : Up-counting direction change Callback.
-    (+) DirectionDownCallback   : Down-counting direction change Callback.
-
-  [..]
-  By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
-  all interrupt callbacks are set to the corresponding weak functions:
-  examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
-
-  [..]
-  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
-  functionalities in the Init/DeInit only when these callbacks are null
-  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
-  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
-  [..]
-  Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
-  Exception done MspInit/MspDeInit that can be registered/unregistered
-  in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
-  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-  In that case first register the MspInit/MspDeInit user callbacks
-  using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
-
-  [..]
-  When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
-  not defined, the callback registration feature is not available and all callbacks
-  are set to the corresponding weak functions.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup LPTIM LPTIM
-  * @brief LPTIM HAL module driver.
-  * @{
-  */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-
-#if defined (LPTIM1)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup LPTIM_Private_Constants
-  * @{
-  */
-#define TIMEOUT                                     1000UL /* Timeout is 1s */
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
-  * @{
-  */
-
-/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
-  *  @brief    Initialization and Configuration functions.
-  *
-@verbatim
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the LPTIM according to the specified parameters in the
-          LPTIM_InitTypeDef and initialize the associated handle.
-      (+) DeInitialize the LPTIM peripheral.
-      (+) Initialize the LPTIM MSP.
-      (+) DeInitialize the LPTIM MSP.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the LPTIM according to the specified parameters in the
-  *         LPTIM_InitTypeDef and initialize the associated handle.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
-{
-  uint32_t tmpcfgr;
-
-  /* Check the LPTIM handle allocation */
-  if (hlptim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
-  assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
-  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
-      || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
-  {
-    assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
-    assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
-  }
-  assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
-  if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
-  {
-    assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
-    assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
-  }
-  assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
-  assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
-  assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
-
-  if (hlptim->State == HAL_LPTIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hlptim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    LPTIM_ResetCallback(hlptim);
-
-    if (hlptim->MspInitCallback == NULL)
-    {
-      hlptim->MspInitCallback = HAL_LPTIM_MspInit;
-    }
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    hlptim->MspInitCallback(hlptim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    HAL_LPTIM_MspInit(hlptim);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-  }
-
-  /* Change the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Get the LPTIMx CFGR value */
-  tmpcfgr = hlptim->Instance->CFGR;
-
-  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
-      || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
-  {
-    tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
-  }
-  if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
-  {
-    tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
-  }
-
-  /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
-  tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
-                          LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
-
-  /* Set initialization parameters */
-  tmpcfgr |= (hlptim->Init.Clock.Source    |
-              hlptim->Init.Clock.Prescaler |
-              hlptim->Init.OutputPolarity  |
-              hlptim->Init.UpdateMode      |
-              hlptim->Init.CounterSource);
-
-  /* Glitch filters for internal triggers and  external inputs are configured
-   * only if an internal clock source is provided to the LPTIM
-   */
-  if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
-  {
-    tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
-                hlptim->Init.UltraLowPowerClock.SampleTime);
-  }
-
-  /* Configure LPTIM external clock polarity and digital filter */
-  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
-      || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
-  {
-    tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
-                hlptim->Init.UltraLowPowerClock.SampleTime);
-  }
-
-  /* Configure LPTIM external trigger */
-  if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
-  {
-    /* Enable External trigger and set the trigger source */
-    tmpcfgr |= (hlptim->Init.Trigger.Source     |
-                hlptim->Init.Trigger.ActiveEdge |
-                hlptim->Init.Trigger.SampleTime);
-  }
-
-  /* Write to LPTIMx CFGR */
-  hlptim->Instance->CFGR = tmpcfgr;
-
-  /* Change the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the LPTIM peripheral.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the LPTIM handle allocation */
-  if (hlptim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Change the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable the LPTIM Peripheral Clock */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-  if (hlptim->MspDeInitCallback == NULL)
-  {
-    hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
-  }
-
-  /* DeInit the low level hardware: CLOCK, NVIC.*/
-  hlptim->MspDeInitCallback(hlptim);
-#else
-  /* DeInit the low level hardware: CLOCK, NVIC.*/
-  HAL_LPTIM_MspDeInit(hlptim);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-
-  /* Change the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hlptim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the LPTIM MSP.
-  * @param  hlptim LPTIM handle
-  * @retval None
-  */
-__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlptim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_LPTIM_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize LPTIM MSP.
-  * @param  hlptim LPTIM handle
-  * @retval None
-  */
-__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlptim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_LPTIM_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
-  *  @brief   Start-Stop operation functions.
-  *
-@verbatim
-  ==============================================================================
-                ##### LPTIM Start Stop operation functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start the PWM mode.
-      (+) Stop the PWM mode.
-      (+) Start the One pulse mode.
-      (+) Stop the One pulse mode.
-      (+) Start the Set once mode.
-      (+) Stop the Set once mode.
-      (+) Start the Encoder mode.
-      (+) Stop the Encoder mode.
-      (+) Start the Timeout mode.
-      (+) Stop the Timeout mode.
-      (+) Start the Counter mode.
-      (+) Stop the Counter mode.
-
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the LPTIM PWM generation.
-  * @param  hlptim LPTIM handle
-  * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @param  Pulse Specifies the compare value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-  assert_param(IS_LPTIM_PERIOD(Period));
-  assert_param(IS_LPTIM_PULSE(Pulse));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Reset WAVE bit to set PWM mode */
-  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-  /* Load the period value in the autoreload register */
-  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
-  /* Wait for the completion of the write operation to the LPTIM_ARR register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
-
-  /* Load the pulse value in the compare register */
-  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
-  /* Wait for the completion of the write operation to the LPTIM_CMP register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Start timer in continuous mode */
-  __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the LPTIM PWM generation.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Change the LPTIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the LPTIM PWM generation in interrupt mode.
-  * @param  hlptim LPTIM handle
-  * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF
-  * @param  Pulse Specifies the compare value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-  assert_param(IS_LPTIM_PERIOD(Period));
-  assert_param(IS_LPTIM_PULSE(Pulse));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Reset WAVE bit to set PWM mode */
-  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-  /* Load the period value in the autoreload register */
-  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
-  /* Wait for the completion of the write operation to the LPTIM_ARR register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
-
-  /* Load the pulse value in the compare register */
-  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
-  /* Wait for the completion of the write operation to the LPTIM_CMP register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Enable Autoreload write complete interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
-
-  /* Enable Compare write complete interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
-  /* Enable Autoreload match interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
-
-  /* Enable Compare match interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
-
-  /* If external trigger source is used, then enable external trigger interrupt */
-  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
-  {
-    /* Enable external trigger interrupt */
-    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Start timer in continuous mode */
-  __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the LPTIM PWM generation in interrupt mode.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Disable Autoreload write complete interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
-
-  /* Disable Compare write complete interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
-  /* Disable Autoreload match interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
-  /* Disable Compare match interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
-
-  /* If external trigger source is used, then disable external trigger interrupt */
-  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
-  {
-    /* Disable external trigger interrupt */
-    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
-  }
-
-  /* Change the LPTIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the LPTIM One pulse generation.
-  * @param  hlptim LPTIM handle
-  * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @param  Pulse Specifies the compare value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-  assert_param(IS_LPTIM_PERIOD(Period));
-  assert_param(IS_LPTIM_PULSE(Pulse));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Reset WAVE bit to set one pulse mode */
-  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-  /* Load the period value in the autoreload register */
-  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
-  /* Wait for the completion of the write operation to the LPTIM_ARR register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
-
-  /* Load the pulse value in the compare register */
-  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
-  /* Wait for the completion of the write operation to the LPTIM_CMP register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Start timer in single (one shot) mode */
-  __HAL_LPTIM_START_SINGLE(hlptim);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the LPTIM One pulse generation.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Change the LPTIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the LPTIM One pulse generation in interrupt mode.
-  * @param  hlptim LPTIM handle
-  * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @param  Pulse Specifies the compare value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-  assert_param(IS_LPTIM_PERIOD(Period));
-  assert_param(IS_LPTIM_PULSE(Pulse));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Reset WAVE bit to set one pulse mode */
-  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-  /* Load the period value in the autoreload register */
-  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
-  /* Wait for the completion of the write operation to the LPTIM_ARR register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
-
-  /* Load the pulse value in the compare register */
-  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
-  /* Wait for the completion of the write operation to the LPTIM_CMP register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Enable Autoreload write complete interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
-
-  /* Enable Compare write complete interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
-  /* Enable Autoreload match interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
-
-  /* Enable Compare match interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
-
-  /* If external trigger source is used, then enable external trigger interrupt */
-  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
-  {
-    /* Enable external trigger interrupt */
-    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Start timer in single (one shot) mode */
-  __HAL_LPTIM_START_SINGLE(hlptim);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the LPTIM One pulse generation in interrupt mode.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Disable Autoreload write complete interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
-
-  /* Disable Compare write complete interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
-  /* Disable Autoreload match interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
-  /* Disable Compare match interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
-
-  /* If external trigger source is used, then disable external trigger interrupt */
-  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
-  {
-    /* Disable external trigger interrupt */
-    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
-  }
-
-  /* Change the LPTIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the LPTIM in Set once mode.
-  * @param  hlptim LPTIM handle
-  * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @param  Pulse Specifies the compare value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-  assert_param(IS_LPTIM_PERIOD(Period));
-  assert_param(IS_LPTIM_PULSE(Pulse));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Set WAVE bit to enable the set once mode */
-  hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-  /* Load the period value in the autoreload register */
-  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
-  /* Wait for the completion of the write operation to the LPTIM_ARR register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
-
-  /* Load the pulse value in the compare register */
-  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
-  /* Wait for the completion of the write operation to the LPTIM_CMP register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Start timer in single (one shot) mode */
-  __HAL_LPTIM_START_SINGLE(hlptim);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the LPTIM Set once mode.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Change the LPTIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the LPTIM Set once mode in interrupt mode.
-  * @param  hlptim LPTIM handle
-  * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @param  Pulse Specifies the compare value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-  assert_param(IS_LPTIM_PERIOD(Period));
-  assert_param(IS_LPTIM_PULSE(Pulse));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Set WAVE bit to enable the set once mode */
-  hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-  /* Load the period value in the autoreload register */
-  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
-  /* Wait for the completion of the write operation to the LPTIM_ARR register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
-
-  /* Load the pulse value in the compare register */
-  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
-  /* Wait for the completion of the write operation to the LPTIM_CMP register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Enable Autoreload write complete interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
-
-  /* Enable Compare write complete interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
-  /* Enable Autoreload match interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
-
-  /* Enable Compare match interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
-
-  /* If external trigger source is used, then enable external trigger interrupt */
-  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
-  {
-    /* Enable external trigger interrupt */
-    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Start timer in single (one shot) mode */
-  __HAL_LPTIM_START_SINGLE(hlptim);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the LPTIM Set once mode in interrupt mode.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Disable Autoreload write complete interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
-
-  /* Disable Compare write complete interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
-  /* Disable Autoreload match interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
-  /* Disable Compare match interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
-
-  /* If external trigger source is used, then disable external trigger interrupt */
-  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
-  {
-    /* Disable external trigger interrupt */
-    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
-  }
-
-  /* Change the LPTIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the Encoder interface.
-  * @param  hlptim LPTIM handle
-  * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
-{
-  uint32_t          tmpcfgr;
-
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-  assert_param(IS_LPTIM_PERIOD(Period));
-  assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
-  assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
-  assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Get the LPTIMx CFGR value */
-  tmpcfgr = hlptim->Instance->CFGR;
-
-  /* Clear CKPOL bits */
-  tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
-
-  /* Set Input polarity */
-  tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
-
-  /* Write to LPTIMx CFGR */
-  hlptim->Instance->CFGR = tmpcfgr;
-
-  /* Set ENC bit to enable the encoder interface */
-  hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-  /* Load the period value in the autoreload register */
-  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
-  /* Wait for the completion of the write operation to the LPTIM_ARR register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Start timer in continuous mode */
-  __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the Encoder interface.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Reset ENC bit to disable the encoder interface */
-  hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the Encoder interface in interrupt mode.
-  * @param  hlptim LPTIM handle
-  * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
-{
-  uint32_t          tmpcfgr;
-
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-  assert_param(IS_LPTIM_PERIOD(Period));
-  assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
-  assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
-  assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Configure edge sensitivity for encoder mode */
-  /* Get the LPTIMx CFGR value */
-  tmpcfgr = hlptim->Instance->CFGR;
-
-  /* Clear CKPOL bits */
-  tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
-
-  /* Set Input polarity */
-  tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
-
-  /* Write to LPTIMx CFGR */
-  hlptim->Instance->CFGR = tmpcfgr;
-
-  /* Set ENC bit to enable the encoder interface */
-  hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-  /* Load the period value in the autoreload register */
-  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
-  /* Wait for the completion of the write operation to the LPTIM_ARR register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Enable "switch to down direction" interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
-
-  /* Enable "switch to up direction" interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Start timer in continuous mode */
-  __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the Encoder interface in interrupt mode.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Reset ENC bit to disable the encoder interface */
-  hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
-
-  /* Disable "switch to down direction" interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
-
-  /* Disable "switch to up direction" interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the Timeout function.
-  * @note   The first trigger event will start the timer, any successive
-  *         trigger event will reset the counter and the timer restarts.
-  * @param  hlptim LPTIM handle
-  * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @param  Timeout Specifies the TimeOut value to reset the counter.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-  assert_param(IS_LPTIM_PERIOD(Period));
-  assert_param(IS_LPTIM_PULSE(Timeout));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Set TIMOUT bit to enable the timeout function */
-  hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-  /* Load the period value in the autoreload register */
-  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
-  /* Wait for the completion of the write operation to the LPTIM_ARR register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
-
-  /* Load the Timeout value in the compare register */
-  __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
-
-  /* Wait for the completion of the write operation to the LPTIM_CMP register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Start timer in continuous mode */
-  __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the Timeout function.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Reset TIMOUT bit to enable the timeout function */
-  hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the Timeout function in interrupt mode.
-  * @note   The first trigger event will start the timer, any successive
-  *         trigger event will reset the counter and the timer restarts.
-  * @param  hlptim LPTIM handle
-  * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @param  Timeout Specifies the TimeOut value to reset the counter.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-  assert_param(IS_LPTIM_PERIOD(Period));
-  assert_param(IS_LPTIM_PULSE(Timeout));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
-  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
-
-  /* Set TIMOUT bit to enable the timeout function */
-  hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-  /* Load the period value in the autoreload register */
-  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
-  /* Wait for the completion of the write operation to the LPTIM_ARR register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
-
-  /* Load the Timeout value in the compare register */
-  __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
-
-  /* Wait for the completion of the write operation to the LPTIM_CMP register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Enable Compare match interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Start timer in continuous mode */
-  __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the Timeout function in interrupt mode.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
-  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Reset TIMOUT bit to enable the timeout function */
-  hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
-
-  /* Disable Compare match interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the Counter mode.
-  * @param  hlptim LPTIM handle
-  * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-  assert_param(IS_LPTIM_PERIOD(Period));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
-  if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
-      && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
-  {
-    /* Check if clock is prescaled */
-    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
-    /* Set clock prescaler to 0 */
-    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
-  }
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-  /* Load the period value in the autoreload register */
-  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
-  /* Wait for the completion of the write operation to the LPTIM_ARR register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Start timer in continuous mode */
-  __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the Counter mode.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the Counter mode in interrupt mode.
-  * @param  hlptim LPTIM handle
-  * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-  assert_param(IS_LPTIM_PERIOD(Period));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
-  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
-
-  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
-  if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
-      && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
-  {
-    /* Check if clock is prescaled */
-    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
-    /* Set clock prescaler to 0 */
-    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
-  }
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Clear flag */
-  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-  /* Load the period value in the autoreload register */
-  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
-  /* Wait for the completion of the write operation to the LPTIM_ARR register */
-  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Enable Autoreload write complete interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
-
-  /* Enable Autoreload match interrupt */
-  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
-
-  /* Enable the Peripheral */
-  __HAL_LPTIM_ENABLE(hlptim);
-
-  /* Start timer in continuous mode */
-  __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the Counter mode in interrupt mode.
-  * @param  hlptim LPTIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  /* Set the LPTIM state */
-  hlptim->State = HAL_LPTIM_STATE_BUSY;
-
-  /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
-  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
-
-  /* Disable the Peripheral */
-  __HAL_LPTIM_DISABLE(hlptim);
-
-  if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Disable Autoreload write complete interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
-
-  /* Disable Autoreload match interrupt */
-  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-  /* Change the TIM state*/
-  hlptim->State = HAL_LPTIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
-  *  @brief  Read operation functions.
-  *
-@verbatim
-  ==============================================================================
-                  ##### LPTIM Read operation functions #####
-  ==============================================================================
-[..]  This section provides LPTIM Reading functions.
-      (+) Read the counter value.
-      (+) Read the period (Auto-reload) value.
-      (+) Read the pulse (Compare)value.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the current counter value.
-  * @param  hlptim LPTIM handle
-  * @retval Counter value.
-  */
-uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  return (hlptim->Instance->CNT);
-}
-
-/**
-  * @brief  Return the current Autoreload (Period) value.
-  * @param  hlptim LPTIM handle
-  * @retval Autoreload value.
-  */
-uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  return (hlptim->Instance->ARR);
-}
-
-/**
-  * @brief  Return the current Compare (Pulse) value.
-  * @param  hlptim LPTIM handle
-  * @retval Compare value.
-  */
-uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
-  return (hlptim->Instance->CMP);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
-  *  @brief  LPTIM  IRQ handler.
-  *
-@verbatim
-  ==============================================================================
-                      ##### LPTIM IRQ handler and callbacks  #####
-  ==============================================================================
-[..]  This section provides LPTIM IRQ handler and callback functions called within
-      the IRQ handler:
-   (+) LPTIM interrupt request handler
-   (+) Compare match Callback
-   (+) Auto-reload match Callback
-   (+) External trigger event detection Callback
-   (+) Compare register write complete Callback
-   (+) Auto-reload register write complete Callback
-   (+) Up-counting direction change Callback
-   (+) Down-counting direction change Callback
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Handle LPTIM interrupt request.
-  * @param  hlptim LPTIM handle
-  * @retval None
-  */
-void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Compare match interrupt */
-  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
-  {
-    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
-    {
-      /* Clear Compare match flag */
-      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
-
-      /* Compare match Callback */
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-      hlptim->CompareMatchCallback(hlptim);
-#else
-      HAL_LPTIM_CompareMatchCallback(hlptim);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Autoreload match interrupt */
-  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
-  {
-    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
-    {
-      /* Clear Autoreload match flag */
-      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
-
-      /* Autoreload match Callback */
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-      hlptim->AutoReloadMatchCallback(hlptim);
-#else
-      HAL_LPTIM_AutoReloadMatchCallback(hlptim);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Trigger detected interrupt */
-  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
-  {
-    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
-    {
-      /* Clear Trigger detected flag */
-      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
-
-      /* Trigger detected callback */
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-      hlptim->TriggerCallback(hlptim);
-#else
-      HAL_LPTIM_TriggerCallback(hlptim);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Compare write interrupt */
-  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
-  {
-    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
-    {
-      /* Clear Compare write flag */
-      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
-
-      /* Compare write Callback */
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-      hlptim->CompareWriteCallback(hlptim);
-#else
-      HAL_LPTIM_CompareWriteCallback(hlptim);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Autoreload write interrupt */
-  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
-  {
-    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
-    {
-      /* Clear Autoreload write flag */
-      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
-      /* Autoreload write Callback */
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-      hlptim->AutoReloadWriteCallback(hlptim);
-#else
-      HAL_LPTIM_AutoReloadWriteCallback(hlptim);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Direction counter changed from Down to Up interrupt */
-  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
-  {
-    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
-    {
-      /* Clear Direction counter changed from Down to Up flag */
-      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
-
-      /* Direction counter changed from Down to Up Callback */
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-      hlptim->DirectionUpCallback(hlptim);
-#else
-      HAL_LPTIM_DirectionUpCallback(hlptim);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Direction counter changed from Up to Down interrupt */
-  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
-  {
-    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
-    {
-      /* Clear Direction counter changed from Up to Down flag */
-      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
-
-      /* Direction counter changed from Up to Down Callback */
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-      hlptim->DirectionDownCallback(hlptim);
-#else
-      HAL_LPTIM_DirectionDownCallback(hlptim);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-    }
-  }
-}
-
-/**
-  * @brief  Compare match callback in non-blocking mode.
-  * @param  hlptim LPTIM handle
-  * @retval None
-  */
-__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlptim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Autoreload match callback in non-blocking mode.
-  * @param  hlptim LPTIM handle
-  * @retval None
-  */
-__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlptim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Trigger detected callback in non-blocking mode.
-  * @param  hlptim LPTIM handle
-  * @retval None
-  */
-__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlptim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_LPTIM_TriggerCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Compare write callback in non-blocking mode.
-  * @param  hlptim LPTIM handle
-  * @retval None
-  */
-__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlptim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Autoreload write callback in non-blocking mode.
-  * @param  hlptim LPTIM handle
-  * @retval None
-  */
-__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlptim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Direction counter changed from Down to Up callback in non-blocking mode.
-  * @param  hlptim LPTIM handle
-  * @retval None
-  */
-__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlptim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Direction counter changed from Up to Down callback in non-blocking mode.
-  * @param  hlptim LPTIM handle
-  * @retval None
-  */
-__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlptim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User LPTIM callback to be used instead of the weak predefined callback
-  * @param hlptim LPTIM handle
-  * @param CallbackID ID of the callback to be registered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID          LPTIM Base Msp Init Callback ID
-  *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID        LPTIM Base Msp DeInit Callback ID
-  *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID    Compare match Callback ID
-  *          @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
-  *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID          External trigger event detection Callback ID
-  *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID    Compare register write complete Callback ID
-  *          @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
-  *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID     Up-counting direction change Callback ID
-  *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID   Down-counting direction change Callback ID
-  * @param pCallback pointer to the callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef        *hlptim,
-                                             HAL_LPTIM_CallbackIDTypeDef CallbackID,
-                                             pLPTIM_CallbackTypeDef      pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hlptim);
-
-  if (hlptim->State == HAL_LPTIM_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_LPTIM_MSPINIT_CB_ID :
-        hlptim->MspInitCallback = pCallback;
-        break;
-
-      case HAL_LPTIM_MSPDEINIT_CB_ID :
-        hlptim->MspDeInitCallback = pCallback;
-        break;
-
-      case HAL_LPTIM_COMPARE_MATCH_CB_ID :
-        hlptim->CompareMatchCallback = pCallback;
-        break;
-
-      case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
-        hlptim->AutoReloadMatchCallback = pCallback;
-        break;
-
-      case HAL_LPTIM_TRIGGER_CB_ID :
-        hlptim->TriggerCallback = pCallback;
-        break;
-
-      case HAL_LPTIM_COMPARE_WRITE_CB_ID :
-        hlptim->CompareWriteCallback = pCallback;
-        break;
-
-      case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
-        hlptim->AutoReloadWriteCallback = pCallback;
-        break;
-
-      case HAL_LPTIM_DIRECTION_UP_CB_ID :
-        hlptim->DirectionUpCallback = pCallback;
-        break;
-
-      case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
-        hlptim->DirectionDownCallback = pCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hlptim->State == HAL_LPTIM_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_LPTIM_MSPINIT_CB_ID :
-        hlptim->MspInitCallback = pCallback;
-        break;
-
-      case HAL_LPTIM_MSPDEINIT_CB_ID :
-        hlptim->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hlptim);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister a LPTIM callback
-  *         LLPTIM callback is redirected to the weak predefined callback
-  * @param hlptim LPTIM handle
-  * @param CallbackID ID of the callback to be unregistered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID          LPTIM Base Msp Init Callback ID
-  *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID        LPTIM Base Msp DeInit Callback ID
-  *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID    Compare match Callback ID
-  *          @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
-  *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID          External trigger event detection Callback ID
-  *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID    Compare register write complete Callback ID
-  *          @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
-  *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID     Up-counting direction change Callback ID
-  *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID   Down-counting direction change Callback ID
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef        *hlptim,
-                                               HAL_LPTIM_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hlptim);
-
-  if (hlptim->State == HAL_LPTIM_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_LPTIM_MSPINIT_CB_ID :
-        /* Legacy weak MspInit Callback */
-        hlptim->MspInitCallback = HAL_LPTIM_MspInit;
-        break;
-
-      case HAL_LPTIM_MSPDEINIT_CB_ID :
-        /* Legacy weak Msp DeInit Callback */
-        hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
-        break;
-
-      case HAL_LPTIM_COMPARE_MATCH_CB_ID :
-        /* Legacy weak Compare match Callback */
-        hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
-        break;
-
-      case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
-        /* Legacy weak Auto-reload match Callback */
-        hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
-        break;
-
-      case HAL_LPTIM_TRIGGER_CB_ID :
-        /* Legacy weak External trigger event detection Callback */
-        hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
-        break;
-
-      case HAL_LPTIM_COMPARE_WRITE_CB_ID :
-        /* Legacy weak Compare register write complete Callback */
-        hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
-        break;
-
-      case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
-        /* Legacy weak Auto-reload register write complete Callback */
-        hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
-        break;
-
-      case HAL_LPTIM_DIRECTION_UP_CB_ID :
-        /* Legacy weak Up-counting direction change Callback */
-        hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
-        break;
-
-      case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
-        /* Legacy weak Down-counting direction change Callback */
-        hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hlptim->State == HAL_LPTIM_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_LPTIM_MSPINIT_CB_ID :
-        /* Legacy weak MspInit Callback */
-        hlptim->MspInitCallback = HAL_LPTIM_MspInit;
-        break;
-
-      case HAL_LPTIM_MSPDEINIT_CB_ID :
-        /* Legacy weak Msp DeInit Callback */
-        hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hlptim);
-
-  return status;
-}
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Group5 Peripheral State functions
-  *  @brief   Peripheral State functions.
-  *
-@verbatim
-  ==============================================================================
-                      ##### Peripheral State functions #####
-  ==============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the LPTIM handle state.
-  * @param  hlptim LPTIM handle
-  * @retval HAL state
-  */
-HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
-{
-  /* Return LPTIM handle state */
-  return hlptim->State;
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
-  * @{
-  */
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
-  * @param  lptim pointer to a LPTIM_HandleTypeDef structure that contains
-  *                the configuration information for LPTIM module.
-  * @retval None
-  */
-static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
-{
-  /* Reset the LPTIM callback to the legacy weak callbacks */
-  lptim->CompareMatchCallback    = HAL_LPTIM_CompareMatchCallback;
-  lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
-  lptim->TriggerCallback         = HAL_LPTIM_TriggerCallback;
-  lptim->CompareWriteCallback    = HAL_LPTIM_CompareWriteCallback;
-  lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
-  lptim->DirectionUpCallback     = HAL_LPTIM_DirectionUpCallback;
-  lptim->DirectionDownCallback   = HAL_LPTIM_DirectionDownCallback;
-}
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-
-/**
-  * @brief  LPTimer Wait for flag set
-  * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
-  *                the configuration information for LPTIM module.
-  * @param  flag   The lptim flag
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
-{
-  HAL_StatusTypeDef result = HAL_OK;
-  uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
-  do
-  {
-    count--;
-    if (count == 0UL)
-    {
-      result = HAL_TIMEOUT;
-    }
-  } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
-
-  return result;
-}
-
-/**
-  * @brief  Disable LPTIM HW instance.
-  * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
-  *                the configuration information for LPTIM module.
-  * @note   The following sequence is required to solve LPTIM disable HW limitation.
-  *         Please check Errata Sheet ES0335 for more details under "MCU may remain
-  *         stuck in LPTIM interrupt when entering Stop mode" section.
-  * @retval None
-  */
-void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
-{
-  uint32_t tmpclksource = 0;
-  uint32_t tmpIER;
-  uint32_t tmpCFGR;
-  uint32_t tmpCMP;
-  uint32_t tmpARR;
-
-  __disable_irq();
-
-  /*********** Save LPTIM Config ***********/
-  /* Save LPTIM source clock */
-  switch ((uint32_t)hlptim->Instance)
-  {
-    case LPTIM1_BASE:
-      tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
-      break;
-    default:
-      break;
-  }
-
-  /* Save LPTIM configuration registers */
-  tmpIER = hlptim->Instance->IER;
-  tmpCFGR = hlptim->Instance->CFGR;
-  tmpCMP = hlptim->Instance->CMP;
-  tmpARR = hlptim->Instance->ARR;
-
-  /*********** Reset LPTIM ***********/
-  switch ((uint32_t)hlptim->Instance)
-  {
-    case LPTIM1_BASE:
-      __HAL_RCC_LPTIM1_FORCE_RESET();
-      __HAL_RCC_LPTIM1_RELEASE_RESET();
-      break;
-    default:
-      break;
-  }
-
-  /*********** Restore LPTIM Config ***********/
-  if ((tmpCMP != 0UL) || (tmpARR != 0UL))
-  {
-    /* Force LPTIM source kernel clock from APB */
-    switch ((uint32_t)hlptim->Instance)
-    {
-      case LPTIM1_BASE:
-        __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
-        break;
-      default:
-        break;
-    }
-
-    if (tmpCMP != 0UL)
-    {
-      /* Restore CMP register (LPTIM should be enabled first) */
-      hlptim->Instance->CR |= LPTIM_CR_ENABLE;
-      hlptim->Instance->CMP = tmpCMP;
-
-      /* Wait for the completion of the write operation to the LPTIM_CMP register */
-      if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
-      {
-        hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
-      }
-      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
-    }
-
-    if (tmpARR != 0UL)
-    {
-      /* Restore ARR register (LPTIM should be enabled first) */
-      hlptim->Instance->CR |= LPTIM_CR_ENABLE;
-      hlptim->Instance->ARR = tmpARR;
-
-      /* Wait for the completion of the write operation to the LPTIM_ARR register */
-      if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
-      {
-        hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
-      }
-
-      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-    }
-
-    /* Restore LPTIM source kernel clock */
-    switch ((uint32_t)hlptim->Instance)
-    {
-      case LPTIM1_BASE:
-        __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
-        break;
-      default:
-        break;
-    }
-  }
-
-  /* Restore configuration registers (LPTIM should be disabled first) */
-  hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
-  hlptim->Instance->IER = tmpIER;
-  hlptim->Instance->CFGR = tmpCFGR;
-
-  __enable_irq();
-}
-/**
-  * @}
-  */
-#endif /* LPTIM1 */
-
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_msp_template.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_msp_template.c
deleted file mode 100644
index 2941b0ee67..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_msp_template.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_msp_template.c
-  * @author  MCD Application Team
-  * @brief   HAL MSP module.
-  *          This file template is located in the HAL folder and should be copied 
-  *          to the user folder.
-  *         
-  @verbatim
- ===============================================================================
-                     ##### How to use this driver #####
- ===============================================================================
-    [..]
-    This file is eventually modified by the user.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup HAL_MSP
-  * @brief HAL MSP module.
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_MSP_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Initializes the Global BSP.
-  * @param  None
-  * @retval None
-  */
-void HAL_MspInit(void)
-{
-  /* NOTE : This function is eventually modified by the user */ 
-}
-
-/**
-  * @brief  DeInitializes the Global MSP.
-  * @param  None  
-  * @retval None
-  */
-void HAL_MspDeInit(void)
-{
-  /* NOTE : This function is eventually modified by the user */
-}
-
-/**
-  * @brief  Initializes the PPP MSP.
-  * @param  None
-  * @retval None
-  */
-void HAL_PPP_MspInit(void)
-{
-  /* NOTE : This function is eventually modified by the user */ 
-}
-
-/**
-  * @brief  DeInitializes the PPP MSP.
-  * @param  None  
-  * @retval None
-  */
-void HAL_PPP_MspDeInit(void)
-{
-  /* NOTE : This function is eventually modified by the user */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c
deleted file mode 100644
index 81b702a9f9..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c
+++ /dev/null
@@ -1,2184 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_pcd.c
-  * @author  MCD Application Team
-  * @brief   PCD HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the USB Peripheral Controller:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The PCD HAL driver can be used as follows:
-
-     (#) Declare a PCD_HandleTypeDef handle structure, for example:
-         PCD_HandleTypeDef  hpcd;
-
-     (#) Fill parameters of Init structure in HCD handle
-
-     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
-
-     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
-         (##) Enable the PCD/USB Low Level interface clock using
-              (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral
-
-         (##) Initialize the related GPIO clocks
-         (##) Configure PCD pin-out
-         (##) Configure PCD NVIC interrupt
-
-     (#)Associate the Upper USB device stack to the HAL PCD Driver:
-         (##) hpcd.pData = pdev;
-
-     (#)Enable PCD transmission and reception:
-         (##) HAL_PCD_Start();
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PCD PCD
-  * @brief PCD HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-#if defined (USB)
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
-  * @{
-  */
-#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
-#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
-/**
-  * @}
-  */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup PCD_Private_Functions PCD Private Functions
-  * @{
-  */
-
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
-static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
-static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Functions PCD Exported Functions
-  * @{
-  */
-
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-            ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the PCD according to the specified
-  *         parameters in the PCD_InitTypeDef and initialize the associated handle.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
-{
-  uint8_t i;
-
-  /* Check the PCD handle allocation */
-  if (hpcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
-
-  if (hpcd->State == HAL_PCD_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hpcd->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-    hpcd->SOFCallback = HAL_PCD_SOFCallback;
-    hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
-    hpcd->ResetCallback = HAL_PCD_ResetCallback;
-    hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
-    hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
-    hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
-    hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
-    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
-    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
-    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
-    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
-    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
-    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
-
-    if (hpcd->MspInitCallback == NULL)
-    {
-      hpcd->MspInitCallback = HAL_PCD_MspInit;
-    }
-
-    /* Init the low level hardware */
-    hpcd->MspInitCallback(hpcd);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    HAL_PCD_MspInit(hpcd);
-#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
-  }
-
-  hpcd->State = HAL_PCD_STATE_BUSY;
-
-  /* Disable the Interrupts */
-  __HAL_PCD_DISABLE(hpcd);
-
-  /* Init endpoints structures */
-  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
-  {
-    /* Init ep structure */
-    hpcd->IN_ep[i].is_in = 1U;
-    hpcd->IN_ep[i].num = i;
-    hpcd->IN_ep[i].tx_fifo_num = i;
-    /* Control until ep is activated */
-    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
-    hpcd->IN_ep[i].maxpacket = 0U;
-    hpcd->IN_ep[i].xfer_buff = 0U;
-    hpcd->IN_ep[i].xfer_len = 0U;
-  }
-
-  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
-  {
-    hpcd->OUT_ep[i].is_in = 0U;
-    hpcd->OUT_ep[i].num = i;
-    /* Control until ep is activated */
-    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
-    hpcd->OUT_ep[i].maxpacket = 0U;
-    hpcd->OUT_ep[i].xfer_buff = 0U;
-    hpcd->OUT_ep[i].xfer_len = 0U;
-  }
-
-  /* Init Device */
-  (void)USB_DevInit(hpcd->Instance, hpcd->Init);
-
-  hpcd->USB_Address = 0U;
-  hpcd->State = HAL_PCD_STATE_READY;
-
-  /* Activate LPM */
-  if (hpcd->Init.lpm_enable == 1U)
-  {
-    (void)HAL_PCDEx_ActivateLPM(hpcd);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the PCD peripheral.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Check the PCD handle allocation */
-  if (hpcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  hpcd->State = HAL_PCD_STATE_BUSY;
-
-  /* Stop Device */
-  if (USB_StopDevice(hpcd->Instance) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-  if (hpcd->MspDeInitCallback == NULL)
-  {
-    hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */
-  }
-
-  /* DeInit the low level hardware */
-  hpcd->MspDeInitCallback(hpcd);
-#else
-  /* DeInit the low level hardware: CLOCK, NVIC.*/
-  HAL_PCD_MspDeInit(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-  hpcd->State = HAL_PCD_STATE_RESET;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the PCD MSP.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes PCD MSP.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_MspDeInit could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  Register a User USB PCD Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hpcd USB PCD handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
-  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
-  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
-  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
-  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
-  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
-  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
-  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
-  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
-                                           HAL_PCD_CallbackIDTypeDef CallbackID,
-                                           pPCD_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_PCD_SOF_CB_ID :
-        hpcd->SOFCallback = pCallback;
-        break;
-
-      case HAL_PCD_SETUPSTAGE_CB_ID :
-        hpcd->SetupStageCallback = pCallback;
-        break;
-
-      case HAL_PCD_RESET_CB_ID :
-        hpcd->ResetCallback = pCallback;
-        break;
-
-      case HAL_PCD_SUSPEND_CB_ID :
-        hpcd->SuspendCallback = pCallback;
-        break;
-
-      case HAL_PCD_RESUME_CB_ID :
-        hpcd->ResumeCallback = pCallback;
-        break;
-
-      case HAL_PCD_CONNECT_CB_ID :
-        hpcd->ConnectCallback = pCallback;
-        break;
-
-      case HAL_PCD_DISCONNECT_CB_ID :
-        hpcd->DisconnectCallback = pCallback;
-        break;
-
-      case HAL_PCD_MSPINIT_CB_ID :
-        hpcd->MspInitCallback = pCallback;
-        break;
-
-      case HAL_PCD_MSPDEINIT_CB_ID :
-        hpcd->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hpcd->State == HAL_PCD_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_PCD_MSPINIT_CB_ID :
-        hpcd->MspInitCallback = pCallback;
-        break;
-
-      case HAL_PCD_MSPDEINIT_CB_ID :
-        hpcd->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-  return status;
-}
-
-/**
-  * @brief  Unregister an USB PCD Callback
-  *         USB PCD callabck is redirected to the weak predefined callback
-  * @param  hpcd USB PCD handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
-  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
-  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
-  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
-  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
-  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
-  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
-  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
-  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  /* Setup Legacy weak Callbacks  */
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_PCD_SOF_CB_ID :
-        hpcd->SOFCallback = HAL_PCD_SOFCallback;
-        break;
-
-      case HAL_PCD_SETUPSTAGE_CB_ID :
-        hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
-        break;
-
-      case HAL_PCD_RESET_CB_ID :
-        hpcd->ResetCallback = HAL_PCD_ResetCallback;
-        break;
-
-      case HAL_PCD_SUSPEND_CB_ID :
-        hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
-        break;
-
-      case HAL_PCD_RESUME_CB_ID :
-        hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
-        break;
-
-      case HAL_PCD_CONNECT_CB_ID :
-        hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
-        break;
-
-      case HAL_PCD_DISCONNECT_CB_ID :
-        hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
-        break;
-
-      case HAL_PCD_MSPINIT_CB_ID :
-        hpcd->MspInitCallback = HAL_PCD_MspInit;
-        break;
-
-      case HAL_PCD_MSPDEINIT_CB_ID :
-        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hpcd->State == HAL_PCD_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_PCD_MSPINIT_CB_ID :
-        hpcd->MspInitCallback = HAL_PCD_MspInit;
-        break;
-
-      case HAL_PCD_MSPDEINIT_CB_ID :
-        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-  return status;
-}
-
-/**
-  * @brief  Register USB PCD Data OUT Stage Callback
-  *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
-                                                       pPCD_DataOutStageCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->DataOutStageCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister the USB PCD Data OUT Stage Callback
-  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Register USB PCD Data IN Stage Callback
-  *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @param  pCallback pointer to the USB PCD Data IN Stage Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
-                                                      pPCD_DataInStageCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->DataInStageCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister the USB PCD Data IN Stage Callback
-  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Register USB PCD Iso OUT incomplete Callback
-  *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
-                                                       pPCD_IsoOutIncpltCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->ISOOUTIncompleteCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister the USB PCD Iso OUT incomplete Callback
-  *         USB PCD Iso OUT incomplete Callback is redirected
-  *         to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Register USB PCD Iso IN incomplete Callback
-  *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
-                                                      pPCD_IsoInIncpltCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->ISOINIncompleteCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister the USB PCD Iso IN incomplete Callback
-  *         USB PCD Iso IN incomplete Callback is redirected
-  *         to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Register USB PCD BCD Callback
-  *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
-  * @param  hpcd PCD handle
-  * @param  pCallback pointer to the USB PCD BCD Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->BCDCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister the USB PCD BCD Callback
-  *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Register USB PCD LPM Callback
-  *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
-  * @param  hpcd PCD handle
-  * @param  pCallback pointer to the USB PCD LPM Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->LPMCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister the USB PCD LPM Callback
-  *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
-  *  @brief   Data transfers functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the PCD data
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the USB device
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd);
-  __HAL_PCD_ENABLE(hpcd);
-  (void)USB_DevConnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the USB device.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd);
-  __HAL_PCD_DISABLE(hpcd);
-  (void)USB_DevDisconnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  This function handles PCD interrupt request.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
-{
-  uint16_t wIstr = hpcd->Instance->ISTR;
- 
-  if (wIstr & USB_ISTR_CTR)
-  {
-    /* servicing of the endpoint correct transfer interrupt */
-    /* clear of the CTR flag into the sub */
-    (void)PCD_EP_ISR_Handler(hpcd);
-  }
-
-  if (wIstr & USB_ISTR_RESET)
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-    hpcd->ResetCallback(hpcd);
-#else
-    HAL_PCD_ResetCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-    (void)HAL_PCD_SetAddress(hpcd, 0U);
-  }
-
-  if (wIstr & USB_ISTR_PMAOVR)
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
-  }
-
-  if (wIstr & USB_ISTR_ERR)
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
-  }
-
-  if (wIstr & USB_ISTR_WKUP)
-  {
-    hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
-    hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
-
-    if (hpcd->LPM_State == LPM_L1)
-    {
-      hpcd->LPM_State = LPM_L0;
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
-#else
-      HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-    }
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-    hpcd->ResumeCallback(hpcd);
-#else
-    HAL_PCD_ResumeCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
-  }
-
-  if (wIstr & USB_ISTR_SUSP)
-  {
-    /* Force low-power mode in the macrocell */
-    hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
-
-    /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
-
-    hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-    hpcd->SuspendCallback(hpcd);
-#else
-    HAL_PCD_SuspendCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-  }
-
-  /* Handle LPM Interrupt */
-  if (wIstr & USB_ISTR_L1REQ)
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
-    if (hpcd->LPM_State == LPM_L0)
-    {
-      /* Force suspend and low-power mode before going to L1 state*/
-      hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
-      hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
-
-      hpcd->LPM_State = LPM_L1;
-      hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
-#else
-      HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-    }
-    else
-    {
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->SuspendCallback(hpcd);
-#else
-      HAL_PCD_SuspendCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-    }
-  }
-
-  if (wIstr & USB_ISTR_SOF)
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-    hpcd->SOFCallback(hpcd);
-#else
-    HAL_PCD_SOFCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-  }
-
-  if (wIstr & USB_ISTR_ESOF)
-  {
-    /* clear ESOF flag in ISTR */
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
-  }
-}
-
-
-/**
-  * @brief  Data OUT stage callback.
-  * @param  hpcd PCD handle
-  * @param  epnum endpoint number
-  * @retval None
-  */
-__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_DataOutStageCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Data IN stage callback
-  * @param  hpcd PCD handle
-  * @param  epnum endpoint number
-  * @retval None
-  */
-__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_DataInStageCallback could be implemented in the user file
-   */
-}
-/**
-  * @brief  Setup stage callback
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_SetupStageCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  USB Start Of Frame callback.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_SOFCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  USB Reset callback.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ResetCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Suspend event callback.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_SuspendCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Resume event callback.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ResumeCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Incomplete ISO OUT callback.
-  * @param  hpcd PCD handle
-  * @param  epnum endpoint number
-  * @retval None
-  */
-__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Incomplete ISO IN callback.
-  * @param  hpcd PCD handle
-  * @param  epnum endpoint number
-  * @retval None
-  */
-__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Connection event callback.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ConnectCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Disconnection event callback.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_DisconnectCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief   management functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the PCD data
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Connect the USB device
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd);
-  (void)USB_DevConnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disconnect the USB device.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd);
-  (void)USB_DevDisconnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the USB Device address.
-  * @param  hpcd PCD handle
-  * @param  address new device address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
-{
-  __HAL_LOCK(hpcd);
-  hpcd->USB_Address = address;
-  (void)USB_SetDevAddress(hpcd->Instance, address);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-/**
-  * @brief  Open and configure an endpoint.
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @param  ep_mps endpoint max packet size
-  * @param  ep_type endpoint type
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
-                                  uint16_t ep_mps, uint8_t ep_type)
-{
-  HAL_StatusTypeDef  ret = HAL_OK;
-  PCD_EPTypeDef *ep;
-
-  if ((ep_addr & 0x80U) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 1U;
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 0U;
-  }
-
-  ep->num = ep_addr & EP_ADDR_MSK;
-  ep->maxpacket = ep_mps;
-  ep->type = ep_type;
-
-  if (ep->is_in != 0U)
-  {
-    /* Assign a Tx FIFO */
-    ep->tx_fifo_num = ep->num;
-  }
-  /* Set initial data PID. */
-  if (ep_type == EP_TYPE_BULK)
-  {
-    ep->data_pid_start = 0U;
-  }
-
-  __HAL_LOCK(hpcd);
-  (void)USB_ActivateEndpoint(hpcd->Instance, ep);
-  __HAL_UNLOCK(hpcd);
-
-  return ret;
-}
-
-/**
-  * @brief  Deactivate an endpoint.
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  PCD_EPTypeDef *ep;
-
-  if ((ep_addr & 0x80U) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 1U;
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 0U;
-  }
-  ep->num   = ep_addr & EP_ADDR_MSK;
-
-  __HAL_LOCK(hpcd);
-  (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
-  __HAL_UNLOCK(hpcd);
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Receive an amount of data.
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @param  pBuf pointer to the reception buffer
-  * @param  len amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-  PCD_EPTypeDef *ep;
-
-  ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
-
-  /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;
-  ep->xfer_len = len;
-  ep->xfer_count = 0U;
-  ep->is_in = 0U;
-  ep->num = ep_addr & EP_ADDR_MSK;
-
-  if ((ep_addr & EP_ADDR_MSK) == 0U)
-  {
-    (void)USB_EP0StartXfer(hpcd->Instance, ep);
-  }
-  else
-  {
-    (void)USB_EPStartXfer(hpcd->Instance, ep);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get Received Data Size
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @retval Data Size
-  */
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
-}
-/**
-  * @brief  Send an amount of data
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @param  pBuf pointer to the transmission buffer
-  * @param  len amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-  PCD_EPTypeDef *ep;
-
-  ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-
-  /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;
-  ep->xfer_len = len;
-  ep->xfer_fill_db = 1U;
-  ep->xfer_len_db = len;
-  ep->xfer_count = 0U;
-  ep->is_in = 1U;
-  ep->num = ep_addr & EP_ADDR_MSK;
-
-  if ((ep_addr & EP_ADDR_MSK) == 0U)
-  {
-    (void)USB_EP0StartXfer(hpcd->Instance, ep);
-  }
-  else
-  {
-    (void)USB_EPStartXfer(hpcd->Instance, ep);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set a STALL condition over an endpoint
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  PCD_EPTypeDef *ep;
-
-  if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
-  {
-    return HAL_ERROR;
-  }
-
-  if ((0x80U & ep_addr) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 1U;
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-    ep->is_in = 0U;
-  }
-
-  ep->is_stall = 1U;
-  ep->num = ep_addr & EP_ADDR_MSK;
-
-  __HAL_LOCK(hpcd);
-
-  (void)USB_EPSetStall(hpcd->Instance, ep);
-
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Clear a STALL condition over in an endpoint
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  PCD_EPTypeDef *ep;
-
-  if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
-  {
-    return HAL_ERROR;
-  }
-
-  if ((0x80U & ep_addr) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 1U;
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 0U;
-  }
-
-  ep->is_stall = 0U;
-  ep->num = ep_addr & EP_ADDR_MSK;
-
-  __HAL_LOCK(hpcd);
-  (void)USB_EPClearStall(hpcd->Instance, ep);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Flush an endpoint
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(ep_addr);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Activate remote wakeup signalling
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
-  return (USB_ActivateRemoteWakeup(hpcd->Instance));
-}
-
-/**
-  * @brief  De-activate remote wakeup signalling.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
-  return (USB_DeActivateRemoteWakeup(hpcd->Instance));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
-  *  @brief   Peripheral State functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the PCD handle state.
-  * @param  hpcd PCD handle
-  * @retval HAL state
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
-{
-  return hpcd->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup PCD_Private_Functions
-  * @{
-  */
-
-
-/**
-  * @brief  This function handles PCD Endpoint interrupt request.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
-{
-  PCD_EPTypeDef *ep;
-  uint16_t count, wIstr, wEPVal, TxByteNbre;
-  uint8_t epindex;
-
-  /* stay in loop while pending interrupts */
-  while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
-  {
-    wIstr = hpcd->Instance->ISTR;
-
-    /* extract highest priority endpoint number */
-    epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
-
-    if (epindex == 0U)
-    {
-      /* Decode and service control endpoint interrupt */
-
-      /* DIR bit = origin of the interrupt */
-      if ((wIstr & USB_ISTR_DIR) == 0U)
-      {
-        /* DIR = 0 */
-
-        /* DIR = 0 => IN  int */
-        /* DIR = 0 implies that (EP_CTR_TX = 1) always */
-        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-        ep = &hpcd->IN_ep[0];
-
-        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
-        ep->xfer_buff += ep->xfer_count;
-
-        /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-        hpcd->DataInStageCallback(hpcd, 0U);
-#else
-        HAL_PCD_DataInStageCallback(hpcd, 0U);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-        if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
-        {
-          hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
-          hpcd->USB_Address = 0U;
-        }
-      }
-      else
-      {
-        /* DIR = 1 */
-
-        /* DIR = 1 & CTR_RX => SETUP or OUT int */
-        /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
-        ep = &hpcd->OUT_ep[0];
-        wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
-
-        if ((wEPVal & USB_EP_SETUP) != 0U)
-        {
-          /* Get SETUP Packet */
-          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
-          USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
-                      ep->pmaadress, (uint16_t)ep->xfer_count);
-
-          /* SETUP bit kept frozen while CTR_RX = 1 */
-          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-
-          /* Process SETUP Packet*/
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-          hpcd->SetupStageCallback(hpcd);
-#else
-          HAL_PCD_SetupStageCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-        }
-        else if ((wEPVal & USB_EP_CTR_RX) != 0U)
-        {
-          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-
-          /* Get Control Data OUT Packet */
-          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
-          if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
-          {
-            USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
-                        ep->pmaadress, (uint16_t)ep->xfer_count);
-
-            ep->xfer_buff += ep->xfer_count;
-
-            /* Process Control Data OUT Packet */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-            hpcd->DataOutStageCallback(hpcd, 0U);
-#else
-            HAL_PCD_DataOutStageCallback(hpcd, 0U);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-          }
-
-          if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U)
-          {
-            PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
-            PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
-          }
-        }
-      }
-    }
-    else
-    {
-      /* Decode and service non control endpoints interrupt */
-      /* process related endpoint register */
-      wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
-
-      if ((wEPVal & USB_EP_CTR_RX) != 0U)
-      {
-        /* clear int flag */
-        PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
-        ep = &hpcd->OUT_ep[epindex];
-
-        /* OUT Single Buffering */
-        if (ep->doublebuffer == 0U)
-        {
-          count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
-          if (count != 0U)
-          {
-            USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
-          }
-        }
-        else
-        {
-          /* manage double buffer bulk out */
-          if (ep->type == EP_TYPE_BULK)
-          {
-            count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
-          }
-          else /* manage double buffer iso out */
-          {
-            /* free EP OUT Buffer */
-            PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
-
-            if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
-            {
-              /* read from endpoint BUF0Addr buffer */
-              count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
-
-              if (count != 0U)
-              {
-                USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
-              }
-            }
-            else
-            {
-              /* read from endpoint BUF1Addr buffer */
-              count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
-
-              if (count != 0U)
-              {
-                USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
-              }
-            }
-          }
-        }
-        /* multi-packet on the NON control OUT endpoint */
-        ep->xfer_count += count;
-        ep->xfer_buff += count;
-
-        if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
-        {
-          /* RX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-          hpcd->DataOutStageCallback(hpcd, ep->num);
-#else
-          HAL_PCD_DataOutStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-        }
-        else
-        {
-          (void) USB_EPStartXfer(hpcd->Instance, ep);
-        }
-      }
-
-      if ((wEPVal & USB_EP_CTR_TX) != 0U)
-      {
-        ep = &hpcd->IN_ep[epindex];
-
-        /* clear int flag */
-        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
-
-        if (ep->type != EP_TYPE_BULK)
-        {
-          ep->xfer_len = 0U;
-
-          if ((wEPVal & USB_EP_DTOG_TX) != 0U)
-          {
-            PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
-          }
-          else
-          {
-            PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
-          }
-
-          /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-          hpcd->DataInStageCallback(hpcd, ep->num);
-#else
-          HAL_PCD_DataInStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-        }
-        else
-        /* Manage Bulk Single Buffer Transaction */
-        if ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U))
-        {
-          /* multi-packet on the NON control IN endpoint */
-          TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
-
-          if (ep->xfer_len > TxByteNbre)
-          {
-            ep->xfer_len -= TxByteNbre;
-          }
-          else
-          {
-            ep->xfer_len = 0U;
-          }
-
-          /* Zero Length Packet? */
-          if (ep->xfer_len == 0U)
-          {
-            /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-            hpcd->DataInStageCallback(hpcd, ep->num);
-#else
-            HAL_PCD_DataInStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-          }
-          else
-          {
-            /* Transfer is not yet Done */
-            ep->xfer_buff += TxByteNbre;
-            ep->xfer_count += TxByteNbre;
-            (void)USB_EPStartXfer(hpcd->Instance, ep);
-          }
-        }
-        /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
-        else
-        {
-          (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
-        }
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Manage double buffer bulk out transaction from ISR
-  * @param  hpcd PCD handle
-  * @param  ep current endpoint handle
-  * @param  wEPVal Last snapshot of EPRx register value taken in ISR
-  * @retval HAL status
-  */
-static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
-                                      PCD_EPTypeDef *ep, uint16_t wEPVal)
-{
-  uint16_t count;
-
-  /* Manage Buffer0 OUT */
-  if ((wEPVal & USB_EP_DTOG_RX) != 0U)
-  {
-    /* Get count of received Data on buffer0 */
-    count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
-
-    if (ep->xfer_len >= count)
-    {
-      ep->xfer_len -= count;
-    }
-    else
-    {
-      ep->xfer_len = 0U;
-    }
-
-    if (ep->xfer_len == 0U)
-    {
-      /* set NAK to OUT endpoint since double buffer is enabled */
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
-    }
-
-    /* Check if Buffer1 is in blocked sate which requires to toggle */
-    if ((wEPVal & USB_EP_DTOG_TX) != 0U)
-    {
-      PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
-    }
-
-    if (count != 0U)
-    {
-      USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
-    }
-  }
-  /* Manage Buffer 1 DTOG_RX=0 */
-  else
-  {
-    /* Get count of received data */
-    count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
-
-    if (ep->xfer_len >= count)
-    {
-      ep->xfer_len -= count;
-    }
-    else
-    {
-      ep->xfer_len = 0U;
-    }
-
-    if (ep->xfer_len == 0U)
-    {
-      /* set NAK on the current endpoint */
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
-    }
-
-    /*Need to FreeUser Buffer*/
-    if ((wEPVal & USB_EP_DTOG_TX) == 0U)
-    {
-      PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
-    }
-
-    if (count != 0U)
-    {
-      USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
-    }
-  }
-
-  return count;
-}
-
-
-/**
-  * @brief  Manage double buffer bulk IN transaction from ISR
-  * @param  hpcd PCD handle
-  * @param  ep current endpoint handle
-  * @param  wEPVal Last snapshot of EPRx register value taken in ISR
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
-                                                PCD_EPTypeDef *ep, uint16_t wEPVal)
-{
-  uint32_t len;
-  uint16_t TxByteNbre;
-
-  /* Data Buffer0 ACK received */
-  if ((wEPVal & USB_EP_DTOG_TX) != 0U)
-  {
-    /* multi-packet on the NON control IN endpoint */
-    TxByteNbre = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
-
-    if (ep->xfer_len > TxByteNbre)
-    {
-      ep->xfer_len -= TxByteNbre;
-    }
-    else
-    {
-      ep->xfer_len = 0U;
-    }
-    /* Transfer is completed */
-    if (ep->xfer_len == 0U)
-    {
-      PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
-      PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
-
-      /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->DataInStageCallback(hpcd, ep->num);
-#else
-      HAL_PCD_DataInStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-      if ((wEPVal & USB_EP_DTOG_RX) != 0U)
-      {
-        PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
-      }
-    }
-    else /* Transfer is not yet Done */
-    {
-      /* need to Free USB Buff */
-      if ((wEPVal & USB_EP_DTOG_RX) != 0U)
-      {
-        PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
-      }
-
-      /* Still there is data to Fill in the next Buffer */
-      if (ep->xfer_fill_db == 1U)
-      {
-        ep->xfer_buff += TxByteNbre;
-        ep->xfer_count += TxByteNbre;
-
-        /* Calculate the len of the new buffer to fill */
-        if (ep->xfer_len_db >= ep->maxpacket)
-        {
-          len = ep->maxpacket;
-          ep->xfer_len_db -= len;
-        }
-        else if (ep->xfer_len_db == 0U)
-        {
-          len = TxByteNbre;
-          ep->xfer_fill_db = 0U;
-        }
-        else
-        {
-          ep->xfer_fill_db = 0U;
-          len = ep->xfer_len_db;
-          ep->xfer_len_db = 0U;
-        }
-
-        /* Write remaining Data to Buffer */
-        /* Set the Double buffer counter for pma buffer1 */
-        PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
-
-        /* Copy user buffer to USB PMA */
-        USB_WritePMA(hpcd->Instance, ep->xfer_buff,  ep->pmaaddr0, (uint16_t)len);
-      }
-    }
-  }
-  else /* Data Buffer1 ACK received */
-  {
-    /* multi-packet on the NON control IN endpoint */
-    TxByteNbre = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
-
-    if (ep->xfer_len >= TxByteNbre)
-    {
-      ep->xfer_len -= TxByteNbre;
-    }
-    else
-    {
-      ep->xfer_len = 0U;
-    }
-
-    /* Transfer is completed */
-    if (ep->xfer_len == 0U)
-    {
-      PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
-      PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
-
-      /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->DataInStageCallback(hpcd, ep->num);
-#else
-      HAL_PCD_DataInStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-      /* need to Free USB Buff */
-      if ((wEPVal & USB_EP_DTOG_RX) == 0U)
-      {
-        PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
-      }
-    }
-    else /* Transfer is not yet Done */
-    {
-      /* need to Free USB Buff */
-      if ((wEPVal & USB_EP_DTOG_RX) == 0U)
-      {
-        PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
-      }
-
-      /* Still there is data to Fill in the next Buffer */
-      if (ep->xfer_fill_db == 1U)
-      {
-        ep->xfer_buff += TxByteNbre;
-        ep->xfer_count += TxByteNbre;
-
-        /* Calculate the len of the new buffer to fill */
-        if (ep->xfer_len_db >= ep->maxpacket)
-        {
-          len = ep->maxpacket;
-          ep->xfer_len_db -= len;
-        }
-        else if (ep->xfer_len_db == 0U)
-        {
-          len = TxByteNbre;
-          ep->xfer_fill_db = 0U;
-        }
-        else
-        {
-          len = ep->xfer_len_db;
-          ep->xfer_len_db = 0U;
-          ep->xfer_fill_db = 0;
-        }
-
-        /* Set the Double buffer counter for pmabuffer1 */
-        PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
-
-        /* Copy the user buffer to USB PMA */
-        USB_WritePMA(hpcd->Instance, ep->xfer_buff,  ep->pmaaddr1, (uint16_t)len);
-      }
-    }
-  }
-
-  /*enable endpoint IN*/
-  PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
-
-  return HAL_OK;
-}
-
-
-
-/**
-  * @}
-  */
-#endif /* defined (USB) */
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c
deleted file mode 100644
index 94e0401364..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_pcd_ex.c
-  * @author  MCD Application Team
-  * @brief   PCD Extended HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the USB Peripheral Controller:
-  *           + Extended features functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PCDEx PCDEx
-  * @brief PCD Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-#if defined (USB)
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
-  * @{
-  */
-
-/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
-  * @brief    PCDEx control functions
-  *
-@verbatim
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Update FIFO configuration
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure PMA for EP
-  * @param  hpcd  Device instance
-  * @param  ep_addr endpoint address
-  * @param  ep_kind endpoint Kind
-  *                  USB_SNG_BUF: Single Buffer used
-  *                  USB_DBL_BUF: Double Buffer used
-  * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
-  *                   this parameter is 16-bit value providing the address
-  *                   in PMA allocated to endpoint.
-  *                   In case of double buffer endpoint this parameter
-  *                   is a 32-bit value providing the endpoint buffer 0 address
-  *                   in the LSB part of 32-bit value and endpoint buffer 1 address
-  *                   in the MSB part of 32-bit value.
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
-                                       uint16_t ep_kind, uint32_t pmaadress)
-{
-  PCD_EPTypeDef *ep;
-
-  /* initialize ep structure*/
-  if ((0x80U & ep_addr) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-  }
-
-  /* Here we check if the endpoint is single or double Buffer*/
-  if (ep_kind == PCD_SNG_BUF)
-  {
-    /* Single Buffer */
-    ep->doublebuffer = 0U;
-    /* Configure the PMA */
-    ep->pmaadress = (uint16_t)pmaadress;
-  }
-  else /* USB_DBL_BUF */
-  {
-    /* Double Buffer Endpoint */
-    ep->doublebuffer = 1U;
-    /* Configure the PMA */
-    ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
-    ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Activate BatteryCharging feature.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
-{
-  USB_TypeDef *USBx = hpcd->Instance;
-  hpcd->battery_charging_active = 1U;
-
-  /* Enable BCD feature */
-  USBx->BCDR |= USB_BCDR_BCDEN;
-
-  /* Enable DCD : Data Contact Detect */
-  USBx->BCDR &= ~(USB_BCDR_PDEN);
-  USBx->BCDR &= ~(USB_BCDR_SDEN);
-  USBx->BCDR |= USB_BCDR_DCDEN;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate BatteryCharging feature.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
-{
-  USB_TypeDef *USBx = hpcd->Instance;
-  hpcd->battery_charging_active = 0U;
-
-  /* Disable BCD feature */
-  USBx->BCDR &= ~(USB_BCDR_BCDEN);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle BatteryCharging Process.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
-{
-  USB_TypeDef *USBx = hpcd->Instance;
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Wait Detect flag or a timeout is happen */
-  while ((USBx->BCDR & USB_BCDR_DCDET) == 0U)
-  {
-    /* Check for the Timeout */
-    if ((HAL_GetTick() - tickstart) > 1000U)
-    {
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
-#else
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-      return;
-    }
-  }
-
-  HAL_Delay(200U);
-
-  /* Data Pin Contact ? Check Detect flag */
-  if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
-  {
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-    hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
-#else
-    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-  }
-  /* Primary detection: checks if connected to Standard Downstream Port
-  (without charging capability) */
-  USBx->BCDR &= ~(USB_BCDR_DCDEN);
-  HAL_Delay(50U);
-  USBx->BCDR |= (USB_BCDR_PDEN);
-  HAL_Delay(50U);
-
-  /* If Charger detect ? */
-  if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)
-  {
-    /* Start secondary detection to check connection to Charging Downstream
-    Port or Dedicated Charging Port */
-    USBx->BCDR &= ~(USB_BCDR_PDEN);
-    HAL_Delay(50U);
-    USBx->BCDR |= (USB_BCDR_SDEN);
-    HAL_Delay(50U);
-
-    /* If CDP ? */
-    if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)
-    {
-      /* Dedicated Downstream Port DCP */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
-#else
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-    }
-    else
-    {
-      /* Charging Downstream Port CDP */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
-#else
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-    }
-  }
-  else /* NO */
-  {
-    /* Standard Downstream Port */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-    hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
-#else
-    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-  }
-
-  /* Battery Charging capability discovery finished Start Enumeration */
-  (void)HAL_PCDEx_DeActivateBCD(hpcd);
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-  hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
-#else
-  HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-}
-
-
-/**
-  * @brief  Activate LPM feature.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
-{
-
-  USB_TypeDef *USBx = hpcd->Instance;
-  hpcd->lpm_active = 1U;
-  hpcd->LPM_State = LPM_L0;
-
-  USBx->LPMCSR |= USB_LPMCSR_LMPEN;
-  USBx->LPMCSR |= USB_LPMCSR_LPMACK;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate LPM feature.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
-{
-  USB_TypeDef *USBx = hpcd->Instance;
-
-  hpcd->lpm_active = 0U;
-
-  USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
-  USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
-
-  return HAL_OK;
-}
-
-
-
-/**
-  * @brief  Send LPM message to user layer callback.
-  * @param  hpcd PCD handle
-  * @param  msg LPM message
-  * @retval HAL status
-  */
-__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(msg);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCDEx_LPM_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Send BatteryCharging message to user layer callback.
-  * @param  hpcd PCD handle
-  * @param  msg LPM message
-  * @retval HAL status
-  */
-__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(msg);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCDEx_BCD_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined (USB) */
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c
deleted file mode 100644
index 00bfc3925e..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c
+++ /dev/null
@@ -1,733 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_pwr.c
-  * @author  MCD Application Team
-  * @brief   PWR HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Power Controller (PWR) peripheral:
-  *           + Initialization/de-initialization functions
-  *           + Peripheral Control functions 
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-#ifdef HAL_PWR_MODULE_ENABLED
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWR
-  * @{
-  */
-
-/** @addtogroup PWR_Private
-  * @{
-  */
-  
-#if defined(PWR_PVD_SUPPORT)
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
-  * @{
-  */ 
-#define PVD_MODE_IT               (0x00010000U)
-#define PVD_MODE_EVT              (0x00020000U)
-#define PVD_RISING_EDGE           (0x00000001U)
-#define PVD_FALLING_EDGE          (0x00000002U)
-/**
-  * @}
-  */
-#endif
-
-/**
-  * @}
-  */  
-  
-
-/** @addtogroup PWR_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup PWR_Exported_Functions_Group1
-  * @brief      Initialization and de-initialization functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
-  * @retval None
-  */
-void HAL_PWR_DeInit(void)
-{
-  __HAL_RCC_PWR_FORCE_RESET();
-  __HAL_RCC_PWR_RELEASE_RESET();
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup PWR_Exported_Functions_Group2
-  * @brief      Low Power modes configuration functions
-  *
-@verbatim
-
- ===============================================================================
-                 ##### Peripheral Control functions #####
- ===============================================================================
-     
-    *** Backup domain ***
-    =========================
-    [..]
-      After reset, the backup domain (RTC registers, RTC backup data
-      registers) is protected against possible unwanted
-      write accesses.
-      To enable access to the RTC Domain and RTC registers, proceed as follows:
-        (+) Enable the Power Controller (PWR) APB1 interface clock using the
-            __HAL_RCC_PWR_CLK_ENABLE() macro.
-        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
-
-    *** PVD configuration ***
-    =========================
-    [..]
-      (+) The PVD is used to monitor the VDD power supply by comparing it to a
-          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
-      (+) The PVD can use an external input analog voltage (PVD_IN) which is compared 
-      internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode 
-      when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
-
-      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
-          than the PVD threshold. This event is internally connected to the EXTI
-          line16 and can generate an interrupt if enabled. This is done through
-          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
-      (+) The PVD is stopped in Standby mode.
-      (+) The PVD feature is not supported on L0 Value line.
-
-    *** WakeUp pin configuration ***
-    ================================
-    [..]
-      (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
-          forced in input pull-down configuration and is active on rising edges.
-      (+) There are two WakeUp pins:
-          WakeUp Pin 1 on PA.00.
-          WakeUp Pin 2 on PC.13.
-          WakeUp Pin 3 on PE.06 .
-          
-
-    [..]
-    *** Main and Backup Regulators configuration ***
-    ================================================
-
-      (+) The main internal regulator can be configured to have a tradeoff between
-          performance and power consumption when the device does not operate at
-          the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG()
-          macro which configures the two VOS bits in PWR_CR register:
-        (++) PWR_REGULATOR_VOLTAGE_SCALE1 (VOS bits = 01), the regulator voltage output Scale 1 mode selected and
-             the System frequency can go up to 32 MHz.
-        (++) PWR_REGULATOR_VOLTAGE_SCALE2 (VOS bits = 10), the regulator voltage output Scale 2 mode selected and
-             the System frequency can go up to 16 MHz.
-        (++) PWR_REGULATOR_VOLTAGE_SCALE3 (VOS bits = 11), the regulator voltage output Scale 3 mode selected and
-             the System frequency can go up to 4.2 MHz.
-              
-        Refer to the datasheets for more details.
-
-    *** Low Power modes configuration ***
-    =====================================
-     [..]
-      The device features 5 low-power modes:
-      (+) Low power run mode: regulator in low power mode, limited clock frequency, 
-        limited number of peripherals running.
-      (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running.
-      (+) Low power sleep mode: Cortex-M0+ core stopped, limited clock frequency, 
-         limited number of peripherals running, regulator in low power mode.
-      (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode.
-      (+) Standby mode: VCORE domain powered off
-  
-   *** Low power run mode ***
-   =========================
-    [..]
-       To further reduce the consumption when the system is in Run mode, the regulator can be
-        configured in low power mode. In this mode, the system frequency should not exceed
-        MSI frequency range1.
-        In Low power run mode, all I/O pins keep the same state as in Run mode.
-  
-      (+) Entry:
-        (++) VCORE in range2
-        (++) Decrease the system frequency not to exceed the frequency of MSI frequency range1.
-        (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode()
-             function.
-      (+) Exit:
-        (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode()
-              function.
-        (++) Increase the system frequency if needed.
-  
-   *** Sleep mode ***
-   ==================
-    [..]
-      (+) Entry:
-          The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
-              functions with
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-     
-      (+) Exit:
-        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
-              controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction was used to enter sleep mode,
-              the MCU exits Sleep mode as soon as an event occurs. 
-
-   *** Low power sleep mode ***
-   ============================
-    [..]
-      (+) Entry:
-          The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx)
-              functions with
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-       (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register. 
-             This reduces power consumption but increases the wake-up time.
-         
-      (+) Exit:
-        (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt
-              acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device
-              from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode,
-              the MCU exits Sleep mode as soon as an event occurs. 
-                
-   *** Stop mode ***
-   =================
-    [..]
-      The Stop mode is based on the Cortex-M0+ deepsleep mode combined with peripheral
-      clock gating. The voltage regulator can be configured either in normal or low-power mode.
-      In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and
-      the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
-      To get the lowest consumption in Stop mode, the internal Flash memory also enters low
-      power mode. When the Flash memory is in power-down mode, an additional startup delay is
-      incurred when waking up from Stop mode.
-      To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
-      sensor can be switched off before entering Stop mode. They can be switched on again by
-      software after exiting Stop mode using the ULP bit in the PWR_CR register.
-      In Stop mode, all I/O pins keep the same state as in Run mode.
-
-      (+) Entry:
-           The Stop mode is entered using the HAL_PWR_EnterSTOPMode
-             function with:
-          (++) Main regulator ON.
-          (++) Low Power regulator ON.
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-      (+) Exit:
-        (++) By issuing an interrupt or a wakeup event, the MSI or HSI16 RC
-             oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR
-             register
-
-   *** Standby mode ***
-   ====================
-     [..]
-      The Standby mode allows to achieve the lowest power consumption. It is based on the
-      Cortex-M0+ deepsleep mode, with the voltage regulator disabled. The VCORE domain is
-      consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are
-      also switched off. SRAM and register contents are lost except for the RTC registers, RTC
-      backup registers and Standby circuitry.
-      
-      To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
-       sensor can be switched off before entering the Standby mode. They can be switched 
-       on again by software after exiting the Standby mode.
-       function.
-      
-      (+) Entry:
-        (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
-      (+) Exit:
-        (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
-             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
-   *** Auto-wakeup (AWU) from low-power mode ***
-   =============================================
-    [..]
-      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
-      Wakeup event, a tamper event, a time-stamp event, or a comparator event, 
-      without depending on an external interrupt (Auto-wakeup mode).
-
-    (+) RTC auto-wakeup (AWU) from the Stop mode
-        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
-             (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt 
-                   or Event modes) using the EXTI_Init() function.
-             (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
-             (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
-                   and RTC_AlarmCmd() functions.
-        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
-             is necessary to:
-             (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt 
-                   or Event modes) using the EXTI_Init() function.
-             (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
-                   function.
-             (+++) Configure the RTC to detect the tamper or time stamp event using the
-                   RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
-                   functions.
-        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
-             (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt 
-                   or Event modes) using the EXTI_Init() function.
-             (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function.
-             (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
-                   RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
-
-    (+) RTC auto-wakeup (AWU) from the Standby mode
-        (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
-             (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
-             (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
-                   and RTC_AlarmCmd() functions.
-        (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it 
-             is necessary to:
-             (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
-                   function.
-             (+++) Configure the RTC to detect the tamper or time stamp event using the
-                   RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
-                   functions.
-        (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
-             (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
-             (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
-                   RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
-
-    (+) Comparator auto-wakeup (AWU) from the Stop mode
-        (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
-             event, it is necessary to:
-             (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 
-                   to be sensitive to to the selected edges (falling, rising or falling 
-                   and rising) (Interrupt or Event modes) using the EXTI_Init() function.
-             (+++) Configure the comparator to generate the event.      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Enables access to the backup domain (RTC registers, RTC
-  *         backup data registers ).
-  * @note   If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
-  *         Backup Domain Access should be kept enabled.
-  * @retval None
-  */
-void HAL_PWR_EnableBkUpAccess(void)
-{
-  /* Enable access to RTC and backup registers */
-  SET_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
-  * @brief  Disables access to the backup domain 
-  * @note   Applies to RTC registers, RTC backup data registers.
-  * @note   If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
-  *         Backup Domain Access should be kept enabled.
-  * @retval None
-  */
-void HAL_PWR_DisableBkUpAccess(void)
-{
-  /* Disable access to RTC and backup registers */
-  CLEAR_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-#if defined(PWR_PVD_SUPPORT)
-/**
-  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
-  * @param  sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
-  *         information for the PVD.
-  * @note   Refer to the electrical characteristics of your device datasheet for
-  *         more details about the voltage threshold corresponding to each
-  *         detection level.
-  * @retval None
-  */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
-  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-
-  /* Set PLS[7:5] bits according to PVDLevel value */
-  MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
-  
-  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
-  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
-  __HAL_PWR_PVD_EXTI_DISABLE_IT();
-  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 
-  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
-
-  /* Configure interrupt mode */
-  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_IT();
-  }
-  
-  /* Configure event mode */
-  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
-  }
-  
-  /* Configure the edge */
-  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
-  }
-  
-  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
-  }
-}
-
-/**
-  * @brief Enables the Power Voltage Detector(PVD).
-  * @retval None
-  */
-void HAL_PWR_EnablePVD(void)
-{
-  /* Enable the power voltage detector */
-  SET_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
-  * @brief Disables the Power Voltage Detector(PVD).
-  * @retval None
-  */
-void HAL_PWR_DisablePVD(void)
-{
-  /* Disable the power voltage detector */
-  CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
-}
-#endif /* PWR_PVD_SUPPORT */
-
-/**
-  * @brief Enables the WakeUp PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
-  *         This parameter can be one of the following values:
-  *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2
-  *           @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only.
-  * @retval None
-  */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
-{
-  /* Check the parameter */
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-  /* Enable the EWUPx pin */
-  SET_BIT(PWR->CSR, WakeUpPinx);
-}
-
-/**
-  * @brief Disables the WakeUp PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
-  *         This parameter can be one of the following values:
-  *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2  
-  *           @arg PWR_WAKEUP_PIN3  for stm32l07xxx and stm32l08xxx devices only.
-  * @retval None
-  */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
-{
-  /* Check the parameter */
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-  /* Disable the EWUPx pin */
-  CLEAR_BIT(PWR->CSR, WakeUpPinx);
-}
-
-/**
-  * @brief Enters Sleep mode.
-  * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
-  * @param Regulator: Specifies the regulator state in SLEEP mode.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
-  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
-  * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
-  *           When WFI entry is used, tick interrupt have to be disabled if not desired as 
-  *           the interrupt wake up source.
-  *           This parameter can be one of the following values:
-  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
-{
-   uint32_t tmpreg = 0U;
-   uint32_t ulpbit, vrefinbit;
-
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
-  /* It is forbidden to configure both EN_VREFINT=1 and ULP=1 if the device is
-     in Stop mode or in Sleep/Low-power sleep mode */
-  ulpbit = READ_BIT(PWR->CR, PWR_CR_ULP);
-  vrefinbit = READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_EN_VREFINT);
-  if((ulpbit != 0) && (vrefinbit != 0))
-  {
-    CLEAR_BIT(PWR->CR, PWR_CR_ULP);
-  }
-
-  /* Select the regulator state in Sleep mode ---------------------------------*/
-  tmpreg = PWR->CR;
-
-  /* Clear PDDS and LPDS bits */
-  CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));
-
- /* Set LPSDSR bit according to PWR_Regulator value */
-  SET_BIT(tmpreg, Regulator);
-
-  /* Store the new value */
-  PWR->CR = tmpreg;
-  
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
-
-  /* Select SLEEP mode entry -------------------------------------------------*/
-  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-
-  if((ulpbit != 0) && (vrefinbit != 0))
-  {
-    SET_BIT(PWR->CR, PWR_CR_ULP);
-  }
-
-  /* Additional NOP to ensure all pending instructions are flushed before entering low power mode */
-  __NOP();
-
-}
-
-/**
-  * @brief Enters Stop mode. 
-  * @note In Stop mode, all I/O pins keep the same state as in Run mode.
-  * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
-  *        MSI or HSI16 RCoscillator is selected as system clock depending 
-  *        the bit STOPWUCK in the RCC_CFGR register.
-  * @note When the voltage regulator operates in low power mode, an additional
-  *         startup delay is incurred when waking up from Stop mode. 
-  *         By keeping the internal regulator ON during Stop mode, the consumption
-  *         is higher although the startup time is reduced.
-  * @note Before entering in this function, it is important to ensure that the WUF
-  *       wakeup flag is cleared. To perform this action, it is possible to call the
-  *       following macro : __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU)
-  *
-  * @param Regulator: Specifies the regulator state in Stop mode.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
-  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
-  * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
-  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction   
-  * @retval None
-  */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
-  uint32_t tmpreg = 0U;
-  uint32_t ulpbit, vrefinbit;
-
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
-  /* It is forbidden to configure both EN_VREFINT=1 and ULP=1 if the device is
-     in Stop mode or in Sleep/Low-power sleep mode */
-  ulpbit = READ_BIT(PWR->CR, PWR_CR_ULP);
-  vrefinbit = READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_EN_VREFINT);
-  if((ulpbit != 0) && (vrefinbit != 0))
-  {
-    CLEAR_BIT(PWR->CR, PWR_CR_ULP);
-  }
-
-  /* Select the regulator state in Stop mode ---------------------------------*/
-  tmpreg = PWR->CR;
-  
-  /* Clear PDDS and LPDS bits */
-  CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));
-
- /* Set LPSDSR bit according to PWR_Regulator value */
-  SET_BIT(tmpreg, Regulator);
-
-  /* Store the new value */
-  PWR->CR = tmpreg;
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
-
-  /* Select Stop mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_STOPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
- 
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
-
-  if((ulpbit != 0) && (vrefinbit != 0))
-  {
-    SET_BIT(PWR->CR, PWR_CR_ULP);
-  }
-}
-
-/**
-  * @brief Enters Standby mode.
-  * @note In Standby mode, all I/O pins are high impedance except for:
-  *          - Reset pad (still available) 
-  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
-  *            Alarm out, or RTC clock calibration out.
-  *          - RTC_AF2 pin (PC13) if configured for tamper.
-  *          - WKUP pin 1 (PA00) if enabled.
-  *          - WKUP pin 2 (PC13) if enabled.
-  *          - WKUP pin 3 (PE06) if enabled, for stm32l07xxx and stm32l08xxx devices only.
-  *          - WKUP pin 3 (PA02) if enabled, for stm32l031xx devices only.
-  * @retval None
-  */
-void HAL_PWR_EnterSTANDBYMode(void)
-{
-  /* Select Standby mode */
-  SET_BIT(PWR->CR, PWR_CR_PDDS);
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
-
-  /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
-  __force_stores();
-#endif
-  /* Request Wait For Interrupt */
-  __WFI();
-}
-
-/**
-  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 
-  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
-  *       re-enters SLEEP mode when an interruption handling is over.
-  *       Setting this bit is useful when the processor is expected to run only on
-  *       interruptions handling.         
-  * @retval None
-  */
-void HAL_PWR_EnableSleepOnExit(void)
-{
-  /* Set SLEEPONEXIT bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-/**
-  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
-  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
-  *       re-enters SLEEP mode when an interruption handling is over.          
-  * @retval None
-  */
-void HAL_PWR_DisableSleepOnExit(void)
-{
-  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-/**
-  * @brief Enables CORTEX M0+ SEVONPEND bit. 
-  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 
-  *       WFE to wake up when an interrupt moves from inactive to pended.
-  * @retval None
-  */
-void HAL_PWR_EnableSEVOnPend(void)
-{
-  /* Set SEVONPEND bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-
-/**
-  * @brief Disables CORTEX M0+ SEVONPEND bit. 
-  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 
-  *       WFE to wake up when an interrupt moves from inactive to pended.         
-  * @retval None
-  */
-void HAL_PWR_DisableSEVOnPend(void)
-{
-  /* Clear SEVONPEND bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-#if defined(PWR_PVD_SUPPORT)
-/**
-  * @brief This function handles the PWR PVD interrupt request.
-  * @note This API should be called under the PVD_IRQHandler().
-  * @retval None
-  */
-void HAL_PWR_PVD_IRQHandler(void)
-{
-  /* Check PWR exti flag */
-  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
-  {
-    /* PWR PVD interrupt user callback */
-    HAL_PWR_PVDCallback();
-
-    /* Clear PWR Exti pending bit */
-    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
-  }
-}
-
-/**
-  * @brief  PWR PVD interrupt callback
-  * @retval None
-  */
-__weak void HAL_PWR_PVDCallback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PWR_PVDCallback could be implemented in the user file
-   */ 
-}
-#endif /* PWR_PVD_SUPPORT */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c
deleted file mode 100644
index 311e59eb58..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_pwr_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended PWR HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Power Controller (PWR) peripheral:
-  *           + Extended Initialization and de-initialization functions
-  *           + Extended Peripheral Control functions
-  *         
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-#ifdef HAL_PWR_MODULE_ENABLED
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWREx 
-  * @{
-  */
-
-/** @addtogroup PWREx_Private
-  * @{
-  */
-
-/** @defgroup PWR_Extended_TimeOut_Value PWREx Flag Setting Time Out Value
-  * @{
-  */ 
-#define PWR_FLAG_SETTING_DELAY_US 50U
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup PWREx_Exported_Functions
-  * @brief      Low Power modes configuration functions 
-  *
-@verbatim
-
- ===============================================================================
-                 ##### Peripheral extended features functions #####
- ===============================================================================
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Return Voltage Scaling Range.   
-  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE3)
-  */  
-uint32_t HAL_PWREx_GetVoltageRange(void)
-{
-  return  (PWR->CR & PWR_CR_VOS);
-}
-
-
-/**
-  * @brief  Enables the Fast WakeUp from Ultra Low Power mode.
-  * @note This bit works in conjunction with ULP bit. 
-  *        Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when 
-  *        exiting from low power mode.
-  * @retval None
-  */
-void HAL_PWREx_EnableFastWakeUp(void)
-{
-  /* Enable the fast wake up */
-  SET_BIT(PWR->CR, PWR_CR_FWU);
-}
-
-/**
-  * @brief  Disables the Fast WakeUp from Ultra Low Power mode.
-  * @retval None
-  */
-void HAL_PWREx_DisableFastWakeUp(void)
-{
-  /* Disable the fast wake up */
-  CLEAR_BIT(PWR->CR, PWR_CR_FWU);
-}
-
-/**
-  * @brief  Enables the Ultra Low Power mode
-  * @retval None
-  */
-void HAL_PWREx_EnableUltraLowPower(void)
-{
-  /* Enable the Ultra Low Power mode */
-  SET_BIT(PWR->CR, PWR_CR_ULP);
-}
-
-/**
-  * @brief  Disables the Ultra Low Power mode
-  * @retval None
-  */
-void HAL_PWREx_DisableUltraLowPower(void)
-{
-  /* Disable the Ultra Low Power mode */
-  CLEAR_BIT(PWR->CR, PWR_CR_ULP);
-}
-
-/**
-  * @brief  Enable the Low Power Run mode.
-  * @note   Low power run mode can only be entered when VCORE is in range 2.
-  *         In addition, the dynamic voltage scaling must not be used when Low
-  *         power run mode is selected. Only Stop and Sleep modes with regulator
-  *         configured in Low power mode is allowed when Low power run mode is 
-  *         selected.
-  * @note   The frequency of the system clock must be decreased to not exceed the
-  *         frequency of RCC_MSIRANGE_1.
-  * @note   In Low power run mode, all I/O pins keep the same state as in Run mode.
-  * @retval None
-  */
-void HAL_PWREx_EnableLowPowerRunMode(void)
-{
-  /* Enters the Low Power Run mode */
-  SET_BIT(PWR->CR, PWR_CR_LPSDSR);
-  SET_BIT(PWR->CR, PWR_CR_LPRUN);
-}
-
-/**
-  * @brief  Disable the Low Power Run mode.
-  * @note  Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that 
-  *        REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode 
-  *        returns HAL_TIMEOUT status). The system clock frequency can then be
-  *        increased above 2 MHz.   
-  * @retval HAL_StatusTypeDef
-  */
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
-{
-  uint32_t wait_loop_index = 0U;
-  
-  /* Exit the Low Power Run mode */
-  CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);
-  CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR);
-  
-  /* Wait until REGLPF is reset */
-  wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U));
-
-  while ((wait_loop_index != 0U) && (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF)))
-  {
-    wait_loop_index--;
-  }
-
-  if (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF))
-  {
-    return HAL_TIMEOUT;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c
deleted file mode 100644
index 23dd7235fd..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c
+++ /dev/null
@@ -1,1504 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_rcc.c
-  * @author  MCD Application Team
-  * @brief   RCC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Reset and Clock Control (RCC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *
-  @verbatim
-  ==============================================================================
-                      ##### RCC specific features #####
-  ==============================================================================
-    [..]
-      After reset the device is running from multispeed internal oscillator clock
-      (MSI 2.097MHz) with Flash 0 wait state and Flash prefetch buffer is disabled,
-      and all peripherals are off except internal SRAM, Flash and JTAG.
-      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
-          all peripherals mapped on these buses are running at MSI speed.
-      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
-      (+) All GPIOs are in input floating state, except the JTAG pins which
-          are assigned to be used for debug purpose.
-    [..] Once the device started from reset, the user application has to:
-      (+) Configure the clock source to be used to drive the System clock
-          (if the application needs higher frequency/performance)
-      (+) Configure the System clock frequency and Flash settings
-      (+) Configure the AHB and APB buses prescalers
-      (+) Enable the clock for the peripheral(s) to be used
-      (+) Configure the clock source(s) for peripherals whose clocks are not
-          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
-          (*) SDIO only for STM32L0xxxD devices
-
-                      ##### RCC Limitations #####
-  ==============================================================================
-    [..]
-      A delay between an RCC peripheral clock enable and the effective peripheral
-      enabling should be taken into account in order to manage the peripheral read/write
-      from/to registers.
-      (+) This delay depends on the peripheral mapping.
-        (++) AHB & APB peripherals, 1 dummy read is necessary
-
-    [..]
-      Workarounds:
-      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
-          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RCC RCC
-* @brief RCC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
-  * @{
-  */
-
-#define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
-#define MCO1_GPIO_PORT        GPIOA
-#define MCO1_PIN              GPIO_PIN_8
-
-#define MCO2_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
-#define MCO2_GPIO_PORT        GPIOA
-#define MCO2_PIN              GPIO_PIN_9
-
-#if defined(RCC_MCO3_SUPPORT)
-#define MCO3_CLK_ENABLE()     __HAL_RCC_GPIOB_CLK_ENABLE()
-#define MCO3_GPIO_PORT        GPIOB
-#define MCO3_PIN              GPIO_PIN_13
-#endif /* RCC_MCO3_SUPPORT */
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Functions RCC Exported Functions
-  * @{
-  */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-  @verbatim
-  ===============================================================================
-           ##### Initialization and de-initialization functions #####
-  ===============================================================================
-    [..]
-      This section provides functions allowing to configure the internal/external oscillators
-      (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
-      and APB2).
-
-    [..] Internal/external clock and PLL configuration
-      (#) MSI (Multispeed internal), Seven frequency ranges are available: 65.536 kHz,
-          131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz.
-
-      (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
-          the PLL as System clock source.
-      (#) LSI (low-speed internal), ~37 KHz low consumption RC used as IWDG and/or RTC
-          clock source.
-
-      (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or
-          through the PLL as System clock source. Can be used also as RTC clock source.
-
-      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
-      (#) PLL (clocked by HSI or HSE), featuring different output clocks:
-        (++) The first output is used to generate the high speed system clock (up to 32 MHz)
-        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
-
-      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
-          and if a HSE clock failure occurs(HSE used directly or through PLL as System
-          clock source), the System clocks automatically switched to MSI and an interrupt
-          is generated if enabled. The interrupt is linked to the Cortex-M0+ NMI
-          (Non-Maskable Interrupt) exception vector.
-
-      (#) MCO1/MCO2/MCO3 (microcontroller clock output), used to output SYSCLK, HSI, LSI, MSI, LSE,
-          HSE, HSI48 or PLL clock (through a configurable prescaler) on PA8/PA9/PB13 pins.
-
-    [..] System, AHB and APB buses clocks configuration
-      (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
-          HSE and PLL.
-          The AHB clock (HCLK) is derived from System clock through configurable
-          prescaler and used to clock the CPU, memory and peripherals mapped
-          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
-          from AHB clock through configurable prescalers and used to clock
-          the peripherals mapped on these buses. You can use
-          "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-
-      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
-          (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
-              divided by 2 to 16. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
-              macros to configure this clock.
-          (+@) LCD: LCD clock can be derived either from the LSI, LSE or HSE clock
-              divided by 2 to 16. You have to use __HAL_RCC_LCD_CONFIG()
-              macros to configure this clock.
-          (+@) USB FS and RNG: USB FS require a frequency equal to 48 MHz to work correctly.
-               This clock is derived of the main PLL through PLL Multiplier or HSI48 RC oscillator.
-
-          (+@) IWDG clock which is always the LSI clock.
-
-      (#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz
-          and PCLK1 32 MHz. Depending on the device voltage range, the maximum
-          frequency should be adapted accordingly.
-  @endverbatim
-  * @{
-  */
-
-/*
-  Additional consideration on the HCLK based on Latency settings:
-  +----------------------------------------------------------------------+
-  | Latency       |                HCLK clock frequency (MHz)            |
-  |               |------------------------------------------------------|
-  |               | voltage range 1  | voltage range 2 | voltage range 3 |
-  |               |      1.8 V       |     1.5 V       |      1.2 V      |
-  |---------------|------------------|-----------------|-----------------|
-  |0WS(1CPU cycle)| 0 < HCLK <= 16   | 0 < HCLK <= 8   | 0 < HCLK <= 4.2 |
-  |---------------|------------------|-----------------|-----------------|
-  |1WS(2CPU cycle)| 16 < HCLK <= 32  | 8 < HCLK <= 16  |                 |
-  +----------------------------------------------------------------------+
-
-  The following table gives the different clock source frequencies depending on the product
-  voltage range:
-  +------------------------------------------------------------------------------------------+
-  | Product voltage |                    Clock frequency                                     |
-  |                 |------------------|-----------------------------|-----------------------|
-  |      range      |   MSI   |   HSI  |              HSE            |          PLL          |
-  |-----------------|---------|--------|-----------------------------|-----------------------|
-  | Range 1 (1.8 V) | 4.2 MHz | 16 MHz | HSE 32 MHz (external clock) |         32 MHz        |
-  |                 |         |        |      or 24 MHz (crystal)    | (PLLVCO max = 96 MHz) |
-  |-----------------|---------|--------|-----------------------------|-----------------------|
-  | Range 2 (1.5 V) | 4.2 MHz | 16 MHz |         16 MHz              |         16 MHz        |
-  |                 |         |        |                             | (PLLVCO max = 48 MHz) |
-  |-----------------|---------|--------|-----------------------------|-----------------------|
-  | Range 3 (1.2 V) | 4.2 MHz |   NA   |         8 MHz               |           4 MHz       |
-  |                 |         |        |                             | (PLLVCO max = 24 MHz) |
-  +------------------------------------------------------------------------------------------+
-  */
-
-/**
-  * @brief  Resets the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *            - MSI ON and used as system clock source
-  *            - HSI, HSE and PLL  OFF
-  *            - AHB, APB1 and APB2 prescaler set to 1.
-  *            - CSS and MCO1/MCO2/MCO3 OFF
-  *            - All interrupts disabled
-  * @note   This function does not modify the configuration of the
-  *            - Peripheral clocks
-  *            - LSI, LSE and RTC clocks
-  *            - HSI48 clock
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_RCC_DeInit(void)
-{
-  __IO uint32_t tmpreg;
-  uint32_t tickstart;
-  uint32_t vl_mask;
-  HAL_StatusTypeDef status;
-
-  /* Set MSIClockRange, HSITRIM and MSITRIM bits to the reset values */
-  MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSITRIM | RCC_ICSCR_HSITRIM | RCC_ICSCR_MSIRANGE), \
-            ((RCC_MSICALIBRATION_DEFAULT << RCC_ICSCR_MSITRIM_Pos) | (RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos) | RCC_ICSCR_MSIRANGE_5));
-
-  /* Set MSION bit */
-  SET_BIT(RCC->CR, RCC_CR_MSION);
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till MSI is ready */
-  while (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Switch SYSCLK to MSI*/
-  CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
-
-  /* Wait till MSI as SYSCLK status is ready */
-  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Update the SystemCoreClock global variable for MSI as system clock source */
-  SystemCoreClock = MSI_VALUE;
-
-  /* Configure the source of time base considering new system clock settings  */
-  status = HAL_InitTick(uwTickPrio);
-  if(status != HAL_OK)
-  {
-    return status;
-  }
-
-  /* Reset HSE, HSI, CSS, PLL */
-#if defined(RCC_CR_CSSHSEON) && defined(RCC_CR_HSIOUTEN)
-  CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
-                     RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
-#elif !defined(RCC_CR_CSSHSEON) && defined(RCC_CR_HSIOUTEN)
-  CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
-                     RCC_CR_HSEON | RCC_CR_PLLON);
-#elif defined(RCC_CR_CSSHSEON) && !defined(RCC_CR_HSIOUTEN)
-  CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \
-                     RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
-#endif
-
-  /* Delay after an RCC peripheral clock */ \
-  tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON);      \
-  UNUSED(tmpreg);
-
-  /* Reset HSEBYP bit */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till PLL is not ready */
-  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Reset CFGR register */
-  CLEAR_REG(RCC->CFGR);
-
-  /* Disable all interrupts */
-  CLEAR_REG(RCC->CIER);
-
-  /* Clear all flags */
-  vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | RCC_CICR_MSIRDYC | RCC_CICR_CSSLSEC;
-#if defined(RCC_HSI48_SUPPORT)
-  vl_mask |= RCC_CICR_HSI48RDYC;
-#endif
-#if defined(RCC_HSECSS_SUPPORT)
-  vl_mask |= RCC_CICR_CSSHSEC;
-#endif
-  WRITE_REG(RCC->CICR, vl_mask);
-
-  /* Clear all reset flags */
-  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
-  *         RCC_OscInitTypeDef.
-  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC Oscillators.
-  * @note   The PLL is not disabled when used as system clock.
-  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
-  *         supported by this macro. User should request a transition to LSE Off
-  *         first and then LSE On or LSE Bypass.
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
-  *         supported by this macro. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  uint32_t tickstart;
-  uint32_t hsi_state;
-  HAL_StatusTypeDef status;
-  uint32_t sysclk_source, pll_config;
-
-  /* Check Null pointer */
-  if(RCC_OscInitStruct == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
-  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
-  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
-
-  /*------------------------------- HSE Configuration ------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-
-    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
-    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
-       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
-    {
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
-      {
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Set the new HSE configuration ---------------------------------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
-      /* Check the HSE State */
-      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
-      {
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
-        {
-           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*----------------------------- HSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
-    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
-    hsi_state = RCC_OscInitStruct->HSIState;
-
-#if defined(RCC_CR_HSIOUTEN)
-    if((hsi_state & RCC_HSI_OUTEN) != 0U)
-    {
-      /* HSI Output enable for timer requested */
-      SET_BIT(RCC->CR, RCC_CR_HSIOUTEN);
-
-      hsi_state &= ~RCC_CR_HSIOUTEN;
-    }
-#endif
-
-    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
-    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
-       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
-    {
-      /* When HSI is used as system clock it will not disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (hsi_state == RCC_HSI_OFF))
-      {
-        return HAL_ERROR;
-      }
-      /* Otherwise, just the calibration and HSI or HSIdiv4 are allowed */
-      else
-      {
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-
-        /* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
-        __HAL_RCC_HSI_CONFIG(hsi_state);
-      }
-
-      /* Update the SystemCoreClock global variable */
-      SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
-
-      /* Configure the source of time base considering new system clocks settings*/
-      status = HAL_InitTick (uwTickPrio);
-      if(status != HAL_OK)
-      {
-        return status;
-      }
-    }
-    else
-    {
-      /* Check the HSI State */
-      if(hsi_state != RCC_HSI_OFF)
-      {
-        /* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
-        __HAL_RCC_HSI_CONFIG(hsi_state);
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_DISABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*----------------------------- MSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
-  {
-    /* When the MSI is used as system clock it will not be disabled */
-    if(sysclk_source == RCC_CFGR_SWS_MSI)
-    {
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
-      {
-        return HAL_ERROR;
-      }
-      /* Otherwise, just the calibration and MSI range change are allowed */
-      else
-      {
-        /* Check MSICalibrationValue and MSIClockRange input parameters */
-        assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
-        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
-
-        /* Selects the Multiple Speed oscillator (MSI) clock range .*/
-        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
-        /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
-        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
-
-
-        /* Update the SystemCoreClock global variable */
-        SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
-                           >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
-
-        /* Configure the source of time base considering new system clocks settings*/
-        status = HAL_InitTick (uwTickPrio);
-        if(status != HAL_OK)
-        {
-          return status;
-        }
-      }
-    }
-    else
-    {
-      /* Check MSI State */
-      assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
-
-      /* Check the MSI State */
-      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
-      {
-        /* Enable the Multi Speed oscillator (MSI). */
-        __HAL_RCC_MSI_ENABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till MSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
-        {
-          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-        /* Check MSICalibrationValue and MSIClockRange input parameters */
-        assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
-        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
-
-        /* Selects the Multiple Speed oscillator (MSI) clock range .*/
-        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
-         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
-        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
-      }
-      else
-      {
-        /* Disable the Multi Speed oscillator (MSI). */
-        __HAL_RCC_MSI_DISABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till MSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
-        {
-          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*------------------------------ LSI Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
-    /* Check the LSI State */
-    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
-    {
-      /* Enable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_ENABLE();
-
-      /* Get Start Tick */
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Disable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_DISABLE();
-
-      /* Get Start Tick */
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSI is disabled */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  /*------------------------------ LSE Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
-  {
-    FlagStatus       pwrclkchanged = RESET;
-
-    /* Check the parameters */
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
-    /* Update LSE configuration in Backup Domain control register    */
-    /* Requires to enable write access to Backup Domain of necessary */
-    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
-    {
-      __HAL_RCC_PWR_CLK_ENABLE();
-      pwrclkchanged = SET;
-    }
-
-    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
-    {
-      /* Enable write access to Backup domain */
-      SET_BIT(PWR->CR, PWR_CR_DBP);
-
-      /* Wait for Backup domain Write protection disable */
-      tickstart = HAL_GetTick();
-
-      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
-      {
-        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Set the new LSE configuration -----------------------------------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
-
-    /* Check the LSE State */
-    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
-    {
-      /* Get Start Tick */
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSE is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Get Start Tick */
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSE is disabled */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Require to disable power clock if necessary */
-    if(pwrclkchanged == SET)
-    {
-      __HAL_RCC_PWR_CLK_DISABLE();
-    }
-  }
-
-#if defined(RCC_HSI48_SUPPORT)
-  /*----------------------------- HSI48 Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
-
-      /* Check the HSI48 State */
-      if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
-      {
-        /* Enable the Internal High Speed oscillator (HSI48). */
-        __HAL_RCC_HSI48_ENABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI48 is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
-        {
-          if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI48). */
-        __HAL_RCC_HSI48_DISABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI48 is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
-        {
-          if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-  }
-#endif /* RCC_HSI48_SUPPORT */
-
-  /*-------------------------------- PLL Configuration -----------------------*/
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
-  {
-    /* Check if the PLL is used as system clock or not */
-    if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-    {
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
-      {
-        /* Check the parameters */
-        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
-        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
-        assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
-
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* Configure the main PLL clock source, multiplication and division factors. */
-        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
-                             RCC_OscInitStruct->PLL.PLLMUL,
-                             RCC_OscInitStruct->PLL.PLLDIV);
-        /* Enable the main PLL. */
-        __HAL_RCC_PLL_ENABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    else
-    {
-      /* Check if there is a request to disable the PLL used as System clock source */
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Do not return HAL_ERROR if request repeats the current configuration */
-        pll_config = RCC->CFGR;
-        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
-           (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
-           (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
-        {
-          return HAL_ERROR;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
-  *         parameters in the RCC_ClkInitStruct.
-  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC peripheral.
-  * @param  FLatency FLASH Latency
-  *          The value of this parameter depend on device used within the same series
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
-  *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
-  *
-  * @note   The MSI is used (enabled by hardware) as system clock source after
-  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
-  *         of failure of the HSE used directly or indirectly as system clock
-  *         (if the Clock Security System CSS is enabled).
-  *
-  * @note   A switch from one clock source to another occurs only if the target
-  *         clock source is ready (clock stable after start-up delay or PLL locked).
-  *         If a clock source which is not yet ready is selected, the switch will
-  *         occur when the clock source will be ready.
-  *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
-  *         currently used as system clock source.
-  * @note   Depending on the device voltage range, the software has to set correctly
-  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
-  *         (for more details refer to section above "Initialization/de-initialization functions")
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
-{
-  uint32_t tickstart;
-  HAL_StatusTypeDef status;
-
-  /* Check Null pointer */
-  if(RCC_ClkInitStruct == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
-  assert_param(IS_FLASH_LATENCY(FLatency));
-
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
-  must be correctly programmed according to the frequency of the CPU clock
-  (HCLK) and the supply voltage of the device. */
-
-  /* Increasing the number of wait states because of higher CPU frequency */
-  if(FLatency > __HAL_FLASH_GET_LATENCY())
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by polling the FLASH_ACR register */
-    tickstart = HAL_GetTick();
-
-    while (__HAL_FLASH_GET_LATENCY() != FLatency)
-    {
-      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /*-------------------------- HCLK Configuration --------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
-  {
-    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
-  }
-
-  /*------------------------- SYSCLK Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
-  {
-    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
-    /* HSE is selected as System Clock Source */
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-    {
-      /* Check the HSE ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* PLL is selected as System Clock Source */
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-    {
-      /* Check the PLL ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* HSI is selected as System Clock Source */
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
-    {
-      /* Check the HSI ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* MSI is selected as System Clock Source */
-    else
-    {
-      /* Check the MSI ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
-      {
-        return HAL_ERROR;
-      }
-    }
-    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
-
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();
-
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  /* Decreasing the number of wait states because of lower CPU frequency */
-  if(FLatency < __HAL_FLASH_GET_LATENCY())
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by polling the FLASH_ACR register */
-    tickstart = HAL_GetTick();
-
-    while (__HAL_FLASH_GET_LATENCY() != FLatency)
-    {
-      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /*-------------------------- PCLK1 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
-  }
-
-  /*-------------------------- PCLK2 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
-  }
-
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
-
-  /* Configure the source of time base considering new system clocks settings*/
-  status = HAL_InitTick(uwTickPrio);
-  if(status != HAL_OK)
-  {
-    return status;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
-  *  @brief   RCC clocks control functions
-  *
-  @verbatim
-  ===============================================================================
-                  ##### Peripheral Control functions #####
-  ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks
-    frequencies.
-
-  @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Selects the clock source to output on MCO pin.
-  * @note   MCO pin should be configured in alternate function mode.
-  * @param  RCC_MCOx specifies the output direction for the clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
-  *            @arg @ref RCC_MCO2 Clock source to output on MCO2 pin(PA9).
-  @if STM32L031xx
-  *            @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
-  @elseif STM32L041xx
-  *            @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
-  @elseif STM32L073xx
-  *            @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
-  @elseif STM32L083xx
-  *            @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
-  @elseif STM32L072xx
-  *            @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
-  @elseif STM32L082xx
-  *            @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
-  @elseif STM32L071xx
-  *            @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
-  @elseif STM32L081xx
-  *            @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
-  @elseif STM32L051xx
-  *            @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
-  @elseif STM32L053xx
-  *            @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
-  @endif
-  * @param  RCC_MCOSource specifies the clock source to output.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK     No clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_SYSCLK      System clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_HSI         HSI selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_HSE         HSE selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_MSI         MSI oscillator clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLL clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_LSI         LSI clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_LSE         LSE clock selected as MCO clock
-  @if STM32L052xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L053xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L062xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L063xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L072xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L073xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L082xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @elseif STM32L083xx
-  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
-  @endif
-  * @param  RCC_MCODiv specifies the MCO DIV.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCODIV_1 no division applied to MCO clock
-  *            @arg @ref RCC_MCODIV_2  division by 2 applied to MCO clock
-  *            @arg @ref RCC_MCODIV_4  division by 4 applied to MCO clock
-  *            @arg @ref RCC_MCODIV_8  division by 8 applied to MCO clock
-  *            @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
-  * @retval None
-  */
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
-{
-  GPIO_InitTypeDef gpio = {0};
-
-  /* Check the parameters */
-  assert_param(IS_RCC_MCO(RCC_MCOx));
-  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
-  assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
-  /* Configure the MCO1 pin in alternate function mode */
-  gpio.Mode      = GPIO_MODE_AF_PP;
-  gpio.Speed     = GPIO_SPEED_FREQ_HIGH;
-  gpio.Pull      = GPIO_NOPULL;
-  if(RCC_MCOx == RCC_MCO1)
-  {
-    gpio.Pin       = MCO1_PIN;
-    gpio.Alternate = GPIO_AF0_MCO;
-
-    /* MCO1 Clock Enable */
-    MCO1_CLK_ENABLE();
-    HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
-  }
-#if defined(RCC_MCO3_SUPPORT)
-  else if (RCC_MCOx == RCC_MCO3)
-  {
-    gpio.Pin       = MCO3_PIN;
-    gpio.Alternate = MCO3_GPIO_AF;
-
-    /* MCO3 Clock Enable */
-    MCO3_CLK_ENABLE();
-    HAL_GPIO_Init(MCO3_GPIO_PORT, &gpio);
-  }
-#endif /* RCC_MCO3_SUPPORT */
-  else
-  {
-    gpio.Pin       = MCO2_PIN;
-    gpio.Alternate = GPIO_AF0_MCO;
-
-    /* MCO2 Clock Enable */
-    MCO2_CLK_ENABLE();
-    HAL_GPIO_Init(MCO2_GPIO_PORT, &gpio);
-  }
-
-  /* Configure the MCO clock source */
-  __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
-}
-
-#if defined(RCC_HSECSS_SUPPORT)
-/**
-  * @brief  Enables the Clock Security System.
-  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
-  *         is automatically disabled and an interrupt is generated to inform the
-  *         software about the failure (Clock Security System Interrupt, CSSI),
-  *         allowing the MCU to perform rescue operations. The CSSI is linked to
-  *         the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector.
-  * @retval None
-  */
-void HAL_RCC_EnableCSS(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_CSSON) ;
-}
-
-#endif /* RCC_HSECSS_SUPPORT */
-/**
-  * @brief  Returns the SYSCLK frequency
-  * @note   The system frequency computed by this function is not the real
-  *         frequency in the chip. It is calculated based on the predefined
-  *         constant and the selected clock source:
-  * @note     If SYSCLK source is MSI, function returns a value based on MSI
-  *             Value as defined by the MSI range.
-  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
-  * @note     If SYSCLK source is HSE, function returns a value based on HSE_VALUE(**)
-  * @note     If SYSCLK source is PLL, function returns a value based on HSE_VALUE(**)
-  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  * @note     (*) HSI_VALUE is a constant defined in stm32l0xx_hal_conf.h file (default value
-  *               16 MHz) but the real value may vary depending on the variations
-  *               in voltage and temperature.
-  * @note     (**) HSE_VALUE is a constant defined in stm32l0xx_hal_conf.h file (default value
-  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *                frequency of the crystal used. Otherwise, this function may
-  *                have wrong result.
-  *
-  * @note   The result of this function could be not correct when using fractional
-  *         value for HSE crystal.
-  *
-  * @note   This function can be used by the user application to compute the
-  *         baud-rate for the communication peripherals or configure other parameters.
-  *
-  * @note   Each time SYSCLK changes, this function must be called to update the
-  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *
-  * @retval SYSCLK frequency
-  */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
-  uint32_t tmpreg, pllm, plld, pllvco, msiclkrange;    /* no init needed */
-  uint32_t sysclockfreq;
-
-  tmpreg = RCC->CFGR;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (tmpreg & RCC_CFGR_SWS)
-  {
-    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
-    {
-      if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
-      {
-        sysclockfreq =  (HSI_VALUE >> 2);
-      }
-      else
-      {
-        sysclockfreq =  HSI_VALUE;
-      }
-      break;
-    }
-    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
-    {
-      sysclockfreq = HSE_VALUE;
-      break;
-    }
-    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
-    {
-      pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
-      plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
-      if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
-      }
-      else
-      {
-        if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
-        {
-          pllvco = (uint32_t)((((uint64_t)(HSI_VALUE >> 2)) * (uint64_t)pllm) / (uint64_t)plld);
-        }
-        else
-        {
-         pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
-        }
-      }
-      sysclockfreq = pllvco;
-      break;
-    }
-    case RCC_SYSCLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
-    default: /* MSI used as system clock */
-    {
-      msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
-      sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
-      break;
-    }
-  }
-  return sysclockfreq;
-}
-
-/**
-  * @brief  Returns the HCLK frequency
-  * @note   Each time HCLK changes, this function must be called to update the
-  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
-  *         and updated within this function
-  * @retval HCLK frequency
-  */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
-  return SystemCoreClock;
-}
-
-/**
-  * @brief  Returns the PCLK1 frequency
-  * @note   Each time PCLK1 changes, this function must be called to update the
-  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK1 frequency
-  */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
-  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
-}
-
-/**
-  * @brief  Returns the PCLK2 frequency
-  * @note   Each time PCLK2 changes, this function must be called to update the
-  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK2 frequency
-  */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
-  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
-}
-
-/**
-  * @brief  Configures the RCC_OscInitStruct according to the internal
-  * RCC configuration registers.
-  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
-  * will be configured.
-  * @retval None
-  */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  /* Check the parameters */
-  assert_param(RCC_OscInitStruct != (void *)NULL);
-
-  /* Set all possible values for the Oscillator type parameter ---------------*/
-  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI  \
-                  | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_MSI;
-#if defined(RCC_HSI48_SUPPORT)
-  RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
-#endif /* RCC_HSI48_SUPPORT */
-
-
-  /* Get the HSE configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
-  }
-  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
-  }
-
-  /* Get the HSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
-  }
-
-  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> 8);
-
-  /* Get the MSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION)
-  {
-    RCC_OscInitStruct->MSIState = RCC_MSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
-  }
-
-  RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
-  RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSIRANGE));
-
-  /* Get the LSE configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
-  }
-  else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
-  }
-
-  /* Get the LSI configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
-  }
-
-#if defined(RCC_HSI48_SUPPORT)
-  /* Get the HSI48 configuration if any-----------------------------------------*/
-  RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE();
-#endif /* RCC_HSI48_SUPPORT */
-
-  /* Get the PLL configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
-  }
-  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
-  RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
-  RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV);
-}
-
-/**
-  * @brief  Get the RCC_ClkInitStruct according to the internal
-  * RCC configuration registers.
-  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
-  * contains the current clock configuration.
-  * @param  pFLatency Pointer on the Flash Latency.
-  * @retval None
-  */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
-{
-  /* Check the parameters */
-  assert_param(RCC_ClkInitStruct != (void *)NULL);
-  assert_param(pFLatency != (void *)NULL);
-
-  /* Set all possible values for the Clock type parameter --------------------*/
-  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
-  /* Get the SYSCLK configuration --------------------------------------------*/
-  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
-  /* Get the HCLK configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
-
-  /* Get the APB1 configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
-
-  /* Get the APB2 configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
-
-  /* Get the Flash Wait State (Latency) configuration ------------------------*/
-  *pFLatency = __HAL_FLASH_GET_LATENCY();
-}
-
-#if defined(RCC_HSECSS_SUPPORT)
-/**
-  * @brief This function handles the RCC CSS interrupt request.
-  * @note This API should be called under the NMI_Handler().
-  * @retval None
-  */
-void HAL_RCC_NMI_IRQHandler(void)
-{
-  /* Check RCC CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
-  {
-    /* RCC Clock Security System interrupt user callback */
-    HAL_RCC_CSSCallback();
-
-    /* Clear RCC CSS pending bit */
-    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
-  }
-}
-
-/**
-  * @brief  RCC Clock Security System interrupt callback
-  * @retval none
-  */
-__weak void HAL_RCC_CSSCallback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-    the HAL_RCC_CSSCallback could be implemented in the user file
-    */
-}
-
-#endif /* RCC_HSECSS_SUPPORT */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup RCC_Private_Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c
deleted file mode 100644
index 1097d53f7e..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c
+++ /dev/null
@@ -1,1214 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_rcc_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended RCC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities RCC extension peripheral:
-  *           + Extended Peripheral Control functions
-  *           + Extended Clock Recovery System Control functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/** @defgroup RCCEx RCCEx
-  * @brief RCC Extension HAL module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
-  * @{
-  */
-#if defined(USB)
-extern const uint8_t PLLMulTable[];
-#endif /* USB */
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
-  * @{
-  */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
- *  @brief  Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-                ##### Extended Peripheral Control functions  #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks
-    frequencies.
-    [..]
-    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
-        select the RTC clock source; in this case the Backup domain will be reset in
-        order to modify the RTC Clock source, as consequence RTC registers (including
-        the backup registers) are set to their reset values.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified
-  *         parameters in the RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1,
-  *         I2C1, I2C3, RTC, USB/RNG  and LPTIM1 clocks).
-  * @retval HAL status
-  * @note   If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()
-  *         to possibly update HSE divider.
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart;
-  uint32_t temp_reg;
-  FlagStatus       pwrclkchanged = RESET;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
-  /*------------------------------- RTC/LCD Configuration ------------------------*/
-  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
-#if defined(LCD)
-   || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
-#endif /* LCD */
-     )
-  {
-    /* check for RTC Parameters used to output RTCCLK */
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
-    {
-      assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-    }
-
-#if defined(LCD)
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
-    {
-      assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection));
-    }
-#endif /* LCD */
-
-    /* As soon as function is called to change RTC clock source, activation of the
-       power domain is done. */
-    /* Requires to enable write access to Backup Domain of necessary */
-    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
-    {
-      __HAL_RCC_PWR_CLK_ENABLE();
-      pwrclkchanged = SET;
-    }
-
-    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
-    {
-      /* Enable write access to Backup domain */
-      SET_BIT(PWR->CR, PWR_CR_DBP);
-
-      /* Wait for Backup domain Write protection disable */
-      tickstart = HAL_GetTick();
-
-      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
-      {
-        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
-    temp_reg = (RCC->CR & RCC_CR_RTCPRE);
-    if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
-#if defined (LCD)
-     || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
-#endif /* LCD */
-       )
-    { /* Check HSE State */
-      if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE)
-      {
-        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
-        {
-          /* To update HSE divider, first switch-OFF HSE clock oscillator*/
-          return HAL_ERROR;
-        }
-      }
-    }
-
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
-    temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);
-
-    if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \
-      && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
-#if defined(LCD)
-      || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \
-       && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))
-#endif /* LCD */
-     ))
-    {
-      /* Store the content of CSR register before the reset of Backup Domain */
-      temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
-
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-
-      /* Restore the Content of CSR register */
-      RCC->CSR = temp_reg;
-
-       /* Wait for LSERDY if LSE was enabled */
-      if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
-      {
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till LSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-
-    /* Require to disable power clock if necessary */
-    if(pwrclkchanged == SET)
-    {
-      __HAL_RCC_PWR_CLK_DISABLE();
-    }
-  }
-
-#if defined (RCC_CCIPR_USART1SEL)
-  /*------------------------------- USART1 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
-
-    /* Configure the USART1 clock source */
-    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
-  }
-#endif /* RCC_CCIPR_USART1SEL */
-
-  /*----------------------------- USART2 Configuration --------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
-
-    /* Configure the USART2 clock source */
-    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
-  }
-
-  /*------------------------------ LPUART1 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
-
-    /* Configure the LPUAR1 clock source */
-    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
-  }
-
-  /*------------------------------ I2C1 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
-
-    /* Configure the I2C1 clock source */
-    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
-  }
-
-#if defined (RCC_CCIPR_I2C3SEL)
-    /*------------------------------ I2C3 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
-
-    /* Configure the I2C3 clock source */
-    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
-  }
-#endif /* RCC_CCIPR_I2C3SEL */
-
-#if defined(USB)
- /*---------------------------- USB and RNG configuration --------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
-  {
-    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
-    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
-  }
-#endif /* USB */
-
-  /*---------------------------- LPTIM1 configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
-  {
-    assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection));
-    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the PeriphClkInit according to the internal RCC configuration registers.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         returns the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1,
-  *         I2C1, I2C3, RTC, USB/RNG  and LPTIM1 clocks).
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t srcclk;
-
-   /* Set all possible values for the extended clock type parameter -----------*/
-  /* Common part first */
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                        RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_RTC     | \
-                                        RCC_PERIPHCLK_LPTIM1;
-#if defined(RCC_CCIPR_USART1SEL)
-  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART1;
-#endif /* RCC_CCIPR_USART1SEL */
-#if  defined(RCC_CCIPR_I2C3SEL)
-  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
-#endif /* RCC_CCIPR_I2C3SEL */
-#if defined(USB)
-  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
-#endif /* USB */
-#if defined(LCD)
-  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD;
-#endif /* LCD */
-
-  /* Get the RTC/LCD configuration -----------------------------------------------*/
-  srcclk = __HAL_RCC_GET_RTC_SOURCE();
-  if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2)
-  {
-    /* Source clock is LSE or LSI*/
-    PeriphClkInit->RTCClockSelection = srcclk;
-  }
-  else
-  {
-    /* Source clock is HSE. Need to get the prescaler value*/
-    PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE));
-  }
-#if defined(LCD)
-  PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
-#endif /* LCD */
-#if defined(RCC_CCIPR_USART1SEL)
-  /* Get the USART1 configuration --------------------------------------------*/
-  PeriphClkInit->Usart1ClockSelection  = __HAL_RCC_GET_USART1_SOURCE();
-#endif /* RCC_CCIPR_USART1SEL */
-  /* Get the USART2 clock source ---------------------------------------------*/
-  PeriphClkInit->Usart2ClockSelection  = __HAL_RCC_GET_USART2_SOURCE();
-  /* Get the LPUART1 clock source ---------------------------------------------*/
-  PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
-  /* Get the I2C1 clock source -----------------------------------------------*/
-  PeriphClkInit->I2c1ClockSelection    = __HAL_RCC_GET_I2C1_SOURCE();
-#if defined(RCC_CCIPR_I2C3SEL)
-/* Get the I2C3 clock source -----------------------------------------------*/
-  PeriphClkInit->I2c3ClockSelection    = __HAL_RCC_GET_I2C3_SOURCE();
-#endif /* RCC_CCIPR_I2C3SEL */
-  /* Get the LPTIM1 clock source -----------------------------------------------*/
-  PeriphClkInit->LptimClockSelection   = __HAL_RCC_GET_LPTIM1_SOURCE();
-  /* Get the RTC clock source -----------------------------------------------*/
-  PeriphClkInit->RTCClockSelection     = __HAL_RCC_GET_RTC_SOURCE();
-#if defined(USB)
-  /* Get the USB/RNG clock source -----------------------------------------------*/
-  PeriphClkInit->UsbClockSelection     = __HAL_RCC_GET_USB_SOURCE();
-#endif /* USB */
-}
-
-/**
-  * @brief  Return the peripheral clock frequency
-  * @note   Return 0 if peripheral clock is unknown
-  * @param  PeriphClk Peripheral clock identifier
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_PERIPHCLK_RTC      RTC peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_LCD      LCD peripheral clock (*)
-  *            @arg @ref RCC_PERIPHCLK_USB      USB or RNG peripheral clock (*)
-  *            @arg @ref RCC_PERIPHCLK_USART1   USART1 peripheral clock (*)
-  *            @arg @ref RCC_PERIPHCLK_USART2   USART2 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_I2C1     I2C1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_I2C2     I2C2 peripheral clock (*)
-  *            @arg @ref RCC_PERIPHCLK_I2C3     I2C3 peripheral clock (*)
-  * @note   (*) means that this peripheral is not present on all the devices
-  * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
-  */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-  uint32_t frequency = 0U;
-  uint32_t temp_reg, clkprediv, srcclk;    /* no init needed */
-#if defined(USB)
-  uint32_t pllmul, plldiv, pllvco;    /* no init needed */
-#endif /* USB */
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
-
-  switch (PeriphClk)
-  {
-  case RCC_PERIPHCLK_RTC:
-#if defined(LCD)
-  case RCC_PERIPHCLK_LCD:
-#endif /* LCD */
-    {
-      /* Get RCC CSR configuration ------------------------------------------------------*/
-      temp_reg = RCC->CSR;
-
-      /* Get the current RTC source */
-      srcclk = __HAL_RCC_GET_RTC_SOURCE();
-
-      /* Check if LSE is ready if RTC clock selection is LSE */
-      if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSERDY)))
-      {
-        frequency = LSE_VALUE;
-      }
-      /* Check if LSI is ready if RTC clock selection is LSI */
-      else if (srcclk == RCC_RTCCLKSOURCE_LSI)
-      {
-        if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSIRDY))
-        {
-          frequency = LSI_VALUE;
-        }
-      }
-      /* Check if HSE is ready and if RTC clock selection is HSE */
-      else if (srcclk == RCC_RTCCLKSOURCE_HSE_DIVX)
-      {
-        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
-        {
-          /* Get the current HSE clock divider */
-          clkprediv = __HAL_RCC_GET_RTC_HSE_PRESCALER();
-
-          switch (clkprediv)
-          {
-            case RCC_RTC_HSE_DIV_16:  /* HSE DIV16 has been selected */
-            {
-              frequency = HSE_VALUE / 16U;
-              break;
-            }
-            case RCC_RTC_HSE_DIV_8:   /* HSE DIV8 has been selected  */
-            {
-              frequency = HSE_VALUE / 8U;
-              break;
-            }
-            case RCC_RTC_HSE_DIV_4:   /* HSE DIV4 has been selected  */
-            {
-              frequency = HSE_VALUE / 4U;
-              break;
-            }
-            default:                  /* HSE DIV2 has been selected  */
-            {
-              frequency = HSE_VALUE / 2U;
-              break;
-            }
-          }
-        }
-      }
-      /* Clock not enabled for RTC */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-    }
-#if defined(USB)
-  case RCC_PERIPHCLK_USB:
-    {
-      /* Get the current USB source */
-      srcclk = __HAL_RCC_GET_USB_SOURCE();
-
-      if (srcclk == RCC_USBCLKSOURCE_PLL)
-      {
-        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
-        {
-          /* Get PLL clock source and multiplication factor ----------------------*/
-          pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-          plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-          pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)];
-          plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U;
-
-          /* Compute PLL clock input */
-          if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)
-          {
-            if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
-            {
-              pllvco =  (HSI_VALUE >> 2U);
-            }
-            else
-            {
-              pllvco =  HSI_VALUE;
-            }
-          }
-          else /* HSE source */
-          {
-            pllvco = HSE_VALUE;
-          }
-          /* pllvco * pllmul / plldiv */
-          pllvco = (pllvco * pllmul);
-          frequency = (pllvco/ plldiv);
-        }
-      }
-      else if (srcclk == RCC_USBCLKSOURCE_HSI48)
-      {
-        if (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))
-        {
-          frequency = HSI48_VALUE;
-        }
-      }
-      else /* RCC_USBCLKSOURCE_NONE */
-      {
-          frequency = 0U;
-      }
-      break;
-    }
-#endif /* USB */
-#if defined(RCC_CCIPR_USART1SEL)
-  case RCC_PERIPHCLK_USART1:
-    {
-      /* Get the current USART1 source */
-      srcclk = __HAL_RCC_GET_USART1_SOURCE();
-
-      /* Check if USART1 clock selection is PCLK2 */
-      if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
-      {
-        frequency = HAL_RCC_GetPCLK2Freq();
-      }
-      /* Check if HSI is ready and if USART1 clock selection is HSI */
-      else if (srcclk == RCC_USART1CLKSOURCE_HSI)
-      {
-        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
-        {
-          if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
-          {
-            frequency =  (HSI_VALUE >> 2U);
-          }
-          else
-          {
-            frequency =  HSI_VALUE;
-          }
-        }
-      }
-      /* Check if USART1 clock selection is SYSCLK */
-      else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      /* Check if LSE is ready  and if USART1 clock selection is LSE */
-      else if (srcclk == RCC_USART1CLKSOURCE_LSE)
-      {
-        if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))
-        {
-          frequency = LSE_VALUE;
-        }
-      }
-      /* Clock not enabled for USART1*/
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-    }
-#endif /* RCC_CCIPR_USART1SEL */
-  case RCC_PERIPHCLK_USART2:
-    {
-      /* Get the current USART2 source */
-      srcclk = __HAL_RCC_GET_USART2_SOURCE();
-
-      /* Check if USART2 clock selection is PCLK1 */
-      if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      /* Check if HSI is ready and if USART2 clock selection is HSI */
-      else if (srcclk == RCC_USART2CLKSOURCE_HSI)
-      {
-        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
-        {
-          if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
-          {
-            frequency =  (HSI_VALUE >> 2U);
-          }
-          else
-          {
-            frequency =  HSI_VALUE;
-          }
-        }
-      }
-      /* Check if USART2 clock selection is SYSCLK */
-      else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      /* Check if LSE is ready  and if USART2 clock selection is LSE */
-      else if (srcclk == RCC_USART2CLKSOURCE_LSE)
-      {
-        if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))
-        {
-          frequency = LSE_VALUE;
-        }
-      }
-      /* Clock not enabled for USART2*/
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-    }
-  case RCC_PERIPHCLK_LPUART1:
-    {
-      /* Get the current LPUART1 source */
-      srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
-
-      /* Check if LPUART1 clock selection is PCLK1 */
-      if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      /* Check if HSI is ready and if LPUART1 clock selection is HSI */
-      else if (srcclk == RCC_LPUART1CLKSOURCE_HSI)
-      {
-        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
-        {
-          if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
-          {
-            frequency =  (HSI_VALUE >> 2U);
-          }
-          else
-          {
-            frequency =  HSI_VALUE;
-          }
-        }
-      }
-      /* Check if LPUART1 clock selection is SYSCLK */
-      else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      /* Check if LSE is ready  and if LPUART1 clock selection is LSE */
-      else if (srcclk == RCC_LPUART1CLKSOURCE_LSE)
-      {
-        if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))
-        {
-          frequency = LSE_VALUE;
-        }
-      }
-      /* Clock not enabled for LPUART1*/
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-    }
-  case RCC_PERIPHCLK_I2C1:
-    {
-      /* Get the current I2C1 source */
-      srcclk = __HAL_RCC_GET_I2C1_SOURCE();
-
-      /* Check if I2C1 clock selection is PCLK1 */
-      if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      /* Check if HSI is ready and if I2C1 clock selection is HSI */
-      else if (srcclk == RCC_I2C1CLKSOURCE_HSI)
-      {
-        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
-        {
-          if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
-          {
-            frequency =  (HSI_VALUE >> 2U);
-          }
-          else
-          {
-            frequency =  HSI_VALUE;
-          }
-        }
-      }
-      /* Check if I2C1 clock selection is SYSCLK */
-      else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      /* Clock not enabled for I2C1*/
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-    }
-#if defined(I2C2)
-  case RCC_PERIPHCLK_I2C2:
-    {
-
-      /* Check if I2C2 on APB1 clock enabled*/
-      if (READ_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))==RCC_APB1ENR_I2C2EN)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-    }
-#endif /* I2C2 */
-
-#if defined(RCC_CCIPR_I2C3SEL)
-  case RCC_PERIPHCLK_I2C3:
-    {
-      /* Get the current I2C3 source */
-      srcclk = __HAL_RCC_GET_I2C3_SOURCE();
-
-      /* Check if I2C3 clock selection is PCLK1 */
-      if (srcclk == RCC_I2C3CLKSOURCE_PCLK1)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      /* Check if HSI is ready and if I2C3 clock selection is HSI */
-      else if (srcclk == RCC_I2C3CLKSOURCE_HSI)
-      {
-        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
-        {
-          if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
-          {
-            frequency =  (HSI_VALUE >> 2U);
-          }
-          else
-          {
-            frequency =  HSI_VALUE;
-          }
-        }
-      }
-      /* Check if I2C3 clock selection is SYSCLK */
-      else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      /* Clock not enabled for I2C3*/
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-    }
-#endif /* RCC_CCIPR_I2C3SEL */
-  default:
-    {
-      break;
-    }
-  }
-  return(frequency);
-}
-
-/**
-  * @brief  Enables the LSE Clock Security System.
-  * @retval None
-  */
-void HAL_RCCEx_EnableLSECSS(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
-}
-
-/**
-  * @brief  Disables the LSE Clock Security System.
-  * @note   Once enabled this bit cannot be disabled, except after an LSE failure detection
-  *         (LSECSSD=1). In that case the software MUST disable the LSECSSON bit.
-  *         Reset by power on reset and RTC software reset (RTCRST bit).
-  * @retval None
-  */
-void HAL_RCCEx_DisableLSECSS(void)
-{
-  /* Disable LSE CSS */
-   CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
-
-  /* Disable LSE CSS IT */
-  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
-}
-
-/**
-  * @brief  Enable the LSE Clock Security System IT & corresponding EXTI line.
-  * @note   LSE Clock Security System IT is mapped on RTC EXTI line 19
-  * @retval None
-  */
-void HAL_RCCEx_EnableLSECSS_IT(void)
-{
-  /* Enable LSE CSS */
-   SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
-
-  /* Enable LSE CSS IT */
-  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
-
-  /* Enable IT on EXTI Line 19 */
-  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
-  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
-}
-
-/**
-  * @brief Handle the RCC LSE Clock Security System interrupt request.
-  * @retval None
-  */
-void HAL_RCCEx_LSECSS_IRQHandler(void)
-{
-  /* Check RCC LSE CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
-  {
-    /* RCC LSE Clock Security System interrupt user callback */
-    HAL_RCCEx_LSECSS_Callback();
-
-    /* Clear RCC LSE CSS pending bit */
-    __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
-  }
-}
-
-/**
-  * @brief  RCCEx LSE Clock Security System interrupt callback.
-  * @retval none
-  */
-__weak void HAL_RCCEx_LSECSS_Callback(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
-   */
-}
-
-#if defined(SYSCFG_CFGR3_ENREF_HSI48)
-/**
-  * @brief Enables Vrefint for the HSI48.
-  * @note  This is functional only if the LOCK is not set
-  * @retval None
-  */
-void HAL_RCCEx_EnableHSI48_VREFINT(void)
-{
-  /* Enable the Buffer for the ADC by setting SYSCFG_CFGR3_ENREF_HSI48 bit in SYSCFG_CFGR3 register   */
-  SET_BIT (SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
-}
-
-/**
-  * @brief Disables the Vrefint for the HSI48.
-  * @note  This is functional only if the LOCK is not set
-  * @retval None
-  */
-void HAL_RCCEx_DisableHSI48_VREFINT(void)
-{
-  /* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit in SYSCFG_CFGR3 register */
-  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
-}
-
-#endif /* SYSCFG_CFGR3_ENREF_HSI48 */
-
-/**
-  * @}
-  */
-
-#if defined (CRS)
-
-/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
- *  @brief  Extended Clock Recovery System Control functions
- *
-@verbatim
- ===============================================================================
-                ##### Extended Clock Recovery System Control functions  #####
- ===============================================================================
-    [..]
-      For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:
-
-      (#) In System clock config, HSI48 needs to be enabled
-
-      (#) Enable CRS clock in IP MSP init which will use CRS functions
-
-      (#) Call CRS functions as follows:
-          (##) Prepare synchronization configuration necessary for HSI48 calibration
-              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
-                        and also HSI48 oscillator smooth trimming.
-              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
-                        directly reload value with target and synchronization frequencies values
-          (##) Call function HAL_RCCEx_CRSConfig which
-              (+++) Reset CRS registers to their default values.
-              (+++) Configure CRS registers with synchronization configuration
-              (+++) Enable automatic calibration and frequency error counter feature
-           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
-           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
-           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
-           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
-           should be used as SYNC signal.
-
-          (##) A polling function is provided to wait for complete synchronization
-              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
-              (+++) According to CRS status, user can decide to adjust again the calibration or continue
-                        application if synchronization is OK
-
-      (#) User can retrieve information related to synchronization in calling function
-            HAL_RCCEx_CRSGetSynchronizationInfo()
-
-      (#) Regarding synchronization status and synchronization information, user can try a new calibration
-           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
-           Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
-           it means that the actual frequency is lower than the target (and so, that the TRIM value should be
-           incremented), while when it is detected during the upcounting phase it means that the actual frequency
-           is higher (and that the TRIM value should be decremented).
-
-      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
-          through CRS Handler (RCC_IRQn/RCC_IRQHandler)
-              (++) Call function HAL_RCCEx_CRSConfig()
-              (++) Enable RCC_IRQn (thanks to NVIC functions)
-              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
-              (++) Implement CRS status management in the following user callbacks called from
-                   HAL_RCCEx_CRS_IRQHandler():
-                   (+++) HAL_RCCEx_CRS_SyncOkCallback()
-                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()
-                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
-                   (+++) HAL_RCCEx_CRS_ErrorCallback()
-
-      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
-          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
-
-@endverbatim
- * @{
- */
-
-/**
-  * @brief  Start automatic synchronization for polling mode
-  * @param  pInit Pointer on RCC_CRSInitTypeDef structure
-  * @retval None
-  */
-void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
-{
-  uint32_t value;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
-  assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
-  assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
-  assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
-  assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
-  assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
-
-  /* CONFIGURATION */
-
-  /* Before configuration, reset CRS registers to their default values*/
-  __HAL_RCC_CRS_FORCE_RESET();
-  __HAL_RCC_CRS_RELEASE_RESET();
-
-  /* Set the SYNCDIV[2:0] bits according to Prescaler value */
-  /* Set the SYNCSRC[1:0] bits according to Source value */
-  /* Set the SYNCSPOL bit according to Polarity value */
-  value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
-  /* Set the RELOAD[15:0] bits according to ReloadValue value */
-  value |= pInit->ReloadValue;
-  /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
-  value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
-  WRITE_REG(CRS->CFGR, value);
-
-  /* Adjust HSI48 oscillator smooth trimming */
-  /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
-  MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
-
-  /* START AUTOMATIC SYNCHRONIZATION*/
-
-  /* Enable Automatic trimming & Frequency error counter */
-  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
-}
-
-/**
-  * @brief  Generate the software synchronization event
-  * @retval None
-  */
-void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
-{
-  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
-}
-
-/**
-  * @brief  Return synchronization info
-  * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
-  * @retval None
-  */
-void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
-{
-  /* Check the parameter */
-  assert_param(pSynchroInfo != (void *)NULL);
-
-  /* Get the reload value */
-  pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
-
-  /* Get HSI48 oscillator smooth trimming */
-  pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
-
-  /* Get Frequency error capture */
-  pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
-
-  /* Get Frequency error direction */
-  pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
-}
-
-/**
-* @brief Wait for CRS Synchronization status.
-* @param Timeout  Duration of the timeout
-* @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
-*        frequency.
-* @note    If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
-* @retval Combination of Synchronization status
-*          This parameter can be a combination of the following values:
-*            @arg @ref RCC_CRS_TIMEOUT
-*            @arg @ref RCC_CRS_SYNCOK
-*            @arg @ref RCC_CRS_SYNCWARN
-*            @arg @ref RCC_CRS_SYNCERR
-*            @arg @ref RCC_CRS_SYNCMISS
-*            @arg @ref RCC_CRS_TRIMOVF
-*/
-uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
-{
-  uint32_t crsstatus = RCC_CRS_NONE;
-  uint32_t tickstart;
-
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-
-  /* Wait for CRS flag or timeout detection */
-  do
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        crsstatus = RCC_CRS_TIMEOUT;
-      }
-    }
-    /* Check CRS SYNCOK flag  */
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
-    {
-      /* CRS SYNC event OK */
-      crsstatus |= RCC_CRS_SYNCOK;
-
-      /* Clear CRS SYNC event OK bit */
-      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
-    }
-
-    /* Check CRS SYNCWARN flag  */
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
-    {
-      /* CRS SYNC warning */
-      crsstatus |= RCC_CRS_SYNCWARN;
-
-      /* Clear CRS SYNCWARN bit */
-      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
-    }
-
-    /* Check CRS TRIM overflow flag  */
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
-    {
-      /* CRS SYNC Error */
-      crsstatus |= RCC_CRS_TRIMOVF;
-
-      /* Clear CRS Error bit */
-      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
-    }
-
-    /* Check CRS Error flag  */
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
-    {
-      /* CRS SYNC Error */
-      crsstatus |= RCC_CRS_SYNCERR;
-
-      /* Clear CRS Error bit */
-      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
-    }
-
-    /* Check CRS SYNC Missed flag  */
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
-    {
-      /* CRS SYNC Missed */
-      crsstatus |= RCC_CRS_SYNCMISS;
-
-      /* Clear CRS SYNC Missed bit */
-      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
-    }
-
-    /* Check CRS Expected SYNC flag  */
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
-    {
-      /* frequency error counter reached a zero value */
-      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
-    }
-  } while(RCC_CRS_NONE == crsstatus);
-
-  return crsstatus;
-}
-
-/**
-  * @brief Handle the Clock Recovery System interrupt request.
-  * @retval None
-  */
-void HAL_RCCEx_CRS_IRQHandler(void)
-{
-  uint32_t crserror = RCC_CRS_NONE;
-  /* Get current IT flags and IT sources values */
-  uint32_t itflags = READ_REG(CRS->ISR);
-  uint32_t itsources = READ_REG(CRS->CR);
-
-  /* Check CRS SYNCOK flag  */
-  if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
-  {
-    /* Clear CRS SYNC event OK flag */
-    WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
-
-    /* user callback */
-    HAL_RCCEx_CRS_SyncOkCallback();
-  }
-  /* Check CRS SYNCWARN flag  */
-  else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
-  {
-    /* Clear CRS SYNCWARN flag */
-    WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
-
-    /* user callback */
-    HAL_RCCEx_CRS_SyncWarnCallback();
-  }
-  /* Check CRS Expected SYNC flag  */
-  else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
-  {
-    /* frequency error counter reached a zero value */
-    WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
-
-    /* user callback */
-    HAL_RCCEx_CRS_ExpectedSyncCallback();
-  }
-  /* Check CRS Error flags  */
-  else
-  {
-    if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
-    {
-      if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
-      {
-        crserror |= RCC_CRS_SYNCERR;
-      }
-      if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
-      {
-        crserror |= RCC_CRS_SYNCMISS;
-      }
-      if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
-      {
-        crserror |= RCC_CRS_TRIMOVF;
-      }
-
-      /* Clear CRS Error flags */
-      WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
-
-      /* user error callback */
-      HAL_RCCEx_CRS_ErrorCallback(crserror);
-    }
-  }
-}
-
-/**
-  * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
-  * @retval none
-  */
-__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
-  * @retval none
-  */
-__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
-  * @retval none
-  */
-__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  RCCEx Clock Recovery System Error interrupt callback.
-  * @param  Error Combination of Error status.
-  *         This parameter can be a combination of the following values:
-  *           @arg @ref RCC_CRS_SYNCERR
-  *           @arg @ref RCC_CRS_SYNCMISS
-  *           @arg @ref RCC_CRS_TRIMOVF
-  * @retval none
-  */
-__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(Error);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-#endif /* CRS */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c
deleted file mode 100644
index 4ab1d1b692..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c
+++ /dev/null
@@ -1,868 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_rng.c
-  * @author  MCD Application Team
-  * @brief   RNG HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Random Number Generator (RNG) peripheral:
-  *           + Initialization and configuration functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-      The RNG HAL driver can be used as follows:
-
-      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
-          in HAL_RNG_MspInit().
-      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
-      (#) Wait until the 32 bit Random Number Generator contains a valid
-          random data using (polling/interrupt) mode.
-      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
-
-    ##### Callback registration #####
-    ==================================
-
-    [..]
-    The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
-    allows the user to configure dynamically the driver callbacks.
-
-    [..]
-    Use Function HAL_RNG_RegisterCallback() to register a user callback.
-    Function HAL_RNG_RegisterCallback() allows to register following callbacks:
-    (+) ErrorCallback             : RNG Error Callback.
-    (+) MspInitCallback           : RNG MspInit.
-    (+) MspDeInitCallback         : RNG MspDeInit.
-    This function takes as parameters the HAL peripheral handle, the Callback ID
-    and a pointer to the user callback function.
-
-    [..]
-    Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-    and the Callback ID.
-    This function allows to reset following callbacks:
-    (+) ErrorCallback             : RNG Error Callback.
-    (+) MspInitCallback           : RNG MspInit.
-    (+) MspDeInitCallback         : RNG MspDeInit.
-
-    [..]
-    For specific callback ReadyDataCallback, use dedicated register callbacks:
-    respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback().
-
-    [..]
-    By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    example HAL_RNG_ErrorCallback().
-    Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the HAL_RNG_Init()
-    and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
-    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
-
-    [..]
-    Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
-    Exception done MspInit/MspDeInit that can be registered/unregistered
-    in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
-    MspInit/DeInit callbacks can be used during the Init/DeInit.
-    In that case first register the MspInit/MspDeInit user callbacks
-    using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit()
-    or HAL_RNG_Init() function.
-
-    [..]
-    When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
-    not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#if defined (RNG)
-
-/** @addtogroup RNG
-  * @brief RNG HAL module driver.
-  * @{
-  */
-
-#ifdef HAL_RNG_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Constants RNG Private Constants
-  * @{
-  */
-#define RNG_TIMEOUT_VALUE     2U
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions prototypes ----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup RNG_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RNG_Exported_Functions_Group1
-  *  @brief   Initialization and configuration functions
-  *
-@verbatim
- ===============================================================================
-          ##### Initialization and configuration functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the RNG according to the specified parameters
-          in the RNG_InitTypeDef and create the associated handle
-      (+) DeInitialize the RNG peripheral
-      (+) Initialize the RNG MSP
-      (+) DeInitialize RNG MSP
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the RNG peripheral and creates the associated handle.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
-{
-  /* Check the RNG handle allocation */
-  if (hrng == NULL)
-  {
-    return HAL_ERROR;
-  }
-  /* Check the parameters */
-  assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
-
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-  if (hrng->State == HAL_RNG_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hrng->Lock = HAL_UNLOCKED;
-
-    hrng->ReadyDataCallback  = HAL_RNG_ReadyDataCallback;  /* Legacy weak ReadyDataCallback  */
-    hrng->ErrorCallback      = HAL_RNG_ErrorCallback;      /* Legacy weak ErrorCallback      */
-
-    if (hrng->MspInitCallback == NULL)
-    {
-      hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit  */
-    }
-
-    /* Init the low level hardware */
-    hrng->MspInitCallback(hrng);
-  }
-#else
-  if (hrng->State == HAL_RNG_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hrng->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware */
-    HAL_RNG_MspInit(hrng);
-  }
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-  /* Change RNG peripheral state */
-  hrng->State = HAL_RNG_STATE_BUSY;
-
-
-  /* Enable the RNG Peripheral */
-  __HAL_RNG_ENABLE(hrng);
-
-  /* Initialize the RNG state */
-  hrng->State = HAL_RNG_STATE_READY;
-
-  /* Initialise the error code */
-  hrng->ErrorCode = HAL_RNG_ERROR_NONE;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the RNG peripheral.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
-{
-  /* Check the RNG handle allocation */
-  if (hrng == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Disable the RNG Peripheral */
-  CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
-
-  /* Clear RNG interrupt status flags */
-  CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
-
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-  if (hrng->MspDeInitCallback == NULL)
-  {
-    hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit  */
-  }
-
-  /* DeInit the low level hardware */
-  hrng->MspDeInitCallback(hrng);
-#else
-  /* DeInit the low level hardware */
-  HAL_RNG_MspDeInit(hrng);
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-  /* Update the RNG state */
-  hrng->State = HAL_RNG_STATE_RESET;
-
-  /* Initialise the error code */
-  hrng->ErrorCode = HAL_RNG_ERROR_NONE;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrng);
-
-  /* Return the function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the RNG MSP.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-  */
-__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_MspInit must be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  DeInitializes the RNG MSP.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-  */
-__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_MspDeInit must be implemented in the user file.
-   */
-}
-
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User RNG Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hrng RNG handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
-  *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
-                                           pRNG_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hrng);
-
-  if (HAL_RNG_STATE_READY == hrng->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_RNG_ERROR_CB_ID :
-        hrng->ErrorCallback = pCallback;
-        break;
-
-      case HAL_RNG_MSPINIT_CB_ID :
-        hrng->MspInitCallback = pCallback;
-        break;
-
-      case HAL_RNG_MSPDEINIT_CB_ID :
-        hrng->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_RNG_STATE_RESET == hrng->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_RNG_MSPINIT_CB_ID :
-        hrng->MspInitCallback = pCallback;
-        break;
-
-      case HAL_RNG_MSPDEINIT_CB_ID :
-        hrng->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrng);
-  return status;
-}
-
-/**
-  * @brief  Unregister an RNG Callback
-  *         RNG callabck is redirected to the weak predefined callback
-  * @param  hrng RNG handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
-  *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hrng);
-
-  if (HAL_RNG_STATE_READY == hrng->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_RNG_ERROR_CB_ID :
-        hrng->ErrorCallback = HAL_RNG_ErrorCallback;          /* Legacy weak ErrorCallback  */
-        break;
-
-      case HAL_RNG_MSPINIT_CB_ID :
-        hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
-        break;
-
-      case HAL_RNG_MSPDEINIT_CB_ID :
-        hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspDeInit  */
-        break;
-
-      default :
-        /* Update the error code */
-        hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_RNG_STATE_RESET == hrng->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_RNG_MSPINIT_CB_ID :
-        hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
-        break;
-
-      case HAL_RNG_MSPDEINIT_CB_ID :
-        hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspInit  */
-        break;
-
-      default :
-        /* Update the error code */
-        hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrng);
-  return status;
-}
-
-/**
-  * @brief  Register Data Ready RNG Callback
-  *         To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
-  * @param  hrng RNG handle
-  * @param  pCallback pointer to the Data Ready Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hrng);
-
-  if (HAL_RNG_STATE_READY == hrng->State)
-  {
-    hrng->ReadyDataCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrng);
-  return status;
-}
-
-/**
-  * @brief  UnRegister the Data Ready RNG Callback
-  *         Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
-  * @param  hrng RNG handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hrng);
-
-  if (HAL_RNG_STATE_READY == hrng->State)
-  {
-    hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrng);
-  return status;
-}
-
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup RNG_Exported_Functions_Group2
-  *  @brief   Peripheral Control functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Get the 32 bit Random number
-      (+) Get the 32 bit Random number with interrupt enabled
-      (+) Handle RNG interrupt request
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Generates a 32-bit random number.
-  * @note   Each time the random number data is read the RNG_FLAG_DRDY flag
-  *         is automatically cleared.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @param  random32bit pointer to generated random number variable if successful.
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
-{
-  uint32_t tickstart;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(hrng);
-
-  /* Check RNG peripheral state */
-  if (hrng->State == HAL_RNG_STATE_READY)
-  {
-    /* Change RNG peripheral state */
-    hrng->State = HAL_RNG_STATE_BUSY;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Check if data register contains valid random data */
-    while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
-    {
-      if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
-      {
-        /* New check to avoid false timeout detection in case of preemption */
-        if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
-        {
-          hrng->State = HAL_RNG_STATE_READY;
-          hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
-          /* Process Unlocked */
-          __HAL_UNLOCK(hrng);
-          return HAL_ERROR;
-        }
-      }
-    }
-
-    /* Get a 32bit Random number */
-    hrng->RandomNumber = hrng->Instance->DR;
-    *random32bit = hrng->RandomNumber;
-
-    hrng->State = HAL_RNG_STATE_READY;
-  }
-  else
-  {
-    hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
-    status = HAL_ERROR;
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrng);
-
-  return status;
-}
-
-/**
-  * @brief  Generates a 32-bit random number in interrupt mode.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(hrng);
-
-  /* Check RNG peripheral state */
-  if (hrng->State == HAL_RNG_STATE_READY)
-  {
-    /* Change RNG peripheral state */
-    hrng->State = HAL_RNG_STATE_BUSY;
-
-    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
-    __HAL_RNG_ENABLE_IT(hrng);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrng);
-
-    hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
-    status = HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Returns generated random number in polling mode (Obsolete)
-  *         Use HAL_RNG_GenerateRandomNumber() API instead.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval Random value
-  */
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
-{
-  if (HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
-  {
-    return hrng->RandomNumber;
-  }
-  else
-  {
-    return 0U;
-  }
-}
-
-/**
-  * @brief  Returns a 32-bit random number with interrupt enabled (Obsolete),
-  *         Use HAL_RNG_GenerateRandomNumber_IT() API instead.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval 32-bit random number
-  */
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
-{
-  uint32_t random32bit = 0U;
-
-  /* Process locked */
-  __HAL_LOCK(hrng);
-
-  /* Change RNG peripheral state */
-  hrng->State = HAL_RNG_STATE_BUSY;
-
-  /* Get a 32bit Random number */
-  random32bit = hrng->Instance->DR;
-
-  /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
-  __HAL_RNG_ENABLE_IT(hrng);
-
-  /* Return the 32 bit random number */
-  return random32bit;
-}
-
-/**
-  * @brief  Handles RNG interrupt request.
-  * @note   In the case of a clock error, the RNG is no more able to generate
-  *         random numbers because the PLL48CLK clock is not correct. User has
-  *         to check that the clock controller is correctly configured to provide
-  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
-  *         The clock error has no impact on the previously generated
-  *         random numbers, and the RNG_DR register contents can be used.
-  * @note   In the case of a seed error, the generation of random numbers is
-  *         interrupted as long as the SECS bit is '1'. If a number is
-  *         available in the RNG_DR register, it must not be used because it may
-  *         not have enough entropy. In this case, it is recommended to clear the
-  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
-  *         the RNG peripheral to reinitialize and restart the RNG.
-  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
-  *         or CEIS are set.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-
-  */
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
-{
-  uint32_t rngclockerror = 0U;
-
-  /* RNG clock error interrupt occurred */
-  if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
-  {
-    /* Update the error code */
-    hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
-    rngclockerror = 1U;
-  }
-  else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
-  {
-    /* Update the error code */
-    hrng->ErrorCode = HAL_RNG_ERROR_SEED;
-    rngclockerror = 1U;
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-
-  if (rngclockerror == 1U)
-  {
-    /* Change RNG peripheral state */
-    hrng->State = HAL_RNG_STATE_ERROR;
-
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-    /* Call registered Error callback */
-    hrng->ErrorCallback(hrng);
-#else
-    /* Call legacy weak Error callback */
-    HAL_RNG_ErrorCallback(hrng);
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-    /* Clear the clock error flag */
-    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
-
-    return;
-  }
-
-  /* Check RNG data ready interrupt occurred */
-  if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
-  {
-    /* Generate random number once, so disable the IT */
-    __HAL_RNG_DISABLE_IT(hrng);
-
-    /* Get the 32bit Random number (DRDY flag automatically cleared) */
-    hrng->RandomNumber = hrng->Instance->DR;
-
-    if (hrng->State != HAL_RNG_STATE_ERROR)
-    {
-      /* Change RNG peripheral state */
-      hrng->State = HAL_RNG_STATE_READY;
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrng);
-
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-      /* Call registered Data Ready callback */
-      hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
-#else
-      /* Call legacy weak Data Ready callback */
-      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-    }
-  }
-}
-
-/**
-  * @brief  Read latest generated random number.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval random value
-  */
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
-{
-  return (hrng->RandomNumber);
-}
-
-/**
-  * @brief  Data Ready callback in non-blocking mode.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @param  random32bit generated random number.
-  * @retval None
-  */
-__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-  UNUSED(random32bit);
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_ReadyDataCallback must be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  RNG error callbacks.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-  */
-__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_ErrorCallback must be implemented in the user file.
-   */
-}
-/**
-  * @}
-  */
-
-
-/** @addtogroup RNG_Exported_Functions_Group3
-  *  @brief   Peripheral State functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the RNG state.
-  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval HAL state
-  */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
-{
-  return hrng->State;
-}
-
-/**
-  * @brief  Return the RNG handle error code.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
-  * @retval RNG Error Code
-  */
-uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
-{
-  /* Return RNG Error Code */
-  return hrng->ErrorCode;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-#endif /* HAL_RNG_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-#endif /* RNG */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c
deleted file mode 100644
index 556452a31a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c
+++ /dev/null
@@ -1,1925 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_rtc.c
-  * @author  MCD Application Team
-  * @brief   RTC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Real-Time Clock (RTC) peripheral:
-  *           + Initialization
-  *           + Calendar (Time and Date) configuration
-  *           + Alarms (Alarm A and Alarm B) configuration
-  *           + WakeUp Timer configuration
-  *           + TimeStamp configuration
-  *           + Tampers configuration
-  *           + Backup Data Registers configuration
-  *           + RTC Tamper and TimeStamp Pins Selection
-  *           + Interrupts and flags management
-  *
-  @verbatim
- ===============================================================================
-                          ##### RTC Operating Condition #####
- ===============================================================================
-  [..] The real-time clock (RTC) and the RTC backup registers can be powered
-       from the VBAT voltage when the main VDD supply is powered off.
-       To retain the content of the RTC backup registers and supply the RTC
-       when VDD is turned off, VBAT pin can be connected to an optional
-       standby voltage supplied by a battery or by another source.
-
-                   ##### Backup Domain Reset #####
- ===============================================================================
-  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
-       to their reset values.
-       A backup domain reset is generated when one of the following events occurs:
-    (+) Software reset, triggered by setting the BDRST bit in the
-        RCC Backup domain control register (RCC_BDCR).
-    (+) VDD or VBAT power on, if both supplies have previously been powered off.
-    (+) Tamper detection event resets all data backup registers.
-
-                   ##### Backup Domain Access #####
- ===================================================================
-  [..] After reset, the backup domain (RTC registers, RTC backup data
-       registers and backup SRAM) is protected against possible unwanted write
-       accesses.
-
-  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
-    (+) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
-        PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
-    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
-
-                  ##### How to use RTC Driver #####
- ===================================================================
-  [..]
-    (+) Enable the RTC domain access (see description in the section above).
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
-        format using the HAL_RTC_Init() function.
-
-  *** Time and Date configuration ***
-  ===================================
-  [..]
-    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
-        and HAL_RTC_SetDate() functions.
-    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
-
-  *** Alarm configuration ***
-  ===========================
-  [..]
-    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
-            You can also configure the RTC Alarm with interrupt mode using the
-            HAL_RTC_SetAlarm_IT() function.
-    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-
-                  ##### RTC and low power modes #####
-  ==================================================================
-  [..] The MCU can be woken up from a low power mode by an RTC alternate
-       function.
-  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
-       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
-       These RTC alternate functions can wake up the system from the Stop and
-       Standby low power modes.
-  [..] The system can also wake up from low power modes without depending
-       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
-       or the RTC wakeup events.
-  [..] The RTC provides a programmable time base for waking up from the
-       Stop or Standby mode at regular intervals.
-       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
-       is LSE or LSI.
-
-  *** Callback registration ***
-  =============================================
-
-  [..]
-  The compilation define  USE_RTC_REGISTER_CALLBACKS when set to 1
-  allows the user to configure dynamically the driver callbacks.
-  Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
-
-  [..]
-  Function HAL_RTC_RegisterCallback() allows to register following callbacks:
-    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
-    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
-    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
-    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
-    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
-    (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
-    (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
-    (+) MspInitCallback              : RTC MspInit callback.
-    (+) MspDeInitCallback            : RTC MspDeInit callback.
-  [..]
-  This function takes as parameters the HAL peripheral handle, the Callback ID
-  and a pointer to the user callback function.
-
-  [..]
-  Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
-  weak function.
-  HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-  and the Callback ID.
-  This function allows to reset following callbacks:
-    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
-    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
-    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
-    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
-    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
-    (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
-    (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
-    (+) MspInitCallback              : RTC MspInit callback.
-    (+) MspDeInitCallback            : RTC MspDeInit callback.
-
-  [..]
-  By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
-  all callbacks are set to the corresponding weak functions :
-  examples AlarmAEventCallback(), WakeUpTimerEventCallback().
-  Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
-  in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
-  (not registered beforehand).
-  If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
-  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
-  [..]
-  Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
-  Exception done MspInit/MspDeInit that can be registered/unregistered
-  in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
-  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-  In that case first register the MspInit/MspDeInit user callbacks
-  using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
-  or HAL_RTC_Init() function.
-
-  [..]
-  When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
-  not defined, the callback registration feature is not available and all callbacks
-  are set to the corresponding weak functions.
-
-   @endverbatim
-
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-
-/** @addtogroup RTC
-  * @brief RTC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup RTC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group1
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-   [..] This section provides functions allowing to initialize and configure the
-         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
-         RTC registers Write protection, enter and exit the RTC initialization mode,
-         RTC registers synchronization check and reference clock detection enable.
-         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
-             It is split into 2 programmable prescalers to minimize power consumption.
-             (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
-             (++) When both prescalers are used, it is recommended to configure the
-                 asynchronous prescaler to a high value to minimize power consumption.
-         (#) All RTC registers are Write protected. Writing to the RTC registers
-             is enabled by writing a key into the Write Protection register, RTC_WPR.
-         (#) To configure the RTC Calendar, user application should enter
-             initialization mode. In this mode, the calendar counter is stopped
-             and its value can be updated. When the initialization sequence is
-             complete, the calendar restarts counting after 4 RTCCLK cycles.
-         (#) To read the calendar through the shadow registers after Calendar
-             initialization, calendar update or after wakeup from low power modes
-             the software must first clear the RSF flag. The software must then
-             wait until it is set again before reading the calendar, which means
-             that the calendar registers have been correctly copied into the
-             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
-             implements the above software sequence (RSF clear and RSF check).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the RTC peripheral
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
-{
-  /* Check the RTC peripheral state */
-  if (hrtc == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-  assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
-  assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
-  assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
-  assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
-  assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
-  assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
-  assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-  if (hrtc->State == HAL_RTC_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hrtc->Lock = HAL_UNLOCKED;
-
-    hrtc->AlarmAEventCallback          =  HAL_RTC_AlarmAEventCallback;        /* Legacy weak AlarmAEventCallback      */
-    hrtc->AlarmBEventCallback          =  HAL_RTCEx_AlarmBEventCallback;      /* Legacy weak AlarmBEventCallback      */
-    hrtc->TimeStampEventCallback       =  HAL_RTCEx_TimeStampEventCallback;   /* Legacy weak TimeStampEventCallback   */
-    hrtc->WakeUpTimerEventCallback     =  HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
-#if defined(RTC_TAMPER1_SUPPORT)
-    hrtc->Tamper1EventCallback         =  HAL_RTCEx_Tamper1EventCallback;     /* Legacy weak Tamper1EventCallback     */
-#endif
-    hrtc->Tamper2EventCallback         =  HAL_RTCEx_Tamper2EventCallback;     /* Legacy weak Tamper2EventCallback     */
-#if defined(RTC_TAMPER3_SUPPORT)
-    hrtc->Tamper3EventCallback         =  HAL_RTCEx_Tamper3EventCallback;     /* Legacy weak Tamper3EventCallback     */
-#endif
-
-    if (hrtc->MspInitCallback == NULL)
-    {
-      hrtc->MspInitCallback = HAL_RTC_MspInit;
-    }
-    /* Init the low level hardware */
-    hrtc->MspInitCallback(hrtc);
-
-    if (hrtc->MspDeInitCallback == NULL)
-    {
-      hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
-    }
-  }
-#else
-  if (hrtc->State == HAL_RTC_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hrtc->Lock = HAL_UNLOCKED;
-
-    /* Initialize RTC MSP */
-    HAL_RTC_MspInit(hrtc);
-  }
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-
-  /* Set RTC state */
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Clear RTC_CR FMT, OSEL and POL Bits */
-    hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
-    /* Set RTC_CR register */
-    hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-
-    /* Configure the RTC PRER */
-    hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
-    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
-    hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
-    hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
-
-    /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
-    {
-      if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_ERROR;
-      }
-    }
-
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_READY;
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @brief  DeInitialize the RTC peripheral.
-  * @param  hrtc RTC handle
-  * @note   This function doesn't reset the RTC Backup Data registers.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-
-  /* Set RTC state */
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Reset TR, DR and CR registers */
-    hrtc->Instance->TR = 0x00000000U;
-    hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
-    /* Reset All CR bits except CR[2:0] */
-    hrtc->Instance->CR &= RTC_CR_WUCKSEL;
-
-    tickstart = HAL_GetTick();
-
-    /* Wait till WUTWF flag is set and if Time out is reached exit */
-    while (((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        /* Set RTC state */
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Reset all RTC CR register bits */
-    hrtc->Instance->CR &= 0x00000000U;
-    hrtc->Instance->WUTR = RTC_WUTR_WUT;
-    hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
-    hrtc->Instance->ALRMAR = 0x00000000U;
-    hrtc->Instance->ALRMBR = 0x00000000U;
-    hrtc->Instance->SHIFTR = 0x00000000U;
-    hrtc->Instance->CALR = 0x00000000U;
-    hrtc->Instance->ALRMASSR = 0x00000000U;
-    hrtc->Instance->ALRMBSSR = 0x00000000U;
-
-    /* Reset ISR register and exit initialization mode */
-    hrtc->Instance->ISR = 0x00000000U;
-
-    /* Reset Tamper configuration register */
-    hrtc->Instance->TAMPCR = 0x00000000U;
-
-    /* Reset Option register */
-    hrtc->Instance->OR = 0x00000000U;
-
-    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
-    {
-      if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        return HAL_ERROR;
-      }
-    }
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-  if (hrtc->MspDeInitCallback == NULL)
-  {
-    hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
-  }
-
-  /* DeInit the low level hardware: CLOCK, NVIC.*/
-  hrtc->MspDeInitCallback(hrtc);
-
-#else
-  /* De-Initialize RTC MSP */
-  HAL_RTC_MspDeInit(hrtc);
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-
-  hrtc->State = HAL_RTC_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User RTC Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hrtc RTC handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
-  *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
-  *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
-  *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      WakeUp Timer Event Callback ID
-  *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID
-  *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID          Tamper 2 Callback ID
-  *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID          Tamper 3 Callback ID
-  *          @arg @ref HAL_RTC_MSPINIT_CB_ID                Msp Init callback ID
-  *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID              Msp DeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hrtc);
-
-  if (HAL_RTC_STATE_READY == hrtc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_RTC_ALARM_A_EVENT_CB_ID :
-        hrtc->AlarmAEventCallback = pCallback;
-        break;
-
-      case HAL_RTC_ALARM_B_EVENT_CB_ID :
-        hrtc->AlarmBEventCallback = pCallback;
-        break;
-
-      case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
-        hrtc->TimeStampEventCallback = pCallback;
-        break;
-
-      case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
-        hrtc->WakeUpTimerEventCallback = pCallback;
-        break;
-
-#if defined(RTC_TAMPER1_SUPPORT)
-      case HAL_RTC_TAMPER1_EVENT_CB_ID :
-        hrtc->Tamper1EventCallback = pCallback;
-        break;
-#endif /* RTC_TAMPER1_SUPPORT */
-
-      case HAL_RTC_TAMPER2_EVENT_CB_ID :
-        hrtc->Tamper2EventCallback = pCallback;
-        break;
-
-#if defined(RTC_TAMPER3_SUPPORT)
-      case HAL_RTC_TAMPER3_EVENT_CB_ID :
-        hrtc->Tamper3EventCallback = pCallback;
-        break;
-#endif /* RTC_TAMPER3_SUPPORT */
-
-      case HAL_RTC_MSPINIT_CB_ID :
-        hrtc->MspInitCallback = pCallback;
-        break;
-
-      case HAL_RTC_MSPDEINIT_CB_ID :
-        hrtc->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_RTC_STATE_RESET == hrtc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_RTC_MSPINIT_CB_ID :
-        hrtc->MspInitCallback = pCallback;
-        break;
-
-      case HAL_RTC_MSPDEINIT_CB_ID :
-        hrtc->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrtc);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister an RTC Callback
-  *         RTC callabck is redirected to the weak predefined callback
-  * @param  hrtc RTC handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
-  *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
-  *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
-  *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      WakeUp Timer Event Callback ID
-  *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID
-  *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID          Tamper 2 Callback ID
-  *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID          Tamper 3 Callback ID
-  *          @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
-  *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hrtc);
-
-  if (HAL_RTC_STATE_READY == hrtc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_RTC_ALARM_A_EVENT_CB_ID :
-        hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback;         /* Legacy weak AlarmAEventCallback    */
-        break;
-
-      case HAL_RTC_ALARM_B_EVENT_CB_ID :
-        hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback;          /* Legacy weak AlarmBEventCallback */
-        break;
-
-      case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
-        hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback;    /* Legacy weak TimeStampEventCallback    */
-        break;
-
-      case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
-        hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
-        break;
-
-#if defined(RTC_TAMPER1_SUPPORT)
-      case HAL_RTC_TAMPER1_EVENT_CB_ID :
-        hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback;         /* Legacy weak Tamper1EventCallback   */
-        break;
-#endif /* RTC_TAMPER1_SUPPORT */
-
-      case HAL_RTC_TAMPER2_EVENT_CB_ID :
-        hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback;         /* Legacy weak Tamper2EventCallback         */
-        break;
-
-#if defined(RTC_TAMPER3_SUPPORT)
-      case HAL_RTC_TAMPER3_EVENT_CB_ID :
-        hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback;         /* Legacy weak Tamper3EventCallback         */
-        break;
-#endif /* RTC_TAMPER3_SUPPORT */
-
-      case HAL_RTC_MSPINIT_CB_ID :
-        hrtc->MspInitCallback = HAL_RTC_MspInit;
-        break;
-
-      case HAL_RTC_MSPDEINIT_CB_ID :
-        hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_RTC_STATE_RESET == hrtc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_RTC_MSPINIT_CB_ID :
-        hrtc->MspInitCallback = HAL_RTC_MspInit;
-        break;
-
-      case HAL_RTC_MSPDEINIT_CB_ID :
-        hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrtc);
-
-  return status;
-}
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Initialize the RTC MSP.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize the RTC MSP.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group2
- *  @brief   RTC Time and Date functions
- *
-@verbatim
- ===============================================================================
-                 ##### RTC Time and Date functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Time and Date features
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set RTC current time.
-  * @param  hrtc RTC handle
-  * @param  sTime Pointer to Time structure
-  * @note   DayLightSaving and StoreOperation interfaces are deprecated.
-  *         To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions.
-  * @param  Format Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
-  assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if (Format == RTC_FORMAT_BIN)
-  {
-    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
-    {
-      assert_param(IS_RTC_HOUR12(sTime->Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
-    }
-    else
-    {
-      sTime->TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(sTime->Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sTime->Minutes));
-    assert_param(IS_RTC_SECONDS(sTime->Seconds));
-
-    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
-                        (((uint32_t)sTime->TimeFormat) << 16U));
-  }
-  else
-  {
-    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
-    {
-      assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
-    }
-    else
-    {
-      sTime->TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
-    }
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
-    tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
-              ((uint32_t)(sTime->Minutes) << 8U) | \
-              ((uint32_t)sTime->Seconds) | \
-              ((uint32_t)(sTime->TimeFormat) << 16U));
-  }
-  UNUSED(tmpreg);
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Set the RTC_TR register */
-    hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
-    /* Clear the bits to be configured (Deprecated. Use HAL_RTC_DST_xxx functions instead) */
-    hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP);
-
-    /* Configure the RTC_CR register (Deprecated. Use HAL_RTC_DST_xxx functions instead) */
-    hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
-    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
-    {
-      if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_ERROR;
-      }
-    }
-
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    hrtc->State = HAL_RTC_STATE_READY;
-
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @brief  Get RTC current time.
-  * @param  hrtc RTC handle
-  * @param  sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned
-  *                with input format (BIN or BCD), also SubSeconds field returning the
-  *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
-  *                factor to be used for second fraction ratio computation.
-  * @param  Format Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
-  *        value in second fraction ratio with time unit following generic formula:
-  *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
-  *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
-  * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
-  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
-  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
-  *        to ensure consistency between the time and date values.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get subseconds structure field from the corresponding register*/
-  sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
-
-  /* Get SecondFraction structure field from the corresponding register field*/
-  sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
-
-  /* Get the TR register */
-  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
-
-  /* Fill the structure fields with the read parameters */
-  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
-  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
-  sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
-  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
-
-  /* Check the input parameters format */
-  if (Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the time structure parameters to Binary format */
-    sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
-    sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
-    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set RTC current date.
-  * @param  hrtc RTC handle
-  * @param  sDate Pointer to date structure
-  * @param  Format specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
-  uint32_t datetmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
-  {
-    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
-  }
-
-  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
-
-  if (Format == RTC_FORMAT_BIN)
-  {
-    assert_param(IS_RTC_YEAR(sDate->Year));
-    assert_param(IS_RTC_MONTH(sDate->Month));
-    assert_param(IS_RTC_DATE(sDate->Date));
-
-    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
-                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
-                  ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
-                  ((uint32_t)sDate->WeekDay << 13U));
-  }
-  else
-  {
-    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
-    assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
-    assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
-
-    datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
-                  (((uint32_t)sDate->Month) << 8U) | \
-                  ((uint32_t)sDate->Date) | \
-                  (((uint32_t)sDate->WeekDay) << 13U));
-  }
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Set the RTC_DR register */
-    hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
-    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
-    {
-      if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_ERROR;
-      }
-    }
-
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    hrtc->State = HAL_RTC_STATE_READY ;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @brief  Get RTC current date.
-  * @param  hrtc RTC handle
-  * @param  sDate Pointer to Date structure
-  * @param  Format Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN:  Binary data format
-  *            @arg RTC_FORMAT_BCD:  BCD data format
-  * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
-  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
-  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
-  uint32_t datetmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get the DR register */
-  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
-
-  /* Fill the structure fields with the read parameters */
-  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
-  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
-  sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
-  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
-
-  /* Check the input parameters format */
-  if (Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the date structure parameters to Binary format */
-    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
-    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
-    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Daylight Saving Time, adda one hour to the calendar in one
-  *         single operation without going through the initialization procedure.
-  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
-{
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  SET_BIT(hrtc->Instance->CR, RTC_CR_ADD1H);
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-}
-
-/**
-  * @brief  Daylight Saving Time, subtracts one hour from the calendar in one
-  *         single operation without going through the initialization procedure.
-  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
-{
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  SET_BIT(hrtc->Instance->CR, RTC_CR_SUB1H);
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-}
-
-/**
-  * @brief  Daylight Saving Time, sets the store operation bit.
-  * @note   It can be used by the software in order to memorize the DST status.
-  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
-{
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  SET_BIT(hrtc->Instance->CR, RTC_CR_BKP);
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-}
-
-/**
-  * @brief  Daylight Saving Time, clears the store operation bit.
-  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
-{
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BKP);
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-}
-
-/**
-  * @brief  Daylight Saving Time, reads the store operation bit.
-  * @param  hrtc RTC handle
-  * @retval operation see RTC_StoreOperation_Definitions
-  */
-uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
-{
-  return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group3
- *  @brief   RTC Alarm functions
- *
-@verbatim
- ===============================================================================
-                 ##### RTC Alarm functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Alarm feature
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Set the specified RTC Alarm.
-  * @param  hrtc RTC handle
-  * @param  sAlarm Pointer to Alarm structure
-  * @param  Format Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
-  uint32_t tickstart;
-  uint32_t tmpreg, subsecondtmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(sAlarm->Alarm));
-  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if (Format == RTC_FORMAT_BIN)
-  {
-    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
-    {
-      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
-    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
-    if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
-    }
-
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-  else
-  {
-    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
-    {
-      assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-    }
-
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
-    if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
-    }
-
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
-              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-
-  /* Configure the Alarm A or Alarm B Sub Second registers */
-  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Alarm register */
-  if (sAlarm->Alarm == RTC_ALARM_A)
-  {
-    /* Disable the Alarm A interrupt */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
-    /* Configure the Alarm A Sub Second register */
-    hrtc->Instance->ALRMASSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMA_ENABLE(hrtc);
-  }
-  else
-  {
-    /* Disable the Alarm B interrupt */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
-    /* Configure the Alarm B Sub Second register */
-    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc);
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the specified RTC Alarm with Interrupt.
-  * @param  hrtc RTC handle
-  * @param  sAlarm Pointer to Alarm structure
-  * @param  Format Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @note   The Alarm register can only be written when the corresponding Alarm
-  *         is disabled (Use the HAL_RTC_DeactivateAlarm()).
-  * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
-  uint32_t tickstart;
-  uint32_t tmpreg, subsecondtmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(sAlarm->Alarm));
-  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if (Format == RTC_FORMAT_BIN)
-  {
-    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
-    {
-      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
-    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
-    if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
-    }
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-  else
-  {
-    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
-    {
-      assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-    }
-
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
-    if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
-    }
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
-              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-  /* Configure the Alarm A or Alarm B Sub Second registers */
-  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Alarm register */
-  if (sAlarm->Alarm == RTC_ALARM_A)
-  {
-    /* Disable the Alarm A interrupt */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* Clear flag alarm A */
-    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
-    /* Configure the Alarm A Sub Second register */
-    hrtc->Instance->ALRMASSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMA_ENABLE(hrtc);
-    /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
-  }
-  else
-  {
-    /* Disable the Alarm B interrupt */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* Clear flag alarm B */
-    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
-    /* Configure the Alarm B Sub Second register */
-    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc);
-    /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
-  }
-
-  /* RTC Alarm Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_ALARM_EXTI_ENABLE_IT();
-
-  __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate the specified RTC Alarm.
-  * @param  hrtc RTC handle
-  * @param  Alarm Specifies the Alarm.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_ALARM_A:  AlarmA
-  *            @arg RTC_ALARM_B:  AlarmB
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALARM(Alarm));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  if (Alarm == RTC_ALARM_A)
-  {
-    /* AlarmA */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
-    {
-      if ((HAL_GetTick()  - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  else
-  {
-    /* AlarmB */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the RTC Alarm value and masks.
-  * @param  hrtc RTC handle
-  * @param  sAlarm Pointer to Date structure
-  * @param  Alarm Specifies the Alarm.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_ALARM_A: AlarmA
-  *             @arg RTC_ALARM_B: AlarmB
-  * @param  Format Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
-{
-  uint32_t tmpreg, subsecondtmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(Alarm));
-
-  if (Alarm == RTC_ALARM_A)
-  {
-    /* AlarmA */
-    sAlarm->Alarm = RTC_ALARM_A;
-
-    tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
-    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS);
-
-    /* Fill the structure with the read parameters */
-    sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
-    sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
-    sAlarm->AlarmTime.Seconds = (uint8_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
-    sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
-    sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
-    sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
-    sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
-    sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-  }
-  else
-  {
-    sAlarm->Alarm = RTC_ALARM_B;
-
-    tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
-    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
-
-    /* Fill the structure with the read parameters */
-    sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> 16U);
-    sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> 8U);
-    sAlarm->AlarmTime.Seconds = (uint8_t)(tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
-    sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> 16U);
-    sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
-    sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> 24U);
-    sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL);
-    sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-  }
-
-  if (Format == RTC_FORMAT_BIN)
-  {
-    sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-    sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
-    sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
-    sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle Alarm interrupt request.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the AlarmA interrupt source enable status */
-  if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U)
-  {
-    /* Get the pending status of the AlarmA Interrupt */
-    if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U)
-    {
-      /* AlarmA callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-      hrtc->AlarmAEventCallback(hrtc);
-#else
-      HAL_RTC_AlarmAEventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-      /* Clear the AlarmA interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-    }
-  }
-
-  /* Get the AlarmB interrupt source enable status */
-  if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U)
-  {
-    /* Get the pending status of the AlarmB Interrupt */
-    if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U)
-    {
-      /* AlarmB callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-      hrtc->AlarmBEventCallback(hrtc);
-#else
-      HAL_RTCEx_AlarmBEventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-      /* Clear the AlarmB interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-    }
-  }
-  /* Clear the EXTI's line Flag for RTC Alarm */
-  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  Alarm A callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTC_AlarmAEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Handle AlarmA Polling request.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-
-  uint32_t tickstart = HAL_GetTick();
-
-  while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Alarm interrupt pending bit */
-  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group4
- *  @brief   Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-                     ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Wait for RTC Time and Date Synchronization
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
-  *         synchronized with RTC APB clock.
-  * @note   The RTC Resynchronization mode is write protected, use the
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @note   To read the calendar through the shadow registers after Calendar
-  *         initialization, calendar update or after wakeup from low power modes
-  *         the software must first clear the RSF flag.
-  *         The software must then wait until it is set again before reading
-  *         the calendar, which means that the calendar registers have been
-  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart;
-
-  /* Clear RSF flag */
-  hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-
-  tickstart = HAL_GetTick();
-
-  /* Wait the registers to be synchronised */
-  while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group5
- *  @brief   Peripheral State functions
- *
-@verbatim
- ===============================================================================
-                     ##### Peripheral State functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Get RTC state
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Return the RTC handle state.
-  * @param  hrtc RTC handle
-  * @retval HAL state
-  */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
-{
-  /* Return RTC handle state */
-  return hrtc->State;
-}
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Private_Functions
-  * @{
-  */
-/**
-  * @brief  Enter the RTC Initialization mode.
-  * @note   The RTC Initialization mode is write protected, use the
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart;
-
-  /* Check if the Initialization mode is set */
-  if ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
-  {
-    /* Set the Initialization mode */
-    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC is in INIT state and if Time out is reached exit */
-    while ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
-    {
-      if ((HAL_GetTick()  - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Convert a 2 digit decimal to BCD format.
-  * @param  Value Byte to be converted
-  * @retval Converted byte
-  */
-uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
-  uint32_t bcdhigh = 0U;
-  uint8_t Param = Value;
-
-  while (Param >= 10U)
-  {
-    bcdhigh++;
-    Param -= 10U;
-  }
-
-  return ((uint8_t)(bcdhigh << 4U) | Param);
-}
-
-/**
-  * @brief  Convert from 2 digit BCD to Binary.
-  * @param  Value BCD value to be converted
-  * @retval Converted word
-  */
-uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
-  uint32_t tmp;
-  tmp = (((uint32_t)Value & 0xF0U) >> 4U) * 10U;
-  return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU));
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c
deleted file mode 100644
index ddfd71ce98..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c
+++ /dev/null
@@ -1,1833 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_rtc_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended RTC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Real Time Clock (RTC) Extended peripheral:
-  *           + RTC Time Stamp functions
-  *           + RTC Tamper functions
-  *           + RTC Wake-up functions
-  *           + Extended Control functions
-  *           + Extended RTC features functions
-  *
-  @verbatim
-  ==============================================================================
-                  ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    (+) Enable the RTC domain access.
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
-        format using the HAL_RTC_Init() function.
-
-  *** RTC Wakeup configuration ***
-  ================================
-  [..]
-    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
-        function. You can also configure the RTC Wakeup timer with interrupt mode
-        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
-    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
-        function.
-
-  *** Outputs configuration ***
-  =============================
-  [..] The RTC has 2 different outputs:
-    (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
-        and WaKeUp signals.
-        To output the selected RTC signal, use the HAL_RTC_Init() function.
-    (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
-        To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
-    (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB14) for STM32L05x/6x/7x/8x
-      and (PA2, PB14) for STM32L03x/4x managed on the RTC_OR register.
-    (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
-        automatically configured in output alternate function.
-
-  *** Smooth digital Calibration configuration ***
-  ================================================
-  [..]
-    (+) Configure the RTC Original Digital Calibration Value and the corresponding
-        calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
-        function.
-
-  *** TimeStamp configuration ***
-  ===============================
-  [..]
-    (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
-        HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
-        interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
-    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
-        function.
-
-  *** Tamper configuration ***
-  ============================
-  [..]
-        (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
-        or Level according to the Tamper filter (if equal to 0 Edge else Level)
-        value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
-        Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
-        with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
-    (+) The default configuration of the Tamper erases the backup registers. To avoid
-        erase, enable the NoErase field on the RTC_TAMPCR register.
-
-  *** Backup Data Registers configuration ***
-  ===========================================
-  [..]
-    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
-        function.
-    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
-        function.
-
-   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RTCEx
-  * @brief RTC Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
-#define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
-                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
-                                       (uint32_t)RTC_TAMPCR_TAMP1IE   | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF  |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF  |\
-                                       (uint32_t)RTC_TAMPCR_TAMP3IE   | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)
-#elif defined(RTC_TAMPER1_SUPPORT)
-#define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
-                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
-                                       (uint32_t)RTC_TAMPCR_TAMP1IE   | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF  |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF)
-#elif defined(RTC_TAMPER3_SUPPORT)
-#define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
-                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF  |\
-                                       (uint32_t)RTC_TAMPCR_TAMP3IE   | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)
-#else
-#define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
-                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF)
-#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup RTCEx_Exported_Functions
-  * @{
-  */
-
-
-/** @addtogroup RTCEx_Exported_Functions_Group1
- *  @brief   RTC TimeStamp and Tamper functions
-  *
-@verbatim
- ===============================================================================
-                 ##### RTC TimeStamp and Tamper functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure TimeStamp feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set TimeStamp.
-  * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  hrtc RTC handle
-  * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
-  *         activated.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
-  *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
-  *                                         falling edge of the related pin.
-  * @param  RTC_TimeStampPin specifies the RTC TimeStamp Pin.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin on STM32L05x/6x/7x/8x
-  *                                            and PA2 on STM32L03x/4x/2x/1x.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
-  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  tmpreg |= TimeStampEdge;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Clear the Timestamp Flag */
-  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-
-  /* Clear the Timestamp overrun Flag */
-  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set TimeStamp with Interrupt.
-  * @param  hrtc RTC handle
-  * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
-  *         activated.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
-  *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
-  *                                         falling edge of the related pin.
-  * @param  RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin on STM32L05x/6x/7x/8x
-  *                                            and PA2 on STM32L03x/4x/2x/1x.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
-  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  tmpreg |= TimeStampEdge;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Clear the Timestamp Flag */
-  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-
-  /* Clear the Timestamp overrun Flag */
-  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
-  /* Enable IT timestamp */
-  __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS);
-
-  /* RTC timestamp Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate TimeStamp.
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tmpreg;
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* In case of interrupt mode is used, the interrupt source must disabled */
-  __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the RTC TimeStamp value.
-  * @param  hrtc RTC handle
-  * @param  sTimeStamp Pointer to Time structure
-  * @param  sTimeStampDate Pointer to Date structure
-  * @param  Format specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
-{
-  uint32_t tmptime, tmpdate;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get the TimeStamp time and date registers values */
-  tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
-  tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
-
-  /* Fill the Time structure fields with the read parameters */
-  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
-  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
-  sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
-  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
-  sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
-
-  /* Fill the Date structure fields with the read parameters */
-  sTimeStampDate->Year = 0U;
-  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
-  sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
-  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
-
-  /* Check the input parameters format */
-  if (Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the TimeStamp structure parameters to Binary format */
-    sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
-    sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
-    sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
-
-    /* Convert the DateTimeStamp structure parameters to Binary format */
-    sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
-    sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
-    sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
-  }
-
-  /* Clear the TIMESTAMP Flags */
-  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set Tamper
-  * @note   By calling this API we disable the tamper interrupt for all tampers.
-  * @param  hrtc RTC handle
-  * @param  sTamper Pointer to Tamper Structure.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
-  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
-  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
-  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
-  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
-  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
-  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
-  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
-  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Configure the tamper trigger */
-  if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
-  {
-    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
-  }
-
-  if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
-  {
-    sTamper->NoErase = 0U;
-#if defined(RTC_TAMPER1_SUPPORT)
-    if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
-    }
-#endif /* RTC_TAMPER1_SUPPORT */
-    if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
-    }
-#if defined(RTC_TAMPER3_SUPPORT)
-    if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
-    }
-#endif /* RTC_TAMPER3_SUPPORT */
-  }
-
-  if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
-  {
-    sTamper->MaskFlag = 0U;
-#if defined(RTC_TAMPER1_SUPPORT)
-    if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
-    }
-#endif /* RTC_TAMPER1_SUPPORT */
-    if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
-    }
-#if defined(RTC_TAMPER3_SUPPORT)
-    if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
-    }
-#endif /* RTC_TAMPER3_SUPPORT */
-  }
-
-  /* Configure the RTC_TAMPCR register */
-  tmpreg = (uint32_t)((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase | \
-                      (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | \
-                      (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | (uint32_t)sTamper->TimeStampOnTamperDetection);
-
-  hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK);
-
-  hrtc->Instance->TAMPCR |= tmpreg;
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set Tamper with interrupt.
-  * @note   By calling this API we force the tamper interrupt for all tampers.
-  * @param  hrtc RTC handle
-  * @param  sTamper Pointer to RTC Tamper.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
-  assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));
-  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
-  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
-  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
-  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
-  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
-  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
-  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
-  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Configure the tamper trigger */
-  if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
-  {
-    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
-  }
-
-  if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
-  {
-    sTamper->NoErase = 0U;
-#if defined(RTC_TAMPER1_SUPPORT)
-    if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
-    }
-#endif /* RTC_TAMPER1_SUPPORT */
-    if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
-    }
-#if defined(RTC_TAMPER3_SUPPORT)
-    if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
-    }
-#endif /* RTC_TAMPER3_SUPPORT */
-  }
-
-  if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
-  {
-    sTamper->MaskFlag = 0U;
-#if defined(RTC_TAMPER1_SUPPORT)
-    if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
-    }
-#endif /* RTC_TAMPER1_SUPPORT */
-    if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
-    }
-#if defined(RTC_TAMPER3_SUPPORT)
-    if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
-    }
-#endif /* RTC_TAMPER3_SUPPORT */
-  }
-
-  /* Configure the RTC_TAMPCR register */
-  tmpreg = (uint32_t)((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase | \
-                      (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency                                | \
-                      (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | (uint32_t)sTamper->TimeStampOnTamperDetection);
-
-  hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK);
-
-  hrtc->Instance->TAMPCR |= tmpreg;
-
-  /* RTC Tamper Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate Tamper.
-  * @param  hrtc RTC handle
-  * @param  Tamper Selected tamper pin.
-  *          This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
-{
-  assert_param(IS_RTC_TAMPER(Tamper));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the selected Tamper pin */
-  hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper);
-
-#if defined(RTC_TAMPER1_SUPPORT)
-  if ((Tamper & RTC_TAMPER_1) != 0U)
-  {
-    /* Disable the Tamper1 interrupt */
-    hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1));
-  }
-#endif /* RTC_TAMPER1_SUPPORT */
-  if ((Tamper & RTC_TAMPER_2) != 0U)
-  {
-    /* Disable the Tamper2 interrupt */
-    hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2));
-  }
-#if defined(RTC_TAMPER3_SUPPORT)
-  if ((Tamper & RTC_TAMPER_3) != 0U)
-  {
-    /* Disable the Tamper3 interrupt */
-    hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3));
-  }
-
-#endif /* RTC_TAMPER3_SUPPORT */
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle TimeStamp interrupt request.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the TimeStamp interrupt source enable status */
-  if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U)
-  {
-    /* Get the pending status of the TIMESTAMP Interrupt */
-    if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U)
-    {
-      /* TIMESTAMP callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-      hrtc->TimeStampEventCallback(hrtc);
-#else
-      HAL_RTCEx_TimeStampEventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-      /* Clear the TIMESTAMP interrupt pending bit */
-      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-    }
-  }
-
-#if defined(RTC_TAMPER1_SUPPORT)
-  /* Get the Tamper1 interrupts source enable status */
-  if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U)
-  {
-    /* Get the pending status of the Tamper1 Interrupt */
-    if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U)
-    {
-      /* Tamper1 callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-      hrtc->Tamper1EventCallback(hrtc);
-#else
-      HAL_RTCEx_Tamper1EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-      /* Clear the Tamper1 interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
-    }
-  }
-#endif /* RTC_TAMPER1_SUPPORT */
-
-
-  /* Get the Tamper2 interrupts source enable status */
-  if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != 0U)
-  {
-    /* Get the pending status of the Tamper2 Interrupt */
-    if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U)
-    {
-      /* Tamper2 callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-      hrtc->Tamper2EventCallback(hrtc);
-#else
-      HAL_RTCEx_Tamper2EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-      /* Clear the Tamper2 interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
-    }
-  }
-
-#if defined(RTC_TAMPER3_SUPPORT)
-  /* Get the Tamper3 interrupts source enable status */
-  if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != 0U)
-  {
-    /* Get the pending status of the Tamper3 Interrupt */
-    if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U)
-    {
-      /* Tamper3 callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-      hrtc->Tamper3EventCallback(hrtc);
-#else
-      HAL_RTCEx_Tamper3EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-      /* Clear the Tamper3 interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
-    }
-  }
-#endif /* RTC_TAMPER3_SUPPORT */
-
-  /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  TimeStamp callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
-  */
-}
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
-  * @brief  Tamper 1 callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
-   */
-}
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
-  * @brief  Tamper 2 callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
-   */
-}
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
-  * @brief  Tamper 3 callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
-   */
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-/**
-  * @brief  Handle TimeStamp polling request.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U)
-  {
-    if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U)
-    {
-      /* Clear the TIMESTAMP OverRun Flag */
-      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-
-      /* Change TIMESTAMP state */
-      hrtc->State = HAL_RTC_STATE_ERROR;
-
-      return HAL_ERROR;
-    }
-
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
-  * @brief  Handle Tamper 1 Polling.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == 0U)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
-  * @brief  Handle Tamper 2 Polling.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == 0U)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
-  * @brief  Handle Tamper 3 Polling.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == 0U)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTCEx_Exported_Functions_Group2
-  * @brief    RTC Wake-up functions
-  *
-@verbatim
- ===============================================================================
-                        ##### RTC Wake-up functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Wake-up feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set wake up timer.
-  * @param  hrtc RTC handle
-  * @param  WakeUpCounter Wake up counter
-  * @param  WakeUpClock Wake up clock
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
-  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
-  if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
-  {
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
-    while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 1U)
-    {
-      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  tickstart = HAL_GetTick();
-
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Clear the Wakeup Timer clock source bits in CR register */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
-  /* Configure the clock source */
-  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
-  /* Configure the Wakeup Timer counter */
-  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
-  /* Enable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set wake up timer with interrupt.
-  * @param  hrtc RTC handle
-  * @param  WakeUpCounter Wake up counter
-  * @param  WakeUpClock Wake up clock
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
-  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
-  if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
-  {
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
-    while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 1U)
-    {
-      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /* Disable the Wake-Up timer */
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  /* Clear flag Wake-Up */
-  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
-  tickstart = HAL_GetTick();
-
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Configure the Wakeup Timer counter */
-  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
-  /* Clear the Wakeup Timer clock source bits in CR register */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
-  /* Configure the clock source */
-  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
-  /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-
-  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
-
-  /* Configure the Interrupt in the RTC_CR register */
-  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT);
-
-  /* Enable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate wake up timer counter.
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart;
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Disable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  /* In case of interrupt mode is used, the interrupt source must disabled */
-  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT);
-
-  tickstart = HAL_GetTick();
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get wake up timer counter.
-  * @param  hrtc RTC handle
-  * @retval Counter value
-  */
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the counter value */
-  return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
-}
-
-/**
-  * @brief  Handle Wake Up Timer interrupt request.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the pending status of the WAKEUPTIMER Interrupt */
-  if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U)
-  {
-    /* WAKEUPTIMER callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-    hrtc->WakeUpTimerEventCallback(hrtc);
-#else
-    HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-    /* Clear the WAKEUPTIMER interrupt pending bit */
-    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-  }
-
-  /* Clear the EXTI's line Flag for RTC WakeUpTimer */
-  __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  Wake Up Timer callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
-   */
-}
-
-
-/**
-  * @brief  Handle Wake Up Timer Polling.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the WAKEUPTIMER Flag */
-  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup RTCEx_Exported_Functions_Group3
-  * @brief    Extended Peripheral Control functions
-  *
-@verbatim
- ===============================================================================
-              ##### Extended Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Write a data in a specified RTC Backup data register
-      (+) Read a data in a specified RTC Backup data register
-      (+) Set the Coarse calibration parameters.
-      (+) Deactivate the Coarse calibration parameters
-      (+) Set the Smooth calibration parameters.
-      (+) Configure the Synchronization Shift Control Settings.
-      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Enable the RTC reference clock detection.
-      (+) Disable the RTC reference clock detection.
-      (+) Enable the Bypass Shadow feature.
-      (+) Disable the Bypass Shadow feature.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Write a data in a specified RTC Backup data register.
-  * @param  hrtc RTC handle
-  * @param  BackupRegister RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
-  *                                 specify the register.
-  * @param  Data Data to be written in the specified RTC Backup data register.
-  * @retval None
-  */
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
-{
-  uint32_t tmp;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(BackupRegister));
-
-  tmp = (uint32_t) & (hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4U);
-
-  /* Write the specified register */
-  *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
-  * @brief  Reads data from the specified RTC Backup data Register.
-  * @param  hrtc RTC handle
-  * @param  BackupRegister RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
-  *                                 specify the register.
-  * @retval Read value
-  */
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
-{
-  uint32_t tmp;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(BackupRegister));
-
-  tmp = (uint32_t) & (hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4U);
-
-  /* Read the specified register */
-  return (*(__IO uint32_t *)tmp);
-}
-
-/**
-  * @brief  Set the Smooth calibration parameters.
-  * @param  hrtc RTC handle
-  * @param  SmoothCalibPeriod Select the Smooth Calibration Period.
-  *          This parameter can be can be one of the following values :
-  *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
-  *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
-  *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
-  * @param  SmoothCalibPlusPulses Select to Set or reset the CALP bit.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
-  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
-  * @param  SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
-  *          This parameter can be one any value from 0 to 0x000001FF.
-  * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
-  *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
-  *         SmoothCalibMinusPulsesValue mut be equal to 0.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
-  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
-  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* check if a calibration is pending*/
-  if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U)
-  {
-    tickstart = HAL_GetTick();
-
-    /* check if a calibration is pending*/
-    while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U)
-    {
-      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        /* Change RTC state */
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Configure the Smooth calibration settings */
-  hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the Synchronization Shift Control Settings.
-  * @note   When REFCKON is set, firmware must not write to Shift control register.
-  * @param  hrtc RTC handle
-  * @param  ShiftAdd1S Select to add or not 1 second to the time calendar.
-  *          This parameter can be one of the following values :
-  *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
-  *             @arg RTC_SHIFTADD1S_RESET: No effect.
-  * @param  ShiftSubFS Select the number of Second Fractions to substitute.
-  *          This parameter can be one any value from 0 to 0x7FFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
-  assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  tickstart = HAL_GetTick();
-
-  /* Wait until the shift is completed*/
-  while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Check if the reference clock detection is disabled */
-  if ((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U)
-  {
-    /* Configure the Shift settings */
-    hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
-
-    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
-    {
-      if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_ERROR;
-      }
-    }
-  }
-  else
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Change RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc RTC handle
-  * @param  CalibOutput : Select the Calibration output Selection .
-  *          This parameter can be one of the following values:
-  *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
-  *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Clear flags before config */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
-
-  /* Configure the RTC_CR register */
-  hrtc->Instance->CR |= (uint32_t)CalibOutput;
-
-  __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enable the RTC reference clock detection.
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the RTC reference clock detection.
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enable the Bypass Shadow feature.
-  * @param  hrtc RTC handle
-  * @note   When the Bypass Shadow is enabled the calendar value are taken
-  *         directly from the Calendar counter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set the BYPSHAD bit */
-  hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the Bypass Shadow feature.
-  * @param  hrtc RTC handle
-  * @note   When the Bypass Shadow is enabled the calendar value are taken
-  *         directly from the Calendar counter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Reset the BYPSHAD bit */
-  hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTCEx_Exported_Functions_Group4
-  * @brief    Extended features functions
-  *
-@verbatim
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) RTC Alram B callback
-      (+) RTC Poll for Alarm B request
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Alarm B callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Handle Alarm B Polling request.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == 0U)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Alarm Flag */
-  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c
deleted file mode 100644
index 7db92a31e4..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c
+++ /dev/null
@@ -1,2939 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_smartcard.c
-  * @author  MCD Application Team
-  * @brief   SMARTCARD HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the SMARTCARD peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Error functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The SMARTCARD HAL driver can be used as follows:
-
-    (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
-    (#) Associate a USART to the SMARTCARD handle hsmartcard.
-    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
-        (++) Enable the USARTx interface clock.
-        (++) USART pins configuration:
-             (+++) Enable the clock for the USART GPIOs.
-             (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
-        (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
-             and HAL_SMARTCARD_Receive_IT() APIs):
-             (+++) Configure the USARTx interrupt priority.
-             (+++) Enable the NVIC USART IRQ handle.
-        (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
-             and HAL_SMARTCARD_Receive_DMA() APIs):
-             (+++) Declare a DMA handle structure for the Tx/Rx channel.
-             (+++) Enable the DMAx interface clock.
-             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-             (+++) Configure the DMA Tx/Rx channel.
-             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
-             (+++) Configure the priority and enable the NVIC for the transfer complete
-                   interrupt on the DMA Tx/Rx channel.
-
-    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
-        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
-        error enabling or disabling in the hsmartcard handle Init structure.
-
-    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
-        in the hsmartcard handle AdvancedInit structure.
-
-    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
-        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-             by calling the customized HAL_SMARTCARD_MspInit() API.
-        [..]
-        (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
-             RXNE interrupt and Error Interrupts) will be managed using the macros
-             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
-
-    [..]
-    [..] Three operation modes are available within this driver :
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
-       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..]
-       (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
-       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
-            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
-       (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
-       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
-            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
-       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..]
-       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
-       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
-            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
-       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
-       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
-            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
-       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
-
-     *** SMARTCARD HAL driver macros list ***
-     ========================================
-     [..]
-       Below the list of most used macros in SMARTCARD HAL driver.
-
-       (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
-       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
-       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
-       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
-       (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
-
-     [..]
-       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
-
-    ##### Callback registration #####
-    ==================================
-
-    [..]
-    The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
-    allows the user to configure dynamically the driver callbacks.
-
-    [..]
-    Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
-    Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-    (+) MspInitCallback           : SMARTCARD MspInit.
-    (+) MspDeInitCallback         : SMARTCARD MspDeInit.
-    This function takes as parameters the HAL peripheral handle, the Callback ID
-    and a pointer to the user callback function.
-
-    [..]
-    Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-    and the Callback ID.
-    This function allows to reset following callbacks:
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-    (+) MspInitCallback           : SMARTCARD MspInit.
-    (+) MspDeInitCallback         : SMARTCARD MspDeInit.
-
-    [..]
-    By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
-    Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
-    and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
-    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
-
-    [..]
-    Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
-    Exception done MspInit/MspDeInit that can be registered/unregistered
-    in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
-    MspInit/DeInit callbacks can be used during the Init/DeInit.
-    In that case first register the MspInit/MspDeInit user callbacks
-    using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
-    or HAL_SMARTCARD_Init() function.
-
-    [..]
-    When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
-    not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
-
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-#if !defined (STM32L010x4) && !defined (STM32L010x6)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SMARTCARD SMARTCARD
-  * @brief HAL SMARTCARD module driver
-  * @{
-  */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
-  * @{
-  */
-#define SMARTCARD_TEACK_REACK_TIMEOUT  1000U       /*!< SMARTCARD TX or RX enable acknowledge time-out value */
-
-#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
-                                        USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
-
-#define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
-                                          USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
-
-#define USART_CR2_FIELDS  ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
-                                      USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
-
-#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | \
-                                      USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
-
-#define USART_BRR_MIN  0x10U        /*!< USART BRR minimum authorized value */
-
-#define USART_BRR_MAX  0x0000FFFFU  /*!< USART BRR maximum authorized value */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SMARTCARD_Private_Functions
-  * @{
-  */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
-                                                          FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
-  * @{
-  */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief    Initialization and Configuration functions
-  *
-@verbatim
-  ==============================================================================
-              ##### Initialization and Configuration functions #####
-  ==============================================================================
-  [..]
-  This subsection provides a set of functions allowing to initialize the USARTx
-  associated to the SmartCard.
-  (+) These parameters can be configured:
-      (++) Baud Rate
-      (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
-      (++) Receiver/transmitter modes
-      (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
-      (++) Prescaler value
-      (++) Guard bit time
-      (++) NACK enabling or disabling on transmission error
-
-  (+) The following advanced features can be configured as well:
-      (++) TX and/or RX pin level inversion
-      (++) data logical level inversion
-      (++) RX and TX pins swap
-      (++) RX overrun detection disabling
-      (++) DMA disabling on RX error
-      (++) MSB first on communication line
-      (++) Time out enabling (and if activated, timeout value)
-      (++) Block length
-      (++) Auto-retry counter
-  [..]
-  The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
-  (details for the procedures are available in reference manual).
-
-@endverbatim
-
-  The USART frame format is given in the following table:
-
-    Table 1. USART frame format.
-    +---------------------------------------------------------------+
-    | M1M0 bits |  PCE bit  |            USART frame                |
-    |-----------------------|---------------------------------------|
-    |     01    |    1      |    | SB | 8 bit data | PB | STB |     |
-    +---------------------------------------------------------------+
-
-
-  * @{
-  */
-
-/**
-  * @brief  Initialize the SMARTCARD mode according to the specified
-  *         parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Check the SMARTCARD handle allocation */
-  if (hsmartcard == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the USART associated to the SMARTCARD handle */
-  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
-
-  if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hsmartcard->Lock = HAL_UNLOCKED;
-
-#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
-    SMARTCARD_InitCallbacksToDefault(hsmartcard);
-
-    if (hsmartcard->MspInitCallback == NULL)
-    {
-      hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
-    }
-
-    /* Init the low level hardware */
-    hsmartcard->MspInitCallback(hsmartcard);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_SMARTCARD_MspInit(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-  }
-
-  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
-
-  /* Disable the Peripheral to set smartcard mode */
-  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
-  /* In SmartCard mode, the following bits must be kept cleared:
-  - LINEN in the USART_CR2 register,
-  - HDSEL and IREN  bits in the USART_CR3 register.*/
-  CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
-  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
-
-  /* set the USART in SMARTCARD mode */
-  SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
-
-  /* Set the SMARTCARD Communication parameters */
-  if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the SMARTCARD transmission completion indication */
-  SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
-
-  if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
-  {
-    SMARTCARD_AdvFeatureConfig(hsmartcard);
-  }
-
-  /* Enable the Peripheral */
-  SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
-  /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
-  return (SMARTCARD_CheckIdleState(hsmartcard));
-}
-
-/**
-  * @brief  DeInitialize the SMARTCARD peripheral.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Check the SMARTCARD handle allocation */
-  if (hsmartcard == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the USART/UART associated to the SMARTCARD handle */
-  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
-
-  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
-  WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
-  WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
-  WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
-  WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
-  WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
-
-  /* DeInit the low level hardware */
-#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
-  if (hsmartcard->MspDeInitCallback == NULL)
-  {
-    hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  hsmartcard->MspDeInitCallback(hsmartcard);
-#else
-  HAL_SMARTCARD_MspDeInit(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-  hsmartcard->gState    = HAL_SMARTCARD_STATE_RESET;
-  hsmartcard->RxState   = HAL_SMARTCARD_STATE_RESET;
-
-  /* Process Unlock */
-  __HAL_UNLOCK(hsmartcard);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the SMARTCARD MSP.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmartcard);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_MspInit can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize the SMARTCARD MSP.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmartcard);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_MspDeInit can be implemented in the user file
-   */
-}
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User SMARTCARD Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hsmartcard smartcard handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
-                                                 HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
-                                                 pSMARTCARD_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hsmartcard);
-
-  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-
-      case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
-        hsmartcard->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
-        hsmartcard->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_ERROR_CB_ID :
-        hsmartcard->ErrorCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
-        hsmartcard->AbortCpltCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        hsmartcard->AbortTransmitCpltCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
-        hsmartcard->AbortReceiveCpltCallback = pCallback;
-        break;
-
-
-      case HAL_SMARTCARD_MSPINIT_CB_ID :
-        hsmartcard->MspInitCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
-        hsmartcard->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SMARTCARD_MSPINIT_CB_ID :
-        hsmartcard->MspInitCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
-        hsmartcard->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsmartcard);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister an SMARTCARD callback
-  *         SMARTCARD callback is redirected to the weak predefined callback
-  * @param  hsmartcard smartcard handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
-                                                   HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hsmartcard);
-
-  if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
-        hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback;                 /* Legacy weak TxCpltCallback */
-        break;
-
-      case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
-        hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback;                 /* Legacy weak RxCpltCallback */
-        break;
-
-      case HAL_SMARTCARD_ERROR_CB_ID :
-        hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback;                   /* Legacy weak ErrorCallback  */
-        break;
-
-      case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
-        hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback;           /* Legacy weak AbortCpltCallback */
-        break;
-
-      case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
-                                                                                            AbortTransmitCpltCallback*/
-        break;
-
-      case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
-        hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback;  /* Legacy weak
-                                                                                           AbortReceiveCpltCallback */
-        break;
-
-
-      case HAL_SMARTCARD_MSPINIT_CB_ID :
-        hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;                       /* Legacy weak MspInitCallback  */
-        break;
-
-      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
-        hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;                   /* Legacy weak MspDeInitCallback */
-        break;
-
-      default :
-        /* Update the error code */
-        hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SMARTCARD_MSPINIT_CB_ID :
-        hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
-        break;
-
-      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
-        hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsmartcard);
-
-  return status;
-}
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
-  * @brief    SMARTCARD Transmit and Receive functions
-  *
-@verbatim
-  ==============================================================================
-                         ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
-
-  [..]
-    Smartcard is a single wire half duplex communication protocol.
-    The Smartcard interface is designed to support asynchronous protocol Smartcards as
-    defined in the ISO 7816-3 standard. The USART should be configured as:
-    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
-    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
-
-  [..]
-    (#) There are two modes of transfer:
-        (##) Blocking mode: The communication is performed in polling mode.
-             The HAL status of all data processing is returned by the same function
-             after finishing transfer.
-        (##) Non-Blocking mode: The communication is performed using Interrupts
-             or DMA, the relevant API's return the HAL status.
-             The end of the data processing will be indicated through the
-             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
-             using DMA mode.
-        (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
-             will be executed respectively at the end of the Transmit or Receive process
-             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
-             error is detected.
-
-    (#) Blocking mode APIs are :
-        (##) HAL_SMARTCARD_Transmit()
-        (##) HAL_SMARTCARD_Receive()
-
-    (#) Non Blocking mode APIs with Interrupt are :
-        (##) HAL_SMARTCARD_Transmit_IT()
-        (##) HAL_SMARTCARD_Receive_IT()
-        (##) HAL_SMARTCARD_IRQHandler()
-
-    (#) Non Blocking mode functions with DMA are :
-        (##) HAL_SMARTCARD_Transmit_DMA()
-        (##) HAL_SMARTCARD_Receive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (##) HAL_SMARTCARD_TxCpltCallback()
-        (##) HAL_SMARTCARD_RxCpltCallback()
-        (##) HAL_SMARTCARD_ErrorCallback()
-
-  [..]
-    (#) Non-Blocking mode transfers could be aborted using Abort API's :
-        (##) HAL_SMARTCARD_Abort()
-        (##) HAL_SMARTCARD_AbortTransmit()
-        (##) HAL_SMARTCARD_AbortReceive()
-        (##) HAL_SMARTCARD_Abort_IT()
-        (##) HAL_SMARTCARD_AbortTransmit_IT()
-        (##) HAL_SMARTCARD_AbortReceive_IT()
-
-    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
-        a set of Abort Complete Callbacks are provided:
-        (##) HAL_SMARTCARD_AbortCpltCallback()
-        (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
-        (##) HAL_SMARTCARD_AbortReceiveCpltCallback()
-
-    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
-        Errors are handled as follows :
-       (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
-           to be evaluated by user : this concerns Frame Error,
-           Parity Error or Noise Error in Interrupt mode reception .
-           Received character is then retrieved and stored in Rx buffer,
-           Error code is set to allow user to identify error type,
-           and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
-           If user wants to abort it, Abort services should be called by user.
-       (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
-           This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
-           mode reception and all errors in DMA mode.
-           Error code is set to allow user to identify error type,
-           and HAL_SMARTCARD_ErrorCallback() user callback is executed.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Send an amount of data in blocking mode.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @param  pData pointer to data buffer.
-  * @param  Size amount of data to be sent.
-  * @param  Timeout  Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
-                                         uint32_t Timeout)
-{
-  uint32_t tickstart;
-  uint8_t  *ptmpdata = pData;
-
-  /* Check that a Tx process is not already ongoing */
-  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
-  {
-    if ((ptmpdata == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsmartcard);
-
-    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    /* Disable the Peripheral first to update mode for TX master */
-    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
-    /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
-       the bidirectional line to detect a NACK signal in case of parity error.
-       Therefore, the receiver block must be enabled as well (RE bit must be set). */
-    if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
-        && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
-    {
-      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
-    }
-    /* Enable Tx */
-    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
-
-    /* Enable the Peripheral */
-    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
-    /* Perform a TX/RX FIFO Flush */
-    __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
-
-    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    hsmartcard->TxXferSize = Size;
-    hsmartcard->TxXferCount = Size;
-
-    while (hsmartcard->TxXferCount > 0U)
-    {
-      hsmartcard->TxXferCount--;
-      if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
-      ptmpdata++;
-    }
-    if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
-                                         tickstart, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Disable the Peripheral first to update mode */
-    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-    if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
-        && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
-    {
-      /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
-         for Transmit phase. Disable this receiver block. */
-      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
-    }
-    if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
-        || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
-    {
-      /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
-      __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
-    }
-    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
-    /* At end of Tx process, restore hsmartcard->gState to Ready */
-    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmartcard);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive an amount of data in blocking mode.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @param  pData pointer to data buffer.
-  * @param  Size amount of data to be received.
-  * @param  Timeout Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
-                                        uint32_t Timeout)
-{
-  uint32_t tickstart;
-  uint8_t  *ptmpdata = pData;
-
-  /* Check that a Rx process is not already ongoing */
-  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
-  {
-    if ((ptmpdata == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsmartcard);
-
-    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    hsmartcard->RxXferSize = Size;
-    hsmartcard->RxXferCount = Size;
-
-    /* Check the remain data to be received */
-    while (hsmartcard->RxXferCount > 0U)
-    {
-      hsmartcard->RxXferCount--;
-
-      if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
-      ptmpdata++;
-    }
-
-    /* At end of Rx process, restore hsmartcard->RxState to Ready */
-    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmartcard);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Send an amount of data in interrupt mode.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @param  pData pointer to data buffer.
-  * @param  Size amount of data to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Tx process is not already ongoing */
-  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsmartcard);
-
-    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
-    hsmartcard->pTxBuffPtr  = pData;
-    hsmartcard->TxXferSize  = Size;
-    hsmartcard->TxXferCount = Size;
-    hsmartcard->TxISR       = NULL;
-
-    /* Disable the Peripheral first to update mode for TX master */
-    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
-    /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
-       the bidirectional line to detect a NACK signal in case of parity error.
-       Therefore, the receiver block must be enabled as well (RE bit must be set). */
-    if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
-        && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
-    {
-      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
-    }
-    /* Enable Tx */
-    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
-
-    /* Enable the Peripheral */
-    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
-    /* Perform a TX/RX FIFO Flush */
-    __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
-
-    /* Configure Tx interrupt processing */
-    /* Set the Tx ISR function pointer */
-    hsmartcard->TxISR = SMARTCARD_TxISR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmartcard);
-
-    /* Enable the SMARTCARD Error Interrupt: (Frame error) */
-    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
-    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive an amount of data in interrupt mode.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @param  pData pointer to data buffer.
-  * @param  Size amount of data to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsmartcard);
-
-    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
-
-    hsmartcard->pRxBuffPtr = pData;
-    hsmartcard->RxXferSize = Size;
-    hsmartcard->RxXferCount = Size;
-
-    /* Configure Rx interrupt processing */
-    /* Set the Rx ISR function pointer */
-    hsmartcard->RxISR = SMARTCARD_RxISR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmartcard);
-
-    /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
-    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-
-    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Send an amount of data in DMA mode.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @param  pData pointer to data buffer.
-  * @param  Size amount of data to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Tx process is not already ongoing */
-  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsmartcard);
-
-    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
-    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    hsmartcard->pTxBuffPtr = pData;
-    hsmartcard->TxXferSize = Size;
-    hsmartcard->TxXferCount = Size;
-
-    /* Disable the Peripheral first to update mode for TX master */
-    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
-    /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
-       the bidirectional line to detect a NACK signal in case of parity error.
-       Therefore, the receiver block must be enabled as well (RE bit must be set). */
-    if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
-        && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
-    {
-      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
-    }
-    /* Enable Tx */
-    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
-
-    /* Enable the Peripheral */
-    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
-    /* Perform a TX/RX FIFO Flush */
-    __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
-
-    /* Set the SMARTCARD DMA transfer complete callback */
-    hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
-
-    /* Set the SMARTCARD error callback */
-    hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
-
-    /* Set the DMA abort callback */
-    hsmartcard->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the SMARTCARD transmit DMA channel */
-    if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR,
-                         Size) == HAL_OK)
-    {
-      /* Clear the TC flag in the ICR register */
-      CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hsmartcard);
-
-      /* Enable the UART Error Interrupt: (Frame error) */
-      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
-      /* Enable the DMA transfer for transmit request by setting the DMAT bit
-         in the SMARTCARD associated USART CR3 register */
-      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
-      return HAL_OK;
-    }
-    else
-    {
-      /* Set error code to DMA */
-      hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hsmartcard);
-
-      /* Restore hsmartcard->State to ready */
-      hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive an amount of data in DMA mode.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @param  pData pointer to data buffer.
-  * @param  Size amount of data to be received.
-  * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
-  *         the received data contain the parity bit (MSB position).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsmartcard);
-
-    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
-
-    hsmartcard->pRxBuffPtr = pData;
-    hsmartcard->RxXferSize = Size;
-
-    /* Set the SMARTCARD DMA transfer complete callback */
-    hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
-
-    /* Set the SMARTCARD DMA error callback */
-    hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
-
-    /* Set the DMA abort callback */
-    hsmartcard->hdmarx->XferAbortCallback = NULL;
-
-    /* Enable the DMA channel */
-    if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr,
-                         Size) == HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hsmartcard);
-
-      /* Enable the SMARTCARD Parity Error Interrupt */
-      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
-
-      /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
-      /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-         in the SMARTCARD associated USART CR3 register */
-      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
-      return HAL_OK;
-    }
-    else
-    {
-      /* Set error code to DMA */
-      hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hsmartcard);
-
-      /* Restore hsmartcard->State to ready */
-      hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Abort ongoing transfers (blocking mode).
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SMARTCARD Interrupts (Tx and Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsmartcard->Instance->CR1,
-            (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE |
-             USART_CR1_EOBIE));
-  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the SMARTCARD DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if (hsmartcard->hdmatx != NULL)
-    {
-      /* Set the SMARTCARD DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hsmartcard->hdmatx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Disable the SMARTCARD DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if (hsmartcard->hdmarx != NULL)
-    {
-      /* Set the SMARTCARD DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hsmartcard->hdmarx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Tx and Rx transfer counters */
-  hsmartcard->TxXferCount = 0U;
-  hsmartcard->RxXferCount = 0U;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
-                             SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
-                             SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
-  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
-  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
-  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-  /* Reset Handle ErrorCode to No Error */
-  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (blocking mode).
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SMARTCARD Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Check if a receive process is ongoing or not. If not disable ERR IT */
-  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
-  {
-    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-  }
-
-  /* Disable the SMARTCARD DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if (hsmartcard->hdmatx != NULL)
-    {
-      /* Set the SMARTCARD DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hsmartcard->hdmatx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Tx transfer counter */
-  hsmartcard->TxXferCount = 0U;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
-
-  /* Restore hsmartcard->gState to Ready */
-  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (blocking mode).
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SMARTCARD Interrupts (Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
-  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
-  /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
-  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
-  {
-    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-  }
-
-  /* Disable the SMARTCARD DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if (hsmartcard->hdmarx != NULL)
-    {
-      /* Set the SMARTCARD DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hsmartcard->hdmarx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Rx transfer counter */
-  hsmartcard->RxXferCount = 0U;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
-                             SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
-                             SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
-  /* Restore hsmartcard->RxState to Ready */
-  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfers (Interrupt mode).
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SMARTCARD Interrupts (Tx and Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  uint32_t abortcplt = 1U;
-
-  /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsmartcard->Instance->CR1,
-            (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE |
-             USART_CR1_EOBIE));
-  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
-  /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
-     DMA Abort complete callbacks should be initialised before any call
-     to DMA Abort functions */
-  /* DMA Tx Handle is valid */
-  if (hsmartcard->hdmatx != NULL)
-  {
-    /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
-    {
-      hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
-    }
-    else
-    {
-      hsmartcard->hdmatx->XferAbortCallback = NULL;
-    }
-  }
-  /* DMA Rx Handle is valid */
-  if (hsmartcard->hdmarx != NULL)
-  {
-    /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
-    {
-      hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
-    }
-    else
-    {
-      hsmartcard->hdmarx->XferAbortCallback = NULL;
-    }
-  }
-
-  /* Disable the SMARTCARD DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
-  {
-    /* Disable DMA Tx at UART level */
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
-    if (hsmartcard->hdmatx != NULL)
-    {
-      /* SMARTCARD Tx DMA Abort callback has already been initialised :
-         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
-      {
-        hsmartcard->hdmatx->XferAbortCallback = NULL;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-
-  /* Disable the SMARTCARD DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
-    if (hsmartcard->hdmarx != NULL)
-    {
-      /* SMARTCARD Rx DMA Abort callback has already been initialised :
-         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
-      {
-        hsmartcard->hdmarx->XferAbortCallback = NULL;
-        abortcplt = 1U;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-
-  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
-  if (abortcplt == 1U)
-  {
-    /* Reset Tx and Rx transfer counters */
-    hsmartcard->TxXferCount = 0U;
-    hsmartcard->RxXferCount = 0U;
-
-    /* Clear ISR function pointers */
-    hsmartcard->RxISR = NULL;
-    hsmartcard->TxISR = NULL;
-
-    /* Reset errorCode */
-    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
-    /* Clear the Error flags in the ICR register */
-    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
-                               SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
-                               SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
-    /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
-    hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
-    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort complete callback */
-    hsmartcard->AbortCpltCallback(hsmartcard);
-#else
-    /* Call legacy weak Abort complete callback */
-    HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SMARTCARD Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Check if a receive process is ongoing or not. If not disable ERR IT */
-  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
-  {
-    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-  }
-
-  /* Disable the SMARTCARD DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
-    if (hsmartcard->hdmatx != NULL)
-    {
-      /* Set the SMARTCARD DMA Abort callback :
-         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-      hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
-      {
-        /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
-        hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
-      }
-    }
-    else
-    {
-      /* Reset Tx transfer counter */
-      hsmartcard->TxXferCount = 0U;
-
-      /* Clear TxISR function pointers */
-      hsmartcard->TxISR = NULL;
-
-      /* Restore hsmartcard->gState to Ready */
-      hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Transmit Complete Callback */
-      hsmartcard->AbortTransmitCpltCallback(hsmartcard);
-#else
-      /* Call legacy weak Abort Transmit Complete Callback */
-      HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-    }
-  }
-  else
-  {
-    /* Reset Tx transfer counter */
-    hsmartcard->TxXferCount = 0U;
-
-    /* Clear TxISR function pointers */
-    hsmartcard->TxISR = NULL;
-
-    /* Clear the Error flags in the ICR register */
-    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
-
-    /* Restore hsmartcard->gState to Ready */
-    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Transmit Complete Callback */
-    hsmartcard->AbortTransmitCpltCallback(hsmartcard);
-#else
-    /* Call legacy weak Abort Transmit Complete Callback */
-    HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (Interrupt mode).
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SMARTCARD Interrupts (Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
-  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
-  /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
-  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
-  {
-    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-  }
-
-  /* Disable the SMARTCARD DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
-    if (hsmartcard->hdmarx != NULL)
-    {
-      /* Set the SMARTCARD DMA Abort callback :
-         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-      hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
-      {
-        /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
-        hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
-      }
-    }
-    else
-    {
-      /* Reset Rx transfer counter */
-      hsmartcard->RxXferCount = 0U;
-
-      /* Clear RxISR function pointer */
-      hsmartcard->RxISR = NULL;
-
-      /* Clear the Error flags in the ICR register */
-      __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
-                                 SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
-                                 SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
-      /* Restore hsmartcard->RxState to Ready */
-      hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Receive Complete Callback */
-      hsmartcard->AbortReceiveCpltCallback(hsmartcard);
-#else
-      /* Call legacy weak Abort Receive Complete Callback */
-      HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-    }
-  }
-  else
-  {
-    /* Reset Rx transfer counter */
-    hsmartcard->RxXferCount = 0U;
-
-    /* Clear RxISR function pointer */
-    hsmartcard->RxISR = NULL;
-
-    /* Clear the Error flags in the ICR register */
-    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
-                               SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
-                               SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
-    /* Restore hsmartcard->RxState to Ready */
-    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Receive Complete Callback */
-    hsmartcard->AbortReceiveCpltCallback(hsmartcard);
-#else
-    /* Call legacy weak Abort Receive Complete Callback */
-    HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle SMARTCARD interrupt requests.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  uint32_t isrflags   = READ_REG(hsmartcard->Instance->ISR);
-  uint32_t cr1its     = READ_REG(hsmartcard->Instance->CR1);
-  uint32_t cr3its     = READ_REG(hsmartcard->Instance->CR3);
-  uint32_t errorflags;
-  uint32_t errorcode;
-
-  /* If no error occurs */
-  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
-  if (errorflags == 0U)
-  {
-    /* SMARTCARD in mode Receiver ---------------------------------------------------*/
-    if (((isrflags & USART_ISR_RXNE) != 0U)
-        && ((cr1its & USART_CR1_RXNEIE) != 0U))
-    {
-      if (hsmartcard->RxISR != NULL)
-      {
-        hsmartcard->RxISR(hsmartcard);
-      }
-      return;
-    }
-  }
-
-  /* If some errors occur */
-  if ((errorflags != 0U)
-      && (((cr3its & USART_CR3_EIE) != 0U)
-          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
-  {
-    /* SMARTCARD parity error interrupt occurred -------------------------------------*/
-    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
-    {
-      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
-
-      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
-    }
-
-    /* SMARTCARD frame error interrupt occurred --------------------------------------*/
-    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
-    {
-      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
-
-      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
-    }
-
-    /* SMARTCARD noise error interrupt occurred --------------------------------------*/
-    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
-    {
-      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
-
-      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
-    }
-
-    /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
-    if (((isrflags & USART_ISR_ORE) != 0U)
-        && (((cr1its & USART_CR1_RXNEIE) != 0U)
-            || ((cr3its & USART_CR3_EIE) != 0U)))
-    {
-      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
-
-      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
-    }
-
-    /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
-    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
-    {
-      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
-
-      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
-    }
-
-    /* Call SMARTCARD Error Call back function if need be --------------------------*/
-    if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
-    {
-      /* SMARTCARD in mode Receiver ---------------------------------------------------*/
-      if (((isrflags & USART_ISR_RXNE) != 0U)
-          && ((cr1its & USART_CR1_RXNEIE) != 0U))
-      {
-        if (hsmartcard->RxISR != NULL)
-        {
-          hsmartcard->RxISR(hsmartcard);
-        }
-      }
-
-      /* If Error is to be considered as blocking :
-          - Receiver Timeout error in Reception
-          - Overrun error in Reception
-          - any error occurs in DMA mode reception
-      */
-      errorcode = hsmartcard->ErrorCode;
-      if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
-          || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U))
-      {
-        /* Blocking error : transfer is aborted
-           Set the SMARTCARD state ready to be able to start again the process,
-           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
-        SMARTCARD_EndRxTransfer(hsmartcard);
-
-        /* Disable the SMARTCARD DMA Rx request if enabled */
-        if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
-        {
-          CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
-          /* Abort the SMARTCARD DMA Rx channel */
-          if (hsmartcard->hdmarx != NULL)
-          {
-            /* Set the SMARTCARD DMA Abort callback :
-               will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
-            hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
-
-            /* Abort DMA RX */
-            if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
-            {
-              /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
-              hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
-            }
-          }
-          else
-          {
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-            /* Call registered user error callback */
-            hsmartcard->ErrorCallback(hsmartcard);
-#else
-            /* Call legacy weak user error callback */
-            HAL_SMARTCARD_ErrorCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-          }
-        }
-        else
-        {
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-          /* Call registered user error callback */
-          hsmartcard->ErrorCallback(hsmartcard);
-#else
-          /* Call legacy weak user error callback */
-          HAL_SMARTCARD_ErrorCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-        }
-      }
-      /* other error type to be considered as blocking :
-          - Frame error in Transmission
-      */
-      else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
-               && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U))
-      {
-        /* Blocking error : transfer is aborted
-           Set the SMARTCARD state ready to be able to start again the process,
-           Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
-        SMARTCARD_EndTxTransfer(hsmartcard);
-
-        /* Disable the SMARTCARD DMA Tx request if enabled */
-        if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
-        {
-          CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
-          /* Abort the SMARTCARD DMA Tx channel */
-          if (hsmartcard->hdmatx != NULL)
-          {
-            /* Set the SMARTCARD DMA Abort callback :
-               will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
-            hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
-
-            /* Abort DMA TX */
-            if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
-            {
-              /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
-              hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
-            }
-          }
-          else
-          {
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-            /* Call registered user error callback */
-            hsmartcard->ErrorCallback(hsmartcard);
-#else
-            /* Call legacy weak user error callback */
-            HAL_SMARTCARD_ErrorCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-          }
-        }
-        else
-        {
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-          /* Call registered user error callback */
-          hsmartcard->ErrorCallback(hsmartcard);
-#else
-          /* Call legacy weak user error callback */
-          HAL_SMARTCARD_ErrorCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-        }
-      }
-      else
-      {
-        /* Non Blocking error : transfer could go on.
-           Error is notified to user through user error callback */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-        /* Call registered user error callback */
-        hsmartcard->ErrorCallback(hsmartcard);
-#else
-        /* Call legacy weak user error callback */
-        HAL_SMARTCARD_ErrorCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-        hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-      }
-    }
-    return;
-
-  } /* End if some error occurs */
-
-  /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
-  if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U))
-  {
-    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-    __HAL_UNLOCK(hsmartcard);
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-    /* Call registered Rx complete callback */
-    hsmartcard->RxCpltCallback(hsmartcard);
-#else
-    /* Call legacy weak Rx complete callback */
-    HAL_SMARTCARD_RxCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-    /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
-       to be available during HAL_SMARTCARD_RxCpltCallback() processing */
-    __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
-    return;
-  }
-
-  /* SMARTCARD in mode Transmitter ------------------------------------------------*/
-  if (((isrflags & USART_ISR_TXE) != 0U)
-      && ((cr1its & USART_CR1_TXEIE) != 0U))
-  {
-    if (hsmartcard->TxISR != NULL)
-    {
-      hsmartcard->TxISR(hsmartcard);
-    }
-    return;
-  }
-
-  /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
-  if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
-  {
-    if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
-    {
-      SMARTCARD_EndTransmit_IT(hsmartcard);
-      return;
-    }
-  }
-
-}
-
-/**
-  * @brief  Tx Transfer completed callback.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmartcard);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callback.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmartcard);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  SMARTCARD error callback.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmartcard);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  SMARTCARD Abort Complete callback.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmartcard);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  SMARTCARD Abort Complete callback.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmartcard);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  SMARTCARD Abort Receive Complete callback.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmartcard);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
-  * @brief    SMARTCARD State and Errors functions
-  *
-@verbatim
-  ==============================================================================
-                  ##### Peripheral State and Errors functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to return the State of SmartCard
-    handle and also return Peripheral Errors occurred during communication process
-     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
-         of the SMARTCARD peripheral.
-     (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
-         communication.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the SMARTCARD handle state.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval SMARTCARD handle state
-  */
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Return SMARTCARD handle state */
-  uint32_t temp1;
-  uint32_t temp2;
-  temp1 = (uint32_t)hsmartcard->gState;
-  temp2 = (uint32_t)hsmartcard->RxState;
-
-  return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
-}
-
-/**
-  * @brief  Return the SMARTCARD handle error code.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval SMARTCARD handle Error Code
-  */
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  return hsmartcard->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
-  * @{
-  */
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Initialize the callbacks to their default values.
-  * @param  hsmartcard SMARTCARD handle.
-  * @retval none
-  */
-void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Init the SMARTCARD Callback settings */
-  hsmartcard->TxCpltCallback            = HAL_SMARTCARD_TxCpltCallback;            /* Legacy weak TxCpltCallback    */
-  hsmartcard->RxCpltCallback            = HAL_SMARTCARD_RxCpltCallback;            /* Legacy weak RxCpltCallback    */
-  hsmartcard->ErrorCallback             = HAL_SMARTCARD_ErrorCallback;             /* Legacy weak ErrorCallback     */
-  hsmartcard->AbortCpltCallback         = HAL_SMARTCARD_AbortCpltCallback;         /* Legacy weak AbortCpltCallback */
-  hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
-                                                                                      AbortTransmitCpltCallback     */
-  hsmartcard->AbortReceiveCpltCallback  = HAL_SMARTCARD_AbortReceiveCpltCallback;  /* Legacy weak
-                                                                                      AbortReceiveCpltCallback      */
-
-}
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Configure the SMARTCARD associated USART peripheral.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  uint32_t tmpreg;
-  SMARTCARD_ClockSourceTypeDef clocksource;
-  HAL_StatusTypeDef ret = HAL_OK;
-  uint32_t pclk;
-
-  /* Check the parameters */
-  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
-  assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
-  assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
-  assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
-  assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
-  assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
-  assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
-  assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
-  assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
-  assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
-  assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
-  assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
-  assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
-   * Oversampling is forced to 16 (OVER8 = 0).
-   * Configure the Parity and Mode:
-   *  set PS bit according to hsmartcard->Init.Parity value
-   *  set TE and RE bits according to hsmartcard->Init.Mode value */
-  tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) |
-            ((uint32_t)hsmartcard->Init.WordLength));
-  MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
-
-  /*-------------------------- USART CR2 Configuration -----------------------*/
-  tmpreg = hsmartcard->Init.StopBits;
-  /* Synchronous mode is activated by default */
-  tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
-  tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
-  tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
-  MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/
-  /* Configure
-   * - one-bit sampling method versus three samples' majority rule
-   *   according to hsmartcard->Init.OneBitSampling
-   * - NACK transmission in case of parity error according
-   *   to hsmartcard->Init.NACKEnable
-   * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
-
-  tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
-  tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos);
-  MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg);
-
-
-  /*-------------------------- USART GTPR Configuration ----------------------*/
-  tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos));
-  MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg);
-
-  /*-------------------------- USART RTOR Configuration ----------------------*/
-  tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos);
-  if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
-  {
-    assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
-    tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
-  }
-  MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
-
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
-  tmpreg =   0U;
-  switch (clocksource)
-  {
-    case SMARTCARD_CLOCKSOURCE_PCLK1:
-      pclk = HAL_RCC_GetPCLK1Freq();
-      tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
-      break;
-    case SMARTCARD_CLOCKSOURCE_PCLK2:
-      pclk = HAL_RCC_GetPCLK2Freq();
-      tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
-      break;
-    case SMARTCARD_CLOCKSOURCE_HSI:
-      tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
-      break;
-    case SMARTCARD_CLOCKSOURCE_SYSCLK:
-      pclk = HAL_RCC_GetSysClockFreq();
-      tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
-      break;
-    case SMARTCARD_CLOCKSOURCE_LSE:
-      tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
-      break;
-    default:
-      ret = HAL_ERROR;
-      break;
-  }
-
-  /* USARTDIV must be greater than or equal to 0d16 */
-  if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
-  {
-    hsmartcard->Instance->BRR = tmpreg;
-  }
-  else
-  {
-    ret = HAL_ERROR;
-  }
-
-
-  /* Clear ISR function pointers */
-  hsmartcard->RxISR   = NULL;
-  hsmartcard->TxISR   = NULL;
-
-  return ret;
-}
-
-
-/**
-  * @brief Configure the SMARTCARD associated USART peripheral advanced features.
-  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                   the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Check whether the set of advanced features to configure is properly set */
-  assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
-
-  /* if required, configure TX pin active level inversion */
-  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
-  {
-    assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
-    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
-  }
-
-  /* if required, configure RX pin active level inversion */
-  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
-  {
-    assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
-    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
-  }
-
-  /* if required, configure data inversion */
-  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
-  {
-    assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
-    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
-  }
-
-  /* if required, configure RX/TX pins swap */
-  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
-  {
-    assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
-    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
-  }
-
-  /* if required, configure RX overrun detection disabling */
-  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
-  {
-    assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
-    MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
-  }
-
-  /* if required, configure DMA disabling on reception error */
-  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
-  {
-    assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
-    MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
-  }
-
-  /* if required, configure MSB first on communication line */
-  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
-  {
-    assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
-    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
-  }
-
-}
-
-/**
-  * @brief Check the SMARTCARD Idle State.
-  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                   the configuration information for the specified SMARTCARD module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  uint32_t tickstart;
-
-  /* Initialize the SMARTCARD ErrorCode */
-  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
-  /* Init tickstart for timeout management */
-  tickstart = HAL_GetTick();
-
-  /* Check if the Transmitter is enabled */
-  if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
-  {
-    /* Wait until TEACK flag is set */
-    if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart,
-                                         SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
-    {
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
-    }
-  }
-  /* Check if the Receiver is enabled */
-  if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
-  {
-    /* Wait until REACK flag is set */
-    if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart,
-                                         SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
-    {
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Initialize the SMARTCARD states */
-  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
-  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hsmartcard);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle SMARTCARD Communication Timeout.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                   the configuration information for the specified SMARTCARD module.
-  * @param  Flag Specifies the SMARTCARD flag to check.
-  * @param  Status The new Flag status (SET or RESET).
-  * @param  Tickstart Tick start value
-  * @param  Timeout Timeout duration.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
-                                                          FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
-  /* Wait until flag is set */
-  while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-      {
-        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
-           interrupts for the interrupt process */
-        CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
-        CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
-        hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
-        hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hsmartcard);
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
-  /* At end of Tx process, restore hsmartcard->gState to Ready */
-  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-}
-
-
-/**
-  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
-  /* At end of Rx process, restore hsmartcard->RxState to Ready */
-  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-}
-
-
-/**
-  * @brief  DMA SMARTCARD transmit process complete callback.
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
-  hsmartcard->TxXferCount = 0U;
-
-  /* Disable the DMA transfer for transmit request by resetting the DMAT bit
-  in the SMARTCARD associated USART CR3 register */
-  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
-  /* Enable the SMARTCARD Transmit Complete Interrupt */
-  __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
-}
-
-/**
-  * @brief  DMA SMARTCARD receive process complete callback.
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
-  hsmartcard->RxXferCount = 0U;
-
-  /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
-  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
-     in the SMARTCARD associated USART CR3 register */
-  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
-  /* At end of Rx process, restore hsmartcard->RxState to Ready */
-  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered Rx complete callback */
-  hsmartcard->RxCpltCallback(hsmartcard);
-#else
-  /* Call legacy weak Rx complete callback */
-  HAL_SMARTCARD_RxCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA SMARTCARD communication error callback.
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
-
-  /* Stop SMARTCARD DMA Tx request if ongoing */
-  if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
-  {
-    if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
-    {
-      hsmartcard->TxXferCount = 0U;
-      SMARTCARD_EndTxTransfer(hsmartcard);
-    }
-  }
-
-  /* Stop SMARTCARD DMA Rx request if ongoing */
-  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
-  {
-    if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
-    {
-      hsmartcard->RxXferCount = 0U;
-      SMARTCARD_EndRxTransfer(hsmartcard);
-    }
-  }
-
-  hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered user error callback */
-  hsmartcard->ErrorCallback(hsmartcard);
-#else
-  /* Call legacy weak user error callback */
-  HAL_SMARTCARD_ErrorCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
-  hsmartcard->RxXferCount = 0U;
-  hsmartcard->TxXferCount = 0U;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered user error callback */
-  hsmartcard->ErrorCallback(hsmartcard);
-#else
-  /* Call legacy weak user error callback */
-  HAL_SMARTCARD_ErrorCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Rx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
-
-  hsmartcard->hdmatx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (hsmartcard->hdmarx != NULL)
-  {
-    if (hsmartcard->hdmarx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  hsmartcard->TxXferCount = 0U;
-  hsmartcard->RxXferCount = 0U;
-
-  /* Reset errorCode */
-  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
-                             SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
-                             SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
-  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
-  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
-  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  hsmartcard->AbortCpltCallback(hsmartcard);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-
-/**
-  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Tx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
-
-  hsmartcard->hdmarx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (hsmartcard->hdmatx != NULL)
-  {
-    if (hsmartcard->hdmatx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  hsmartcard->TxXferCount = 0U;
-  hsmartcard->RxXferCount = 0U;
-
-  /* Reset errorCode */
-  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
-                             SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
-                             SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
-  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
-  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
-  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  hsmartcard->AbortCpltCallback(hsmartcard);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-
-/**
-  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
-  *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
-  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
-  *         and leads to user Tx Abort Complete callback execution).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
-
-  hsmartcard->TxXferCount = 0U;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
-
-  /* Restore hsmartcard->gState to Ready */
-  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Transmit Complete Callback */
-  hsmartcard->AbortTransmitCpltCallback(hsmartcard);
-#else
-  /* Call legacy weak Abort Transmit Complete Callback */
-  HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
-  *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
-  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
-  *         and leads to user Rx Abort Complete callback execution).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
-
-  hsmartcard->RxXferCount = 0U;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
-                             SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
-                             SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
-  /* Restore hsmartcard->RxState to Ready */
-  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Receive Complete Callback */
-  hsmartcard->AbortReceiveCpltCallback(hsmartcard);
-#else
-  /* Call legacy weak Abort Receive Complete Callback */
-  HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  Send an amount of data in non-blocking mode.
-  * @note   Function called under interruption only, once
-  *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT().
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Check that a Tx process is ongoing */
-  if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
-  {
-    if (hsmartcard->TxXferCount == 0U)
-    {
-      /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
-      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
-
-      /* Enable the SMARTCARD Transmit Complete Interrupt */
-      __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
-    }
-    else
-    {
-      hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
-      hsmartcard->pTxBuffPtr++;
-      hsmartcard->TxXferCount--;
-    }
-  }
-}
-
-/**
-  * @brief  Wrap up transmission in non-blocking mode.
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Disable the SMARTCARD Transmit Complete Interrupt */
-  __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
-
-  /* Check if a receive process is ongoing or not. If not disable ERR IT */
-  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
-  {
-    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
-    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-  }
-
-  /* Disable the Peripheral first to update mode */
-  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-  if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
-      && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
-  {
-    /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
-       for Transmit phase. Disable this receiver block. */
-    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
-  }
-  if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
-      || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
-  {
-    /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
-    __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
-  }
-  SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
-  /* Tx process is ended, restore hsmartcard->gState to Ready */
-  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
-  /* Clear TxISR function pointer */
-  hsmartcard->TxISR = NULL;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered Tx complete callback */
-  hsmartcard->TxCpltCallback(hsmartcard);
-#else
-  /* Call legacy weak Tx complete callback */
-  HAL_SMARTCARD_TxCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode.
-  * @note   Function called under interruption only, once
-  *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
-  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Check that a Rx process is ongoing */
-  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
-  {
-    *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
-    hsmartcard->pRxBuffPtr++;
-
-    hsmartcard->RxXferCount--;
-    if (hsmartcard->RxXferCount == 0U)
-    {
-      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
-
-      /* Check if a transmit process is ongoing or not. If not disable ERR IT */
-      if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
-      {
-        /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-        CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-      }
-
-      /* Disable the SMARTCARD Parity Error Interrupt */
-      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
-
-      hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
-      /* Clear RxISR function pointer */
-      hsmartcard->RxISR = NULL;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-      /* Call registered Rx complete callback */
-      hsmartcard->RxCpltCallback(hsmartcard);
-#else
-      /* Call legacy weak Rx complete callback */
-      HAL_SMARTCARD_RxCpltCallback(hsmartcard);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-    }
-  }
-  else
-  {
-    /* Clear RXNE interrupt flag */
-    __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* !defined (STM32L010x4) && !defined (STM32L010x6) */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard_ex.c
deleted file mode 100644
index f0db48941a..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard_ex.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_smartcard_ex.c
-  * @author  MCD Application Team
-  * @brief   SMARTCARD HAL module driver.
-  *          This file provides extended firmware functions to manage the following
-  *          functionalities of the SmartCard.
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *
-  @verbatim
-  =============================================================================
-               ##### SMARTCARD peripheral extended features  #####
-  =============================================================================
-  [..]
-  The Extended SMARTCARD HAL driver can be used as follows:
-
-    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
-        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
-        auto-retry counter,...) in the hsmartcard AdvancedInit structure.
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-#if !defined (STM32L010x4) && !defined (STM32L010x6)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SMARTCARDEx SMARTCARDEx
-  * @brief SMARTCARD Extended HAL module driver
-  * @{
-  */
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
-  * @{
-  */
-
-/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
-  * @brief    Extended control functions
-  *
-@verbatim
-  ===============================================================================
-                      ##### Peripheral Control functions #####
-  ===============================================================================
-  [..]
-  This subsection provides a set of functions allowing to initialize the SMARTCARD.
-     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
-     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
-     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
-     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
-
-@endverbatim
-  * @{
-  */
-
-/** @brief Update on the fly the SMARTCARD block length in RTOR register.
-  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @param BlockLength SMARTCARD block length (8-bit long at most)
-  * @retval None
-  */
-void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
-{
-  MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
-}
-
-/** @brief Update on the fly the receiver timeout value in RTOR register.
-  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
-  *                     value must be less or equal to 0x0FFFFFFFF.
-  * @retval None
-  */
-void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
-{
-  assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
-  MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
-}
-
-/** @brief Enable the SMARTCARD receiver timeout feature.
-  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsmartcard);
-
-    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
-
-    /* Set the USART RTOEN bit */
-    SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
-
-    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmartcard);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/** @brief Disable the SMARTCARD receiver timeout feature.
-  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                    the configuration information for the specified SMARTCARD module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsmartcard);
-
-    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
-
-    /* Clear the USART RTOEN bit */
-    CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
-
-    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmartcard);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
-  * @brief   SMARTCARD Transmit and Receive functions
-  *
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_Private_Functions  SMARTCARD Extended Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* !defined (STM32L010x4) && !defined (STM32L010x6) */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c
deleted file mode 100644
index e88a7c420e..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c
+++ /dev/null
@@ -1,2750 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_smbus.c
-  * @author  MCD Application Team
-  * @brief   SMBUS HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the System Management Bus (SMBus) peripheral,
-  *          based on I2C principles of operation :
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and Errors functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The SMBUS HAL driver can be used as follows:
-
-    (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
-        SMBUS_HandleTypeDef  hsmbus;
-
-    (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
-        (##) Enable the SMBUSx interface clock
-        (##) SMBUS pins configuration
-            (+++) Enable the clock for the SMBUS GPIOs
-            (+++) Configure SMBUS pins as alternate function open-drain
-        (##) NVIC configuration if you need to use interrupt process
-            (+++) Configure the SMBUSx interrupt priority
-            (+++) Enable the NVIC SMBUS IRQ Channel
-
-    (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
-        Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
-        Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
-
-    (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
-        (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-             by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
-
-    (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
-
-    (#) For SMBUS IO operations, only one mode of operations is available within this driver
-
-    *** Interrupt mode IO operation ***
-    ===================================
-    [..]
-      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode
-          using HAL_SMBUS_Master_Transmit_IT()
-      (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
-      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode
-          using HAL_SMBUS_Master_Receive_IT()
-      (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
-      (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
-      (++) The associated previous transfer callback is called at the end of abort process
-      (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
-      (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
-      (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
-           using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
-      (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can
-           add their own code to check the Address Match Code and the transmission direction
-           request by master/host (Write/Read).
-      (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
-      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode
-          using HAL_SMBUS_Slave_Transmit_IT()
-      (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
-      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode
-          using HAL_SMBUS_Slave_Receive_IT()
-      (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can
-           add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
-      (+) Enable/Disable the SMBUS alert mode using
-          HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT()
-      (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can
-           add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
-           to check the Alert Error Code using function HAL_SMBUS_GetError()
-      (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
-      (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can
-           add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
-           to check the Error Code using function HAL_SMBUS_GetError()
-
-     *** SMBUS HAL driver macros list ***
-     ==================================
-     [..]
-       Below the list of most used macros in SMBUS HAL driver.
-
-      (+) __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
-      (+) __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
-      (+) __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
-      (+) __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
-      (+) __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
-      (+) __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt
-
-     *** Callback registration ***
-     =============================================
-    [..]
-     The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
-     allows the user to configure dynamically the driver callbacks.
-     Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback()
-     to register an interrupt callback.
-    [..]
-     Function HAL_SMBUS_RegisterCallback() allows to register following callbacks:
-       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
-       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
-       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
-       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
-       (+) ListenCpltCallback   : callback for end of listen mode.
-       (+) ErrorCallback        : callback for error detection.
-       (+) MspInitCallback      : callback for Msp Init.
-       (+) MspDeInitCallback    : callback for Msp DeInit.
-     This function takes as parameters the HAL peripheral handle, the Callback ID
-     and a pointer to the user callback function.
-    [..]
-     For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback.
-    [..]
-     Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default
-     weak function.
-     HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
-     and the Callback ID.
-     This function allows to reset following callbacks:
-       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
-       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
-       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
-       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
-       (+) ListenCpltCallback   : callback for end of listen mode.
-       (+) ErrorCallback        : callback for error detection.
-       (+) MspInitCallback      : callback for Msp Init.
-       (+) MspDeInitCallback    : callback for Msp DeInit.
-    [..]
-     For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback.
-    [..]
-     By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET
-     all callbacks are set to the corresponding weak functions:
-     examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback().
-     Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when
-     these callbacks are null (not registered beforehand).
-     If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit()
-     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-    [..]
-     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
-     Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
-     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-     Then, the user first registers the MspInit/MspDeInit user callbacks
-     using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit()
-     or HAL_SMBUS_Init() function.
-    [..]
-     When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
-     not defined, the callback registration feature is not available and all callbacks
-     are set to the corresponding weak functions.
-
-     [..]
-       (@) You can refer to the SMBUS HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SMBUS SMBUS
-  * @brief SMBUS HAL module driver
-  * @{
-  */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Define SMBUS Private Constants
-  * @{
-  */
-#define TIMING_CLEAR_MASK   (0xF0FFFFFFUL)     /*!< SMBUS TIMING clear register Mask */
-#define HAL_TIMEOUT_ADDR    (10000U)           /*!< 10 s  */
-#define HAL_TIMEOUT_BUSY    (25U)              /*!< 25 ms */
-#define HAL_TIMEOUT_DIR     (25U)              /*!< 25 ms */
-#define HAL_TIMEOUT_RXNE    (25U)              /*!< 25 ms */
-#define HAL_TIMEOUT_STOPF   (25U)              /*!< 25 ms */
-#define HAL_TIMEOUT_TC      (25U)              /*!< 25 ms */
-#define HAL_TIMEOUT_TCR     (25U)              /*!< 25 ms */
-#define HAL_TIMEOUT_TXIS    (25U)              /*!< 25 ms */
-#define MAX_NBYTE_SIZE      255U
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
-  * @{
-  */
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
-                                                      FlagStatus Status, uint32_t Timeout);
-
-static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
-static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
-static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-
-static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
-
-static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
-
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size,
-                                 uint32_t Mode, uint32_t Request);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
-  * @{
-  */
-
-/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          deinitialize the SMBUSx peripheral:
-
-      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
-
-      (+) Call the function HAL_SMBUS_Init() to configure the selected device with
-          the selected configuration:
-        (++) Clock Timing
-        (++) Bus Timeout
-        (++) Analog Filer mode
-        (++) Own Address 1
-        (++) Addressing mode (Master, Slave)
-        (++) Dual Addressing mode
-        (++) Own Address 2
-        (++) Own Address 2 Mask
-        (++) General call mode
-        (++) Nostretch mode
-        (++) Packet Error Check mode
-        (++) Peripheral mode
-
-
-      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
-          of the selected SMBUSx peripheral.
-
-      (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
-          HAL_SMBUS_ConfigDigitalFilter().
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the SMBUS according to the specified parameters
-  *         in the SMBUS_InitTypeDef and initialize the associated handle.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Check the SMBUS handle allocation */
-  if (hsmbus == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
-  assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
-  assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
-  assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
-  assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
-  assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
-  assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
-  assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
-  assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
-  assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
-  assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
-
-  if (hsmbus->State == HAL_SMBUS_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hsmbus->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-    hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
-    hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
-    hsmbus->SlaveTxCpltCallback  = HAL_SMBUS_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
-    hsmbus->SlaveRxCpltCallback  = HAL_SMBUS_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
-    hsmbus->ListenCpltCallback   = HAL_SMBUS_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
-    hsmbus->ErrorCallback        = HAL_SMBUS_ErrorCallback;        /* Legacy weak ErrorCallback        */
-    hsmbus->AddrCallback         = HAL_SMBUS_AddrCallback;         /* Legacy weak AddrCallback         */
-
-    if (hsmbus->MspInitCallback == NULL)
-    {
-      hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit  */
-    }
-
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
-    hsmbus->MspInitCallback(hsmbus);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    HAL_SMBUS_MspInit(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-  }
-
-  hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
-  /* Disable the selected SMBUS peripheral */
-  __HAL_SMBUS_DISABLE(hsmbus);
-
-  /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
-  /* Configure SMBUSx: Frequency range */
-  hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
-
-  /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
-  /* Configure SMBUSx: Bus Timeout  */
-  hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
-  hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
-  hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
-
-  /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
-  /* Configure SMBUSx: Own Address1 and ack own address1 mode */
-  hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
-
-  if (hsmbus->Init.OwnAddress1 != 0UL)
-  {
-    if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
-    {
-      hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
-    }
-    else /* SMBUS_ADDRESSINGMODE_10BIT */
-    {
-      hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
-    }
-  }
-
-  /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
-  /* Configure SMBUSx: Addressing Master mode */
-  if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
-  {
-    hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
-  }
-  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
-  /* AUTOEND and NACK bit will be manage during Transfer process */
-  hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
-
-  /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
-  /* Configure SMBUSx: Dual mode and Own Address2 */
-  hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \
-                            (hsmbus->Init.OwnAddress2Masks << 8U));
-
-  /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
-  /* Configure SMBUSx: Generalcall and NoStretch mode */
-  hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \
-                           hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \
-                           hsmbus->Init.AnalogFilter);
-
-  /* Enable Slave Byte Control only in case of Packet Error Check is enabled
-     and SMBUS Peripheral is set in Slave mode */
-  if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \
-      ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
-       (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
-  {
-    hsmbus->Instance->CR1 |= I2C_CR1_SBC;
-  }
-
-  /* Enable the selected SMBUS peripheral */
-  __HAL_SMBUS_ENABLE(hsmbus);
-
-  hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-  hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
-  hsmbus->State = HAL_SMBUS_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the SMBUS peripheral.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Check the SMBUS handle allocation */
-  if (hsmbus == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
-
-  hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
-  /* Disable the SMBUS Peripheral Clock */
-  __HAL_SMBUS_DISABLE(hsmbus);
-
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-  if (hsmbus->MspDeInitCallback == NULL)
-  {
-    hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit  */
-  }
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  hsmbus->MspDeInitCallback(hsmbus);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_SMBUS_MspDeInit(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-
-  hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-  hsmbus->PreviousState =  HAL_SMBUS_STATE_RESET;
-  hsmbus->State = HAL_SMBUS_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsmbus);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Initialize the SMBUS MSP.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval None
-  */
-__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmbus);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMBUS_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief DeInitialize the SMBUS MSP.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval None
-  */
-__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmbus);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMBUS_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Configure Analog noise filter.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  AnalogFilter This parameter can be one of the following values:
-  *         @arg @ref SMBUS_ANALOGFILTER_ENABLE
-  *         @arg @ref SMBUS_ANALOGFILTER_DISABLE
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
-{
-  /* Check the parameters */
-  assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
-  assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
-
-  if (hsmbus->State == HAL_SMBUS_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsmbus);
-
-    hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
-    /* Disable the selected SMBUS peripheral */
-    __HAL_SMBUS_DISABLE(hsmbus);
-
-    /* Reset ANOFF bit */
-    hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
-
-    /* Set analog filter bit*/
-    hsmbus->Instance->CR1 |= AnalogFilter;
-
-    __HAL_SMBUS_ENABLE(hsmbus);
-
-    hsmbus->State = HAL_SMBUS_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Configure Digital noise filter.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
-  assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
-
-  if (hsmbus->State == HAL_SMBUS_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsmbus);
-
-    hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
-    /* Disable the selected SMBUS peripheral */
-    __HAL_SMBUS_DISABLE(hsmbus);
-
-    /* Get the old register value */
-    tmpreg = hsmbus->Instance->CR1;
-
-    /* Reset I2C DNF bits [11:8] */
-    tmpreg &= ~(I2C_CR1_DNF);
-
-    /* Set I2Cx DNF coefficient */
-    tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
-
-    /* Store the new register value */
-    hsmbus->Instance->CR1 = tmpreg;
-
-    __HAL_SMBUS_ENABLE(hsmbus);
-
-    hsmbus->State = HAL_SMBUS_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User SMBUS Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
-  *          @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
-  *          @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
-  *          @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
-  *          @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
-  *          @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
-  *          @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
-                                             HAL_SMBUS_CallbackIDTypeDef CallbackID,
-                                             pSMBUS_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hsmbus);
-
-  if (HAL_SMBUS_STATE_READY == hsmbus->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
-        hsmbus->MasterTxCpltCallback = pCallback;
-        break;
-
-      case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
-        hsmbus->MasterRxCpltCallback = pCallback;
-        break;
-
-      case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
-        hsmbus->SlaveTxCpltCallback = pCallback;
-        break;
-
-      case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
-        hsmbus->SlaveRxCpltCallback = pCallback;
-        break;
-
-      case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
-        hsmbus->ListenCpltCallback = pCallback;
-        break;
-
-      case HAL_SMBUS_ERROR_CB_ID :
-        hsmbus->ErrorCallback = pCallback;
-        break;
-
-      case HAL_SMBUS_MSPINIT_CB_ID :
-        hsmbus->MspInitCallback = pCallback;
-        break;
-
-      case HAL_SMBUS_MSPDEINIT_CB_ID :
-        hsmbus->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SMBUS_MSPINIT_CB_ID :
-        hsmbus->MspInitCallback = pCallback;
-        break;
-
-      case HAL_SMBUS_MSPDEINIT_CB_ID :
-        hsmbus->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsmbus);
-  return status;
-}
-
-/**
-  * @brief  Unregister an SMBUS Callback
-  *         SMBUS callback is redirected to the weak predefined callback
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
-  *          @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
-  *          @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
-  *          @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
-  *          @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
-  *          @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
-  *          @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
-                                               HAL_SMBUS_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hsmbus);
-
-  if (HAL_SMBUS_STATE_READY == hsmbus->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
-        hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
-        break;
-
-      case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
-        hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
-        break;
-
-      case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
-        hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
-        break;
-
-      case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
-        hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
-        break;
-
-      case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
-        hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
-        break;
-
-      case HAL_SMBUS_ERROR_CB_ID :
-        hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback;               /* Legacy weak ErrorCallback        */
-        break;
-
-      case HAL_SMBUS_MSPINIT_CB_ID :
-        hsmbus->MspInitCallback = HAL_SMBUS_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_SMBUS_MSPDEINIT_CB_ID :
-        hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SMBUS_MSPINIT_CB_ID :
-        hsmbus->MspInitCallback = HAL_SMBUS_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_SMBUS_MSPDEINIT_CB_ID :
-        hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsmbus);
-  return status;
-}
-
-/**
-  * @brief  Register the Slave Address Match SMBUS Callback
-  *         To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  pCallback pointer to the Address Match Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
-                                                 pSMBUS_AddrCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hsmbus);
-
-  if (HAL_SMBUS_STATE_READY == hsmbus->State)
-  {
-    hsmbus->AddrCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsmbus);
-  return status;
-}
-
-/**
-  * @brief  UnRegister the Slave Address Match SMBUS Callback
-  *         Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hsmbus);
-
-  if (HAL_SMBUS_STATE_READY == hsmbus->State)
-  {
-    hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsmbus);
-  return status;
-}
-
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
-  *  @brief   Data transfers functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the SMBUS data
-    transfers.
-
-    (#) Blocking mode function to check if device is ready for usage is :
-        (++) HAL_SMBUS_IsDeviceReady()
-
-    (#) There is only one mode of transfer:
-       (++) Non-Blocking mode : The communication is performed using Interrupts.
-            These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the
-            dedicated SMBUS IRQ when using Interrupt mode.
-
-    (#) Non-Blocking mode functions with Interrupt are :
-        (++) HAL_SMBUS_Master_Transmit_IT()
-        (++) HAL_SMBUS_Master_Receive_IT()
-        (++) HAL_SMBUS_Slave_Transmit_IT()
-        (++) HAL_SMBUS_Slave_Receive_IT()
-        (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
-        (++) HAL_SMBUS_DisableListen_IT()
-        (++) HAL_SMBUS_EnableAlert_IT()
-        (++) HAL_SMBUS_DisableAlert_IT()
-
-    (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
-        (++) HAL_SMBUS_MasterTxCpltCallback()
-        (++) HAL_SMBUS_MasterRxCpltCallback()
-        (++) HAL_SMBUS_SlaveTxCpltCallback()
-        (++) HAL_SMBUS_SlaveRxCpltCallback()
-        (++) HAL_SMBUS_AddrCallback()
-        (++) HAL_SMBUS_ListenCpltCallback()
-        (++) HAL_SMBUS_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
-                                               uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  uint32_t tmp;
-
-  /* Check the parameters */
-  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (hsmbus->State == HAL_SMBUS_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsmbus);
-
-    hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
-    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-    /* Prepare transfer parameters */
-    hsmbus->pBuffPtr = pData;
-    hsmbus->XferCount = Size;
-    hsmbus->XferOptions = XferOptions;
-
-    /* In case of Quick command, remove autoend mode */
-    /* Manage the stop generation by software */
-    if (hsmbus->pBuffPtr == NULL)
-    {
-      hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
-    }
-
-    if (Size > MAX_NBYTE_SIZE)
-    {
-      hsmbus->XferSize = MAX_NBYTE_SIZE;
-    }
-    else
-    {
-      hsmbus->XferSize = Size;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
-    {
-      SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
-                           SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
-                           SMBUS_GENERATE_START_WRITE);
-    }
-    else
-    {
-      /* If transfer direction not change, do not generate Restart Condition */
-      /* Mean Previous state is same as current state */
-
-      /* Store current volatile XferOptions, misra rule */
-      tmp = hsmbus->XferOptions;
-
-      if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \
-          (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
-      {
-        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
-                             SMBUS_NO_STARTSTOP);
-      }
-      /* Else transfer direction change, so generate Restart with new transfer direction */
-      else
-      {
-        /* Convert OTHER_xxx XferOptions if any */
-        SMBUS_ConvertOtherXferOptions(hsmbus);
-
-        /* Handle Transfer */
-        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
-                             hsmbus->XferOptions,
-                             SMBUS_GENERATE_START_WRITE);
-      }
-
-      /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
-      /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
-      if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
-      {
-        hsmbus->XferSize--;
-        hsmbus->XferCount--;
-      }
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus);
-
-    /* Note : The SMBUS interrupts must be enabled after unlocking current process
-              to avoid the risk of SMBUS interrupt handle execution before current
-              process unlock */
-    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
-                                              uint16_t Size, uint32_t XferOptions)
-{
-  uint32_t tmp;
-
-  /* Check the parameters */
-  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (hsmbus->State == HAL_SMBUS_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsmbus);
-
-    hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
-    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hsmbus->pBuffPtr = pData;
-    hsmbus->XferCount = Size;
-    hsmbus->XferOptions = XferOptions;
-
-    /* In case of Quick command, remove autoend mode */
-    /* Manage the stop generation by software */
-    if (hsmbus->pBuffPtr == NULL)
-    {
-      hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
-    }
-
-    if (Size > MAX_NBYTE_SIZE)
-    {
-      hsmbus->XferSize = MAX_NBYTE_SIZE;
-    }
-    else
-    {
-      hsmbus->XferSize = Size;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
-    {
-      SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
-                           SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
-                           SMBUS_GENERATE_START_READ);
-    }
-    else
-    {
-      /* If transfer direction not change, do not generate Restart Condition */
-      /* Mean Previous state is same as current state */
-
-      /* Store current volatile XferOptions, Misra rule */
-      tmp = hsmbus->XferOptions;
-
-      if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \
-          (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
-      {
-        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
-                             SMBUS_NO_STARTSTOP);
-      }
-      /* Else transfer direction change, so generate Restart with new transfer direction */
-      else
-      {
-        /* Convert OTHER_xxx XferOptions if any */
-        SMBUS_ConvertOtherXferOptions(hsmbus);
-
-        /* Handle Transfer */
-        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
-                             hsmbus->XferOptions,
-                             SMBUS_GENERATE_START_READ);
-      }
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus);
-
-    /* Note : The SMBUS interrupts must be enabled after unlocking current process
-              to avoid the risk of SMBUS interrupt handle execution before current
-              process unlock */
-    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Abort a master/host SMBUS process communication with Interrupt.
-  * @note   This abort can be called only if state is ready
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
-{
-  if (hsmbus->State == HAL_SMBUS_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsmbus);
-
-    /* Keep the same state as previous */
-    /* to perform as well the call of the corresponding end of transfer callback */
-    if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
-    {
-      hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
-    }
-    else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
-    {
-      hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
-    }
-    else
-    {
-      /* Wrong usage of abort function */
-      /* This function should be used only in case of abort monitored by master device */
-      return HAL_ERROR;
-    }
-    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
-    /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
-    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
-    SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus);
-
-    /* Note : The SMBUS interrupts must be enabled after unlocking current process
-              to avoid the risk of SMBUS interrupt handle execution before current
-              process unlock */
-    if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
-    {
-      SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
-    }
-    else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
-    {
-      SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
-                                              uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
-  {
-    if ((pData == NULL) || (Size == 0UL))
-    {
-      hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
-      return HAL_ERROR;
-    }
-
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
-
-    /* Process Locked */
-    __HAL_LOCK(hsmbus);
-
-    hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN);
-    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
-    /* Set SBC bit to manage Acknowledge at each bit */
-    hsmbus->Instance->CR1 |= I2C_CR1_SBC;
-
-    /* Enable Address Acknowledge */
-    hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hsmbus->pBuffPtr = pData;
-    hsmbus->XferCount = Size;
-    hsmbus->XferOptions = XferOptions;
-
-    /* Convert OTHER_xxx XferOptions if any */
-    SMBUS_ConvertOtherXferOptions(hsmbus);
-
-    if (Size > MAX_NBYTE_SIZE)
-    {
-      hsmbus->XferSize = MAX_NBYTE_SIZE;
-    }
-    else
-    {
-      hsmbus->XferSize = Size;
-    }
-
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
-    {
-      SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize,
-                           SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
-                           SMBUS_NO_STARTSTOP);
-    }
-    else
-    {
-      /* Set NBYTE to transmit */
-      SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
-                           SMBUS_NO_STARTSTOP);
-
-      /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
-      /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
-      if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
-      {
-        hsmbus->XferSize--;
-        hsmbus->XferCount--;
-      }
-    }
-
-    /* Clear ADDR flag after prepare the transfer parameters */
-    /* This action will generate an acknowledge to the HOST */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus);
-
-    /* Note : The SMBUS interrupts must be enabled after unlocking current process
-              to avoid the risk of SMBUS interrupt handle execution before current
-              process unlock */
-    /* REnable ADDR interrupt */
-    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
-                                             uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
-  {
-    if ((pData == NULL) || (Size == 0UL))
-    {
-      hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
-      return HAL_ERROR;
-    }
-
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
-
-    /* Process Locked */
-    __HAL_LOCK(hsmbus);
-
-    hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN);
-    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
-    /* Set SBC bit to manage Acknowledge at each bit */
-    hsmbus->Instance->CR1 |= I2C_CR1_SBC;
-
-    /* Enable Address Acknowledge */
-    hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hsmbus->pBuffPtr = pData;
-    hsmbus->XferSize = Size;
-    hsmbus->XferCount = Size;
-    hsmbus->XferOptions = XferOptions;
-
-    /* Convert OTHER_xxx XferOptions if any */
-    SMBUS_ConvertOtherXferOptions(hsmbus);
-
-    /* Set NBYTE to receive */
-    /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
-    /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
-    /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
-    /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
-    if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
-    {
-      SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
-                           SMBUS_NO_STARTSTOP);
-    }
-    else
-    {
-      SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
-    }
-
-    /* Clear ADDR flag after prepare the transfer parameters */
-    /* This action will generate an acknowledge to the HOST */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus);
-
-    /* Note : The SMBUS interrupts must be enabled after unlocking current process
-              to avoid the risk of SMBUS interrupt handle execution before current
-              process unlock */
-    /* REnable ADDR interrupt */
-    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Enable the Address listen mode with Interrupt.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
-{
-  hsmbus->State = HAL_SMBUS_STATE_LISTEN;
-
-  /* Enable the Address Match interrupt */
-  SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the Address listen mode with Interrupt.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Disable Address listen mode only if a transfer is not ongoing */
-  if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
-  {
-    hsmbus->State = HAL_SMBUS_STATE_READY;
-
-    /* Disable the Address Match interrupt */
-    SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Enable the SMBUS alert mode with Interrupt.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUSx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Enable SMBus alert */
-  hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
-
-  /* Clear ALERT flag */
-  __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
-
-  /* Enable Alert Interrupt */
-  SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
-
-  return HAL_OK;
-}
-/**
-  * @brief  Disable the SMBUS alert mode with Interrupt.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUSx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Enable SMBus alert */
-  hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
-
-  /* Disable Alert Interrupt */
-  SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Check if target device is ready for communication.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  Trials Number of trials
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
-                                          uint32_t Timeout)
-{
-  uint32_t tickstart;
-
-  __IO uint32_t SMBUS_Trials = 0UL;
-
-  FlagStatus tmp1;
-  FlagStatus tmp2;
-
-  if (hsmbus->State == HAL_SMBUS_STATE_READY)
-  {
-    if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsmbus);
-
-    hsmbus->State = HAL_SMBUS_STATE_BUSY;
-    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
-    do
-    {
-      /* Generate Start */
-      hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
-
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-      /* Wait until STOPF flag is set or a NACK flag is set*/
-      tickstart = HAL_GetTick();
-
-      tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-      tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
-
-      while ((tmp1 == RESET) && (tmp2 == RESET))
-      {
-        if (Timeout != HAL_MAX_DELAY)
-        {
-          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
-          {
-            /* Device is ready */
-            hsmbus->State = HAL_SMBUS_STATE_READY;
-
-            /* Update SMBUS error code */
-            hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
-
-            /* Process Unlocked */
-            __HAL_UNLOCK(hsmbus);
-            return HAL_ERROR;
-          }
-        }
-
-        tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-        tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
-      }
-
-      /* Check if the NACKF flag has not been set */
-      if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
-      {
-        /* Wait until STOPF flag is reset */
-        if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        /* Clear STOP Flag */
-        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
-        /* Device is ready */
-        hsmbus->State = HAL_SMBUS_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hsmbus);
-
-        return HAL_OK;
-      }
-      else
-      {
-        /* Wait until STOPF flag is reset */
-        if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        /* Clear NACK Flag */
-        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
-        /* Clear STOP Flag, auto generated with autoend*/
-        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-      }
-
-      /* Check if the maximum allowed number of trials has been reached */
-      if (SMBUS_Trials == Trials)
-      {
-        /* Generate Stop */
-        hsmbus->Instance->CR2 |= I2C_CR2_STOP;
-
-        /* Wait until STOPF flag is reset */
-        if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        /* Clear STOP Flag */
-        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-      }
-
-      /* Increment Trials */
-      SMBUS_Trials++;
-    } while (SMBUS_Trials < Trials);
-
-    hsmbus->State = HAL_SMBUS_STATE_READY;
-
-    /* Update SMBUS error code */
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
-  * @{
-  */
-
-/**
-  * @brief  Handle SMBUS event interrupt request.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval None
-  */
-void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Use a local variable to store the current ISR flags */
-  /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
-  uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR);
-  uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
-
-  /* SMBUS in mode Transmitter ---------------------------------------------------*/
-  if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
-                                           SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
-      ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) ||
-       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
-       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
-       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
-       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
-  {
-    /* Slave mode selected */
-    if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
-    {
-      (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
-    }
-    /* Master mode selected */
-    else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
-    {
-      (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-  }
-
-  /* SMBUS in mode Receiver ----------------------------------------------------*/
-  if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
-                                           SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
-      ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) ||
-       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
-       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
-       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
-       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
-  {
-    /* Slave mode selected */
-    if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
-    {
-      (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
-    }
-    /* Master mode selected */
-    else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
-    {
-      (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-  }
-
-  /* SMBUS in mode Listener Only --------------------------------------------------*/
-  if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) ||
-       (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) ||
-       (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) &&
-      ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) ||
-       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
-       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
-  {
-    if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
-    {
-      (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
-    }
-  }
-}
-
-/**
-  * @brief  Handle SMBUS error interrupt request.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval None
-  */
-void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
-{
-  SMBUS_ITErrorHandler(hsmbus);
-}
-
-/**
-  * @brief  Master Tx Transfer completed callback.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval None
-  */
-__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmbus);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Master Rx Transfer completed callback.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval None
-  */
-__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmbus);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
-   */
-}
-
-/** @brief  Slave Tx Transfer completed callback.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval None
-  */
-__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmbus);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Rx Transfer completed callback.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval None
-  */
-__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmbus);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Address Match callback.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  TransferDirection Master request Transfer Direction (Write/Read)
-  * @param  AddrMatchCode Address Match Code
-  * @retval None
-  */
-__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
-                                   uint16_t AddrMatchCode)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmbus);
-  UNUSED(TransferDirection);
-  UNUSED(AddrMatchCode);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMBUS_AddrCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Listen Complete callback.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval None
-  */
-__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmbus);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  SMBUS error callback.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval None
-  */
-__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsmbus);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMBUS_ErrorCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
-  *  @brief   Peripheral State and Errors functions
-  *
-@verbatim
- ===============================================================================
-            ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the SMBUS handle state.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @retval HAL state
-  */
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Return SMBUS handle state */
-  return hsmbus->State;
-}
-
-/**
-  * @brief  Return the SMBUS error code.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *              the configuration information for the specified SMBUS.
-  * @retval SMBUS Error Code
-  */
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
-{
-  return hsmbus->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
-  *  @brief   Data transfers Private functions
-  * @{
-  */
-
-/**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  StatusFlags Value of Interrupt Flags.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
-{
-  uint16_t DevAddress;
-
-  /* Process Locked */
-  __HAL_LOCK(hsmbus);
-
-  if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
-  {
-    /* Clear NACK Flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
-    /* Set corresponding Error Code */
-    /* No need to generate STOP, it is automatically done */
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus);
-
-    /* Call the Error callback to inform upper layer */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-    hsmbus->ErrorCallback(hsmbus);
-#else
-    HAL_SMBUS_ErrorCallback(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-  }
-  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
-  {
-    /* Check and treat errors if errors occurs during STOP process */
-    SMBUS_ITErrorHandler(hsmbus);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
-    {
-      /* Disable Interrupt */
-      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
-
-      /* Clear STOP Flag */
-      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      SMBUS_RESET_CR2(hsmbus);
-
-      /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
-      /* Disable the selected SMBUS peripheral */
-      __HAL_SMBUS_DISABLE(hsmbus);
-
-      hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
-      hsmbus->State = HAL_SMBUS_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hsmbus);
-
-      /* Re-enable the selected SMBUS peripheral */
-      __HAL_SMBUS_ENABLE(hsmbus);
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-      hsmbus->MasterTxCpltCallback(hsmbus);
-#else
-      HAL_SMBUS_MasterTxCpltCallback(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-    }
-    else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
-    {
-      /* Store Last receive data if any */
-      if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
-      {
-        /* Read data from RXDR */
-        *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
-
-        /* Increment Buffer pointer */
-        hsmbus->pBuffPtr++;
-
-        if ((hsmbus->XferSize > 0U))
-        {
-          hsmbus->XferSize--;
-          hsmbus->XferCount--;
-        }
-      }
-
-      /* Disable Interrupt */
-      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
-
-      /* Clear STOP Flag */
-      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      SMBUS_RESET_CR2(hsmbus);
-
-      hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
-      hsmbus->State = HAL_SMBUS_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hsmbus);
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-      hsmbus->MasterRxCpltCallback(hsmbus);
-#else
-      HAL_SMBUS_MasterRxCpltCallback(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-  }
-  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
-  {
-    /* Read data from RXDR */
-    *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
-
-    /* Increment Buffer pointer */
-    hsmbus->pBuffPtr++;
-
-    /* Increment Size counter */
-    hsmbus->XferSize--;
-    hsmbus->XferCount--;
-  }
-  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
-  {
-    /* Write data to TXDR */
-    hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
-
-    /* Increment Buffer pointer */
-    hsmbus->pBuffPtr++;
-
-    /* Increment Size counter */
-    hsmbus->XferSize--;
-    hsmbus->XferCount--;
-  }
-  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)
-  {
-    if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
-    {
-      DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD);
-
-      if (hsmbus->XferCount > MAX_NBYTE_SIZE)
-      {
-        SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE,
-                             (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
-                             SMBUS_NO_STARTSTOP);
-        hsmbus->XferSize = MAX_NBYTE_SIZE;
-      }
-      else
-      {
-        hsmbus->XferSize = hsmbus->XferCount;
-        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
-                             SMBUS_NO_STARTSTOP);
-        /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
-        /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
-        if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
-        {
-          hsmbus->XferSize--;
-          hsmbus->XferCount--;
-        }
-      }
-    }
-    else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U))
-    {
-      /* Call TxCpltCallback() if no stop mode is set */
-      if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
-      {
-        /* Call the corresponding callback to inform upper layer of End of Transfer */
-        if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
-        {
-          /* Disable Interrupt */
-          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
-          hsmbus->PreviousState = hsmbus->State;
-          hsmbus->State = HAL_SMBUS_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hsmbus);
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-          hsmbus->MasterTxCpltCallback(hsmbus);
-#else
-          HAL_SMBUS_MasterTxCpltCallback(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-        }
-        else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
-        {
-          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
-          hsmbus->PreviousState = hsmbus->State;
-          hsmbus->State = HAL_SMBUS_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hsmbus);
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-          hsmbus->MasterRxCpltCallback(hsmbus);
-#else
-          HAL_SMBUS_MasterRxCpltCallback(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-        }
-        else
-        {
-          /* Nothing to do */
-        }
-      }
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-  }
-  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET)
-  {
-    if (hsmbus->XferCount == 0U)
-    {
-      /* Specific use case for Quick command */
-      if (hsmbus->pBuffPtr == NULL)
-      {
-        /* Generate a Stop command */
-        hsmbus->Instance->CR2 |= I2C_CR2_STOP;
-      }
-      /* Call TxCpltCallback() if no stop mode is set */
-      else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
-      {
-        /* No Generate Stop, to permit restart mode */
-        /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
-
-        /* Call the corresponding callback to inform upper layer of End of Transfer */
-        if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
-        {
-          /* Disable Interrupt */
-          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
-          hsmbus->PreviousState = hsmbus->State;
-          hsmbus->State = HAL_SMBUS_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hsmbus);
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-          hsmbus->MasterTxCpltCallback(hsmbus);
-#else
-          HAL_SMBUS_MasterTxCpltCallback(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-        }
-        else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
-        {
-          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
-          hsmbus->PreviousState = hsmbus->State;
-          hsmbus->State = HAL_SMBUS_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hsmbus);
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-          hsmbus->MasterRxCpltCallback(hsmbus);
-#else
-          HAL_SMBUS_MasterRxCpltCallback(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-        }
-        else
-        {
-          /* Nothing to do */
-        }
-      }
-      else
-      {
-        /* Nothing to do */
-      }
-    }
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hsmbus);
-
-  return HAL_OK;
-}
-/**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  StatusFlags Value of Interrupt Flags.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
-{
-  uint8_t TransferDirection;
-  uint16_t SlaveAddrCode;
-
-  /* Process Locked */
-  __HAL_LOCK(hsmbus);
-
-  if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
-  {
-    /* Check that SMBUS transfer finished */
-    /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
-    /* Mean XferCount == 0*/
-    /* So clear Flag NACKF only */
-    if (hsmbus->XferCount == 0U)
-    {
-      /* Clear NACK Flag */
-      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hsmbus);
-    }
-    else
-    {
-      /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
-      /* Clear NACK Flag */
-      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
-      /* Set HAL State to "Idle" State, mean to LISTEN state */
-      /* So reset Slave Busy state */
-      hsmbus->PreviousState = hsmbus->State;
-      hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
-      hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
-
-      /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
-      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
-
-      /* Set ErrorCode corresponding to a Non-Acknowledge */
-      hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hsmbus);
-
-      /* Call the Error callback to inform upper layer */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-      hsmbus->ErrorCallback(hsmbus);
-#else
-      HAL_SMBUS_ErrorCallback(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-    }
-  }
-  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET)
-  {
-    TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus));
-    SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus));
-
-    /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
-    /* Other ADDRInterrupt will be treat in next Listen usecase */
-    __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus);
-
-    /* Call Slave Addr callback */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-    hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
-#else
-    HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-  }
-  else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) ||
-           (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
-  {
-    if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
-    {
-      /* Read data from RXDR */
-      *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
-
-      /* Increment Buffer pointer */
-      hsmbus->pBuffPtr++;
-
-      hsmbus->XferSize--;
-      hsmbus->XferCount--;
-
-      if (hsmbus->XferCount == 1U)
-      {
-        /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
-        /* or only the last Byte of Transfer */
-        /* So reset the RELOAD bit mode */
-        hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
-        SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
-      }
-      else if (hsmbus->XferCount == 0U)
-      {
-        /* Last Byte is received, disable Interrupt */
-        SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
-
-        /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
-        hsmbus->PreviousState = hsmbus->State;
-        hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hsmbus);
-
-        /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-        hsmbus->SlaveRxCpltCallback(hsmbus);
-#else
-        HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-      }
-      else
-      {
-        /* Set Reload for next Bytes */
-        SMBUS_TransferConfig(hsmbus, 0, 1,
-                             SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
-                             SMBUS_NO_STARTSTOP);
-
-        /* Ack last Byte Read */
-        hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
-      }
-    }
-    else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
-    {
-      if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
-      {
-        if (hsmbus->XferCount > MAX_NBYTE_SIZE)
-        {
-          SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE,
-                               (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
-                               SMBUS_NO_STARTSTOP);
-          hsmbus->XferSize = MAX_NBYTE_SIZE;
-        }
-        else
-        {
-          hsmbus->XferSize = hsmbus->XferCount;
-          SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
-                               SMBUS_NO_STARTSTOP);
-          /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
-          /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
-          if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
-          {
-            hsmbus->XferSize--;
-            hsmbus->XferCount--;
-          }
-        }
-      }
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-  }
-  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
-  {
-    /* Write data to TXDR only if XferCount not reach "0" */
-    /* A TXIS flag can be set, during STOP treatment      */
-    /* Check if all Data have already been sent */
-    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
-    if (hsmbus->XferCount > 0U)
-    {
-      /* Write data to TXDR */
-      hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
-
-      /* Increment Buffer pointer */
-      hsmbus->pBuffPtr++;
-
-      hsmbus->XferCount--;
-      hsmbus->XferSize--;
-    }
-
-    if (hsmbus->XferCount == 0U)
-    {
-      /* Last Byte is Transmitted */
-      /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
-      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
-      hsmbus->PreviousState = hsmbus->State;
-      hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hsmbus);
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-      hsmbus->SlaveTxCpltCallback(hsmbus);
-#else
-      HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-    }
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-
-  /* Check if STOPF is set */
-  if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
-  {
-    if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
-    {
-      /* Store Last receive data if any */
-      if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
-      {
-        /* Read data from RXDR */
-        *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
-
-        /* Increment Buffer pointer */
-        hsmbus->pBuffPtr++;
-
-        if ((hsmbus->XferSize > 0U))
-        {
-          hsmbus->XferSize--;
-          hsmbus->XferCount--;
-        }
-      }
-
-      /* Disable RX and TX Interrupts */
-      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
-
-      /* Disable ADDR Interrupt */
-      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
-
-      /* Disable Address Acknowledge */
-      hsmbus->Instance->CR2 |= I2C_CR2_NACK;
-
-      /* Clear Configuration Register 2 */
-      SMBUS_RESET_CR2(hsmbus);
-
-      /* Clear STOP Flag */
-      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
-      /* Clear ADDR flag */
-      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
-
-      hsmbus->XferOptions = 0;
-      hsmbus->PreviousState = hsmbus->State;
-      hsmbus->State = HAL_SMBUS_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hsmbus);
-
-      /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-      hsmbus->ListenCpltCallback(hsmbus);
-#else
-      HAL_SMBUS_ListenCpltCallback(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hsmbus);
-
-  return HAL_OK;
-}
-/**
-  * @brief  Manage the enabling of Interrupts.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
-  * @retval HAL status
-  */
-static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
-{
-  uint32_t tmpisr = 0UL;
-
-  if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
-  {
-    /* Enable ERR interrupt */
-    tmpisr |= SMBUS_IT_ERRI;
-  }
-
-  if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
-  {
-    /* Enable ADDR, STOP interrupt */
-    tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
-  }
-
-  if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
-  {
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
-    tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
-  }
-
-  if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
-  {
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-    tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
-  }
-
-  /* Enable interrupts only at the end */
-  /* to avoid the risk of SMBUS interrupt handle execution before */
-  /* all interrupts requested done */
-  __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
-}
-/**
-  * @brief  Manage the disabling of Interrupts.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
-  * @retval HAL status
-  */
-static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
-{
-  uint32_t tmpisr = 0UL;
-  uint32_t tmpstate = hsmbus->State;
-
-  if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT))
-  {
-    /* Disable ERR interrupt */
-    tmpisr |= SMBUS_IT_ERRI;
-  }
-
-  if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
-  {
-    /* Disable TC, STOP, NACK and TXI interrupt */
-    tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
-
-    if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
-        && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
-    {
-      /* Disable ERR interrupt */
-      tmpisr |= SMBUS_IT_ERRI;
-    }
-
-    if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
-    {
-      /* Disable STOP and NACK interrupt */
-      tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
-    }
-  }
-
-  if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
-  {
-    /* Disable TC, STOP, NACK and RXI interrupt */
-    tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
-
-    if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
-        && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
-    {
-      /* Disable ERR interrupt */
-      tmpisr |= SMBUS_IT_ERRI;
-    }
-
-    if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
-    {
-      /* Disable STOP and NACK interrupt */
-      tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
-    }
-  }
-
-  if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
-  {
-    /* Disable ADDR, STOP and NACK interrupt */
-    tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
-
-    if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
-    {
-      /* Disable ERR interrupt */
-      tmpisr |= SMBUS_IT_ERRI;
-    }
-  }
-
-  /* Disable interrupts only at the end */
-  /* to avoid a breaking situation like at "t" time */
-  /* all disable interrupts request are not done */
-  __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
-}
-
-/**
-  * @brief  SMBUS interrupts error handler.
-  * @param  hsmbus SMBUS handle.
-  * @retval None
-  */
-static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
-{
-  uint32_t itflags   = READ_REG(hsmbus->Instance->ISR);
-  uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
-  uint32_t tmpstate;
-  uint32_t tmperror;
-
-  /* SMBUS Bus error interrupt occurred ------------------------------------*/
-  if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \
-      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
-  {
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
-
-    /* Clear BERR flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
-  }
-
-  /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
-  if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \
-      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
-  {
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
-
-    /* Clear OVR flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
-  }
-
-  /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
-  if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \
-      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
-  {
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
-
-    /* Clear ARLO flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
-  }
-
-  /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
-  if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \
-      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
-  {
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
-
-    /* Clear TIMEOUT flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
-  }
-
-  /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
-  if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \
-      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
-  {
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
-
-    /* Clear ALERT flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
-  }
-
-  /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
-  if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \
-      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
-  {
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
-
-    /* Clear PEC error flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
-  }
-
-  /* Store current volatile hsmbus->State, misra rule */
-  tmperror = hsmbus->ErrorCode;
-
-  /* Call the Error Callback in case of Error detected */
-  if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF))
-  {
-    /* Do not Reset the HAL state in case of ALERT error */
-    if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
-    {
-      /* Store current volatile hsmbus->State, misra rule */
-      tmpstate = hsmbus->State;
-
-      if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
-          || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
-      {
-        /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
-        /* keep HAL_SMBUS_STATE_LISTEN if set */
-        hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
-        hsmbus->State = HAL_SMBUS_STATE_LISTEN;
-      }
-    }
-
-    /* Call the Error callback to inform upper layer */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-    hsmbus->ErrorCallback(hsmbus);
-#else
-    HAL_SMBUS_ErrorCallback(hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  Handle SMBUS Communication Timeout.
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUS.
-  * @param  Flag Specifies the SMBUS flag to check.
-  * @param  Status The new Flag status (SET or RESET).
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
-                                                      FlagStatus Status, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Wait until flag is set */
-  while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
-      {
-        hsmbus->PreviousState = hsmbus->State;
-        hsmbus->State = HAL_SMBUS_STATE_READY;
-
-        /* Update SMBUS error code */
-        hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hsmbus);
-
-        return HAL_ERROR;
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
-  * @param  hsmbus SMBUS handle.
-  * @param  DevAddress specifies the slave address to be programmed.
-  * @param  Size specifies the number of bytes to be programmed.
-  *   This parameter must be a value between 0 and 255.
-  * @param  Mode New state of the SMBUS START condition generation.
-  *   This parameter can be one or a combination  of the following values:
-  *     @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
-  *     @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
-  *     @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
-  *     @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
-  * @param  Request New state of the SMBUS START condition generation.
-  *   This parameter can be one of the following values:
-  *     @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
-  *     @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
-  *     @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
-  *     @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
-  * @retval None
-  */
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size,
-                                 uint32_t Mode, uint32_t Request)
-{
-  /* Check the parameters */
-  assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
-  assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
-  assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
-
-  /* update CR2 register */
-  MODIFY_REG(hsmbus->Instance->CR2,
-             ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
-               (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \
-               I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
-             (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
-                        (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
-                        (uint32_t)Mode | (uint32_t)Request));
-}
-
-/**
-  * @brief  Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
-  * @param  hsmbus SMBUS handle.
-  * @retval None
-  */
-static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC   */
-  /* it request implicitly to generate a restart condition */
-  /* set XferOptions to SMBUS_FIRST_FRAME                  */
-  if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
-  {
-    hsmbus->XferOptions = SMBUS_FIRST_FRAME;
-  }
-  /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
-  /* it request implicitly to generate a restart condition      */
-  /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE  */
-  else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
-  {
-    hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
-  }
-  /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
-  /* it request implicitly to generate a restart condition             */
-  /* then generate a stop condition at the end of transfer             */
-  /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC              */
-  else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
-  {
-    hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
-  }
-  /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
-  /* it request implicitly to generate a restart condition               */
-  /* then generate a stop condition at the end of transfer               */
-  /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC              */
-  else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
-  {
-    hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-}
-/**
-  * @}
-  */
-
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus_ex.c
deleted file mode 100644
index 717d95f5ed..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus_ex.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_smbus_ex.c
-  * @author  MCD Application Team
-  * @brief   SMBUS Extended HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of SMBUS Extended peripheral:
-  *           + Extended features functions
-  *
-  @verbatim
-  ==============================================================================
-               ##### SMBUS peripheral Extended features  #####
-  ==============================================================================
-
-  [..] Comparing to other previous devices, the SMBUS interface for STM32L0xx
-       devices contains the following additional features
-
-       (+) Disable or enable wakeup from Stop mode(s)
-       (+) Disable or enable Fast Mode Plus
-
-                     ##### How to use this driver #####
-  ==============================================================================
-    (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
-          (++) HAL_SMBUSEx_EnableWakeUp()
-          (++) HAL_SMBUSEx_DisableWakeUp()
-    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
-          (++) HAL_SMBUSEx_EnableFastModePlus()
-          (++) HAL_SMBUSEx_DisableFastModePlus()
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SMBUSEx SMBUSEx
-  * @brief SMBUS Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
-  * @{
-  */
-
-/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
-  * @brief    WakeUp Mode Functions
-  *
-@verbatim
- ===============================================================================
-                      ##### WakeUp Mode Functions #####
- ===============================================================================
-    [..] This section provides functions allowing to:
-      (+) Configure Wake Up Feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enable SMBUS wakeup from Stop mode(s).
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUSx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
-
-  if (hsmbus->State == HAL_SMBUS_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsmbus);
-
-    hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
-    /* Disable the selected SMBUS peripheral */
-    __HAL_SMBUS_DISABLE(hsmbus);
-
-    /* Enable wakeup from stop mode */
-    hsmbus->Instance->CR1 |= I2C_CR1_WUPEN;
-
-    __HAL_SMBUS_ENABLE(hsmbus);
-
-    hsmbus->State = HAL_SMBUS_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Disable SMBUS wakeup from Stop mode(s).
-  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMBUSx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
-
-  if (hsmbus->State == HAL_SMBUS_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsmbus);
-
-    hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
-    /* Disable the selected SMBUS peripheral */
-    __HAL_SMBUS_DISABLE(hsmbus);
-
-    /* Disable wakeup from stop mode */
-    hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN);
-
-    __HAL_SMBUS_ENABLE(hsmbus);
-
-    hsmbus->State = HAL_SMBUS_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @}
-  */
-#if  (defined(SYSCFG_CFGR2_I2C_PB6_FMP) || defined(SYSCFG_CFGR2_I2C_PB7_FMP)) || (defined(SYSCFG_CFGR2_I2C_PB8_FMP) || defined(SYSCFG_CFGR2_I2C_PB9_FMP)) || (defined(SYSCFG_CFGR2_I2C1_FMP)) || defined(SYSCFG_CFGR2_I2C2_FMP) || defined(SYSCFG_CFGR2_I2C3_FMP)
-
-/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
-  * @brief    Fast Mode Plus Functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Fast Mode Plus Functions #####
- ===============================================================================
-    [..] This section provides functions allowing to:
-      (+) Configure Fast Mode Plus
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Enable the SMBUS fast mode plus driving capability.
-  * @param ConfigFastModePlus Selects the pin.
-  *   This parameter can be one of the @ref SMBUSEx_FastModePlus values
-  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
-  *        I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
-  *        on each one of the following pins PB6, PB7, PB8 and PB9.
-  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
-  *        can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
-  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
-  *        only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
-  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
-  *        only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
-  * @retval None
-  */
-void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  /* Check the parameter */
-  assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
-
-  /* Enable SYSCFG clock */
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-  /* Enable fast mode plus driving capability for selected pin */
-  SET_BIT(SYSCFG->CFGR2, (uint32_t)ConfigFastModePlus);
-}
-
-/**
-  * @brief Disable the SMBUS fast mode plus driving capability.
-  * @param ConfigFastModePlus Selects the pin.
-  *   This parameter can be one of the @ref SMBUSEx_FastModePlus values
-  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
-  *        I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
-  *        on each one of the following pins PB6, PB7, PB8 and PB9.
-  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
-  *        can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
-  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
-  *        only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
-  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
-  *        only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
-  * @retval None
-  */
-void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  /* Check the parameter */
-  assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
-
-  /* Enable SYSCFG clock */
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-  /* Disable fast mode plus driving capability for selected pin */
-  CLEAR_BIT(SYSCFG->CFGR2, (uint32_t)ConfigFastModePlus);
-}
-
-/**
-  * @}
-  */
-
-#endif /* Fast Mode Plus Availability */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c
deleted file mode 100644
index 8caa16fd44..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c
+++ /dev/null
@@ -1,3970 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_spi.c
-  * @author  MCD Application Team
-  * @brief   SPI HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The SPI HAL driver can be used as follows:
-
-      (#) Declare a SPI_HandleTypeDef handle structure, for example:
-          SPI_HandleTypeDef  hspi;
-
-      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
-          (##) Enable the SPIx interface clock
-          (##) SPI pins configuration
-              (+++) Enable the clock for the SPI GPIOs
-              (+++) Configure these SPI pins as alternate function push-pull
-          (##) NVIC configuration if you need to use interrupt process
-              (+++) Configure the SPIx interrupt priority
-              (+++) Enable the NVIC SPI IRQ handle
-          (##) DMA Configuration if you need to use DMA process
-              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
-              (+++) Enable the DMAx clock
-              (+++) Configure the DMA handle parameters
-              (+++) Configure the DMA Tx or Rx Stream/Channel
-              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
-              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
-
-      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
-          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
-
-      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
-          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-              by calling the customized HAL_SPI_MspInit() API.
-     [..]
-       Circular mode restriction:
-      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
-          (##) Master 2Lines RxOnly
-          (##) Master 1Line Rx
-      (#) The CRC feature is not managed when the DMA circular mode is enabled
-      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
-          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
-     [..]
-       Master Receive mode restriction:
-      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
-          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
-          does not initiate a new transfer the following procedure has to be respected:
-          (##) HAL_SPI_DeInit()
-          (##) HAL_SPI_Init()
-     [..]
-       Data buffer address alignment restriction:
-      (#) There is no support for unaligned accesses on the Cortex-M0 processor.
-          If the user wants to transfer in 16Bit data mode, it shall ensure that 16-bit aligned address is used for:
-          (##) pData parameter in HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_Receive() and HAL_SPI_Receive_IT()
-          (##) pTxData and pRxData parameters in HAL_SPI_TransmitReceive() and HAL_SPI_TransmitReceive_IT()
-      (#) There is no such restriction when going through DMA by using HAL_SPI_Transmit_DMA(), HAL_SPI_Receive_DMA()
-          and HAL_SPI_TransmitReceive_DMA().
-     [..]
-       Callback registration:
-
-      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
-          allows the user to configure dynamically the driver callbacks.
-          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
-
-          Function HAL_SPI_RegisterCallback() allows to register following callbacks:
-            (++) TxCpltCallback        : SPI Tx Completed callback
-            (++) RxCpltCallback        : SPI Rx Completed callback
-            (++) TxRxCpltCallback      : SPI TxRx Completed callback
-            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
-            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
-            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
-            (++) ErrorCallback         : SPI Error callback
-            (++) AbortCpltCallback     : SPI Abort callback
-            (++) MspInitCallback       : SPI Msp Init callback
-            (++) MspDeInitCallback     : SPI Msp DeInit callback
-          This function takes as parameters the HAL peripheral handle, the Callback ID
-          and a pointer to the user callback function.
-
-
-      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
-          weak function.
-          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
-          and the Callback ID.
-          This function allows to reset following callbacks:
-            (++) TxCpltCallback        : SPI Tx Completed callback
-            (++) RxCpltCallback        : SPI Rx Completed callback
-            (++) TxRxCpltCallback      : SPI TxRx Completed callback
-            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
-            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
-            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
-            (++) ErrorCallback         : SPI Error callback
-            (++) AbortCpltCallback     : SPI Abort callback
-            (++) MspInitCallback       : SPI Msp Init callback
-            (++) MspDeInitCallback     : SPI Msp DeInit callback
-
-       [..]
-       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
-       all callbacks are set to the corresponding weak functions:
-       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
-       Exception done for MspInit and MspDeInit functions that are
-       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
-       these callbacks are null (not registered beforehand).
-       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
-       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
-       [..]
-       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
-       Exception done MspInit/MspDeInit functions that can be registered/unregistered
-       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
-       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-       Then, the user first registers the MspInit/MspDeInit user callbacks
-       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
-       or HAL_SPI_Init() function.
-
-       [..]
-       When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
-       not defined, the callback registering feature is not available
-       and weak (surcharged) callbacks are used.
-
-     [..]
-       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
-       the following table resume the max SPI frequency reached with data size 8bits/16bits,
-         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
-
-  @endverbatim
-
-  Additional table :
-
-       DataSize = SPI_DATASIZE_8BIT:
-       +----------------------------------------------------------------------------------------------+
-       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
-       | Process | Transfer mode  |---------------------|----------------------|----------------------|
-       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
-       |==============================================================================================|
-       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    /    |     Interrupt  | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
-       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    R    |     Interrupt  | Fpclk/8  | Fpclk/8  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
-       +----------------------------------------------------------------------------------------------+
-
-       DataSize = SPI_DATASIZE_16BIT:
-       +----------------------------------------------------------------------------------------------+
-       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
-       | Process | Transfer mode  |---------------------|----------------------|----------------------|
-       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
-       |==============================================================================================|
-       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    /    |     Interrupt  | Fpclk/4  | Fpclk/4  |    NA     |    NA    |    NA     |   NA     |
-       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/32  | Fpclk/2  |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    R    |     Interrupt  | Fpclk/4  | Fpclk/4  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/32 |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    T    |     Interrupt  | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
-       +----------------------------------------------------------------------------------------------+
-       @note The max SPI frequency depend on SPI data size (8bits, 16bits),
-             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
-       @note
-            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
-            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
-            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
-
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SPI SPI
-  * @brief SPI HAL module driver
-  * @{
-  */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
-  * @{
-  */
-#define SPI_DEFAULT_TIMEOUT 100U
-#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs             */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
-  * @{
-  */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
-                                                       uint32_t Timeout, uint32_t Tickstart);
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-#if (USE_SPI_CRC != 0U)
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-#endif /* USE_SPI_CRC */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Functions SPI Exported Functions
-  * @{
-  */
-
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          de-initialize the SPIx peripheral:
-
-      (+) User must implement HAL_SPI_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_SPI_Init() to configure the selected device with
-          the selected configuration:
-        (++) Mode
-        (++) Direction
-        (++) Data Size
-        (++) Clock Polarity and Phase
-        (++) NSS Management
-        (++) BaudRate Prescaler
-        (++) FirstBit
-        (++) TIMode
-        (++) CRC Calculation
-        (++) CRC Polynomial if CRC enabled
-
-      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
-          of the selected SPIx peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the SPI according to the specified parameters
-  *         in the SPI_InitTypeDef and initialize the associated handle.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
-{
-  /* Check the SPI handle allocation */
-  if (hspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-  assert_param(IS_SPI_MODE(hspi->Init.Mode));
-  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
-  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
-  assert_param(IS_SPI_NSS(hspi->Init.NSS));
-  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
-  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
-  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
-  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
-  {
-    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
-    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
-
-    if (hspi->Init.Mode == SPI_MODE_MASTER)
-    {
-      assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
-    }
-    else
-    {
-      /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
-      hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
-    }
-  }
-  else
-  {
-    assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
-
-    /* Force polarity and phase to TI protocaol requirements */
-    hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
-    hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;
-  }
-#if (USE_SPI_CRC != 0U)
-  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
-  }
-#else
-  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-#endif /* USE_SPI_CRC */
-
-  if (hspi->State == HAL_SPI_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hspi->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-    /* Init the SPI Callback settings */
-    hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
-    hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
-    hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
-    hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
-    hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
-    hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
-    hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
-    hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
-
-    if (hspi->MspInitCallback == NULL)
-    {
-      hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
-    }
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    hspi->MspInitCallback(hspi);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    HAL_SPI_MspInit(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-  }
-
-  hspi->State = HAL_SPI_STATE_BUSY;
-
-  /* Disable the selected SPI peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
-  /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
-  Communication speed, First bit and CRC calculation state */
-  WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
-                                  (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
-                                  (hspi->Init.DataSize & SPI_CR1_DFF) |
-                                  (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
-                                  (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
-                                  (hspi->Init.NSS & SPI_CR1_SSM) |
-                                  (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
-                                  (hspi->Init.FirstBit  & SPI_CR1_LSBFIRST) |
-                                  (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
-
-  /* Configure : NSS management, TI Mode */
-  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
-
-#if (USE_SPI_CRC != 0U)
-  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
-  /* Configure : CRC Polynomial */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
-  }
-#endif /* USE_SPI_CRC */
-
-#if defined(SPI_I2SCFGR_I2SMOD)
-  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
-  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2SCFGR_I2SMOD */
-
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State     = HAL_SPI_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  De-Initialize the SPI peripheral.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
-{
-  /* Check the SPI handle allocation */
-  if (hspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check SPI Instance parameter */
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-
-  hspi->State = HAL_SPI_STATE_BUSY;
-
-  /* Disable the SPI Peripheral Clock */
-  __HAL_SPI_DISABLE(hspi);
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  if (hspi->MspDeInitCallback == NULL)
-  {
-    hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
-  }
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  hspi->MspDeInitCallback(hspi);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_SPI_MspDeInit(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State = HAL_SPI_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the SPI MSP.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_MspInit should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  De-Initialize the SPI MSP.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_MspDeInit should be implemented in the user file
-   */
-}
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  Register a User SPI Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for the specified SPI.
-  * @param  CallbackID ID of the callback to be registered
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
-                                           pSPI_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  if (HAL_SPI_STATE_READY == hspi->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SPI_TX_COMPLETE_CB_ID :
-        hspi->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_RX_COMPLETE_CB_ID :
-        hspi->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
-        hspi->TxRxCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
-        hspi->TxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
-        hspi->RxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
-        hspi->TxRxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_ERROR_CB_ID :
-        hspi->ErrorCallback = pCallback;
-        break;
-
-      case HAL_SPI_ABORT_CB_ID :
-        hspi->AbortCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_MSPINIT_CB_ID :
-        hspi->MspInitCallback = pCallback;
-        break;
-
-      case HAL_SPI_MSPDEINIT_CB_ID :
-        hspi->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_SPI_STATE_RESET == hspi->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SPI_MSPINIT_CB_ID :
-        hspi->MspInitCallback = pCallback;
-        break;
-
-      case HAL_SPI_MSPDEINIT_CB_ID :
-        hspi->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hspi);
-  return status;
-}
-
-/**
-  * @brief  Unregister an SPI Callback
-  *         SPI callback is redirected to the weak predefined callback
-  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for the specified SPI.
-  * @param  CallbackID ID of the callback to be unregistered
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  if (HAL_SPI_STATE_READY == hspi->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SPI_TX_COMPLETE_CB_ID :
-        hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
-        break;
-
-      case HAL_SPI_RX_COMPLETE_CB_ID :
-        hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
-        break;
-
-      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
-        hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
-        break;
-
-      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
-        hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
-        break;
-
-      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
-        hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
-        break;
-
-      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
-        hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
-        break;
-
-      case HAL_SPI_ERROR_CB_ID :
-        hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
-        break;
-
-      case HAL_SPI_ABORT_CB_ID :
-        hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
-        break;
-
-      case HAL_SPI_MSPINIT_CB_ID :
-        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_SPI_MSPDEINIT_CB_ID :
-        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_SPI_STATE_RESET == hspi->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SPI_MSPINIT_CB_ID :
-        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_SPI_MSPDEINIT_CB_ID :
-        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hspi);
-  return status;
-}
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
-  *  @brief   Data transfers functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
- [..]
-    This subsection provides a set of functions allowing to manage the SPI
-    data transfers.
-
-    [..] The SPI supports master and slave mode :
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode.
-            The HAL status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode: The communication is performed using Interrupts
-            or DMA, These APIs return the HAL status.
-            The end of the data processing will be indicated through the
-            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
-            will be executed respectively at the end of the transmit or Receive process
-            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
-
-    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
-        exist for 1Line (simplex) and 2Lines (full duplex) modes.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmit an amount of data in blocking mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData pointer to data buffer
-  * @param  Size amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  uint16_t initial_TxXferCount;
-
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* in this case, 16-bit access is performed on Data
-       So, check Data is 16-bit aligned address */
-    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
-  }
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-  initial_TxXferCount = Size;
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->RxXferSize  = 0U;
-  hspi->RxXferCount = 0U;
-  hspi->TxISR       = NULL;
-  hspi->RxISR       = NULL;
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
-    __HAL_SPI_DISABLE(hspi);
-    SPI_1LINE_TX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Transmit data in 16 Bit mode */
-  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-  {
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
-    {
-      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-      hspi->pTxBuffPtr += sizeof(uint16_t);
-      hspi->TxXferCount--;
-    }
-    /* Transmit data in 16 Bit mode */
-    while (hspi->TxXferCount > 0U)
-    {
-      /* Wait until TXE flag is set to send data */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
-      {
-        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr += sizeof(uint16_t);
-        hspi->TxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-  /* Transmit data in 8 Bit mode */
-  else
-  {
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
-    {
-      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
-      hspi->pTxBuffPtr += sizeof(uint8_t);
-      hspi->TxXferCount--;
-    }
-    while (hspi->TxXferCount > 0U)
-    {
-      /* Wait until TXE flag is set to send data */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
-      {
-        *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr += sizeof(uint8_t);
-        hspi->TxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-#if (USE_SPI_CRC != 0U)
-  /* Enable CRC Transmission */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    errorcode = HAL_ERROR;
-  }
-
-error:
-  hspi->State = HAL_SPI_STATE_READY;
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in blocking mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData pointer to data buffer
-  * @param  Size amount of data to be received
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-#if (USE_SPI_CRC != 0U)
-  __IO uint32_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-  uint32_t tickstart;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* in this case, 16-bit access is performed on Data
-       So, check Data is 16-bit aligned address */
-    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
-  }
-
-  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_RX;
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxXferSize  = 0U;
-  hspi->TxXferCount = 0U;
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-    /* this is done to handle the CRCNEXT before the latest data */
-    hspi->RxXferCount--;
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Configure communication direction: 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
-    __HAL_SPI_DISABLE(hspi);
-    SPI_1LINE_RX(hspi);
-  }
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Receive data in 8 Bit mode */
-  if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
-  {
-    /* Transfer loop */
-    while (hspi->RxXferCount > 0U)
-    {
-      /* Check the RXNE flag */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
-      {
-        /* read the received data */
-        (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
-        hspi->pRxBuffPtr += sizeof(uint8_t);
-        hspi->RxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-  else
-  {
-    /* Transfer loop */
-    while (hspi->RxXferCount > 0U)
-    {
-      /* Check the RXNE flag */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
-      {
-        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
-        hspi->pRxBuffPtr += sizeof(uint16_t);
-        hspi->RxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Handle the CRC Transmission */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    /* freeze the CRC before the latest data */
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-
-    /* Read the latest data */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* the latest data has not been received */
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-
-    /* Receive last data in 16 Bit mode */
-    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-    {
-      *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
-    }
-    /* Receive last data in 8 Bit mode */
-    else
-    {
-      (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
-    }
-
-    /* Wait the CRC data */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-
-    /* Read CRC to Flush DR and RXNE flag */
-    tmpreg = READ_REG(hspi->Instance->DR);
-    /* To avoid GCC warning */
-    UNUSED(tmpreg);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Check if CRC error occurred */
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    errorcode = HAL_ERROR;
-  }
-
-error :
-  hspi->State = HAL_SPI_STATE_READY;
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in blocking mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData pointer to transmission data buffer
-  * @param  pRxData pointer to reception data buffer
-  * @param  Size amount of data to be sent and received
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
-                                          uint32_t Timeout)
-{
-  uint16_t             initial_TxXferCount;
-  uint32_t             tmp_mode;
-  HAL_SPI_StateTypeDef tmp_state;
-  uint32_t             tickstart;
-#if (USE_SPI_CRC != 0U)
-  __IO uint32_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-
-  /* Variable used to alternate Rx and Tx during transfer */
-  uint32_t             txallowed = 1U;
-  HAL_StatusTypeDef    errorcode = HAL_OK;
-
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* in this case, 16-bit access is performed on Data
-       So, check Data is 16-bit aligned address */
-    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData));
-    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData));
-  }
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* Init temporary variables */
-  tmp_state           = hspi->State;
-  tmp_mode            = hspi->Init.Mode;
-  initial_TxXferCount = Size;
-
-  if (!((tmp_state == HAL_SPI_STATE_READY) || \
-        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  /* Set the transaction information */
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
-  hspi->RxXferCount = Size;
-  hspi->RxXferSize  = Size;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
-  hspi->TxXferCount = Size;
-  hspi->TxXferSize  = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Transmit and Receive data in 16 Bit mode */
-  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-  {
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
-    {
-      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-      hspi->pTxBuffPtr += sizeof(uint16_t);
-      hspi->TxXferCount--;
-    }
-    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
-    {
-      /* Check TXE flag */
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
-      {
-        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr += sizeof(uint16_t);
-        hspi->TxXferCount--;
-        /* Next Data is a reception (Rx). Tx not allowed */
-        txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
-        /* Enable CRC Transmission */
-        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-        {
-          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-        }
-#endif /* USE_SPI_CRC */
-      }
-
-      /* Check RXNE flag */
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
-      {
-        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
-        hspi->pRxBuffPtr += sizeof(uint16_t);
-        hspi->RxXferCount--;
-        /* Next Data is a Transmission (Tx). Tx is allowed */
-        txallowed = 1U;
-      }
-      if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))
-      {
-        errorcode = HAL_TIMEOUT;
-        goto error;
-      }
-    }
-  }
-  /* Transmit and Receive data in 8 Bit mode */
-  else
-  {
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
-    {
-      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
-      hspi->pTxBuffPtr += sizeof(uint8_t);
-      hspi->TxXferCount--;
-    }
-    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
-    {
-      /* Check TXE flag */
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
-      {
-        *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr++;
-        hspi->TxXferCount--;
-        /* Next Data is a reception (Rx). Tx not allowed */
-        txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
-        /* Enable CRC Transmission */
-        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-        {
-          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-        }
-#endif /* USE_SPI_CRC */
-      }
-
-      /* Wait until RXNE flag is reset */
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
-      {
-        (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
-        hspi->pRxBuffPtr++;
-        hspi->RxXferCount--;
-        /* Next Data is a Transmission (Tx). Tx is allowed */
-        txallowed = 1U;
-      }
-      if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
-      {
-        errorcode = HAL_TIMEOUT;
-        goto error;
-      }
-    }
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Read CRC from DR to close CRC calculation process */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    /* Wait until TXE flag */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Error on the CRC reception */
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-    /* Read CRC */
-    tmpreg = READ_REG(hspi->Instance->DR);
-    /* To avoid GCC warning */
-    UNUSED(tmpreg);
-  }
-
-  /* Check if CRC error occurred */
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    /* Clear CRC Flag */
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
-    errorcode = HAL_ERROR;
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
-  {
-    errorcode = HAL_ERROR;
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-    goto error;
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-error :
-  hspi->State = HAL_SPI_STATE_READY;
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData pointer to data buffer
-  * @param  Size amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* in this case, 16-bit access is performed on Data
-       So, check Data is 16-bit aligned address */
-    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
-  }
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->RxXferSize  = 0U;
-  hspi->RxXferCount = 0U;
-  hspi->RxISR       = NULL;
-
-  /* Set the function for IT treatment */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    hspi->TxISR = SPI_TxISR_16BIT;
-  }
-  else
-  {
-    hspi->TxISR = SPI_TxISR_8BIT;
-  }
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
-    __HAL_SPI_DISABLE(hspi);
-    SPI_1LINE_TX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Enable TXE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData pointer to data buffer
-  * @param  Size amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* in this case, 16-bit access is performed on Data
-       So, check Data is 16-bit aligned address */
-    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
-  }
-
-  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_RX;
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxXferSize  = 0U;
-  hspi->TxXferCount = 0U;
-  hspi->TxISR       = NULL;
-
-  /* Set the function for IT treatment */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    hspi->RxISR = SPI_RxISR_16BIT;
-  }
-  else
-  {
-    hspi->RxISR = SPI_RxISR_8BIT;
-  }
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
-    __HAL_SPI_DISABLE(hspi);
-    SPI_1LINE_RX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Enable TXE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Note : The SPI must be enabled after unlocking current process
-            to avoid the risk of SPI interrupt handle execution before current
-            process unlock */
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData pointer to transmission data buffer
-  * @param  pRxData pointer to reception data buffer
-  * @param  Size amount of data to be sent and received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-  uint32_t             tmp_mode;
-  HAL_SPI_StateTypeDef tmp_state;
-  HAL_StatusTypeDef    errorcode = HAL_OK;
-
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* in this case, 16-bit access is performed on Data
-       So, check Data is 16-bit aligned address */
-    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData));
-    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData));
-  }
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  /* Init temporary variables */
-  tmp_state           = hspi->State;
-  tmp_mode            = hspi->Init.Mode;
-
-  if (!((tmp_state == HAL_SPI_STATE_READY) || \
-        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  /* Set the transaction information */
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Set the function for IT treatment */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    hspi->RxISR     = SPI_2linesRxISR_16BIT;
-    hspi->TxISR     = SPI_2linesTxISR_16BIT;
-  }
-  else
-  {
-    hspi->RxISR     = SPI_2linesRxISR_8BIT;
-    hspi->TxISR     = SPI_2linesTxISR_8BIT;
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Enable TXE, RXNE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with DMA.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData pointer to data buffer
-  * @param  Size amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check tx dma handle */
-  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxISR       = NULL;
-  hspi->RxISR       = NULL;
-  hspi->RxXferSize  = 0U;
-  hspi->RxXferCount = 0U;
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
-    __HAL_SPI_DISABLE(hspi);
-    SPI_1LINE_TX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Set the SPI TxDMA Half transfer complete callback */
-  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-
-  /* Set the SPI TxDMA transfer complete callback */
-  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
-  /* Set the DMA error callback */
-  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
-  /* Set the DMA AbortCpltCallback */
-  hspi->hdmatx->XferAbortCallback = NULL;
-
-  /* Enable the Tx DMA Stream/Channel */
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
-                                 hspi->TxXferCount))
-  {
-    /* Update SPI error code */
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-    errorcode = HAL_ERROR;
-
-    hspi->State = HAL_SPI_STATE_READY;
-    goto error;
-  }
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Enable the SPI Error Interrupt Bit */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
-  /* Enable Tx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with DMA.
-  * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData pointer to data buffer
-  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
-  * @param  Size amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check rx dma handle */
-  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
-
-  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_RX;
-
-    /* Check tx dma handle */
-    assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-  hspi->TxXferSize  = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
-    __HAL_SPI_DISABLE(hspi);
-    SPI_1LINE_RX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Set the SPI RxDMA Half transfer complete callback */
-  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
-  /* Set the SPI Rx DMA transfer complete callback */
-  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
-  /* Set the DMA error callback */
-  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
-  /* Set the DMA AbortCpltCallback */
-  hspi->hdmarx->XferAbortCallback = NULL;
-
-  /* Enable the Rx DMA Stream/Channel  */
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
-                                 hspi->RxXferCount))
-  {
-    /* Update SPI error code */
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-    errorcode = HAL_ERROR;
-
-    hspi->State = HAL_SPI_STATE_READY;
-    goto error;
-  }
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Enable the SPI Error Interrupt Bit */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
-  /* Enable Rx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-error:
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData pointer to transmission data buffer
-  * @param  pRxData pointer to reception data buffer
-  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
-  * @param  Size amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-                                              uint16_t Size)
-{
-  uint32_t             tmp_mode;
-  HAL_SPI_StateTypeDef tmp_state;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check rx & tx dma handles */
-  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
-  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  /* Init temporary variables */
-  tmp_state           = hspi->State;
-  tmp_mode            = hspi->Init.Mode;
-
-  if (!((tmp_state == HAL_SPI_STATE_READY) ||
-        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  /* Set the transaction information */
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
-  if (hspi->State == HAL_SPI_STATE_BUSY_RX)
-  {
-    /* Set the SPI Rx DMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
-  }
-  else
-  {
-    /* Set the SPI Tx/Rx DMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
-    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
-  }
-
-  /* Set the DMA error callback */
-  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
-  /* Set the DMA AbortCpltCallback */
-  hspi->hdmarx->XferAbortCallback = NULL;
-
-  /* Enable the Rx DMA Stream/Channel  */
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
-                                 hspi->RxXferCount))
-  {
-    /* Update SPI error code */
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-    errorcode = HAL_ERROR;
-
-    hspi->State = HAL_SPI_STATE_READY;
-    goto error;
-  }
-
-  /* Enable Rx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
-  is performed in DMA reception complete callback  */
-  hspi->hdmatx->XferHalfCpltCallback = NULL;
-  hspi->hdmatx->XferCpltCallback     = NULL;
-  hspi->hdmatx->XferErrorCallback    = NULL;
-  hspi->hdmatx->XferAbortCallback    = NULL;
-
-  /* Enable the Tx DMA Stream/Channel  */
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
-                                 hspi->TxXferCount))
-  {
-    /* Update SPI error code */
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-    errorcode = HAL_ERROR;
-
-    hspi->State = HAL_SPI_STATE_READY;
-    goto error;
-  }
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-  /* Enable the SPI Error Interrupt Bit */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
-  /* Enable Tx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Abort ongoing transfer (blocking mode).
-  * @param  hspi SPI handle.
-  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
-  *         started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SPI Interrupts (depending of transfer direction)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
-{
-  HAL_StatusTypeDef errorcode;
-  __IO uint32_t count;
-  __IO uint32_t resetcount;
-
-  /* Initialized local variable  */
-  errorcode = HAL_OK;
-  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-  count = resetcount;
-
-  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
-  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
-  {
-    hspi->TxISR = SPI_AbortTx_ISR;
-    /* Wait HAL_SPI_STATE_ABORT state */
-    do
-    {
-      if (count == 0U)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-        break;
-      }
-      count--;
-    } while (hspi->State != HAL_SPI_STATE_ABORT);
-    /* Reset Timeout Counter */
-    count = resetcount;
-  }
-
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
-  {
-    hspi->RxISR = SPI_AbortRx_ISR;
-    /* Wait HAL_SPI_STATE_ABORT state */
-    do
-    {
-      if (count == 0U)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-        break;
-      }
-      count--;
-    } while (hspi->State != HAL_SPI_STATE_ABORT);
-    /* Reset Timeout Counter */
-    count = resetcount;
-  }
-
-  /* Disable the SPI DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
-  {
-    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
-    if (hspi->hdmatx != NULL)
-    {
-      /* Set the SPI DMA Abort callback :
-      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
-      hspi->hdmatx->XferAbortCallback = NULL;
-
-      /* Abort DMA Tx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
-      {
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-
-      /* Disable Tx DMA Request */
-      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
-
-      /* Wait until TXE flag is set */
-      do
-      {
-        if (count == 0U)
-        {
-          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-          break;
-        }
-        count--;
-      } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-    }
-  }
-
-  /* Disable the SPI DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
-  {
-    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
-    if (hspi->hdmarx != NULL)
-    {
-      /* Set the SPI DMA Abort callback :
-      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
-      hspi->hdmarx->XferAbortCallback = NULL;
-
-      /* Abort DMA Rx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
-      {
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-
-      /* Disable peripheral */
-      __HAL_SPI_DISABLE(hspi);
-
-      /* Disable Rx DMA Request */
-      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
-    }
-  }
-  /* Reset Tx and Rx transfer counters */
-  hspi->RxXferCount = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Check error during Abort procedure */
-  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
-  {
-    /* return HAL_Error in case of error during Abort procedure */
-    errorcode = HAL_ERROR;
-  }
-  else
-  {
-    /* Reset errorCode */
-    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  }
-
-  /* Clear the Error flags in the SR register */
-  __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  __HAL_SPI_CLEAR_FREFLAG(hspi);
-
-  /* Restore hspi->state to ready */
-  hspi->State = HAL_SPI_STATE_READY;
-
-  return errorcode;
-}
-
-/**
-  * @brief  Abort ongoing transfer (Interrupt mode).
-  * @param  hspi SPI handle.
-  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
-  *         started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SPI Interrupts (depending of transfer direction)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
-{
-  HAL_StatusTypeDef errorcode;
-  uint32_t abortcplt ;
-  __IO uint32_t count;
-  __IO uint32_t resetcount;
-
-  /* Initialized local variable  */
-  errorcode = HAL_OK;
-  abortcplt = 1U;
-  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-  count = resetcount;
-
-  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
-  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
-  {
-    hspi->TxISR = SPI_AbortTx_ISR;
-    /* Wait HAL_SPI_STATE_ABORT state */
-    do
-    {
-      if (count == 0U)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-        break;
-      }
-      count--;
-    } while (hspi->State != HAL_SPI_STATE_ABORT);
-    /* Reset Timeout Counter */
-    count = resetcount;
-  }
-
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
-  {
-    hspi->RxISR = SPI_AbortRx_ISR;
-    /* Wait HAL_SPI_STATE_ABORT state */
-    do
-    {
-      if (count == 0U)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-        break;
-      }
-      count--;
-    } while (hspi->State != HAL_SPI_STATE_ABORT);
-    /* Reset Timeout Counter */
-    count = resetcount;
-  }
-
-  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
-     before any call to DMA Abort functions */
-  /* DMA Tx Handle is valid */
-  if (hspi->hdmatx != NULL)
-  {
-    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
-    {
-      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
-    }
-    else
-    {
-      hspi->hdmatx->XferAbortCallback = NULL;
-    }
-  }
-  /* DMA Rx Handle is valid */
-  if (hspi->hdmarx != NULL)
-  {
-    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
-    {
-      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
-    }
-    else
-    {
-      hspi->hdmarx->XferAbortCallback = NULL;
-    }
-  }
-
-  /* Disable the SPI DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
-  {
-    /* Abort the SPI DMA Tx Stream/Channel */
-    if (hspi->hdmatx != NULL)
-    {
-      /* Abort DMA Tx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
-      {
-        hspi->hdmatx->XferAbortCallback = NULL;
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-  /* Disable the SPI DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
-  {
-    /* Abort the SPI DMA Rx Stream/Channel */
-    if (hspi->hdmarx != NULL)
-    {
-      /* Abort DMA Rx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
-      {
-        hspi->hdmarx->XferAbortCallback = NULL;
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-
-  if (abortcplt == 1U)
-  {
-    /* Reset Tx and Rx transfer counters */
-    hspi->RxXferCount = 0U;
-    hspi->TxXferCount = 0U;
-
-    /* Check error during Abort procedure */
-    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
-    {
-      /* return HAL_Error in case of error during Abort procedure */
-      errorcode = HAL_ERROR;
-    }
-    else
-    {
-      /* Reset errorCode */
-      hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-    }
-
-    /* Clear the Error flags in the SR register */
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-    __HAL_SPI_CLEAR_FREFLAG(hspi);
-
-    /* Restore hspi->State to Ready */
-    hspi->State = HAL_SPI_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-    hspi->AbortCpltCallback(hspi);
-#else
-    HAL_SPI_AbortCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-  }
-
-  return errorcode;
-}
-
-/**
-  * @brief  Pause the DMA Transfer.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Resume the DMA Transfer.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Enable the SPI DMA Tx & Rx requests */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the DMA Transfer.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
-     */
-
-  /* Abort the SPI DMA tx Stream/Channel  */
-  if (hspi->hdmatx != NULL)
-  {
-    if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-      errorcode = HAL_ERROR;
-    }
-  }
-  /* Abort the SPI DMA rx Stream/Channel  */
-  if (hspi->hdmarx != NULL)
-  {
-    if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-      errorcode = HAL_ERROR;
-    }
-  }
-
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-  hspi->State = HAL_SPI_STATE_READY;
-  return errorcode;
-}
-
-/**
-  * @brief  Handle SPI interrupt request.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval None
-  */
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
-{
-  uint32_t itsource = hspi->Instance->CR2;
-  uint32_t itflag   = hspi->Instance->SR;
-
-  /* SPI in mode Receiver ----------------------------------------------------*/
-  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
-      (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
-  {
-    hspi->RxISR(hspi);
-    return;
-  }
-
-  /* SPI in mode Transmitter -------------------------------------------------*/
-  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
-  {
-    hspi->TxISR(hspi);
-    return;
-  }
-
-  /* SPI in Error Treatment --------------------------------------------------*/
-  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
-       || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
-  {
-    /* SPI Overrun error interrupt occurred ----------------------------------*/
-    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
-    {
-      if (hspi->State != HAL_SPI_STATE_BUSY_TX)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);
-      }
-      else
-      {
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);
-        return;
-      }
-    }
-
-    /* SPI Mode Fault error interrupt occurred -------------------------------*/
-    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
-      __HAL_SPI_CLEAR_MODFFLAG(hspi);
-    }
-
-    /* SPI Frame error interrupt occurred ------------------------------------*/
-    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
-      __HAL_SPI_CLEAR_FREFLAG(hspi);
-    }
-
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      /* Disable all interrupts */
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
-
-      hspi->State = HAL_SPI_STATE_READY;
-      /* Disable the SPI DMA requests if enabled */
-      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
-      {
-        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
-
-        /* Abort the SPI DMA Rx channel */
-        if (hspi->hdmarx != NULL)
-        {
-          /* Set the SPI DMA Abort callback :
-          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
-          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
-          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
-          {
-            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-          }
-        }
-        /* Abort the SPI DMA Tx channel */
-        if (hspi->hdmatx != NULL)
-        {
-          /* Set the SPI DMA Abort callback :
-          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
-          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
-          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
-          {
-            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-          }
-        }
-      }
-      else
-      {
-        /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-        hspi->ErrorCallback(hspi);
-#else
-        HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-      }
-    }
-    return;
-  }
-}
-
-/**
-  * @brief  Tx Transfer completed callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_RxCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx and Rx Transfer completed callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer completed callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx and Rx Half Transfer callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  SPI error callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_ErrorCallback should be implemented in the user file
-   */
-  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
-            and user can use HAL_SPI_GetError() API to check the latest error occurred
-   */
-}
-
-/**
-  * @brief  SPI Abort Complete callback.
-  * @param  hspi SPI handle.
-  * @retval None
-  */
-__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_AbortCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
-  * @brief   SPI control functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the SPI.
-     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
-     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the SPI handle state.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval SPI state
-  */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
-{
-  /* Return SPI handle state */
-  return hspi->State;
-}
-
-/**
-  * @brief  Return the SPI error code.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval SPI error code in bitmap format
-  */
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
-{
-  /* Return SPI ErrorCode */
-  return hspi->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Private_Functions
-  * @brief   Private functions
-  * @{
-  */
-
-/**
-  * @brief  DMA SPI transmit process complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-  uint32_t tickstart;
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* DMA Normal Mode */
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
-  {
-    /* Disable ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-    /* Disable Tx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    /* Check the end of the transaction */
-    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Clear overrun flag in 2 Lines communication mode because received data is not read */
-    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-    {
-      __HAL_SPI_CLEAR_OVRFLAG(hspi);
-    }
-
-    hspi->TxXferCount = 0U;
-    hspi->State = HAL_SPI_STATE_READY;
-
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-      hspi->ErrorCallback(hspi);
-#else
-      HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-      return;
-    }
-  }
-  /* Call user Tx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->TxCpltCallback(hspi);
-#else
-  HAL_SPI_TxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI receive process complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-  uint32_t tickstart;
-#if (USE_SPI_CRC != 0U)
-  __IO uint32_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* DMA Normal Mode */
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
-  {
-    /* Disable ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-#if (USE_SPI_CRC != 0U)
-    /* CRC handling */
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Wait until RXNE flag */
-      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-      {
-        /* Error on the CRC reception */
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      }
-      /* Read CRC */
-      tmpreg = READ_REG(hspi->Instance->DR);
-      /* To avoid GCC warning */
-      UNUSED(tmpreg);
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Check if we are in Master RX 2 line mode */
-    if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-    {
-      /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
-      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-    }
-    else
-    {
-      /* Normal case */
-      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-    }
-
-    /* Check the end of the transaction */
-    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-    {
-      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-    }
-
-    hspi->RxXferCount = 0U;
-    hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
-    /* Check if CRC error occurred */
-    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    }
-#endif /* USE_SPI_CRC */
-
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-      hspi->ErrorCallback(hspi);
-#else
-      HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-      return;
-    }
-  }
-  /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->RxCpltCallback(hspi);
-#else
-  HAL_SPI_RxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI transmit receive process complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-  uint32_t tickstart;
-#if (USE_SPI_CRC != 0U)
-  __IO uint32_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* DMA Normal Mode */
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
-  {
-    /* Disable ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-#if (USE_SPI_CRC != 0U)
-    /* CRC handling */
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Wait the CRC data */
-      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      }
-      /* Read CRC to Flush DR and RXNE flag */
-      tmpreg = READ_REG(hspi->Instance->DR);
-      /* To avoid GCC warning */
-      UNUSED(tmpreg);
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Check the end of the transaction */
-    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Disable Rx/Tx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-    hspi->TxXferCount = 0U;
-    hspi->RxXferCount = 0U;
-    hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
-    /* Check if CRC error occurred */
-    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    }
-#endif /* USE_SPI_CRC */
-
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-      hspi->ErrorCallback(hspi);
-#else
-      HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-      return;
-    }
-  }
-  /* Call user TxRx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->TxRxCpltCallback(hspi);
-#else
-  HAL_SPI_TxRxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI half transmit process complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Call user Tx half complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->TxHalfCpltCallback(hspi);
-#else
-  HAL_SPI_TxHalfCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI half receive process complete callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Call user Rx half complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->RxHalfCpltCallback(hspi);
-#else
-  HAL_SPI_RxHalfCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI half transmit receive process complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Call user TxRx half complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->TxRxHalfCpltCallback(hspi);
-#else
-  HAL_SPI_TxRxHalfCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI communication error callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Stop the disable DMA transfer on SPI side */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-  hspi->State = HAL_SPI_STATE_READY;
-  /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->ErrorCallback(hspi);
-#else
-  HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-  hspi->RxXferCount = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->ErrorCallback(hspi);
-#else
-  HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI Tx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Rx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-  __IO uint32_t count;
-
-  hspi->hdmatx->XferAbortCallback = NULL;
-  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
-  /* Disable Tx DMA Request */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-  /* Wait until TXE flag is set */
-  do
-  {
-    if (count == 0U)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-      break;
-    }
-    count--;
-  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
-  /* Check if an Abort process is still ongoing */
-  if (hspi->hdmarx != NULL)
-  {
-    if (hspi->hdmarx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
-  hspi->RxXferCount = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Check no error during Abort procedure */
-  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
-  {
-    /* Reset errorCode */
-    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  }
-
-  /* Clear the Error flags in the SR register */
-  __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  __HAL_SPI_CLEAR_FREFLAG(hspi);
-
-  /* Restore hspi->State to Ready */
-  hspi->State  = HAL_SPI_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->AbortCpltCallback(hspi);
-#else
-  HAL_SPI_AbortCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI Rx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Tx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Disable SPI Peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  hspi->hdmarx->XferAbortCallback = NULL;
-
-  /* Disable Rx DMA Request */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-  /* Check Busy flag */
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-  }
-
-  /* Check if an Abort process is still ongoing */
-  if (hspi->hdmatx != NULL)
-  {
-    if (hspi->hdmatx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
-  hspi->RxXferCount = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Check no error during Abort procedure */
-  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
-  {
-    /* Reset errorCode */
-    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  }
-
-  /* Clear the Error flags in the SR register */
-  __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  __HAL_SPI_CLEAR_FREFLAG(hspi);
-
-  /* Restore hspi->State to Ready */
-  hspi->State  = HAL_SPI_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->AbortCpltCallback(hspi);
-#else
-  HAL_SPI_AbortCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 8bit mode */
-  *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
-  hspi->pRxBuffPtr++;
-  hspi->RxXferCount--;
-
-  /* Check end of the reception */
-  if (hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable RXNE  and ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-    if (hspi->TxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint8_t  * ptmpreg8;
-  __IO uint8_t  tmpreg8 = 0;
-
-  /* Initialize the 8bit temporary pointer */
-  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
-  /* Read 8bit CRC to flush Data Register */
-  tmpreg8 = *ptmpreg8;
-  /* To avoid GCC warning */
-  UNUSED(tmpreg8);
-
-  /* Disable RXNE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  if (hspi->TxXferCount == 0U)
-  {
-    SPI_CloseRxTx_ISR(hspi);
-  }
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr++;
-  hspi->TxXferCount--;
-
-  /* Check the end of the transmission */
-  if (hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Set CRC Next Bit to send CRC */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-      /* Disable TXE interrupt */
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable TXE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
-    if (hspi->RxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-/**
-  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 16 Bit mode */
-  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
-  hspi->pRxBuffPtr += sizeof(uint16_t);
-  hspi->RxXferCount--;
-
-  if (hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable RXNE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
-    if (hspi->TxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint32_t tmpreg = 0U;
-
-  /* Read 16bit CRC to flush Data Register */
-  tmpreg = READ_REG(hspi->Instance->DR);
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);  
-
-  /* Disable RXNE interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
-  SPI_CloseRxTx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in 16 Bit mode */
-  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr += sizeof(uint16_t);
-  hspi->TxXferCount--;
-
-  /* Enable CRC Transmission */
-  if (hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Set CRC Next Bit to send CRC */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-      /* Disable TXE interrupt */
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable TXE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
-    if (hspi->RxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Manage the CRC 8-bit receive in Interrupt context.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint8_t  * ptmpreg8;
-  __IO uint8_t  tmpreg8 = 0;
-
-  /* Initialize the 8bit temporary pointer */
-  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
-  /* Read 8bit CRC to flush Data Register */
-  tmpreg8 = *ptmpreg8;
-  /* To avoid GCC warning */
-  UNUSED(tmpreg8);
-
-  SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Manage the receive 8-bit in Interrupt context.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
-  hspi->pRxBuffPtr++;
-  hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
-  /* Enable CRC Transmission */
-  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-  {
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-#endif /* USE_SPI_CRC */
-
-  if (hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_RxISR_8BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseRx_ISR(hspi);
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Manage the CRC 16-bit receive in Interrupt context.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint32_t tmpreg = 0U;
-
-  /* Read 16bit CRC to flush Data Register */
-  tmpreg = READ_REG(hspi->Instance->DR);
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);
-
-  /* Disable RXNE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Manage the 16-bit receive in Interrupt context.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
-  hspi->pRxBuffPtr += sizeof(uint16_t);
-  hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
-  /* Enable CRC Transmission */
-  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-  {
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-#endif /* USE_SPI_CRC */
-
-  if (hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR = SPI_RxISR_16BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseRx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Handle the data 8-bit transmit in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr++;
-  hspi->TxXferCount--;
-
-  if (hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Enable CRC Transmission */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseTx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Handle the data 16-bit transmit in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in 16 Bit mode */
-  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr += sizeof(uint16_t);
-  hspi->TxXferCount--;
-
-  if (hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Enable CRC Transmission */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseTx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Handle SPI Communication Timeout.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *              the configuration information for SPI module.
-  * @param  Flag SPI flag to check
-  * @param  State flag state to check
-  * @param  Timeout Timeout duration
-  * @param  Tickstart tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
-                                                       uint32_t Timeout, uint32_t Tickstart)
-{
-  __IO uint32_t count;
-  uint32_t tmp_timeout;
-  uint32_t tmp_tickstart;
-
-  /* Adjust Timeout value  in case of end of transfer */
-  tmp_timeout   = Timeout - (HAL_GetTick() - Tickstart);
-  tmp_tickstart = HAL_GetTick();
-
-  /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
-  count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
-
-  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
-      {
-        /* Disable the SPI and reset the CRC: the CRC value should be cleared
-           on both master and slave sides in order to resynchronize the master
-           and slave for their respective CRC calculation */
-
-        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
-        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
-                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-        {
-          /* Disable SPI peripheral */
-          __HAL_SPI_DISABLE(hspi);
-        }
-
-        /* Reset CRC Calculation */
-        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-        {
-          SPI_RESET_CRC(hspi);
-        }
-
-        hspi->State = HAL_SPI_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hspi);
-
-        return HAL_TIMEOUT;
-      }
-      /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
-      if(count == 0U)
-      {
-        tmp_timeout = 0U;
-      }
-      count--;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle the check of the RX transaction complete.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
-{
-  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
-                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-  {
-    /* Disable SPI peripheral */
-    __HAL_SPI_DISABLE(hspi);
-  }
-
-  /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
-  if (hspi->Init.Mode == SPI_MODE_MASTER)
-  {
-    if (hspi->Init.Direction != SPI_DIRECTION_2LINES_RXONLY)
-    {
-      /* Control the BSY flag */
-      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-        return HAL_TIMEOUT;
-      }
-    }
-    else
-    {
-      /* Wait the RXNE reset */
-      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  else
-  {
-    /* Wait the RXNE reset */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle the check of the RXTX or TX transaction complete.
-  * @param  hspi SPI handle
-  * @param  Timeout Timeout duration
-  * @param  Tickstart tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Timeout in µs */
-  __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
-  /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
-  if (hspi->Init.Mode == SPI_MODE_MASTER)
-  {
-    /* Control the BSY flag */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      return HAL_TIMEOUT;
-    }
-  }
-  else
-  {
-    /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer
-    * If Timeout is reached, the transfer is considered as finish.
-    * User have to calculate the timeout value to fit with the time of 1 byte transfer.
-    * This time is directly link with the SPI clock from Master device.
-    */
-    do
-    {
-      if (count == 0U)
-      {
-        break;
-      }
-      count--;
-    } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle the end of the RXTX transaction.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  uint32_t tickstart;
-  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
-  /* Init tickstart for timeout management */
-  tickstart = HAL_GetTick();
-
-  /* Disable ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-  /* Wait until TXE flag is set */
-  do
-  {
-    if (count == 0U)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      break;
-    }
-    count--;
-  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Check if CRC error occurred */
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-  {
-    hspi->State = HAL_SPI_STATE_READY;
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-    hspi->ErrorCallback(hspi);
-#else
-    HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-  }
-  else
-  {
-#endif /* USE_SPI_CRC */
-    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
-    {
-      if (hspi->State == HAL_SPI_STATE_BUSY_RX)
-      {
-        hspi->State = HAL_SPI_STATE_READY;
-        /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-        hspi->RxCpltCallback(hspi);
-#else
-        HAL_SPI_RxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-      }
-      else
-      {
-        hspi->State = HAL_SPI_STATE_READY;
-        /* Call user TxRx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-        hspi->TxRxCpltCallback(hspi);
-#else
-        HAL_SPI_TxRxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-      }
-    }
-    else
-    {
-      hspi->State = HAL_SPI_STATE_READY;
-      /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-      hspi->ErrorCallback(hspi);
-#else
-      HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-    }
-#if (USE_SPI_CRC != 0U)
-  }
-#endif /* USE_SPI_CRC */
-}
-
-/**
-  * @brief  Handle the end of the RX transaction.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
-{
-  /* Disable RXNE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-  hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
-  /* Check if CRC error occurred */
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-    hspi->ErrorCallback(hspi);
-#else
-    HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-  }
-  else
-  {
-#endif /* USE_SPI_CRC */
-    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
-    {
-      /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-      hspi->RxCpltCallback(hspi);
-#else
-      HAL_SPI_RxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-    }
-    else
-    {
-      /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-      hspi->ErrorCallback(hspi);
-#else
-      HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-    }
-#if (USE_SPI_CRC != 0U)
-  }
-#endif /* USE_SPI_CRC */
-}
-
-/**
-  * @brief  Handle the end of the TX transaction.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  uint32_t tickstart;
-  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* Wait until TXE flag is set */
-  do
-  {
-    if (count == 0U)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      break;
-    }
-    count--;
-  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
-  /* Disable TXE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-  hspi->State = HAL_SPI_STATE_READY;
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-    hspi->ErrorCallback(hspi);
-#else
-    HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-    hspi->TxCpltCallback(hspi);
-#else
-    HAL_SPI_TxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  Handle abort a Rx transaction.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
-{
-  __IO uint32_t tmpreg = 0U;
-  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
-  /* Wait until TXE flag is set */
-  do
-  {
-    if (count == 0U)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-      break;
-    }
-    count--;
-  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
-  /* Disable SPI Peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
-  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
-
-  /* Flush Data Register by a blank read */
-  tmpreg = READ_REG(hspi->Instance->DR);
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);
-
-  hspi->State = HAL_SPI_STATE_ABORT;
-}
-
-/**
-  * @brief  Handle abort a Tx or Rx/Tx transaction.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  /* Disable TXEIE interrupt */
-  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
-
-  /* Disable SPI Peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  hspi->State = HAL_SPI_STATE_ABORT;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c
deleted file mode 100644
index 16e99ba153..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c
+++ /dev/null
@@ -1,7187 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_tim.c
-  * @author  MCD Application Team
-  * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Timer (TIM) peripheral:
-  *           + TIM Time Base Initialization
-  *           + TIM Time Base Start
-  *           + TIM Time Base Start Interruption
-  *           + TIM Time Base Start DMA
-  *           + TIM Output Compare/PWM Initialization
-  *           + TIM Output Compare/PWM Channel Configuration
-  *           + TIM Output Compare/PWM  Start
-  *           + TIM Output Compare/PWM  Start Interruption
-  *           + TIM Output Compare/PWM Start DMA
-  *           + TIM Input Capture Initialization
-  *           + TIM Input Capture Channel Configuration
-  *           + TIM Input Capture Start
-  *           + TIM Input Capture Start Interruption
-  *           + TIM Input Capture Start DMA
-  *           + TIM One Pulse Initialization
-  *           + TIM One Pulse Channel Configuration
-  *           + TIM One Pulse Start
-  *           + TIM Encoder Interface Initialization
-  *           + TIM Encoder Interface Start
-  *           + TIM Encoder Interface Start Interruption
-  *           + TIM Encoder Interface Start DMA
-  *           + Commutation Event configuration with Interruption and DMA
-  *           + TIM OCRef clear configuration
-  *           + TIM External Clock configuration
-  @verbatim
-  ==============================================================================
-                      ##### TIMER Generic features #####
-  ==============================================================================
-  [..] The Timer features include:
-       (#) 16-bit up, down, up/down auto-reload counter.
-       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
-           counter clock frequency either by any factor between 1 and 65536.
-       (#) Up to 4 independent channels for:
-           (++) Input Capture
-           (++) Output Compare
-           (++) PWM generation (Edge and Center-aligned Mode)
-           (++) One-pulse mode output
-       (#) Synchronization circuit to control the timer with external signals and to interconnect
-            several timers together.
-       (#) Supports incremental encoder for positioning purposes
-
-            ##### How to use this driver #####
-  ==============================================================================
-    [..]
-     (#) Initialize the TIM low level resources by implementing the following functions
-         depending on the selected feature:
-           (++) Time Base : HAL_TIM_Base_MspInit()
-           (++) Input Capture : HAL_TIM_IC_MspInit()
-           (++) Output Compare : HAL_TIM_OC_MspInit()
-           (++) PWM generation : HAL_TIM_PWM_MspInit()
-           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
-           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
-     (#) Initialize the TIM low level resources :
-        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
-        (##) TIM pins configuration
-            (+++) Enable the clock for the TIM GPIOs using the following function:
-             __HAL_RCC_GPIOx_CLK_ENABLE();
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
-     (#) The external Clock can be configured, if needed (the default clock is the
-         internal clock from the APBx), using the following function:
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before
-         any start function.
-
-     (#) Configure the TIM in the desired functioning mode using one of the
-       Initialization function of this driver:
-       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
-       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
-            Output Compare signal.
-       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
-            PWM signal.
-       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
-            external signal.
-       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
-            in One Pulse Mode.
-       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
-
-     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
-           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
-           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
-           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
-           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
-           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
-           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
-
-     (#) The DMA Burst is managed with the two following functions:
-         HAL_TIM_DMABurst_WriteStart()
-         HAL_TIM_DMABurst_ReadStart()
-
-    *** Callback registration ***
-  =============================================
-
-  [..]
-  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
-  allows the user to configure dynamically the driver callbacks.
-
-  [..]
-  Use Function HAL_TIM_RegisterCallback() to register a callback.
-  HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
-  the Callback ID and a pointer to the user callback function.
-
-  [..]
-  Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
-  weak function.
-  HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
-  and the Callback ID.
-
-  [..]
-  These functions allow to register/unregister following callbacks:
-    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
-    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
-    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
-    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
-    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
-    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
-    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
-    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
-    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
-    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
-    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
-    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
-    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
-    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
-    (+) TriggerCallback                   : TIM Trigger Callback.
-    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
-    (+) IC_CaptureCallback                : TIM Input Capture Callback.
-    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
-    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
-    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
-    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
-    (+) ErrorCallback                     : TIM Error Callback.
-
-  [..]
-By default, after the Init and when the state is HAL_TIM_STATE_RESET
-all interrupt callbacks are set to the corresponding weak functions:
-  examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
-
-  [..]
-  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
-  functionalities in the Init / DeInit only when these callbacks are null
-  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
-    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
-
-  [..]
-    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
-    Exception done MspInit / MspDeInit that can be registered / unregistered
-    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
-    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
-  In that case first register the MspInit/MspDeInit user callbacks
-      using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
-
-  [..]
-      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
-      not defined, the callback registration feature is not available and all callbacks
-      are set to the corresponding weak functions.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TIM TIM
-  * @brief TIM HAL module driver
-  * @{
-  */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
-  * @{
-  */
-static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter);
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter);
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter);
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter);
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
-static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
-                              uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);
-/**
-  * @}
-  */
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
-  *  @brief    Time Base functions
-  *
-@verbatim
-  ==============================================================================
-              ##### Time Base functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM base.
-    (+) De-initialize the TIM base.
-    (+) Start the Time Base.
-    (+) Stop the Time Base.
-    (+) Start the Time Base and enable interrupt.
-    (+) Stop the Time Base and disable interrupt.
-    (+) Start the Time Base and enable DMA transfer.
-    (+) Stop the Time Base and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Time base Unit according to the specified
-  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *         requires a timer reset to avoid unexpected direction
-  *         due to DIR bit readonly in center aligned mode.
-  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_PERIOD(htim->Init.Period));
-  assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    TIM_ResetCallback(htim);
-
-    if (htim->Base_MspInitCallback == NULL)
-    {
-      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->Base_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    HAL_TIM_Base_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Set the Time Base configuration */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Initialize the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM Base peripheral
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  if (htim->Base_MspDeInitCallback == NULL)
-  {
-    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  htim->Base_MspDeInitCallback(htim);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_Base_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
-  /* Change the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Base MSP.
-  * @param  htim TIM Base handle
-  * @retval None
-  */
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_Base_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Base MSP.
-  * @param  htim TIM Base handle
-  * @retval None
-  */
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_Base_MspDeInit could be implemented in the user file
-   */
-}
-
-
-/**
-  * @brief  Starts the TIM Base generation.
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Check the TIM state */
-  if (htim->State != HAL_TIM_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation.
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Base generation in interrupt mode.
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Check the TIM state */
-  if (htim->State != HAL_TIM_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Enable the TIM Update interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation in interrupt mode.
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Disable the TIM Update interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Base generation in DMA mode.
-  * @param  htim TIM Base handle
-  * @param  pData The source Buffer address.
-  * @param  Length The length of data to be transferred from memory to peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
-  /* Set the TIM state */
-  if (htim->State == HAL_TIM_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (htim->State == HAL_TIM_STATE_READY)
-  {
-    if ((pData == NULL) && (Length > 0U))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the DMA Period elapsed callbacks */
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
-
-  /* Set the DMA error callback */
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
-  /* Enable the DMA channel */
-  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
-                       Length) != HAL_OK)
-  {
-    /* Return error status */
-    return HAL_ERROR;
-  }
-
-  /* Enable the TIM Update DMA request */
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation in DMA mode.
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
-  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
-  *  @brief    TIM Output Compare functions
-  *
-@verbatim
-  ==============================================================================
-                  ##### TIM Output Compare functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM Output Compare.
-    (+) De-initialize the TIM Output Compare.
-    (+) Start the TIM Output Compare.
-    (+) Stop the TIM Output Compare.
-    (+) Start the TIM Output Compare and enable interrupt.
-    (+) Stop the TIM Output Compare and disable interrupt.
-    (+) Start the TIM Output Compare and enable DMA transfer.
-    (+) Stop the TIM Output Compare and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Output Compare according to the specified
-  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *         requires a timer reset to avoid unexpected direction
-  *         due to DIR bit readonly in center aligned mode.
-  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
-  * @param  htim TIM Output Compare handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_PERIOD(htim->Init.Period));
-  assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    TIM_ResetCallback(htim);
-
-    if (htim->OC_MspInitCallback == NULL)
-    {
-      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->OC_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_OC_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the Output Compare */
-  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Initialize the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral
-  * @param  htim TIM Output Compare handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  if (htim->OC_MspDeInitCallback == NULL)
-  {
-    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  htim->OC_MspDeInitCallback(htim);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_OC_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
-  /* Change the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Output Compare MSP.
-  * @param  htim TIM Output Compare handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Output Compare MSP.
-  * @param  htim TIM Output Compare handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation.
-  * @param  htim TIM Output Compare handle
-  * @param  Channel TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation.
-  * @param  htim TIM Output Compare handle
-  * @param  Channel TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim TIM Output Compare handle
-  * @param  Channel TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Enable the Output compare channel */
-    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-    {
-      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-      {
-        __HAL_TIM_ENABLE(htim);
-      }
-    }
-    else
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim TIM Output Compare handle
-  * @param  Channel TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Disable the Output compare channel */
-    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-    /* Disable the Peripheral */
-    __HAL_TIM_DISABLE(htim);
-
-    /* Set the TIM channel state */
-    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
-  * @param  htim TIM Output Compare handle
-  * @param  Channel TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData The source Buffer address.
-  * @param  Length The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Set the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
-  {
-    if ((pData == NULL) && (Length > 0U))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Enable the Output compare channel */
-    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-    {
-      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-      {
-        __HAL_TIM_ENABLE(htim);
-      }
-    }
-    else
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
-  * @param  htim TIM Output Compare handle
-  * @param  Channel TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Disable the Output compare channel */
-    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-    /* Disable the Peripheral */
-    __HAL_TIM_DISABLE(htim);
-
-    /* Set the TIM channel state */
-    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
-  *  @brief    TIM PWM functions
-  *
-@verbatim
-  ==============================================================================
-                          ##### TIM PWM functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM PWM.
-    (+) De-initialize the TIM PWM.
-    (+) Start the TIM PWM.
-    (+) Stop the TIM PWM.
-    (+) Start the TIM PWM and enable interrupt.
-    (+) Stop the TIM PWM and disable interrupt.
-    (+) Start the TIM PWM and enable DMA transfer.
-    (+) Stop the TIM PWM and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM PWM Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *         requires a timer reset to avoid unexpected direction
-  *         due to DIR bit readonly in center aligned mode.
-  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
-  * @param  htim TIM PWM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_PERIOD(htim->Init.Period));
-  assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    TIM_ResetCallback(htim);
-
-    if (htim->PWM_MspInitCallback == NULL)
-    {
-      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->PWM_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_PWM_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the PWM */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Initialize the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral
-  * @param  htim TIM PWM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  if (htim->PWM_MspDeInitCallback == NULL)
-  {
-    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  htim->PWM_MspDeInitCallback(htim);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_PWM_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
-  /* Change the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM PWM MSP.
-  * @param  htim TIM PWM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM PWM MSP.
-  * @param  htim TIM PWM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the PWM signal generation.
-  * @param  htim TIM handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation.
-  * @param  htim TIM PWM handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the PWM signal generation in interrupt mode.
-  * @param  htim TIM PWM handle
-  * @param  Channel TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Enable the Capture compare channel */
-    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-    {
-      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-      {
-        __HAL_TIM_ENABLE(htim);
-      }
-    }
-    else
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Stops the PWM signal generation in interrupt mode.
-  * @param  htim TIM PWM handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Disable the Capture compare channel */
-    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-    /* Disable the Peripheral */
-    __HAL_TIM_DISABLE(htim);
-
-    /* Set the TIM channel state */
-    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Starts the TIM PWM signal generation in DMA mode.
-  * @param  htim TIM PWM handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData The source Buffer address.
-  * @param  Length The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Set the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
-  {
-    if ((pData == NULL) && (Length > 0U))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Output Capture/Compare 3 request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Enable the Capture compare channel */
-    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-    {
-      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-      {
-        __HAL_TIM_ENABLE(htim);
-      }
-    }
-    else
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Stops the TIM PWM signal generation in DMA mode.
-  * @param  htim TIM PWM handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Disable the Capture compare channel */
-    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-    /* Disable the Peripheral */
-    __HAL_TIM_DISABLE(htim);
-
-    /* Set the TIM channel state */
-    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
-  *  @brief    TIM Input Capture functions
-  *
-@verbatim
-  ==============================================================================
-              ##### TIM Input Capture functions #####
-  ==============================================================================
- [..]
-   This section provides functions allowing to:
-   (+) Initialize and configure the TIM Input Capture.
-   (+) De-initialize the TIM Input Capture.
-   (+) Start the TIM Input Capture.
-   (+) Stop the TIM Input Capture.
-   (+) Start the TIM Input Capture and enable interrupt.
-   (+) Stop the TIM Input Capture and disable interrupt.
-   (+) Start the TIM Input Capture and enable DMA transfer.
-   (+) Stop the TIM Input Capture and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Input Capture Time base according to the specified
-  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *         requires a timer reset to avoid unexpected direction
-  *         due to DIR bit readonly in center aligned mode.
-  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
-  * @param  htim TIM Input Capture handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_PERIOD(htim->Init.Period));
-  assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    TIM_ResetCallback(htim);
-
-    if (htim->IC_MspInitCallback == NULL)
-    {
-      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->IC_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_IC_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the input capture */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Initialize the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral
-  * @param  htim TIM Input Capture handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  if (htim->IC_MspDeInitCallback == NULL)
-  {
-    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  htim->IC_MspDeInitCallback(htim);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_IC_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
-  /* Change the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Input Capture MSP.
-  * @param  htim TIM Input Capture handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_IC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Input Capture MSP.
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_IC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement.
-  * @param  htim TIM Input Capture handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpsmcr;
-  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement.
-  * @param  htim TIM Input Capture handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
-  * @param  htim TIM Input Capture handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmpsmcr;
-
-  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Enable the Input Capture channel */
-    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-    {
-      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-      {
-        __HAL_TIM_ENABLE(htim);
-      }
-    }
-    else
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
-  * @param  htim TIM Input Capture handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Disable the Input Capture channel */
-    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-    /* Disable the Peripheral */
-    __HAL_TIM_DISABLE(htim);
-
-    /* Set the TIM channel state */
-    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement in DMA mode.
-  * @param  htim TIM Input Capture handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData The destination Buffer address.
-  * @param  Length The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmpsmcr;
-
-  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  /* Set the TIM channel state */
-  if (channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  if (channel_state == HAL_TIM_CHANNEL_STATE_READY)
-  {
-    if ((pData == NULL) && (Length > 0U))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 2  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 3  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 4  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement in DMA mode.
-  * @param  htim TIM Input Capture handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3  DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4  DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Disable the Peripheral */
-    __HAL_TIM_DISABLE(htim);
-
-    /* Set the TIM channel state */
-    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  }
-
-  /* Return function status */
-  return status;
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
-  *  @brief    TIM One Pulse functions
-  *
-@verbatim
-  ==============================================================================
-                        ##### TIM One Pulse functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM One Pulse.
-    (+) De-initialize the TIM One Pulse.
-    (+) Start the TIM One Pulse.
-    (+) Stop the TIM One Pulse.
-    (+) Start the TIM One Pulse and enable interrupt.
-    (+) Stop the TIM One Pulse and disable interrupt.
-    (+) Start the TIM One Pulse and enable DMA transfer.
-    (+) Stop the TIM One Pulse and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM One Pulse Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *         requires a timer reset to avoid unexpected direction
-  *         due to DIR bit readonly in center aligned mode.
-  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
-  * @note   When the timer instance is initialized in One Pulse mode, timer
-  *         channels 1 and channel 2 are reserved and cannot be used for other
-  *         purpose.
-  * @param  htim TIM One Pulse handle
-  * @param  OnePulseMode Select the One pulse mode.
-  *         This parameter can be one of the following values:
-  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
-  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
-{
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
-  assert_param(IS_TIM_PERIOD(htim->Init.Period));
-  assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    TIM_ResetCallback(htim);
-
-    if (htim->OnePulse_MspInitCallback == NULL)
-    {
-      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->OnePulse_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_OnePulse_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Configure the Time base in the One Pulse Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Reset the OPM Bit */
-  htim->Instance->CR1 &= ~TIM_CR1_OPM;
-
-  /* Configure the OPM Mode */
-  htim->Instance->CR1 |= OnePulseMode;
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Initialize the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM One Pulse
-  * @param  htim TIM One Pulse handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  if (htim->OnePulse_MspDeInitCallback == NULL)
-  {
-    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  htim->OnePulse_MspDeInitCallback(htim);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_OnePulse_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM One Pulse MSP.
-  * @param  htim TIM One Pulse handle
-  * @retval None
-  */
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM One Pulse MSP.
-  * @param  htim TIM One Pulse handle
-  * @retval None
-  */
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation.
-  * @note Though OutputChannel parameter is deprecated and ignored by the function
-  *        it has been kept to avoid HAL_TIM API compatibility break.
-  * @note The pulse output channel is determined when calling
-  *       @ref HAL_TIM_OnePulse_ConfigChannel().
-  * @param  htim TIM One Pulse handle
-  * @param  OutputChannel See note above
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(OutputChannel);
-
-  /* Check the TIM channels state */
-  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  /* Enable the Capture compare and the Input Capture channels
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
-    No need to enable the counter, it's enabled automatically by hardware
-    (the counter starts in response to a stimulus and generate a pulse */
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation.
-  * @note Though OutputChannel parameter is deprecated and ignored by the function
-  *        it has been kept to avoid HAL_TIM API compatibility break.
-  * @note The pulse output channel is determined when calling
-  *       @ref HAL_TIM_OnePulse_ConfigChannel().
-  * @param  htim TIM One Pulse handle
-  * @param  OutputChannel See note above
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(OutputChannel);
-
-  /* Disable the Capture compare and the Input Capture channels
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
-  * @note Though OutputChannel parameter is deprecated and ignored by the function
-  *        it has been kept to avoid HAL_TIM API compatibility break.
-  * @note The pulse output channel is determined when calling
-  *       @ref HAL_TIM_OnePulse_ConfigChannel().
-  * @param  htim TIM One Pulse handle
-  * @param  OutputChannel See note above
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(OutputChannel);
-
-  /* Check the TIM channels state */
-  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  /* Enable the Capture compare and the Input Capture channels
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
-    No need to enable the counter, it's enabled automatically by hardware
-    (the counter starts in response to a stimulus and generate a pulse */
-
-  /* Enable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
-  /* Enable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
-  * @note Though OutputChannel parameter is deprecated and ignored by the function
-  *        it has been kept to avoid HAL_TIM API compatibility break.
-  * @note The pulse output channel is determined when calling
-  *       @ref HAL_TIM_OnePulse_ConfigChannel().
-  * @param  htim TIM One Pulse handle
-  * @param  OutputChannel See note above
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(OutputChannel);
-
-  /* Disable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
-  /* Disable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
-  /* Disable the Capture compare and the Input Capture channels
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
-  *  @brief    TIM Encoder functions
-  *
-@verbatim
-  ==============================================================================
-                          ##### TIM Encoder functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM Encoder.
-    (+) De-initialize the TIM Encoder.
-    (+) Start the TIM Encoder.
-    (+) Stop the TIM Encoder.
-    (+) Start the TIM Encoder and enable interrupt.
-    (+) Stop the TIM Encoder and disable interrupt.
-    (+) Start the TIM Encoder and enable DMA transfer.
-    (+) Stop the TIM Encoder and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *         requires a timer reset to avoid unexpected direction
-  *         due to DIR bit readonly in center aligned mode.
-  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
-  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
-  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
-  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
-  * @note   When the timer instance is initialized in Encoder mode, timer
-  *         channels 1 and channel 2 are reserved and cannot be used for other
-  *         purpose.
-  * @param  htim TIM Encoder Interface handle
-  * @param  sConfig TIM Encoder Interface configuration structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
-{
-  uint32_t tmpsmcr;
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
-  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
-  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-  assert_param(IS_TIM_PERIOD(htim->Init.Period));
-  assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    TIM_ResetCallback(htim);
-
-    if (htim->Encoder_MspInitCallback == NULL)
-    {
-      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->Encoder_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_Encoder_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Reset the SMS and ECE bits */
-  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
-
-  /* Configure the Time base in the Encoder Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = htim->Instance->CCMR1;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = htim->Instance->CCER;
-
-  /* Set the encoder Mode */
-  tmpsmcr |= sConfig->EncoderMode;
-
-  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
-  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
-  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
-
-  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
-  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
-  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
-  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
-  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
-
-  /* Set the TI1 and the TI2 Polarities */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
-  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
-  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  /* Write to TIMx CCMR1 */
-  htim->Instance->CCMR1 = tmpccmr1;
-
-  /* Write to TIMx CCER */
-  htim->Instance->CCER = tmpccer;
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  DeInitializes the TIM Encoder interface
-  * @param  htim TIM Encoder Interface handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  if (htim->Encoder_MspDeInitCallback == NULL)
-  {
-    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  htim->Encoder_MspDeInitCallback(htim);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_Encoder_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Encoder Interface MSP.
-  * @param  htim TIM Encoder Interface handle
-  * @retval None
-  */
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_Encoder_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Encoder Interface MSP.
-  * @param  htim TIM Encoder Interface handle
-  * @retval None
-  */
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface.
-  * @param  htim TIM Encoder Interface handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Set the TIM channel(s) state */
-  if (Channel == TIM_CHANNEL_1)
-  {
-    if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else
-  {
-    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-
-  /* Enable the encoder interface channels */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      break;
-    }
-
-    default :
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      break;
-    }
-  }
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface.
-  * @param  htim TIM Encoder Interface handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-      break;
-    }
-
-    default :
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-      break;
-    }
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel(s) state */
-  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
-  {
-    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else
-  {
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface in interrupt mode.
-  * @param  htim TIM Encoder Interface handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Set the TIM channel(s) state */
-  if (Channel == TIM_CHANNEL_1)
-  {
-    if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else
-  {
-    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-
-  /* Enable the encoder interface channels */
-  /* Enable the capture compare Interrupts 1 and/or 2 */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    default :
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface in interrupt mode.
-  * @param  htim TIM Encoder Interface handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  if (Channel == TIM_CHANNEL_1)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 1 */
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 2 */
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }
-  else
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 1 and 2 */
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel(s) state */
-  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
-  {
-    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else
-  {
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface in DMA mode.
-  * @param  htim TIM Encoder Interface handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @param  pData1 The destination Buffer address for IC1.
-  * @param  pData2 The destination Buffer address for IC2.
-  * @param  Length The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
-                                            uint32_t *pData2, uint16_t Length)
-{
-  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Set the TIM channel(s) state */
-  if (Channel == TIM_CHANNEL_1)
-  {
-    if (channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
-    {
-      return HAL_BUSY;
-    }
-    else if (channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
-    {
-      if ((pData1 == NULL) && (Length > 0U))
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-      }
-    }
-    else
-    {
-      return HAL_ERROR;
-    }
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    if (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
-    {
-      return HAL_BUSY;
-    }
-    else if (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
-    {
-      if ((pData2 == NULL) && (Length > 0U))
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-      }
-    }
-    else
-    {
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
-        || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
-    {
-      return HAL_BUSY;
-    }
-    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
-             && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
-    {
-      if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-      }
-    }
-    else
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Input Capture DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      break;
-    }
-
-    default:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
-                           Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      break;
-    }
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface in DMA mode.
-  * @param  htim TIM Encoder Interface handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  if (Channel == TIM_CHANNEL_1)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 1 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 2 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-  }
-  else
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 1 and 2 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel(s) state */
-  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
-  {
-    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else
-  {
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
-  *  @brief    TIM IRQ handler management
-  *
-@verbatim
-  ==============================================================================
-                        ##### IRQ handler management #####
-  ==============================================================================
-  [..]
-    This section provides Timer IRQ handler function.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  This function handles TIM interrupts requests.
-  * @param  htim TIM  handle
-  * @retval None
-  */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
-  /* Capture compare 1 event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
-  {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
-    {
-      {
-        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
-        /* Input capture event */
-        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
-        {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-          htim->IC_CaptureCallback(htim);
-#else
-          HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-        }
-        /* Output compare event */
-        else
-        {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-          htim->OC_DelayElapsedCallback(htim);
-          htim->PWM_PulseFinishedCallback(htim);
-#else
-          HAL_TIM_OC_DelayElapsedCallback(htim);
-          HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-        }
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-      }
-    }
-  }
-  /* Capture compare 2 event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
-  {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-      /* Input capture event */
-      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->IC_CaptureCallback(htim);
-#else
-        HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      /* Output compare event */
-      else
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->OC_DelayElapsedCallback(htim);
-        htim->PWM_PulseFinishedCallback(htim);
-#else
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* Capture compare 3 event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
-  {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-      /* Input capture event */
-      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->IC_CaptureCallback(htim);
-#else
-        HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      /* Output compare event */
-      else
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->OC_DelayElapsedCallback(htim);
-        htim->PWM_PulseFinishedCallback(htim);
-#else
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* Capture compare 4 event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
-  {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-      /* Input capture event */
-      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->IC_CaptureCallback(htim);
-#else
-        HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      /* Output compare event */
-      else
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->OC_DelayElapsedCallback(htim);
-        htim->PWM_PulseFinishedCallback(htim);
-#else
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* TIM Update event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
-  {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-      htim->PeriodElapsedCallback(htim);
-#else
-      HAL_TIM_PeriodElapsedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-    }
-  }
-  /* TIM Trigger detection event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
-  {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-      htim->TriggerCallback(htim);
-#else
-      HAL_TIM_TriggerCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
-  *  @brief    TIM Peripheral Control functions
-  *
-@verbatim
-  ==============================================================================
-                   ##### Peripheral Control functions #####
-  ==============================================================================
- [..]
-   This section provides functions allowing to:
-      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
-      (+) Configure External Clock source.
-      (+) Configure Master and the Slave synchronization.
-      (+) Configure the DMA Burst Mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the TIM Output Compare Channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim TIM Output Compare handle
-  * @param  sConfig TIM Output Compare configuration structure
-  * @param  Channel TIM Channels to configure
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
-                                           TIM_OC_InitTypeDef *sConfig,
-                                           uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Configure the TIM Channel 1 in Output Compare */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Configure the TIM Channel 2 in Output Compare */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Configure the TIM Channel 3 in Output Compare */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-      /* Configure the TIM Channel 4 in Output Compare */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  __HAL_UNLOCK(htim);
-
-  return status;
-}
-
-/**
-  * @brief  Initializes the TIM Input Capture Channels according to the specified
-  *         parameters in the TIM_IC_InitTypeDef.
-  * @param  htim TIM IC handle
-  * @param  sConfig TIM Input Capture configuration structure
-  * @param  Channel TIM Channel to configure
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  if (Channel == TIM_CHANNEL_1)
-  {
-    /* TI1 Configuration */
-    TIM_TI1_SetConfig(htim->Instance,
-                      sConfig->ICPolarity,
-                      sConfig->ICSelection,
-                      sConfig->ICFilter);
-
-    /* Reset the IC1PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
-    /* Set the IC1PSC value */
-    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    /* TI2 Configuration */
-    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-    TIM_TI2_SetConfig(htim->Instance,
-                      sConfig->ICPolarity,
-                      sConfig->ICSelection,
-                      sConfig->ICFilter);
-
-    /* Reset the IC2PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-    /* Set the IC2PSC value */
-    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
-  }
-  else if (Channel == TIM_CHANNEL_3)
-  {
-    /* TI3 Configuration */
-    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-    TIM_TI3_SetConfig(htim->Instance,
-                      sConfig->ICPolarity,
-                      sConfig->ICSelection,
-                      sConfig->ICFilter);
-
-    /* Reset the IC3PSC Bits */
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
-
-    /* Set the IC3PSC value */
-    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
-  }
-  else if (Channel == TIM_CHANNEL_4)
-  {
-    /* TI4 Configuration */
-    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-    TIM_TI4_SetConfig(htim->Instance,
-                      sConfig->ICPolarity,
-                      sConfig->ICSelection,
-                      sConfig->ICFilter);
-
-    /* Reset the IC4PSC Bits */
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
-
-    /* Set the IC4PSC value */
-    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-
-  __HAL_UNLOCK(htim);
-
-  return status;
-}
-
-/**
-  * @brief  Initializes the TIM PWM  channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim TIM PWM handle
-  * @param  sConfig TIM PWM configuration structure
-  * @param  Channel TIM Channels to be configured
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
-                                            TIM_OC_InitTypeDef *sConfig,
-                                            uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 1 in PWM mode */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel1 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode;
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 2 in PWM mode */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel2 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 3 in PWM mode */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel3 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode;
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 4 in PWM mode */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel4 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  __HAL_UNLOCK(htim);
-
-  return status;
-}
-
-/**
-  * @brief  Initializes the TIM One Pulse Channels according to the specified
-  *         parameters in the TIM_OnePulse_InitTypeDef.
-  * @param  htim TIM One Pulse handle
-  * @param  sConfig TIM One Pulse configuration structure
-  * @param  OutputChannel TIM output channel to configure
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @param  InputChannel TIM input Channel to configure
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @note  To output a waveform with a minimum delay user can enable the fast
-  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
-  *        output is forced in response to the edge detection on TIx input,
-  *        without taking in account the comparison.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
-                                                 uint32_t OutputChannel,  uint32_t InputChannel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  TIM_OC_InitTypeDef temp1;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
-  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
-
-  if (OutputChannel != InputChannel)
-  {
-    /* Process Locked */
-    __HAL_LOCK(htim);
-
-    htim->State = HAL_TIM_STATE_BUSY;
-
-    /* Extract the Output compare configuration from sConfig structure */
-    temp1.OCMode = sConfig->OCMode;
-    temp1.Pulse = sConfig->Pulse;
-    temp1.OCPolarity = sConfig->OCPolarity;
-
-    switch (OutputChannel)
-    {
-      case TIM_CHANNEL_1:
-      {
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-        TIM_OC1_SetConfig(htim->Instance, &temp1);
-        break;
-      }
-
-      case TIM_CHANNEL_2:
-      {
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-        TIM_OC2_SetConfig(htim->Instance, &temp1);
-        break;
-      }
-
-      default:
-        status = HAL_ERROR;
-        break;
-    }
-
-    if (status == HAL_OK)
-    {
-      switch (InputChannel)
-      {
-        case TIM_CHANNEL_1:
-        {
-          assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-          TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
-                            sConfig->ICSelection, sConfig->ICFilter);
-
-          /* Reset the IC1PSC Bits */
-          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
-          /* Select the Trigger source */
-          htim->Instance->SMCR &= ~TIM_SMCR_TS;
-          htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
-          /* Select the Slave Mode */
-          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-          break;
-        }
-
-        case TIM_CHANNEL_2:
-        {
-          assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-          TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
-                            sConfig->ICSelection, sConfig->ICFilter);
-
-          /* Reset the IC2PSC Bits */
-          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-          /* Select the Trigger source */
-          htim->Instance->SMCR &= ~TIM_SMCR_TS;
-          htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
-          /* Select the Slave Mode */
-          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-          break;
-        }
-
-        default:
-          status = HAL_ERROR;
-          break;
-      }
-    }
-
-    htim->State = HAL_TIM_STATE_READY;
-
-    __HAL_UNLOCK(htim);
-
-    return status;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
-  * @param  htim TIM handle
-  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMABASE_CR1
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT
-  *            @arg TIM_DMABASE_PSC
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_OR
-  * @param  BurstRequestSrc TIM DMA Request sources
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer The Buffer address.
-  * @param  BurstLength DMA Burst length. This parameter can be one value
-  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
-  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                              uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (status == HAL_OK)
-  {
-    status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
-                                              ((BurstLength) >> 8U) + 1U);
-  }
-
-
-  return status;
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
-  * @param  htim TIM handle
-  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMABASE_CR1
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT
-  *            @arg TIM_DMABASE_PSC
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_OR
-  * @param  BurstRequestSrc TIM DMA Request sources
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer The Buffer address.
-  * @param  BurstLength DMA Burst length. This parameter can be one value
-  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
-  * @param  DataLength Data length. This parameter can be one value
-  *         between 1 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
-                                                   uint32_t  BurstLength,  uint32_t  DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
-
-  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
-  {
-    if ((BurstBuffer == NULL) && (BurstLength > 0U))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
-    }
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-  switch (BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      /* Set the DMA Period elapsed callbacks */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
-                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC1:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
-                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC2:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
-                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC3:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
-                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC4:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
-                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_TRIGGER:
-    {
-      /* Set the DMA trigger callbacks */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
-                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Configure the DMA Burst Mode */
-    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
-    /* Enable the TIM DMA Request */
-    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Stops the TIM DMA Burst mode
-  * @param  htim TIM handle
-  * @param  BurstRequestSrc TIM DMA Request sources to disable
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch (BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
-      break;
-    }
-    case TIM_DMA_CC1:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-      break;
-    }
-    case TIM_DMA_CC2:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-      break;
-    }
-    case TIM_DMA_CC3:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
-      break;
-    }
-    case TIM_DMA_CC4:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
-      break;
-    }
-    case TIM_DMA_TRIGGER:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
-      break;
-    }
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Disable the TIM Update DMA request */
-    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
-    /* Change the DMA burst operation state */
-    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
-  * @param  htim TIM handle
-  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMABASE_CR1
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT
-  *            @arg TIM_DMABASE_PSC
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_OR
-  * @param  BurstRequestSrc TIM DMA Request sources
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer The Buffer address.
-  * @param  BurstLength DMA Burst length. This parameter can be one value
-  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
-  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (status == HAL_OK)
-  {
-    status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
-                                             ((BurstLength) >> 8U) + 1U);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
-  * @param  htim TIM handle
-  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMABASE_CR1
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT
-  *            @arg TIM_DMABASE_PSC
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_OR
-  * @param  BurstRequestSrc TIM DMA Request sources
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer The Buffer address.
-  * @param  BurstLength DMA Burst length. This parameter can be one value
-  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
-  * @param  DataLength Data length. This parameter can be one value
-  *         between 1 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
-                                                  uint32_t  BurstLength, uint32_t  DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
-
-  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
-  {
-    if ((BurstBuffer == NULL) && (BurstLength > 0U))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
-    }
-  }
-  else
-  {
-    /* nothing to do */
-  }
-  switch (BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      /* Set the DMA Period elapsed callbacks */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                           DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC1:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                           DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC2:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                           DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC3:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                           DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC4:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                           DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_TRIGGER:
-    {
-      /* Set the DMA trigger callbacks */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                           DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Configure the DMA Burst Mode */
-    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
-
-    /* Enable the TIM DMA Request */
-    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Stop the DMA burst reading
-  * @param  htim TIM handle
-  * @param  BurstRequestSrc TIM DMA Request sources to disable.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch (BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
-      break;
-    }
-    case TIM_DMA_CC1:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-      break;
-    }
-    case TIM_DMA_CC2:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-      break;
-    }
-    case TIM_DMA_CC3:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
-      break;
-    }
-    case TIM_DMA_CC4:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
-      break;
-    }
-    case TIM_DMA_TRIGGER:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
-      break;
-    }
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    /* Disable the TIM Update DMA request */
-    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
-    /* Change the DMA burst operation state */
-    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Generate a software event
-  * @param  htim TIM handle
-  * @param  EventSource specifies the event source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
-  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
-  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
-  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
-  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
-  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
-  * @note   Basic timers can only generate an update event.
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  /* Change the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Set the event sources */
-  htim->Instance->EGR = EventSource;
-
-  /* Change the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the OCRef clear feature
-  * @param  htim TIM handle
-  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
-  *         contains the OCREF clear feature and parameters for the TIM peripheral.
-  * @param  Channel specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1
-  *            @arg TIM_CHANNEL_2: TIM Channel 2
-  *            @arg TIM_CHANNEL_3: TIM Channel 3
-  *            @arg TIM_CHANNEL_4: TIM Channel 4
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
-                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
-                                           uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (sClearInputConfig->ClearInputSource)
-  {
-    case TIM_CLEARINPUTSOURCE_NONE:
-    {
-      /* Clear the OCREF clear selection bit and the the ETR Bits */
-      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
-      break;
-    }
-
-    case TIM_CLEARINPUTSOURCE_ETR:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
-      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
-      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
-      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
-      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
-      {
-        htim->State = HAL_TIM_STATE_READY;
-        __HAL_UNLOCK(htim);
-        return HAL_ERROR;
-      }
-
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClearInputConfig->ClearInputPrescaler,
-                        sClearInputConfig->ClearInputPolarity,
-                        sClearInputConfig->ClearInputFilter);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  if (status == HAL_OK)
-  {
-    switch (Channel)
-    {
-      case TIM_CHANNEL_1:
-      {
-        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-        {
-          /* Enable the OCREF clear feature for Channel 1 */
-          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
-        }
-        else
-        {
-          /* Disable the OCREF clear feature for Channel 1 */
-          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
-        }
-        break;
-      }
-      case TIM_CHANNEL_2:
-      {
-        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-        {
-          /* Enable the OCREF clear feature for Channel 2 */
-          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
-        }
-        else
-        {
-          /* Disable the OCREF clear feature for Channel 2 */
-          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
-        }
-        break;
-      }
-      case TIM_CHANNEL_3:
-      {
-        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-        {
-          /* Enable the OCREF clear feature for Channel 3 */
-          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
-        }
-        else
-        {
-          /* Disable the OCREF clear feature for Channel 3 */
-          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
-        }
-        break;
-      }
-      case TIM_CHANNEL_4:
-      {
-        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-        {
-          /* Enable the OCREF clear feature for Channel 4 */
-          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
-        }
-        else
-        {
-          /* Disable the OCREF clear feature for Channel 4 */
-          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
-        }
-        break;
-      }
-      default:
-        break;
-    }
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return status;
-}
-
-/**
-  * @brief   Configures the clock source to be used
-  * @param  htim TIM handle
-  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
-  *         contains the clock source information for the TIM peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmpsmcr;
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
-  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
-  tmpsmcr = htim->Instance->SMCR;
-  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-  htim->Instance->SMCR = tmpsmcr;
-
-  switch (sClockSourceConfig->ClockSource)
-  {
-    case TIM_CLOCKSOURCE_INTERNAL:
-    {
-      assert_param(IS_TIM_INSTANCE(htim->Instance));
-      break;
-    }
-
-    case TIM_CLOCKSOURCE_ETRMODE1:
-    {
-      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-
-      /* Check ETR input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClockSourceConfig->ClockPrescaler,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-
-      /* Select the External clock mode1 and the ETRF trigger */
-      tmpsmcr = htim->Instance->SMCR;
-      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
-      /* Write to TIMx SMCR */
-      htim->Instance->SMCR = tmpsmcr;
-      break;
-    }
-
-    case TIM_CLOCKSOURCE_ETRMODE2:
-    {
-      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
-
-      /* Check ETR input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClockSourceConfig->ClockPrescaler,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      /* Enable the External clock mode2 */
-      htim->Instance->SMCR |= TIM_SMCR_ECE;
-      break;
-    }
-
-    case TIM_CLOCKSOURCE_TI1:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 */
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sClockSourceConfig->ClockPolarity,
-                               sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
-      break;
-    }
-
-    case TIM_CLOCKSOURCE_TI2:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      /* Check TI2 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI2_ConfigInputStage(htim->Instance,
-                               sClockSourceConfig->ClockPolarity,
-                               sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
-      break;
-    }
-
-    case TIM_CLOCKSOURCE_TI1ED:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 */
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sClockSourceConfig->ClockPolarity,
-                               sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
-      break;
-    }
-
-    case TIM_CLOCKSOURCE_ITR0:
-    case TIM_CLOCKSOURCE_ITR1:
-    case TIM_CLOCKSOURCE_ITR2:
-    case TIM_CLOCKSOURCE_ITR3:
-    {
-      /* Check whether or not the timer instance supports internal trigger input */
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
-      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return status;
-}
-
-/**
-  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
-  *         or a XOR combination between CH1_input, CH2_input & CH3_input
-  * @param  htim TIM handle.
-  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
-  *         output of a XOR gate.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
-  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
-  *            pins are connected to the TI1 input (XOR combination)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
-{
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = htim->Instance->CR2;
-
-  /* Reset the TI1 selection */
-  tmpcr2 &= ~TIM_CR2_TI1S;
-
-  /* Set the TI1 selection */
-  tmpcr2 |= TI1_Selection;
-
-  /* Write to TIMxCR2 */
-  htim->Instance->CR2 = tmpcr2;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM in Slave mode
-  * @param  htim TIM handle.
-  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the Slave mode
-  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
-  {
-    htim->State = HAL_TIM_STATE_READY;
-    __HAL_UNLOCK(htim);
-    return HAL_ERROR;
-  }
-
-  /* Disable Trigger Interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-
-  /* Disable Trigger DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM in Slave mode in interrupt mode
-  * @param  htim TIM handle.
-  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the Slave mode
-  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
-                                                TIM_SlaveConfigTypeDef *sSlaveConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
-  {
-    htim->State = HAL_TIM_STATE_READY;
-    __HAL_UNLOCK(htim);
-    return HAL_ERROR;
-  }
-
-  /* Enable Trigger Interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-
-  /* Disable Trigger DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Read the captured value from Capture Compare unit
-  * @param  htim TIM handle.
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval Captured value
-  */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpreg = 0U;
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Return the capture 1 value */
-      tmpreg =  htim->Instance->CCR1;
-
-      break;
-    }
-    case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Return the capture 2 value */
-      tmpreg =   htim->Instance->CCR2;
-
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Return the capture 3 value */
-      tmpreg =   htim->Instance->CCR3;
-
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-      /* Return the capture 4 value */
-      tmpreg =   htim->Instance->CCR4;
-
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  return tmpreg;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
-  *  @brief    TIM Callbacks functions
-  *
-@verbatim
-  ==============================================================================
-                        ##### TIM Callbacks functions #####
-  ==============================================================================
- [..]
-   This section provides TIM callback functions:
-   (+) TIM Period elapsed callback
-   (+) TIM Output Compare callback
-   (+) TIM Input capture callback
-   (+) TIM Trigger callback
-   (+) TIM Error callback
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Period elapsed callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Period elapsed half complete callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Output Compare callback in non-blocking mode
-  * @param  htim TIM OC handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Input Capture callback in non-blocking mode
-  * @param  htim TIM IC handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Input Capture half complete callback in non-blocking mode
-  * @param  htim TIM IC handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  PWM Pulse finished callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  PWM Pulse finished half complete callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Hall Trigger detection callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_TriggerCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Hall Trigger detection half complete callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Timer error callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_ErrorCallback could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
-  * @param htim tim handle
-  * @param CallbackID ID of the callback to be registered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
-  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
-  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
-  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
-  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
-  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
-  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
-  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
-  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
-  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
-  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
-  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
-  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
-  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
-  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
-  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
-  *          @param pCallback pointer to the callback function
-  *          @retval status
-  */
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
-                                           pTIM_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(htim);
-
-  if (htim->State == HAL_TIM_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_TIM_BASE_MSPINIT_CB_ID :
-        htim->Base_MspInitCallback                 = pCallback;
-        break;
-
-      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
-        htim->Base_MspDeInitCallback               = pCallback;
-        break;
-
-      case HAL_TIM_IC_MSPINIT_CB_ID :
-        htim->IC_MspInitCallback                   = pCallback;
-        break;
-
-      case HAL_TIM_IC_MSPDEINIT_CB_ID :
-        htim->IC_MspDeInitCallback                 = pCallback;
-        break;
-
-      case HAL_TIM_OC_MSPINIT_CB_ID :
-        htim->OC_MspInitCallback                   = pCallback;
-        break;
-
-      case HAL_TIM_OC_MSPDEINIT_CB_ID :
-        htim->OC_MspDeInitCallback                 = pCallback;
-        break;
-
-      case HAL_TIM_PWM_MSPINIT_CB_ID :
-        htim->PWM_MspInitCallback                  = pCallback;
-        break;
-
-      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
-        htim->PWM_MspDeInitCallback                = pCallback;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
-        htim->OnePulse_MspInitCallback             = pCallback;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
-        htim->OnePulse_MspDeInitCallback           = pCallback;
-        break;
-
-      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
-        htim->Encoder_MspInitCallback              = pCallback;
-        break;
-
-      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
-        htim->Encoder_MspDeInitCallback            = pCallback;
-        break;
-
-      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
-        htim->PeriodElapsedCallback                = pCallback;
-        break;
-
-      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
-        htim->PeriodElapsedHalfCpltCallback        = pCallback;
-        break;
-
-      case HAL_TIM_TRIGGER_CB_ID :
-        htim->TriggerCallback                      = pCallback;
-        break;
-
-      case HAL_TIM_TRIGGER_HALF_CB_ID :
-        htim->TriggerHalfCpltCallback              = pCallback;
-        break;
-
-      case HAL_TIM_IC_CAPTURE_CB_ID :
-        htim->IC_CaptureCallback                   = pCallback;
-        break;
-
-      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
-        htim->IC_CaptureHalfCpltCallback           = pCallback;
-        break;
-
-      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
-        htim->OC_DelayElapsedCallback              = pCallback;
-        break;
-
-      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
-        htim->PWM_PulseFinishedCallback            = pCallback;
-        break;
-
-      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
-        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
-        break;
-
-      case HAL_TIM_ERROR_CB_ID :
-        htim->ErrorCallback                        = pCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_TIM_BASE_MSPINIT_CB_ID :
-        htim->Base_MspInitCallback         = pCallback;
-        break;
-
-      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
-        htim->Base_MspDeInitCallback       = pCallback;
-        break;
-
-      case HAL_TIM_IC_MSPINIT_CB_ID :
-        htim->IC_MspInitCallback           = pCallback;
-        break;
-
-      case HAL_TIM_IC_MSPDEINIT_CB_ID :
-        htim->IC_MspDeInitCallback         = pCallback;
-        break;
-
-      case HAL_TIM_OC_MSPINIT_CB_ID :
-        htim->OC_MspInitCallback           = pCallback;
-        break;
-
-      case HAL_TIM_OC_MSPDEINIT_CB_ID :
-        htim->OC_MspDeInitCallback         = pCallback;
-        break;
-
-      case HAL_TIM_PWM_MSPINIT_CB_ID :
-        htim->PWM_MspInitCallback          = pCallback;
-        break;
-
-      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
-        htim->PWM_MspDeInitCallback        = pCallback;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
-        htim->OnePulse_MspInitCallback     = pCallback;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
-        htim->OnePulse_MspDeInitCallback   = pCallback;
-        break;
-
-      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
-        htim->Encoder_MspInitCallback      = pCallback;
-        break;
-
-      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
-        htim->Encoder_MspDeInitCallback    = pCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status = HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister a TIM callback
-  *         TIM callback is redirected to the weak predefined callback
-  * @param htim tim handle
-  * @param CallbackID ID of the callback to be unregistered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
-  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
-  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
-  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
-  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
-  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
-  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
-  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
-  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
-  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
-  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
-  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
-  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
-  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
-  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
-  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
-  *          @retval status
-  */
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(htim);
-
-  if (htim->State == HAL_TIM_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_TIM_BASE_MSPINIT_CB_ID :
-        /* Legacy weak Base MspInit Callback */
-        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
-        break;
-
-      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
-        /* Legacy weak Base Msp DeInit Callback */
-        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
-        break;
-
-      case HAL_TIM_IC_MSPINIT_CB_ID :
-        /* Legacy weak IC Msp Init Callback */
-        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
-        break;
-
-      case HAL_TIM_IC_MSPDEINIT_CB_ID :
-        /* Legacy weak IC Msp DeInit Callback */
-        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
-        break;
-
-      case HAL_TIM_OC_MSPINIT_CB_ID :
-        /* Legacy weak OC Msp Init Callback */
-        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
-        break;
-
-      case HAL_TIM_OC_MSPDEINIT_CB_ID :
-        /* Legacy weak OC Msp DeInit Callback */
-        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
-        break;
-
-      case HAL_TIM_PWM_MSPINIT_CB_ID :
-        /* Legacy weak PWM Msp Init Callback */
-        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
-        break;
-
-      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
-        /* Legacy weak PWM Msp DeInit Callback */
-        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
-        /* Legacy weak One Pulse Msp Init Callback */
-        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
-        /* Legacy weak One Pulse Msp DeInit Callback */
-        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
-        break;
-
-      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
-        /* Legacy weak Encoder Msp Init Callback */
-        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
-        break;
-
-      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
-        /* Legacy weak Encoder Msp DeInit Callback */
-        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
-        break;
-
-      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
-        /* Legacy weak Period Elapsed Callback */
-        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
-        break;
-
-      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
-        /* Legacy weak Period Elapsed half complete Callback */
-        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
-        break;
-
-      case HAL_TIM_TRIGGER_CB_ID :
-        /* Legacy weak Trigger Callback */
-        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
-        break;
-
-      case HAL_TIM_TRIGGER_HALF_CB_ID :
-        /* Legacy weak Trigger half complete Callback */
-        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
-        break;
-
-      case HAL_TIM_IC_CAPTURE_CB_ID :
-        /* Legacy weak IC Capture Callback */
-        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
-        break;
-
-      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
-        /* Legacy weak IC Capture half complete Callback */
-        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
-        break;
-
-      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
-        /* Legacy weak OC Delay Elapsed Callback */
-        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
-        break;
-
-      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
-        /* Legacy weak PWM Pulse Finished Callback */
-        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
-        break;
-
-      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
-        /* Legacy weak PWM Pulse Finished half complete Callback */
-        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
-        break;
-
-      case HAL_TIM_ERROR_CB_ID :
-        /* Legacy weak Error Callback */
-        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_TIM_BASE_MSPINIT_CB_ID :
-        /* Legacy weak Base MspInit Callback */
-        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
-        break;
-
-      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
-        /* Legacy weak Base Msp DeInit Callback */
-        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
-        break;
-
-      case HAL_TIM_IC_MSPINIT_CB_ID :
-        /* Legacy weak IC Msp Init Callback */
-        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
-        break;
-
-      case HAL_TIM_IC_MSPDEINIT_CB_ID :
-        /* Legacy weak IC Msp DeInit Callback */
-        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
-        break;
-
-      case HAL_TIM_OC_MSPINIT_CB_ID :
-        /* Legacy weak OC Msp Init Callback */
-        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
-        break;
-
-      case HAL_TIM_OC_MSPDEINIT_CB_ID :
-        /* Legacy weak OC Msp DeInit Callback */
-        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
-        break;
-
-      case HAL_TIM_PWM_MSPINIT_CB_ID :
-        /* Legacy weak PWM Msp Init Callback */
-        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
-        break;
-
-      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
-        /* Legacy weak PWM Msp DeInit Callback */
-        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
-        /* Legacy weak One Pulse Msp Init Callback */
-        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
-        /* Legacy weak One Pulse Msp DeInit Callback */
-        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
-        break;
-
-      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
-        /* Legacy weak Encoder Msp Init Callback */
-        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
-        break;
-
-      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
-        /* Legacy weak Encoder Msp DeInit Callback */
-        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
-        break;
-
-      default :
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status = HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return status;
-}
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
-  *  @brief   TIM Peripheral State functions
-  *
-@verbatim
-  ==============================================================================
-                        ##### Peripheral State functions #####
-  ==============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the TIM Base handle state.
-  * @param  htim TIM Base handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM OC handle state.
-  * @param  htim TIM Output Compare handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM PWM handle state.
-  * @param  htim TIM handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Input Capture handle state.
-  * @param  htim TIM IC handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM One Pulse Mode handle state.
-  * @param  htim TIM OPM handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Encoder Mode handle state.
-  * @param  htim TIM Encoder Interface handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Encoder Mode handle state.
-  * @param  htim TIM handle
-  * @retval Active channel
-  */
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
-{
-  return htim->Channel;
-}
-
-/**
-  * @brief  Return actual state of the TIM channel.
-  * @param  htim TIM handle
-  * @param  Channel TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1
-  *            @arg TIM_CHANNEL_2: TIM Channel 2
-  *            @arg TIM_CHANNEL_3: TIM Channel 3
-  *            @arg TIM_CHANNEL_4: TIM Channel 4
-  *            @arg TIM_CHANNEL_5: TIM Channel 5
-  *            @arg TIM_CHANNEL_6: TIM Channel 6
-  * @retval TIM Channel state
-  */
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel)
-{
-  HAL_TIM_ChannelStateTypeDef channel_state;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
-  return channel_state;
-}
-
-/**
-  * @brief  Return actual state of a DMA burst operation.
-  * @param  htim TIM handle
-  * @retval DMA burst state
-  */
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-
-  return htim->DMABurstState;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Functions TIM Private Functions
-  * @{
-  */
-
-/**
-  * @brief  TIM DMA error callback
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-void TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else
-  {
-    htim->State = HAL_TIM_STATE_READY;
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->ErrorCallback(htim);
-#else
-  HAL_TIM_ErrorCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Delay Pulse complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->PWM_PulseFinishedCallback(htim);
-#else
-  HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Delay Pulse half complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->PWM_PulseFinishedHalfCpltCallback(htim);
-#else
-  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Capture complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->IC_CaptureCallback(htim);
-#else
-  HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Capture half complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->IC_CaptureHalfCpltCallback(htim);
-#else
-  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Period Elapse complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
-  {
-    htim->State = HAL_TIM_STATE_READY;
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->PeriodElapsedCallback(htim);
-#else
-  HAL_TIM_PeriodElapsedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  TIM DMA Period Elapse half complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->PeriodElapsedHalfCpltCallback(htim);
-#else
-  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  TIM DMA Trigger callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
-  {
-    htim->State = HAL_TIM_STATE_READY;
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->TriggerCallback(htim);
-#else
-  HAL_TIM_TriggerCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  TIM DMA Trigger half complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->TriggerHalfCpltCallback(htim);
-#else
-  HAL_TIM_TriggerHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  Time Base configuration
-  * @param  TIMx TIM peripheral
-  * @param  Structure TIM Base configuration structure
-  * @retval None
-  */
-static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
-  uint32_t tmpcr1;
-  tmpcr1 = TIMx->CR1;
-
-  /* Set TIM Time Base Unit parameters ---------------------------------------*/
-  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
-  {
-    /* Select the Counter Mode */
-    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
-    tmpcr1 |= Structure->CounterMode;
-  }
-
-  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
-  {
-    /* Set the clock division */
-    tmpcr1 &= ~TIM_CR1_CKD;
-    tmpcr1 |= (uint32_t)Structure->ClockDivision;
-  }
-
-  /* Set the auto-reload preload */
-  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
-
-  TIMx->CR1 = tmpcr1;
-
-  /* Set the Autoreload value */
-  TIMx->ARR = (uint32_t)Structure->Period ;
-
-  /* Set the Prescaler value */
-  TIMx->PSC = Structure->Prescaler;
-
-  /* Generate an update event to reload the Prescaler
-     and the repetition counter (only for advanced timer) value immediately */
-  TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
-  * @brief  Timer Output Compare 1 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config The output configuration structure
-  * @retval None
-  */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC1M;
-  tmpccmrx &= ~TIM_CCMR1_CC1S;
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC1P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= OC_Config->OCPolarity;
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR1 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Timer Output Compare 2 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config The output configuration structure
-  * @retval None
-  */
-static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC2M;
-  tmpccmrx &= ~TIM_CCMR1_CC2S;
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8U);
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC2P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 4U);
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR2 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Timer Output Compare 3 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config The output configuration structure
-  * @retval None
-  */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Disable the Channel 3: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC3E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR2_OC3M;
-  tmpccmrx &= ~TIM_CCMR2_CC3S;
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC3P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 8U);
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR3 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Timer Output Compare 4 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config The output configuration structure
-  * @retval None
-  */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC4E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR2_OC4M;
-  tmpccmrx &= ~TIM_CCMR2_CC4S;
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8U);
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC4P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 12U);
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR4 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Slave Timer configuration function
-  * @param  htim TIM handle
-  * @param  sSlaveConfig Slave timer configuration
-  * @retval None
-  */
-static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmpsmcr;
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Reset the Trigger Selection Bits */
-  tmpsmcr &= ~TIM_SMCR_TS;
-  /* Set the Input Trigger source */
-  tmpsmcr |= sSlaveConfig->InputTrigger;
-
-  /* Reset the slave mode Bits */
-  tmpsmcr &= ~TIM_SMCR_SMS;
-  /* Set the slave mode */
-  tmpsmcr |= sSlaveConfig->SlaveMode;
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  /* Configure the trigger prescaler, filter, and polarity */
-  switch (sSlaveConfig->InputTrigger)
-  {
-    case TIM_TS_ETRF:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-      /* Configure the ETR Trigger source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sSlaveConfig->TriggerPrescaler,
-                        sSlaveConfig->TriggerPolarity,
-                        sSlaveConfig->TriggerFilter);
-      break;
-    }
-
-    case TIM_TS_TI1F_ED:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
-      {
-        return HAL_ERROR;
-      }
-
-      /* Disable the Channel 1: Reset the CC1E Bit */
-      tmpccer = htim->Instance->CCER;
-      htim->Instance->CCER &= ~TIM_CCER_CC1E;
-      tmpccmr1 = htim->Instance->CCMR1;
-
-      /* Set the filter */
-      tmpccmr1 &= ~TIM_CCMR1_IC1F;
-      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
-
-      /* Write to TIMx CCMR1 and CCER registers */
-      htim->Instance->CCMR1 = tmpccmr1;
-      htim->Instance->CCER = tmpccer;
-      break;
-    }
-
-    case TIM_TS_TI1FP1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Configure TI1 Filter and Polarity */
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sSlaveConfig->TriggerPolarity,
-                               sSlaveConfig->TriggerFilter);
-      break;
-    }
-
-    case TIM_TS_TI2FP2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Configure TI2 Filter and Polarity */
-      TIM_TI2_ConfigInputStage(htim->Instance,
-                               sSlaveConfig->TriggerPolarity,
-                               sSlaveConfig->TriggerFilter);
-      break;
-    }
-
-    case TIM_TS_ITR0:
-    case TIM_TS_ITR1:
-    case TIM_TS_ITR2:
-    case TIM_TS_ITR3:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      break;
-    }
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Configure the TI1 as Input.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICSelection specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
-  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
-  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
-  {
-    tmpccmr1 &= ~TIM_CCMR1_CC1S;
-    tmpccmr1 |= TIM_ICSelection;
-  }
-  else
-  {
-    tmpccmr1 |= TIM_CCMR1_CC1S_0;
-  }
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI1.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  tmpccer = TIMx->CCER;
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= (TIM_ICFilter << 4U);
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= TIM_ICPolarity;
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI2 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICSelection specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
-  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
-  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr1 &= ~TIM_CCMR1_CC2S;
-  tmpccmr1 |= (TIM_ICSelection << 8U);
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI2.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= (TIM_ICFilter << 12U);
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= (TIM_ICPolarity << 4U);
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI3 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICSelection specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
-  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
-  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr2;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC3E;
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr2 &= ~TIM_CCMR2_CC3S;
-  tmpccmr2 |= TIM_ICSelection;
-
-  /* Set the filter */
-  tmpccmr2 &= ~TIM_CCMR2_IC3F;
-  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
-
-  /* Select the Polarity and set the CC3E Bit */
-  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
-  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
-
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI4 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICSelection specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
-  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
-  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
-  *        protected against un-initialized filter and polarity values.
-  * @retval None
-  */
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr2;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC4E;
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr2 &= ~TIM_CCMR2_CC4S;
-  tmpccmr2 |= (TIM_ICSelection << 8U);
-
-  /* Set the filter */
-  tmpccmr2 &= ~TIM_CCMR2_IC4F;
-  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
-
-  /* Select the Polarity and set the CC4E Bit */
-  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
-  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
-
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer ;
-}
-
-/**
-  * @brief  Selects the Input Trigger source
-  * @param  TIMx to select the TIM peripheral
-  * @param  InputTriggerSource The Input Trigger source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal Trigger 0
-  *            @arg TIM_TS_ITR1: Internal Trigger 1
-  *            @arg TIM_TS_ITR2: Internal Trigger 2
-  *            @arg TIM_TS_ITR3: Internal Trigger 3
-  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
-  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
-  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
-  *            @arg TIM_TS_ETRF: External Trigger input
-  * @retval None
-  */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
-{
-  uint32_t tmpsmcr;
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = TIMx->SMCR;
-  /* Reset the TS Bits */
-  tmpsmcr &= ~TIM_SMCR_TS;
-  /* Set the Input Trigger source and the slave mode*/
-  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-/**
-  * @brief  Configures the TIMx External Trigger (ETR).
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
-  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
-  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
-  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
-  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
-  * @param  ExtTRGFilter External Trigger Filter.
-  *          This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
-                              uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
-  uint32_t tmpsmcr;
-
-  tmpsmcr = TIMx->SMCR;
-
-  /* Reset the ETR Bits */
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
-  /* Set the Prescaler, the Filter value and the Polarity */
-  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
-
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel x.
-  * @param  TIMx to select the TIM peripheral
-  * @param  Channel specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1
-  *            @arg TIM_CHANNEL_2: TIM Channel 2
-  *            @arg TIM_CHANNEL_3: TIM Channel 3
-  *            @arg TIM_CHANNEL_4: TIM Channel 4
-  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
-  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
-  * @retval None
-  */
-static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
-{
-  uint32_t tmp;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
-  assert_param(IS_TIM_CHANNELS(Channel));
-
-  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
-
-  /* Reset the CCxE Bit */
-  TIMx->CCER &= ~tmp;
-
-  /* Set or reset the CCxE Bit */
-  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
-}
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
-  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-void TIM_ResetCallback(TIM_HandleTypeDef *htim)
-{
-  /* Reset the TIM callback to the legacy weak callbacks */
-  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
-  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
-  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
-  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
-  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
-  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
-  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
-  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
-  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
-  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
-}
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c
deleted file mode 100644
index 57132189c1..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c
+++ /dev/null
@@ -1,427 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_tim_ex.c
-  * @author  MCD Application Team
-  * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Timer Extended peripheral:
-  *           + Time Master and Slave synchronization configuration
-  *           + Timer remapping capabilities configuration
-  @verbatim
-  ==============================================================================
-                      ##### TIMER Extended features #####
-  ==============================================================================
-  [..]
-    The Timer Extended features include:
-    (#) Synchronization circuit to control the timer with external signals and to
-        interconnect several timers together.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TIMEx TIMEx
-  * @brief TIM Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
-  * @{
-  */
-/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
-  * @brief    Peripheral Control functions
-  *
-@verbatim
-  ==============================================================================
-                    ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-      (+) Configure Master synchronization.
-      (+) Configure timer remapping capabilities.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the TIM in master mode.
-  * @param  htim TIM handle.
-  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
-  *         contains the selected trigger output (TRGO) and the Master/Slave
-  *         mode.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
-                                                        TIM_MasterConfigTypeDef *sMasterConfig)
-{
-  uint32_t tmpcr2;
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
-  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  /* Change the handler state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = htim->Instance->CR2;
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Reset the MMS Bits */
-  tmpcr2 &= ~TIM_CR2_MMS;
-  /* Select the TRGO source */
-  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
-
-  /* Update TIMx CR2 */
-  htim->Instance->CR2 = tmpcr2;
-
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    /* Reset the MSM Bit */
-    tmpsmcr &= ~TIM_SMCR_MSM;
-    /* Set master mode */
-    tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
-    /* Update TIMx SMCR */
-    htim->Instance->SMCR = tmpsmcr;
-  }
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIMx Remapping input capabilities.
-  @if STM32L073xx
-  * @note   It is not possible to connect TIM2 and TIM21 on PB5(AF4) at the same time.
-  *         When selecting TIM3_TI2_GPIOB5_AF4, Channel2 of TIM3 will be
-  *         connected to PB5(AF4) and Channel2 of TIM21 will be connected to
-  *         some other GPIOs. (refer to alternate functions for more details)
-  *         When selecting TIM3_TI2_GPIO_DEF, Channel2 of Timer 3 will be
-  *         connected an GPIO (other than PB5(AF4)) and Channel2 of TIM21
-  *         will be connected to PB5(AF4).
-  * @note   When TIM2 ETR is fed with HSI48, this ETR must be prescaled internally
-  *         to the TIMER2 because the maximum system frequency is 32 MHz
-  @endif
-  * @param  htim TIM handle.
-  * @param  Remap specifies the TIM remapping source.
-  @if STM32L073xx
-  *         For TIM2, the parameter is a combination of 2 fields (field1 | field2):
-  *
-  *                   field1 can have the following values:
-  *           @arg TIM2_ETR_GPIO:      TIM2  ETR connected to GPIO (default):
-  *                                    PA0(AF5) or PA5(AF2) or PA15(AF2) or PE9(AF2)
-  *           @arg TIM2_ETR_HSI48:     TIM2  ETR connected to HSI48
-  *           @arg TIM2_ETR_HSI16:     TIM2  ETR connected to HSI16
-  *           @arg TIM2_ETR_LSE:       TIM2  ETR connected to LSE
-  *           @arg TIM2_ETR_COMP2_OUT: TIM2  ETR connected to COMP2 output
-  *           @arg TIM2_ETR_COMP1_OUT: TIM2  ETR connected to COMP1 output
-  *
-  *                   field2 can have the following values:
-  *           @arg TIM2_TI4_GPIO :     TIM2  TI4 connected to GPIO1(default):
-  *                                    PA3(AF2) or PB11(AF2) or PE12(AF0)
-  *           @arg TIM2_TI4_COMP1:     TIM2  TI4 connected to COMP1
-  *           @arg TIM2_TI4_COMP2:     TIM2  TI4 connected to COMP2
-  @endif
-  @if STM32L031xx
-  *         For TIM2, the parameter is a combination of 2 fields (field1 | field2):
-  *
-  *                   field1 can have the following values:
-  *           @arg TIM2_ETR_GPIO:      TIM2  ETR connected to GPIO (default):
-  *                                    PA0(AF5) or PA5(AF2) or PA15(AF2)
-  *           @arg TIM2_ETR_HSI16:     TIM2  ETR connected to HS16 (HSIOUT)
-  *           @arg TIM2_ETR_LSE:       TIM2  ETR connected to LSE
-  *           @arg TIM2_ETR_COMP2_OUT: TIM2  ETR connected to COMP2 output
-  *           @arg TIM2_ETR_COMP1_OUT: TIM2  ETR connected to COMP1 output
-  *
-  *                   field2 can have the following values:
-  *           @arg TIM2_TI4_GPIO :     TIM2  TI4 connected to GPIO (default):
-  *                                    PA3(AF2) or PB11(AF2) or PB1(AF5)
-  *           @arg TIM2_TI4_COMP1_OUT: TIM2  TI4 connected to COMP1 output
-  *           @arg TIM2_TI4_COMP2_OUT: TIM2  TI4 connected to COMP2 output
-  @endif
-  @if STM32L011xx
-  *         For TIM2, the parameter is a combination of 2 fields (field1 | field2):
-  *
-  *                   field1 can have the following values:
-  *           @arg TIM2_ETR_GPIO:      TIM2  ETR connected to GPIO (default):
-  *                                    PA0(AF5) or PA5(AF2) or PA15(AF2)
-  *           @arg TIM2_ETR_HSI16:     TIM2  ETR connected to HS16 (HSIOUT)
-  *           @arg TIM2_ETR_LSE:       TIM2  ETR connected to LSE
-  *           @arg TIM2_ETR_COMP2_OUT: TIM2  ETR connected to COMP2 output
-  *           @arg TIM2_ETR_COMP1_OUT: TIM2  ETR connected to COMP1 output
-  *
-  *                   field2 can have the following values:
-  *           @arg TIM2_TI4_GPIO :     TIM2  TI4 connected to GPIO (default):
-  *                                    PA3(AF2) or PB11(AF2) or PB1(AF5)
-  *           @arg TIM2_TI4_COMP1_OUT: TIM2  TI4 connected to COMP1 output
-  *           @arg TIM2_TI4_COMP2_OUT: TIM2  TI4 connected to COMP2 output
-  @endif
-  @if STM32L051xx
-  *         For TIM2, the parameter is a combination of 2 fields (field1 | field2):
-  *
-  *                   field1 can have the following values:
-  *           @arg TIM2_ETR_GPIO:      TIM2  ETR connected to GPIO (default):
-  *                                    PA0(AF5) or PA5(AF2) or PA15(AF2) or PE9(AF2)
-  *           @arg TIM2_ETR_HSI48:     TIM2  ETR connected to HSI48
-  *           @arg TIM2_ETR_LSE:       TIM2  ETR connected to LSE
-  *           @arg TIM2_ETR_COMP2_OUT: TIM2  ETR connected to COMP2 output
-  *           @arg TIM2_ETR_COMP1_OUT: TIM2  ETR connected to COMP1 output
-  *
-  *                   field2 can have the following values:
-  *           @arg TIM2_TI4_GPIO:      TIM2  TI4 connected to GPIO1(default):
-  *                                    PA3(AF2) or PB11(AF2) or PE12(AF0)
-  *           @arg TIM2_TI4_COMP1:     TIM2  TI4 connected to COMP1
-  *           @arg TIM2_TI4_COMP2:     TIM2  TI4 connected to COMP2
-  *           @arg TIM2_TI4_GPIO2:     TIM2  TI4 connected to GPIO2 :
-  *                                    PA3(AF2) or PB11(AF2) or PE12(AF0)
-  @endif
-  @if STM32L073xx
-  *
-  *         For TIM3, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):
-  *
-  *                   field1 can have the following values:
-  *           @arg TIM3_ETR_GPIO:      TIM3  ETR connected to GPIO (default):
-  *                                    PE2(AF2) or PD2(AF2) or PE2(AF2)
-  *           @arg TIM3_ETR_HSI:       TIM3 ETR connected to HSI
-  *
-  *                   field2 can have the following values:
-  *           @arg TIM3_TI1_USB_SOF:   TIM3 TI1 connected to USB_SOF (default)
-  *           @arg TIM3_TI1_GPIO:      TIM3 TI1 connected to GPIO :
-  *                                    PE3(AF2) or PA6(AF2) or PC6(AF2) or PB4(AF2)
-  *
-  *                   field3 can have the following values:
-  *           @arg TIM3_TI2_GPIOB5_AF4:TIM3 TI3 connected to P5(AF4)
-  *                                    (refer to note)
-  *           @arg TIM3_TI2_GPIO_DEF:  TIM3 TI3 connected to GPIO (default):
-  *                                    PA7(AF2) or PB5(AF4) or PC7(AF2) or PE7(AF2)
-  *
-  *                   field4 can have the following values:
-  *           @arg TIM3_TI4_GPIO_DEF:  TIM3 TI4 connected to GPIO:
-  *                                    PB1(AF2) or PE6(AF2)
-  *           @arg TIM3_TI4_GPIOC9_AF2:TIM3 TI4 connected to PC9(AF)2
-  @endif
-  @if STM32L073xx
-  *         For TIM21, the parameter is a combination of 3 fields (field1 | field2 | field3):
-  *
-  *                   field1 can have the following values:
-  *           @arg TIM21_ETR_GPIO:     TIM21 ETR connected to GPIO(default) :
-  *                                    PC9(AF0) or PA1(AF5)
-  *           @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output
-  *           @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output
-  *           @arg TIM21_ETR_LSE:      TIM21 ETR connected to LSE
-  *
-  *                   field2 can have the following values:
-  *           @arg TIM21_TI1_MCO:      TIM21 TI1 connected to MCO
-  *           @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt
-  *           @arg TIM21_TI1_HSE_RTC:  TIM21 TI1 connected to HSE_RTC
-  *           @arg TIM21_TI1_MSI:      TIM21 TI1 connected to MSI clock
-  *           @arg TIM21_TI1_LSE:      TIM21 TI1 connected to LSE
-  *           @arg TIM21_TI1_LSI:      TIM21 TI1 connected to LSI
-  *           @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT
-  *           @arg TIM21_TI1_GPIO:     TIM21 TI1 connected to GPIO(default):
-  *                                    PA2(AF0) or PB13(AF6) or PE5(AF0) or PD0(AF0)
-  *
-  *                   field3 can have the following values:
-  *           @arg TIM21_TI2_GPIO:     TIM21 TI2 connected to GPIO(default):
-  *                                    PA3(AF0) or PB14(AF6) or PE6(AF0) or PD7(AF1)
-  *           @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output
-  @endif
-  @if STM32L031xx
-  *         For TIM21, the parameter is a combination of 3 fields (field1 | field2 | field3):
-  *
-  *                   field1 can have the following values:
-  *           @arg TIM21_ETR_GPIO:     TIM21 ETR connected to GPIO(default) :
-  *                                    PA1(AF5)
-  *           @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output
-  *           @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output
-  *           @arg TIM21_ETR_LSE:      TIM21 ETR connected to LSE
-  *
-  *                   field2 can have the following values:
-  *           @arg TIM21_TI1_MCO:      TIM21 TI1 connected to MCO
-  *           @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt
-  *           @arg TIM21_TI1_HSE_RTC:  TIM21 TI1 connected to HSE_RTC
-  *           @arg TIM21_TI1_MSI:      TIM21 TI1 connected to MSI clock
-  *           @arg TIM21_TI1_LSE:      TIM21 TI1 connected to LSE
-  *           @arg TIM21_TI1_LSI:      TIM21 TI1 connected to LSI
-  *           @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT
-  *
-  *                   field3 can have the following values:
-  *           @arg TIM21_TI2_GPIO:     TIM21 TI2 connected to GPIO(default):
-  *                                    PA3(AF0) or PB14(AF6)
-  *           @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output
-  @endif
-  @if STM32L011xx
-  *         For TIM21, the parameter is a combination of 3 fields (field1 | field2 | field3):
-  *
-  *                   field1 can have the following values:
-  *           @arg TIM21_ETR_GPIO:     TIM21 ETR connected to GPIO(default) :
-  *                                    PA1(AF5)
-  *           @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output
-  *           @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output
-  *           @arg TIM21_ETR_LSE:      TIM21 ETR connected to LSE
-  *
-  *                   field2 can have the following values:
-  *           @arg TIM21_TI1_MCO:      TIM21 TI1 connected to MCO
-  *           @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt
-  *           @arg TIM21_TI1_HSE_RTC:  TIM21 TI1 connected to HSE_RTC
-  *           @arg TIM21_TI1_MSI:      TIM21 TI1 connected to MSI clock
-  *           @arg TIM21_TI1_LSE:      TIM21 TI1 connected to LSE
-  *           @arg TIM21_TI1_LSI:      TIM21 TI1 connected to LSI
-  *           @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT
-  *
-  *                   field3 can have the following values:
-  *           @arg TIM21_TI2_GPIO:     TIM21 TI2 connected to GPIO(default):
-  *                                    PA3(AF0) or PB14(AF6)
-  *           @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output
-  @endif
-  @if STM32L051xx
-  *         For TIM21, the parameter is a combination of 3 fields (field1 | field2 | field3):
-  *
-  *                   field1 can have the following values:
-  *           @arg TIM21_ETR_GPIO:     TIM21 ETR connected to GPIO(default) :
-  *                                    PC9(AF0) or PA1(AF5)
-  *           @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output
-  *           @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output
-  *           @arg TIM21_ETR_LSE:      TIM21 ETR connected to LSE
-  *
-  *                   field2 can have the following values:
-  *           @arg TIM21_TI1_MCO:      TIM21 TI1 connected to MCO
-  *           @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt
-  *           @arg TIM21_TI1_HSE_RTC:  TIM21 TI1 connected to HSE_RTC
-  *           @arg TIM21_TI1_MSI:      TIM21 TI1 connected to MSI clock
-  *           @arg TIM21_TI1_LSE:      TIM21 TI1 connected to LSE
-  *           @arg TIM21_TI1_LSI:      TIM21 TI1 connected to LSI
-  *           @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT
-  *           @arg TIM21_TI1_GPIO:     TIM21 TI1 connected to GPIO(default):
-  *                                    PA2(AF0) or PB13(AF6) or PE5(AF0) or PD0(AF0)
-  *
-  *                   field3 can have the following values:
-  *           @arg TIM21_TI2_GPIO:     TIM21 TI2 connected to GPIO(default):
-  *                                    PA3(AF0) or PB14(AF6) or PE6(AF0) or PD7(AF1)
-  *           @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output
-  @endif
-  @if STM32L073xx
-  *
-  *         For TIM22, the parameter can have the following values:
-  *           @arg TIM22_ETR_LSE:      TIM22 ETR connected to LSE
-  *           @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output
-  *           @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output
-  *           @arg TIM22_ETR_GPIO:     TIM22 ETR connected to GPIO(default):
-  *                                    PC8(AF0) or PA4(AF5)
-  *           @arg TIM22_TI1_GPIO:     TIM22 TI1 connected to GPIO(default):
-  *                                    PC6(AF0) or PA6(AF5) or PB4(AF4) or PE0(AF3)
-  *           @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output
-  *           @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output
-  @endif
-  @if STM32L031xx
-  *
-  *         For TIM22, the parameter is a combination of 2 fields (field1 | field2):
-  *
-  *                   field1 can have the following values:
-  *           @arg TIM22_ETR_LSE:      TIM22 ETR connected to LSE
-  *           @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output
-  *           @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output
-  *           @arg TIM22_ETR_GPIO:     TIM22 ETR connected to GPIO(default):
-  *                                    PA4(AF5)
-  *
-  *                   field2 can have the following values:
-  *           @arg TIM22_TI1_GPIO:     TIM22 TI1 connected to GPIO(default):
-  *                                    PC0(AF6) or PA5(AF6) or PB4(AF4)
-  *           @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output
-  *           @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output
-  *
-  @endif
-  @if STM32L051xx
-  *
-  *         For TIM22, the parameter is a combination of 2 fields (field1 | field2):
-  *
-  *                   field1 can have the following values:
-  *           @arg TIM22_ETR_LSE:      TIM22 ETR connected to LSE
-  *           @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output
-  *           @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output
-  *           @arg TIM22_ETR_GPIO:     TIM22 ETR connected to GPIO(default):
-  *                                    PC8(AF0) or PA4(AF5)
-  *
-  *                   field2 can have the following values:
-  *           @arg TIM22_TI1_GPIO:     TIM22 TI1 connected to GPIO(default):
-  *                                    PC6(AF0) or PA6(AF5) or PB4(AF4) or PE0(AF3)
-  *           @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output
-  *           @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output
-  @endif
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
-{
-  __HAL_LOCK(htim);
-
-  /* Check parameters */
-  assert_param(IS_TIM_REMAP(htim->Instance, Remap));
-
-  /* Set the Timer remapping configuration */
-  WRITE_REG(htim->Instance->OR, Remap);
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_timebase_tim_template.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_timebase_tim_template.c
deleted file mode 100644
index dc9122de64..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_timebase_tim_template.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_timebase_tim_template.c
-  * @author  MCD Application Team
-  * @brief   HAL time base based on the hardware TIM Template.
-  *
-  *          This file override the native HAL time base functions (defined as weak)
-  *          the TIM time base:
-  *           + Intializes the TIM peripheral to generate a Period elapsed Event each 1ms
-  *           + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
-  *
- @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    This file must be copied to the application folder and modified as follows:
-    (#) Rename it to 'stm32l0xx_hal_timebase_tim.c'
-    (#) Add this file and the TIM HAL driver files to your project and make sure
-       HAL_TIM_MODULE_ENABLED is defined in stm32l0xx_hal_conf.h
-
-    [..]
-    (@) The application needs to ensure that the time base is always set to 1 millisecond
-       to have correct HAL operation.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup HAL_TimeBase
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_HandleTypeDef        TimHandle;
-/* Private function prototypes -----------------------------------------------*/
-void TIM21_IRQHandler(void);
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  This function configures the TIM21 as a time base source.
-  *         The time source is configured  to have 1ms time base with a dedicated
-  *         Tick interrupt priority.
-  * @note   This function is called  automatically at the beginning of program after
-  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
-  * @param  TickPriority: Tick interrupt priority.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
-  RCC_ClkInitTypeDef    clkconfig;
-  uint32_t              uwTimclock;
-  uint32_t              uwAPB2Prescaler;
-  uint32_t              uwPrescalerValue;
-  uint32_t              pFLatency;
-  HAL_StatusTypeDef     status;
-
-  /* Configure the TIM21 IRQ priority */
-  HAL_NVIC_SetPriority(TIM21_IRQn, TickPriority, 0U);
-
-  /* Enable the TIM21 global Interrupt */
-  HAL_NVIC_EnableIRQ(TIM21_IRQn);
-
-  /* Enable TIM21 clock */
-  __HAL_RCC_TIM21_CLK_ENABLE();
-
-  /* Get clock configuration */
-  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
-
-  /* Get APB2 prescaler */
-  uwAPB2Prescaler = clkconfig.APB2CLKDivider;
-
-  /* Compute TIM21 clock */
-  if (uwAPB2Prescaler == RCC_HCLK_DIV1)
-  {
-    uwTimclock = HAL_RCC_GetPCLK2Freq();
-  }
-  else
-  {
-    uwTimclock = 2U * HAL_RCC_GetPCLK2Freq();
-  }
-
-  /* Compute the prescaler value to have TIM21 counter clock equal to 1MHz */
-  uwPrescalerValue = (uint32_t)((uwTimclock / 1000000U) - 1U);
-
-  /* Initialize TIM21 */
-  TimHandle.Instance = TIM21;
-
-  /* Initialize TIMx peripheral as follow:
-  + Period = [(TIM21CLK/1000) - 1]. to have a (1/1000) s time base.
-  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
-  + ClockDivision = 0
-  + Counter direction = Up
-  */
-  TimHandle.Init.Period = (1000000U / 1000U) - 1U;
-  TimHandle.Init.Prescaler = uwPrescalerValue;
-  TimHandle.Init.ClockDivision = 0;
-  TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
-  status = HAL_TIM_Base_Init(&TimHandle);
-  if (status == HAL_OK)
-  {
-    /* Start the TIM time Base generation in interrupt mode */
-    status = HAL_TIM_Base_Start_IT(&TimHandle);
-    if (status == HAL_OK)
-    {
-      /* Configure the SysTick IRQ priority */
-      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
-      {
-        /* Configure the TIM IRQ priority */
-        HAL_NVIC_SetPriority(TIM21_IRQn, TickPriority, 0U);
-        uwTickPrio = TickPriority;
-      }
-      else
-      {
-        status = HAL_ERROR;
-      }
-    }
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Suspend Tick increment.
-  * @note   Disable the tick increment by disabling TIM21 update interrupt.
-  * @param  None
-  * @retval None
-  */
-void HAL_SuspendTick(void)
-{
-  /* Disable TIM21 update interrupt */
-  __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
-}
-
-/**
-  * @brief  Resume Tick increment.
-  * @note   Enable the tick increment by enabling TIM21 update interrupt.
-  * @param  None
-  * @retval None
-  */
-void HAL_ResumeTick(void)
-{
-  /* Enable TIM21 update interrupt */
-  __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
-}
-
-/**
-  * @brief  Period elapsed callback in non blocking mode
-  * @note   This function is called  when TIM21 interrupt took place, inside
-  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
-  * a global variable "uwTick" used as application time base.
-  * @param  htim : TIM handle
-  * @retval None
-  */
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  HAL_IncTick();
-}
-
-/**
-  * @brief  This function handles TIM interrupt request.
-  * @param  None
-  * @retval None
-  */
-void TIM21_IRQHandler(void)
-{
-  HAL_TIM_IRQHandler(&TimHandle);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tsc.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tsc.c
deleted file mode 100644
index 6e6d43d6ff..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tsc.c
+++ /dev/null
@@ -1,1080 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_tsc.c
-  * @author  MCD Application Team
-  * @brief   This file provides firmware functions to manage the following
-  *          functionalities of the Touch Sensing Controller (TSC) peripheral:
-  *           + Initialization and De-initialization
-  *           + Channel IOs, Shield IOs and Sampling IOs configuration
-  *           + Start and Stop an acquisition
-  *           + Read acquisition result
-  *           + Interrupts and flags management
-  *
-  @verbatim
-================================================================================
-                       ##### TSC specific features #####
-================================================================================
-  [..]
-  (#) Proven and robust surface charge transfer acquisition principle
-
-  (#) Supports up to 3 capacitive sensing channels per group
-
-  (#) Capacitive sensing channels can be acquired in parallel offering a very good
-      response time
-
-  (#) Spread spectrum feature to improve system robustness in noisy environments
-
-  (#) Full hardware management of the charge transfer acquisition sequence
-
-  (#) Programmable charge transfer frequency
-
-  (#) Programmable sampling capacitor I/O pin
-
-  (#) Programmable channel I/O pin
-
-  (#) Programmable max count value to avoid long acquisition when a channel is faulty
-
-  (#) Dedicated end of acquisition and max count error flags with interrupt capability
-
-  (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
-      components
-
-  (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
-
-                          ##### How to use this driver #####
-================================================================================
-  [..]
-    (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.
-
-    (#) GPIO pins configuration
-      (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
-      (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
-           and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
-           using HAL_GPIO_Init() function.
-
-    (#) Interrupts configuration
-      (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority()
-           and HAL_NVIC_EnableIRQ() and function.
-
-    (#) TSC configuration
-      (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
-
- [..]   TSC peripheral alternate functions are mapped on AF3.
-
-  *** Acquisition sequence ***
-  ===================================
-  [..]
-    (+) Discharge all IOs using HAL_TSC_IODischarge() function.
-    (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
-        of the sampling capacitor and electrodes design.
-    (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
-    (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
-        If the synchronized mode is selected, the acquisition will start as soon as the signal
-        is received on the synchro pin.
-    (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
-        HAL_TSC_GetState() function or using WFI instruction for example.
-    (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
-    (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
-
-     *** Callback registration ***
-     =============================================
-
-  [..]
-     The compilation flag USE_HAL_TSC_REGISTER_CALLBACKS when set to 1
-     allows the user to configure dynamically the driver callbacks.
-     Use Functions HAL_TSC_RegisterCallback() to register an interrupt callback.
-
-  [..]
-     Function HAL_TSC_RegisterCallback() allows to register following callbacks:
-       (+) ConvCpltCallback   : callback for conversion complete process.
-       (+) ErrorCallback      : callback for error detection.
-       (+) MspInitCallback    : callback for Msp Init.
-       (+) MspDeInitCallback  : callback for Msp DeInit.
-  [..]
-     This function takes as parameters the HAL peripheral handle, the Callback ID
-     and a pointer to the user callback function.
-
-  [..]
-     Use function HAL_TSC_UnRegisterCallback to reset a callback to the default
-     weak function.
-     HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle,
-     and the Callback ID.
-  [..]
-     This function allows to reset following callbacks:
-       (+) ConvCpltCallback   : callback for conversion complete process.
-       (+) ErrorCallback      : callback for error detection.
-       (+) MspInitCallback    : callback for Msp Init.
-       (+) MspDeInitCallback  : callback for Msp DeInit.
-
-  [..]
-     By default, after the HAL_TSC_Init() and when the state is HAL_TSC_STATE_RESET
-     all callbacks are set to the corresponding weak functions:
-     examples HAL_TSC_ConvCpltCallback(), HAL_TSC_ErrorCallback().
-     Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the HAL_TSC_Init()/ HAL_TSC_DeInit() only when
-     these callbacks are null (not registered beforehand).
-     If MspInit or MspDeInit are not null, the HAL_TSC_Init()/ HAL_TSC_DeInit()
-     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
-  [..]
-     Callbacks can be registered/unregistered in HAL_TSC_STATE_READY state only.
-     Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in HAL_TSC_STATE_READY or HAL_TSC_STATE_RESET state,
-     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-     Then, the user first registers the MspInit/MspDeInit user callbacks
-     using HAL_TSC_RegisterCallback() before calling HAL_TSC_DeInit()
-     or HAL_TSC_Init() function.
-
-  [..]
-     When the compilation flag USE_HAL_TSC_REGISTER_CALLBACKS is set to 0 or
-     not defined, the callback registration feature is not available and all callbacks
-     are set to the corresponding weak functions.
-
-  @endverbatim
-  ******************************************************************************
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-#if defined(TSC)
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TSC TSC
-  * @brief HAL TSC module driver
-  * @{
-  */
-
-#ifdef HAL_TSC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint32_t TSC_extract_groups(uint32_t iomask);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup TSC_Exported_Functions TSC Exported Functions
-  * @{
-  */
-
-/** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the TSC.
-      (+) De-initialize the TSC.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the TSC peripheral according to the specified parameters
-  *         in the TSC_InitTypeDef structure and initialize the associated handle.
-  * @param  htsc TSC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc)
-{
-  /* Check TSC handle allocation */
-  if (htsc == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-  assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength));
-  assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength));
-  assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum));
-  assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
-  assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
-  assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
-  assert_param(IS_TSC_PG_PRESC_VS_CTPL(htsc->Init.PulseGeneratorPrescaler, htsc->Init.CTPulseLowLength));
-  assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
-  assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
-  assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
-  assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
-  assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
-  assert_param(IS_TSC_GROUP(htsc->Init.ChannelIOs));
-  assert_param(IS_TSC_GROUP(htsc->Init.ShieldIOs));
-  assert_param(IS_TSC_GROUP(htsc->Init.SamplingIOs));
-
-  if (htsc->State == HAL_TSC_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htsc->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-    /* Init the TSC Callback settings */
-    htsc->ConvCpltCallback  = HAL_TSC_ConvCpltCallback; /* Legacy weak ConvCpltCallback     */
-    htsc->ErrorCallback     = HAL_TSC_ErrorCallback;    /* Legacy weak ErrorCallback        */
-
-    if (htsc->MspInitCallback == NULL)
-    {
-      htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit  */
-    }
-
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
-    htsc->MspInitCallback(htsc);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
-    HAL_TSC_MspInit(htsc);
-#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
-  }
-
-  /* Initialize the TSC state */
-  htsc->State = HAL_TSC_STATE_BUSY;
-
-  /*--------------------------------------------------------------------------*/
-  /* Set TSC parameters */
-
-  /* Enable TSC */
-  htsc->Instance->CR = TSC_CR_TSCE;
-
-  /* Set all functions */
-  htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
-                         htsc->Init.CTPulseLowLength |
-                         (htsc->Init.SpreadSpectrumDeviation << TSC_CR_SSD_Pos) |
-                         htsc->Init.SpreadSpectrumPrescaler |
-                         htsc->Init.PulseGeneratorPrescaler |
-                         htsc->Init.MaxCountValue |
-                         htsc->Init.SynchroPinPolarity |
-                         htsc->Init.AcquisitionMode);
-
-  /* Spread spectrum */
-  if (htsc->Init.SpreadSpectrum == ENABLE)
-  {
-    htsc->Instance->CR |= TSC_CR_SSE;
-  }
-
-  /* Disable Schmitt trigger hysteresis on all used TSC IOs */
-  htsc->Instance->IOHCR = (~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
-
-  /* Set channel and shield IOs */
-  htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
-
-  /* Set sampling IOs */
-  htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
-
-  /* Set the groups to be acquired */
-  htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
-
-  /* Disable interrupts */
-  htsc->Instance->IER &= (~(TSC_IT_EOA | TSC_IT_MCE));
-
-  /* Clear flags */
-  htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
-
-  /*--------------------------------------------------------------------------*/
-
-  /* Initialize the TSC state */
-  htsc->State = HAL_TSC_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deinitialize the TSC peripheral registers to their default reset values.
-  * @param  htsc TSC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc)
-{
-  /* Check TSC handle allocation */
-  if (htsc == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
-  /* Change TSC state */
-  htsc->State = HAL_TSC_STATE_BUSY;
-
-#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-  if (htsc->MspDeInitCallback == NULL)
-  {
-    htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit  */
-  }
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  htsc->MspDeInitCallback(htsc);
-#else
-  /* DeInit the low level hardware */
-  HAL_TSC_MspDeInit(htsc);
-#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
-
-  /* Change TSC state */
-  htsc->State = HAL_TSC_STATE_RESET;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(htsc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the TSC MSP.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @retval None
-  */
-__weak void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htsc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TSC_MspInit could be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  DeInitialize the TSC MSP.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @retval None
-  */
-__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htsc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TSC_MspDeInit could be implemented in the user file.
-   */
-}
-
-#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User TSC Callback
-  *         To be used instead of the weak predefined callback
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *                the configuration information for the specified TSC.
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID
-  *          @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID
-  *          @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID,
-                                           pTSC_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(htsc);
-
-  if (HAL_TSC_STATE_READY == htsc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_TSC_CONV_COMPLETE_CB_ID :
-        htsc->ConvCpltCallback = pCallback;
-        break;
-
-      case HAL_TSC_ERROR_CB_ID :
-        htsc->ErrorCallback = pCallback;
-        break;
-
-      case HAL_TSC_MSPINIT_CB_ID :
-        htsc->MspInitCallback = pCallback;
-        break;
-
-      case HAL_TSC_MSPDEINIT_CB_ID :
-        htsc->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_TSC_STATE_RESET == htsc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_TSC_MSPINIT_CB_ID :
-        htsc->MspInitCallback = pCallback;
-        break;
-
-      case HAL_TSC_MSPDEINIT_CB_ID :
-        htsc->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(htsc);
-  return status;
-}
-
-/**
-  * @brief  Unregister an TSC Callback
-  *         TSC callback is redirected to the weak predefined callback
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *                the configuration information for the specified TSC.
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID
-  *          @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID
-  *          @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(htsc);
-
-  if (HAL_TSC_STATE_READY == htsc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_TSC_CONV_COMPLETE_CB_ID :
-        htsc->ConvCpltCallback = HAL_TSC_ConvCpltCallback;       /* Legacy weak ConvCpltCallback      */
-        break;
-
-      case HAL_TSC_ERROR_CB_ID :
-        htsc->ErrorCallback = HAL_TSC_ErrorCallback;               /* Legacy weak ErrorCallback        */
-        break;
-
-      case HAL_TSC_MSPINIT_CB_ID :
-        htsc->MspInitCallback = HAL_TSC_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_TSC_MSPDEINIT_CB_ID :
-        htsc->MspDeInitCallback = HAL_TSC_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_TSC_STATE_RESET == htsc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_TSC_MSPINIT_CB_ID :
-        htsc->MspInitCallback = HAL_TSC_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_TSC_MSPDEINIT_CB_ID :
-        htsc->MspDeInitCallback = HAL_TSC_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(htsc);
-  return status;
-}
-
-#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions
-  *  @brief    Input and Output operation functions
-  *
-@verbatim
- ===============================================================================
-             ##### IO Operation functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start acquisition in polling mode.
-      (+) Start acquisition in interrupt mode.
-      (+) Stop conversion in polling mode.
-      (+) Stop conversion in interrupt mode.
-      (+) Poll for acquisition completed.
-      (+) Get group acquisition status.
-      (+) Get group acquisition value.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the acquisition.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc)
-{
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(htsc);
-
-  /* Change TSC state */
-  htsc->State = HAL_TSC_STATE_BUSY;
-
-  /* Clear interrupts */
-  __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
-
-  /* Clear flags */
-  __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
-
-  /* Set touch sensing IOs not acquired to the specified IODefaultMode */
-  if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
-  {
-    __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
-  }
-  else
-  {
-    __HAL_TSC_SET_IODEF_INFLOAT(htsc);
-  }
-
-  /* Launch the acquisition */
-  __HAL_TSC_START_ACQ(htsc);
-
-  /* Process unlocked */
-  __HAL_UNLOCK(htsc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the acquisition in interrupt mode.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc)
-{
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-  assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
-
-  /* Process locked */
-  __HAL_LOCK(htsc);
-
-  /* Change TSC state */
-  htsc->State = HAL_TSC_STATE_BUSY;
-
-  /* Enable end of acquisition interrupt */
-  __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
-
-  /* Enable max count error interrupt (optional) */
-  if (htsc->Init.MaxCountInterrupt == ENABLE)
-  {
-    __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE);
-  }
-  else
-  {
-    __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE);
-  }
-
-  /* Clear flags */
-  __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
-
-  /* Set touch sensing IOs not acquired to the specified IODefaultMode */
-  if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
-  {
-    __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
-  }
-  else
-  {
-    __HAL_TSC_SET_IODEF_INFLOAT(htsc);
-  }
-
-  /* Launch the acquisition */
-  __HAL_TSC_START_ACQ(htsc);
-
-  /* Process unlocked */
-  __HAL_UNLOCK(htsc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the acquisition previously launched in polling mode.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc)
-{
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(htsc);
-
-  /* Stop the acquisition */
-  __HAL_TSC_STOP_ACQ(htsc);
-
-  /* Set touch sensing IOs in low power mode (output push-pull) */
-  __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
-
-  /* Clear flags */
-  __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
-
-  /* Change TSC state */
-  htsc->State = HAL_TSC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(htsc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the acquisition previously launched in interrupt mode.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc)
-{
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(htsc);
-
-  /* Stop the acquisition */
-  __HAL_TSC_STOP_ACQ(htsc);
-
-  /* Set touch sensing IOs in low power mode (output push-pull) */
-  __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
-
-  /* Disable interrupts */
-  __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
-
-  /* Clear flags */
-  __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
-
-  /* Change TSC state */
-  htsc->State = HAL_TSC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(htsc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start acquisition and wait until completion.
-  * @note   There is no need of a timeout parameter as the max count error is already
-  *         managed by the TSC peripheral.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @retval HAL state
-  */
-HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc)
-{
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(htsc);
-
-  /* Check end of acquisition */
-  while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
-  {
-    /* The timeout (max count error) is managed by the TSC peripheral itself. */
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(htsc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the acquisition status for a group.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @param  gx_index Index of the group
-  * @retval Group status
-  */
-TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index)
-{
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-  assert_param(IS_TSC_GROUP_INDEX(gx_index));
-
-  /* Return the group status */
-  return (__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
-}
-
-/**
-  * @brief  Get the acquisition measure for a group.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @param  gx_index Index of the group
-  * @retval Acquisition measure
-  */
-uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index)
-{
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-  assert_param(IS_TSC_GROUP_INDEX(gx_index));
-
-  /* Return the group acquisition counter */
-  return htsc->Instance->IOGXCR[gx_index];
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief    Peripheral Control functions
-  *
-@verbatim
- ===============================================================================
-             ##### Peripheral Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure TSC IOs
-      (+) Discharge TSC IOs
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure TSC IOs.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @param  config Pointer to the configuration structure.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
-{
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-  assert_param(IS_TSC_GROUP(config->ChannelIOs));
-  assert_param(IS_TSC_GROUP(config->ShieldIOs));
-  assert_param(IS_TSC_GROUP(config->SamplingIOs));
-
-  /* Process locked */
-  __HAL_LOCK(htsc);
-
-  /* Stop acquisition */
-  __HAL_TSC_STOP_ACQ(htsc);
-
-  /* Disable Schmitt trigger hysteresis on all used TSC IOs */
-  htsc->Instance->IOHCR = (~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
-
-  /* Set channel and shield IOs */
-  htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
-
-  /* Set sampling IOs */
-  htsc->Instance->IOSCR = config->SamplingIOs;
-
-  /* Set groups to be acquired */
-  htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
-
-  /* Process unlocked */
-  __HAL_UNLOCK(htsc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Discharge TSC IOs.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @param  choice This parameter can be set to ENABLE or DISABLE.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice)
-{
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(htsc);
-
-  if (choice == ENABLE)
-  {
-    __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
-  }
-  else
-  {
-    __HAL_TSC_SET_IODEF_INFLOAT(htsc);
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(htsc);
-
-  /* Return the group acquisition counter */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
-  *  @brief   Peripheral State and Errors functions
-  *
-@verbatim
- ===============================================================================
-            ##### State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Get TSC state.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the TSC handle state.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @retval HAL state
-  */
-HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc)
-{
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
-  if (htsc->State == HAL_TSC_STATE_BUSY)
-  {
-    /* Check end of acquisition flag */
-    if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
-    {
-      /* Check max count error flag */
-      if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
-      {
-        /* Change TSC state */
-        htsc->State = HAL_TSC_STATE_ERROR;
-      }
-      else
-      {
-        /* Change TSC state */
-        htsc->State = HAL_TSC_STATE_READY;
-      }
-    }
-  }
-
-  /* Return TSC state */
-  return htsc->State;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
-  * @{
-  */
-
-/**
-  * @brief  Handle TSC interrupt request.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @retval None
-  */
-void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc)
-{
-  /* Check the parameters */
-  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
-  /* Check if the end of acquisition occurred */
-  if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
-  {
-    /* Clear EOA flag */
-    __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
-  }
-
-  /* Check if max count error occurred */
-  if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
-  {
-    /* Clear MCE flag */
-    __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
-    /* Change TSC state */
-    htsc->State = HAL_TSC_STATE_ERROR;
-#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-    htsc->ErrorCallback(htsc);
-#else
-    /* Conversion completed callback */
-    HAL_TSC_ErrorCallback(htsc);
-#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* Change TSC state */
-    htsc->State = HAL_TSC_STATE_READY;
-#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-    htsc->ConvCpltCallback(htsc);
-#else
-    /* Conversion completed callback */
-    HAL_TSC_ConvCpltCallback(htsc);
-#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  Acquisition completed callback in non-blocking mode.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @retval None
-  */
-__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htsc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TSC_ConvCpltCallback could be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Error callback in non-blocking mode.
-  * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
-  *         the configuration information for the specified TSC.
-  * @retval None
-  */
-__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htsc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TSC_ErrorCallback could be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup TSC_Private_Functions TSC Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Utility function used to set the acquired groups mask.
-  * @param  iomask Channels IOs mask
-  * @retval Acquired groups mask
-  */
-static uint32_t TSC_extract_groups(uint32_t iomask)
-{
-  uint32_t groups = 0UL;
-  uint32_t idx;
-
-  for (idx = 0UL; idx < (uint32_t)TSC_NB_OF_GROUPS; idx++)
-  {
-    if ((iomask & (0x0FUL << (idx * 4UL))) != 0UL)
-    {
-      groups |= (1UL << idx);
-    }
-  }
-
-  return groups;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* TSC */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c
deleted file mode 100644
index ad1afc4ca3..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c
+++ /dev/null
@@ -1,4161 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_uart.c
-  * @author  MCD Application Team
-  * @brief   UART HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *
-  *
-  @verbatim
- ===============================================================================
-                        ##### How to use this driver #####
- ===============================================================================
-  [..]
-    The UART HAL driver can be used as follows:
-
-    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
-    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
-        (++) Enable the USARTx interface clock.
-        (++) UART pins configuration:
-            (+++) Enable the clock for the UART GPIOs.
-            (+++) Configure these UART pins as alternate function pull-up.
-        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
-             and HAL_UART_Receive_IT() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-        (++) UART interrupts handling:
-              -@@-  The specific UART interrupts (Transmission complete interrupt,
-                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
-                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
-                inside the transmit and receive processes.
-        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
-             and HAL_UART_Receive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx channel.
-            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete
-                  interrupt on the DMA Tx/Rx channel.
-
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
-        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
-
-    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
-        in the huart handle AdvancedInit structure.
-
-    (#) For the UART asynchronous mode, initialize the UART registers by calling
-        the HAL_UART_Init() API.
-
-    (#) For the UART Half duplex mode, initialize the UART registers by calling
-        the HAL_HalfDuplex_Init() API.
-
-    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
-        by calling the HAL_LIN_Init() API.
-
-    (#) For the UART Multiprocessor mode, initialize the UART registers
-        by calling the HAL_MultiProcessor_Init() API.
-
-    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
-        by calling the HAL_RS485Ex_Init() API.
-
-    [..]
-    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
-        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
-        calling the customized HAL_UART_MspInit() API.
-
-    ##### Callback registration #####
-    ==================================
-
-    [..]
-    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
-    allows the user to configure dynamically the driver callbacks.
-
-    [..]
-    Use Function HAL_UART_RegisterCallback() to register a user callback.
-    Function HAL_UART_RegisterCallback() allows to register following callbacks:
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-    (+) WakeupCallback            : Wakeup Callback.
-    (+) MspInitCallback           : UART MspInit.
-    (+) MspDeInitCallback         : UART MspDeInit.
-    This function takes as parameters the HAL peripheral handle, the Callback ID
-    and a pointer to the user callback function.
-
-    [..]
-    Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-    and the Callback ID.
-    This function allows to reset following callbacks:
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-    (+) WakeupCallback            : Wakeup Callback.
-    (+) MspInitCallback           : UART MspInit.
-    (+) MspDeInitCallback         : UART MspDeInit.
-
-    [..]
-    For specific callback RxEventCallback, use dedicated registration/reset functions:
-    respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
-
-    [..]
-    By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
-    Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
-    and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
-    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
-
-    [..]
-    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
-    Exception done MspInit/MspDeInit that can be registered/unregistered
-    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
-    MspInit/DeInit callbacks can be used during the Init/DeInit.
-    In that case first register the MspInit/MspDeInit user callbacks
-    using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
-    or HAL_UART_Init() function.
-
-    [..]
-    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
-    not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
-
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup UART UART
-  * @brief HAL UART module driver
-  * @{
-  */
-
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup UART_Private_Constants UART Private Constants
-  * @{
-  */
-#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
-                                      USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
-
-#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE |\
-                            USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
-
-#define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */
-#define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */
-
-#define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */
-#define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions
-  * @{
-  */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma);
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
-static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
-static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
-static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/* Exported Constants --------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup UART_Exported_Functions UART Exported Functions
-  * @{
-  */
-
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
-    in asynchronous mode.
-      (+) For the asynchronous mode the parameters below can be configured:
-        (++) Baud Rate
-        (++) Word Length
-        (++) Stop Bit
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written
-             in the data register is transmitted but is changed by the parity bit.
-        (++) Hardware flow control
-        (++) Receiver/transmitter modes
-        (++) Over Sampling Method
-        (++) One-Bit Sampling Method
-      (+) For the asynchronous mode, the following advanced features can be configured as well:
-        (++) TX and/or RX pin level inversion
-        (++) data logical level inversion
-        (++) RX and TX pins swap
-        (++) RX overrun detection disabling
-        (++) DMA disabling on RX error
-        (++) MSB first on communication line
-        (++) auto Baud rate detection
-    [..]
-    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
-    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
-    and UART multiprocessor mode configuration procedures (details for the procedures
-    are available in reference manual).
-
-@endverbatim
-
-  Depending on the frame length defined by the M1 and M0 bits (7-bit,
-  8-bit or 9-bit), the possible UART formats are listed in the
-  following table.
-
-  Table 1. UART frame format.
-    +-----------------------------------------------------------------------+
-    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
-    +-----------------------------------------------------------------------+
-
-  * @{
-  */
-
-/**
-  * @brief Initialize the UART mode according to the specified
-  *        parameters in the UART_InitTypeDef and initialize the associated handle.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
-  {
-    /* Check the parameters */
-    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
-  }
-  else
-  {
-    /* Check the parameters */
-    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
-  }
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* In asynchronous mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @brief Initialize the half-duplex mode according to the specified
-  *        parameters in the UART_InitTypeDef and creates the associated handle.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check UART instance */
-  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* In half-duplex mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
-
-  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
-  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
-
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-
-/**
-  * @brief Initialize the LIN mode according to the specified
-  *        parameters in the UART_InitTypeDef and creates the associated handle.
-  * @param huart             UART handle.
-  * @param BreakDetectLength Specifies the LIN break detection length.
-  *        This parameter can be one of the following values:
-  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
-  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the LIN UART instance */
-  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
-  /* Check the Break detection length parameter */
-  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-
-  /* LIN mode limited to 16-bit oversampling only */
-  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
-  {
-    return HAL_ERROR;
-  }
-  /* LIN mode limited to 8-bit data length */
-  if (huart->Init.WordLength != UART_WORDLENGTH_8B)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* In LIN mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
-
-  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
-  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
-
-  /* Set the USART LIN Break detection length. */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
-
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-
-/**
-  * @brief Initialize the multiprocessor mode according to the specified
-  *        parameters in the UART_InitTypeDef and initialize the associated handle.
-  * @param huart        UART handle.
-  * @param Address      UART node address (4-, 6-, 7- or 8-bit long).
-  * @param WakeUpMethod Specifies the UART wakeup method.
-  *        This parameter can be one of the following values:
-  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
-  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
-  * @note  If the user resorts to idle line detection wake up, the Address parameter
-  *        is useless and ignored by the initialization function.
-  * @note  If the user resorts to address mark wake up, the address length detection
-  *        is configured by default to 4 bits only. For the UART to be able to
-  *        manage 6-, 7- or 8-bit long addresses detection, the API
-  *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
-  *        HAL_MultiProcessor_Init().
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the wake up method parameter */
-  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* In multiprocessor mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
-  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
-  {
-    /* If address mark wake up method is chosen, set the USART address node */
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
-  }
-
-  /* Set the wake up method by setting the WAKE bit in the CR1 register */
-  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
-
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-
-/**
-  * @brief DeInitialize the UART peripheral.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  __HAL_UART_DISABLE(huart);
-
-  huart->Instance->CR1 = 0x0U;
-  huart->Instance->CR2 = 0x0U;
-  huart->Instance->CR3 = 0x0U;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  if (huart->MspDeInitCallback == NULL)
-  {
-    huart->MspDeInitCallback = HAL_UART_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  huart->MspDeInitCallback(huart);
-#else
-  /* DeInit the low level hardware */
-  HAL_UART_MspDeInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState = HAL_UART_STATE_RESET;
-  huart->RxState = HAL_UART_STATE_RESET;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Initialize the UART MSP.
-  * @param huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_MspInit can be implemented in the user file
-   */
-}
-
-/**
-  * @brief DeInitialize the UART MSP.
-  * @param huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_MspDeInit can be implemented in the user file
-   */
-}
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User UART Callback
-  *         To be used instead of the weak predefined callback
-  * @param  huart uart handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
-  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
-                                            pUART_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
-        huart->TxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_TX_COMPLETE_CB_ID :
-        huart->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
-        huart->RxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_RX_COMPLETE_CB_ID :
-        huart->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_ERROR_CB_ID :
-        huart->ErrorCallback = pCallback;
-        break;
-
-      case HAL_UART_ABORT_COMPLETE_CB_ID :
-        huart->AbortCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        huart->AbortTransmitCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
-        huart->AbortReceiveCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_WAKEUP_CB_ID :
-        huart->WakeupCallback = pCallback;
-        break;
-
-
-      case HAL_UART_MSPINIT_CB_ID :
-        huart->MspInitCallback = pCallback;
-        break;
-
-      case HAL_UART_MSPDEINIT_CB_ID :
-        huart->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_UART_MSPINIT_CB_ID :
-        huart->MspInitCallback = pCallback;
-        break;
-
-      case HAL_UART_MSPDEINIT_CB_ID :
-        huart->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    status =  HAL_ERROR;
-  }
-
-  __HAL_UNLOCK(huart);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister an UART Callback
-  *         UART callaback is redirected to the weak predefined callback
-  * @param  huart uart handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
-  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  __HAL_LOCK(huart);
-
-  if (HAL_UART_STATE_READY == huart->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
-        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback    */
-        break;
-
-      case HAL_UART_TX_COMPLETE_CB_ID :
-        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback         */
-        break;
-
-      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
-        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback     */
-        break;
-
-      case HAL_UART_RX_COMPLETE_CB_ID :
-        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback         */
-        break;
-
-      case HAL_UART_ERROR_CB_ID :
-        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback          */
-        break;
-
-      case HAL_UART_ABORT_COMPLETE_CB_ID :
-        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback      */
-        break;
-
-      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
-                                                                                  AbortTransmitCpltCallback          */
-        break;
-
-      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
-        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak
-                                                                                  AbortReceiveCpltCallback           */
-        break;
-
-      case HAL_UART_WAKEUP_CB_ID :
-        huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback         */
-        break;
-
-      case HAL_UART_MSPINIT_CB_ID :
-        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback        */
-        break;
-
-      case HAL_UART_MSPDEINIT_CB_ID :
-        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback      */
-        break;
-
-      default :
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_UART_STATE_RESET == huart->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_UART_MSPINIT_CB_ID :
-        huart->MspInitCallback = HAL_UART_MspInit;
-        break;
-
-      case HAL_UART_MSPDEINIT_CB_ID :
-        huart->MspDeInitCallback = HAL_UART_MspDeInit;
-        break;
-
-      default :
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    status =  HAL_ERROR;
-  }
-
-  __HAL_UNLOCK(huart);
-
-  return status;
-}
-
-/**
-  * @brief  Register a User UART Rx Event Callback
-  *         To be used instead of the weak predefined callback
-  * @param  huart     Uart handle
-  * @param  pCallback Pointer to the Rx Event Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    huart->RxEventCallback = pCallback;
-  }
-  else
-  {
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(huart);
-
-  return status;
-}
-
-/**
-  * @brief  UnRegister the UART Rx Event Callback
-  *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
-  * @param  huart     Uart handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
-  }
-  else
-  {
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(huart);
-  return status;
-}
-
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions
-  * @brief UART Transmit/Receive functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    This subsection provides a set of functions allowing to manage the UART asynchronous
-    and Half duplex data transfers.
-
-    (#) There are two mode of transfer:
-       (+) Blocking mode: The communication is performed in polling mode.
-           The HAL status of all data processing is returned by the same function
-           after finishing transfer.
-       (+) Non-Blocking mode: The communication is performed using Interrupts
-           or DMA, These API's return the HAL status.
-           The end of the data processing will be indicated through the
-           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
-           using DMA mode.
-           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
-           will be executed respectively at the end of the transmit or Receive process
-           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
-
-    (#) Blocking mode API's are :
-        (+) HAL_UART_Transmit()
-        (+) HAL_UART_Receive()
-
-    (#) Non-Blocking mode API's with Interrupt are :
-        (+) HAL_UART_Transmit_IT()
-        (+) HAL_UART_Receive_IT()
-        (+) HAL_UART_IRQHandler()
-
-    (#) Non-Blocking mode API's with DMA are :
-        (+) HAL_UART_Transmit_DMA()
-        (+) HAL_UART_Receive_DMA()
-        (+) HAL_UART_DMAPause()
-        (+) HAL_UART_DMAResume()
-        (+) HAL_UART_DMAStop()
-
-    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
-        (+) HAL_UART_TxHalfCpltCallback()
-        (+) HAL_UART_TxCpltCallback()
-        (+) HAL_UART_RxHalfCpltCallback()
-        (+) HAL_UART_RxCpltCallback()
-        (+) HAL_UART_ErrorCallback()
-
-    (#) Non-Blocking mode transfers could be aborted using Abort API's :
-        (+) HAL_UART_Abort()
-        (+) HAL_UART_AbortTransmit()
-        (+) HAL_UART_AbortReceive()
-        (+) HAL_UART_Abort_IT()
-        (+) HAL_UART_AbortTransmit_IT()
-        (+) HAL_UART_AbortReceive_IT()
-
-    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
-        (+) HAL_UART_AbortCpltCallback()
-        (+) HAL_UART_AbortTransmitCpltCallback()
-        (+) HAL_UART_AbortReceiveCpltCallback()
-
-    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
-        reception services:
-        (+) HAL_UARTEx_RxEventCallback()
-
-    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
-        Errors are handled as follows :
-       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
-           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
-           in Interrupt mode reception .
-           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
-           to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
-           Transfer is kept ongoing on UART side.
-           If user wants to abort it, Abort services should be called by user.
-       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
-           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
-           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
-           user callback is executed.
-
-    -@- In the Half duplex communication, it is forbidden to run the transmit
-        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Send an amount of data in blocking mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pData.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
-  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required
-  *         to ensure proper alignment for pData.
-  * @param huart   UART handle.
-  * @param pData   Pointer to data buffer (u8 or u16 data elements).
-  * @param Size    Amount of data elements (u8 or u16) to be sent.
-  * @param Timeout Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-  uint32_t tickstart;
-
-  /* Check that a Tx process is not already ongoing */
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be filled into TDR will be
-       handled through a u16 cast. */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    huart->TxXferSize  = Size;
-    huart->TxXferCount = Size;
-
-    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) pData;
-    }
-    else
-    {
-      pdata8bits  = pData;
-      pdata16bits = NULL;
-    }
-
-    __HAL_UNLOCK(huart);
-
-    while (huart->TxXferCount > 0U)
-    {
-      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if (pdata8bits == NULL)
-      {
-        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
-        pdata16bits++;
-      }
-      else
-      {
-        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
-        pdata8bits++;
-      }
-      huart->TxXferCount--;
-    }
-
-    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* At end of Tx process, restore huart->gState to Ready */
-    huart->gState = HAL_UART_STATE_READY;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pData.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer for storing data to be received, should be aligned on a half word frontier
-  *         (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required
-  *         to ensure proper alignment for pData.
-  * @param huart   UART handle.
-  * @param pData   Pointer to data buffer (u8 or u16 data elements).
-  * @param Size    Amount of data elements (u8 or u16) to be received.
-  * @param Timeout Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-  uint16_t uhMask;
-  uint32_t tickstart;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be received from RDR will be
-       handled through a u16 cast. */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->RxState = HAL_UART_STATE_BUSY_RX;
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    huart->RxXferSize  = Size;
-    huart->RxXferCount = Size;
-
-    /* Computation of UART mask to apply to RDR register */
-    UART_MASK_COMPUTATION(huart);
-    uhMask = huart->Mask;
-
-    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) pData;
-    }
-    else
-    {
-      pdata8bits  = pData;
-      pdata16bits = NULL;
-    }
-
-    __HAL_UNLOCK(huart);
-
-    /* as long as data have to be received */
-    while (huart->RxXferCount > 0U)
-    {
-      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if (pdata8bits == NULL)
-      {
-        *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
-        pdata16bits++;
-      }
-      else
-      {
-        *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
-        pdata8bits++;
-      }
-      huart->RxXferCount--;
-    }
-
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in interrupt mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pData.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
-  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required
-  *         to ensure proper alignment for pData.
-  * @param huart UART handle.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size  Amount of data elements (u8 or u16) to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Tx process is not already ongoing */
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be filled into TDR will be
-       handled through a u16 cast. */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    __HAL_LOCK(huart);
-
-    huart->pTxBuffPtr  = pData;
-    huart->TxXferSize  = Size;
-    huart->TxXferCount = Size;
-    huart->TxISR       = NULL;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Set the Tx ISR function pointer according to the data word length */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      huart->TxISR = UART_TxISR_16BIT;
-    }
-    else
-    {
-      huart->TxISR = UART_TxISR_8BIT;
-    }
-
-    __HAL_UNLOCK(huart);
-
-    /* Enable the Transmit Data Register Empty interrupt */
-    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in interrupt mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pData.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer for storing data to be received, should be aligned on a half word frontier
-  *         (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required
-  *         to ensure proper alignment for pData.
-  * @param huart UART handle.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size  Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be received from RDR will be
-       handled through a u16 cast. */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    __HAL_LOCK(huart);
-
-    /* Set Reception type to Standard reception */
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    if (!(IS_LPUART_INSTANCE(huart->Instance)))
-    {
-      /* Check that USART RTOEN bit is set */
-      if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
-      {
-        /* Enable the UART Receiver Timeout Interrupt */
-        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
-      }
-    }
-
-    return (UART_Start_Receive_IT(huart, pData, Size));
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in DMA mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pData.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
-  *         (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required
-  *         to ensure proper alignment for pData.
-  * @param huart UART handle.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size  Amount of data elements (u8 or u16) to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Tx process is not already ongoing */
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data copy into TDR will be
-       handled by DMA from a u16 frontier. */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    __HAL_LOCK(huart);
-
-    huart->pTxBuffPtr  = pData;
-    huart->TxXferSize  = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    if (huart->hdmatx != NULL)
-    {
-      /* Set the UART DMA transfer complete callback */
-      huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-
-      /* Set the UART DMA Half transfer complete callback */
-      huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-
-      /* Set the DMA error callback */
-      huart->hdmatx->XferErrorCallback = UART_DMAError;
-
-      /* Set the DMA abort callback */
-      huart->hdmatx->XferAbortCallback = NULL;
-
-      /* Enable the UART transmit DMA channel */
-      if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
-      {
-        /* Set error code to DMA */
-        huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-        __HAL_UNLOCK(huart);
-
-        /* Restore huart->gState to ready */
-        huart->gState = HAL_UART_STATE_READY;
-
-        return HAL_ERROR;
-      }
-    }
-    /* Clear the TC flag in the ICR register */
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
-
-    __HAL_UNLOCK(huart);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-    in the UART CR3 register */
-    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in DMA mode.
-  * @note   When the UART parity is enabled (PCE = 1), the received data contain
-  *         the parity bit (MSB position).
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pData.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer for storing data to be received, should be aligned on a half word frontier
-  *         (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required
-  *         to ensure proper alignment for pData.
-  * @param huart UART handle.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size  Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data copy from RDR will be
-       handled by DMA from a u16 frontier. */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    __HAL_LOCK(huart);
-
-    /* Set Reception type to Standard reception */
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    if (!(IS_LPUART_INSTANCE(huart->Instance)))
-    {
-      /* Check that USART RTOEN bit is set */
-      if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
-      {
-        /* Enable the UART Receiver Timeout Interrupt */
-        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
-      }
-    }
-
-    return (UART_Start_Receive_DMA(huart, pData, Size));
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pause the DMA Transfer.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
-{
-  const HAL_UART_StateTypeDef gstate = huart->gState;
-  const HAL_UART_StateTypeDef rxstate = huart->RxState;
-
-  __HAL_LOCK(huart);
-
-  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
-      (gstate == HAL_UART_STATE_BUSY_TX))
-  {
-    /* Disable the UART DMA Tx request */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-  }
-  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
-      (rxstate == HAL_UART_STATE_BUSY_RX))
-  {
-    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the UART DMA Rx request */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-  }
-
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Resume the DMA Transfer.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
-{
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)
-  {
-    /* Enable the UART DMA Tx request */
-    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-  }
-  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
-  {
-    /* Clear the Overrun flag before resuming the Rx transfer */
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
-
-    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the UART DMA Rx request */
-    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-  }
-
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stop the DMA Transfer.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
-{
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
-     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
-     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
-     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
-     the stream and the corresponding call back is executed. */
-
-  const HAL_UART_StateTypeDef gstate = huart->gState;
-  const HAL_UART_StateTypeDef rxstate = huart->RxState;
-
-  /* Stop UART DMA Tx request if ongoing */
-  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
-      (gstate == HAL_UART_STATE_BUSY_TX))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx channel */
-    if (huart->hdmatx != NULL)
-    {
-      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    UART_EndTxTransfer(huart);
-  }
-
-  /* Stop UART DMA Rx request if ongoing */
-  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
-      (rxstate == HAL_UART_STATE_BUSY_RX))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx channel */
-    if (huart->hdmarx != NULL)
-    {
-      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    UART_EndRxTransfer(huart);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfers (blocking mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Tx and Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
-  }
-
-  /* Disable the UART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if (huart->hdmatx != NULL)
-    {
-      /* Set the UART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      huart->hdmatx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Disable the UART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if (huart->hdmarx != NULL)
-    {
-      /* Set the UART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      huart->hdmarx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Tx and Rx transfer counters */
-  huart->TxXferCount = 0U;
-  huart->RxXferCount = 0U;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
-
-  /* Discard the received data */
-  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
-  /* Restore huart->gState and huart->RxState to Ready */
-  huart->gState  = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (blocking mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Disable the UART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if (huart->hdmatx != NULL)
-    {
-      /* Set the UART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      huart->hdmatx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Tx transfer counter */
-  huart->TxXferCount = 0U;
-
-
-  /* Restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (blocking mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
-  }
-
-  /* Disable the UART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if (huart->hdmarx != NULL)
-    {
-      /* Set the UART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      huart->hdmarx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Rx transfer counter */
-  huart->RxXferCount = 0U;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
-  /* Discard the received data */
-  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
-  /* Restore huart->RxState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfers (Interrupt mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Tx and Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
-{
-  uint32_t abortcplt = 1U;
-
-  /* Disable interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
-  }
-
-  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
-     before any call to DMA Abort functions */
-  /* DMA Tx Handle is valid */
-  if (huart->hdmatx != NULL)
-  {
-    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-    {
-      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
-    }
-    else
-    {
-      huart->hdmatx->XferAbortCallback = NULL;
-    }
-  }
-  /* DMA Rx Handle is valid */
-  if (huart->hdmarx != NULL)
-  {
-    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-    {
-      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
-    }
-    else
-    {
-      huart->hdmarx->XferAbortCallback = NULL;
-    }
-  }
-
-  /* Disable the UART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-  {
-    /* Disable DMA Tx at UART level */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
-    if (huart->hdmatx != NULL)
-    {
-      /* UART Tx DMA Abort callback has already been initialised :
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
-      {
-        huart->hdmatx->XferAbortCallback = NULL;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-
-  /* Disable the UART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
-    if (huart->hdmarx != NULL)
-    {
-      /* UART Rx DMA Abort callback has already been initialised :
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
-      {
-        huart->hdmarx->XferAbortCallback = NULL;
-        abortcplt = 1U;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-
-  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
-  if (abortcplt == 1U)
-  {
-    /* Reset Tx and Rx transfer counters */
-    huart->TxXferCount = 0U;
-    huart->RxXferCount = 0U;
-
-    /* Clear ISR function pointers */
-    huart->RxISR = NULL;
-    huart->TxISR = NULL;
-
-    /* Reset errorCode */
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-    /* Clear the Error flags in the ICR register */
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
-
-    /* Discard the received data */
-    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
-    /* Restore huart->gState and huart->RxState to Ready */
-    huart->gState  = HAL_UART_STATE_READY;
-    huart->RxState = HAL_UART_STATE_READY;
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort complete callback */
-    huart->AbortCpltCallback(huart);
-#else
-    /* Call legacy weak Abort complete callback */
-    HAL_UART_AbortCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Disable the UART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
-    if (huart->hdmatx != NULL)
-    {
-      /* Set the UART DMA Abort callback :
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
-      {
-        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
-        huart->hdmatx->XferAbortCallback(huart->hdmatx);
-      }
-    }
-    else
-    {
-      /* Reset Tx transfer counter */
-      huart->TxXferCount = 0U;
-
-      /* Clear TxISR function pointers */
-      huart->TxISR = NULL;
-
-      /* Restore huart->gState to Ready */
-      huart->gState = HAL_UART_STATE_READY;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Transmit Complete Callback */
-      huart->AbortTransmitCpltCallback(huart);
-#else
-      /* Call legacy weak Abort Transmit Complete Callback */
-      HAL_UART_AbortTransmitCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-    }
-  }
-  else
-  {
-    /* Reset Tx transfer counter */
-    huart->TxXferCount = 0U;
-
-    /* Clear TxISR function pointers */
-    huart->TxISR = NULL;
-
-
-    /* Restore huart->gState to Ready */
-    huart->gState = HAL_UART_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Transmit Complete Callback */
-    huart->AbortTransmitCpltCallback(huart);
-#else
-    /* Call legacy weak Abort Transmit Complete Callback */
-    HAL_UART_AbortTransmitCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (Interrupt mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
-  }
-
-  /* Disable the UART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
-    if (huart->hdmarx != NULL)
-    {
-      /* Set the UART DMA Abort callback :
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
-      {
-        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
-        huart->hdmarx->XferAbortCallback(huart->hdmarx);
-      }
-    }
-    else
-    {
-      /* Reset Rx transfer counter */
-      huart->RxXferCount = 0U;
-
-      /* Clear RxISR function pointer */
-      huart->pRxBuffPtr = NULL;
-
-      /* Clear the Error flags in the ICR register */
-      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
-      /* Discard the received data */
-      __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
-      /* Restore huart->RxState to Ready */
-      huart->RxState = HAL_UART_STATE_READY;
-      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Receive Complete Callback */
-      huart->AbortReceiveCpltCallback(huart);
-#else
-      /* Call legacy weak Abort Receive Complete Callback */
-      HAL_UART_AbortReceiveCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-    }
-  }
-  else
-  {
-    /* Reset Rx transfer counter */
-    huart->RxXferCount = 0U;
-
-    /* Clear RxISR function pointer */
-    huart->pRxBuffPtr = NULL;
-
-    /* Clear the Error flags in the ICR register */
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
-    /* Restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Receive Complete Callback */
-    huart->AbortReceiveCpltCallback(huart);
-#else
-    /* Call legacy weak Abort Receive Complete Callback */
-    HAL_UART_AbortReceiveCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Handle UART interrupt request.
-  * @param huart UART handle.
-  * @retval None
-  */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
-  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
-  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
-  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
-
-  uint32_t errorflags;
-  uint32_t errorcode;
-
-  /* If no error occurs */
-  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
-  if (errorflags == 0U)
-  {
-    /* UART in mode Receiver ---------------------------------------------------*/
-    if (((isrflags & USART_ISR_RXNE) != 0U)
-        && ((cr1its & USART_CR1_RXNEIE) != 0U))
-    {
-      if (huart->RxISR != NULL)
-      {
-        huart->RxISR(huart);
-      }
-      return;
-    }
-  }
-
-  /* If some errors occur */
-  if ((errorflags != 0U)
-      && (((cr3its & USART_CR3_EIE) != 0U)
-          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))
-  {
-    /* UART parity error interrupt occurred -------------------------------------*/
-    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
-    {
-      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
-
-      huart->ErrorCode |= HAL_UART_ERROR_PE;
-    }
-
-    /* UART frame error interrupt occurred --------------------------------------*/
-    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
-    {
-      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
-
-      huart->ErrorCode |= HAL_UART_ERROR_FE;
-    }
-
-    /* UART noise error interrupt occurred --------------------------------------*/
-    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
-    {
-      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
-
-      huart->ErrorCode |= HAL_UART_ERROR_NE;
-    }
-
-    /* UART Over-Run interrupt occurred -----------------------------------------*/
-    if (((isrflags & USART_ISR_ORE) != 0U)
-        && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
-            ((cr3its & USART_CR3_EIE) != 0U)))
-    {
-      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
-
-      huart->ErrorCode |= HAL_UART_ERROR_ORE;
-    }
-
-    /* UART Receiver Timeout interrupt occurred ---------------------------------*/
-    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
-    {
-      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
-
-      huart->ErrorCode |= HAL_UART_ERROR_RTO;
-    }
-
-    /* Call UART Error Call back function if need be ----------------------------*/
-    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
-    {
-      /* UART in mode Receiver --------------------------------------------------*/
-      if (((isrflags & USART_ISR_RXNE) != 0U)
-          && ((cr1its & USART_CR1_RXNEIE) != 0U))
-      {
-        if (huart->RxISR != NULL)
-        {
-          huart->RxISR(huart);
-        }
-      }
-
-      /* If Error is to be considered as blocking :
-          - Receiver Timeout error in Reception
-          - Overrun error in Reception
-          - any error occurs in DMA mode reception
-      */
-      errorcode = huart->ErrorCode;
-      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
-          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
-      {
-        /* Blocking error : transfer is aborted
-           Set the UART state ready to be able to start again the process,
-           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
-        UART_EndRxTransfer(huart);
-
-        /* Disable the UART DMA Rx request if enabled */
-        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-        {
-          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-          /* Abort the UART DMA Rx channel */
-          if (huart->hdmarx != NULL)
-          {
-            /* Set the UART DMA Abort callback :
-               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
-            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
-
-            /* Abort DMA RX */
-            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
-            {
-              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
-              huart->hdmarx->XferAbortCallback(huart->hdmarx);
-            }
-          }
-          else
-          {
-            /* Call user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-            /*Call registered error callback*/
-            huart->ErrorCallback(huart);
-#else
-            /*Call legacy weak error callback*/
-            HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-          }
-        }
-        else
-        {
-          /* Call user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-          /*Call registered error callback*/
-          huart->ErrorCallback(huart);
-#else
-          /*Call legacy weak error callback*/
-          HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-        }
-      }
-      else
-      {
-        /* Non Blocking error : transfer could go on.
-           Error is notified to user through user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered error callback*/
-        huart->ErrorCallback(huart);
-#else
-        /*Call legacy weak error callback*/
-        HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-        huart->ErrorCode = HAL_UART_ERROR_NONE;
-      }
-    }
-    return;
-
-  } /* End if some error occurs */
-
-  /* Check current reception Mode :
-     If Reception till IDLE event has been selected : */
-  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      && ((isrflags & USART_ISR_IDLE) != 0U)
-      && ((cr1its & USART_ISR_IDLE) != 0U))
-  {
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
-
-    /* Check if DMA mode is enabled in UART */
-    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-    {
-      /* DMA mode enabled */
-      /* Check received length : If all expected data are received, do nothing,
-         (DMA cplt callback will be called).
-         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
-      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
-      if ((nb_remaining_rx_data > 0U)
-          && (nb_remaining_rx_data < huart->RxXferSize))
-      {
-        /* Reception is not complete */
-        huart->RxXferCount = nb_remaining_rx_data;
-
-        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
-        if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
-        {
-          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
-             in the UART CR3 register */
-          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-          /* At end of Rx process, restore huart->RxState to Ready */
-          huart->RxState = HAL_UART_STATE_READY;
-          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-
-          /* Last bytes received, so no need as the abort is immediate */
-          (void)HAL_DMA_Abort(huart->hdmarx);
-        }
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx Event callback*/
-        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
-#else
-        /*Call legacy weak Rx Event callback*/
-        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-      }
-      return;
-    }
-    else
-    {
-      /* DMA mode not enabled */
-      /* Check received length : If all expected data are received, do nothing.
-         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
-      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
-      if ((huart->RxXferCount > 0U)
-          && (nb_rx_data > 0U))
-      {
-        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
-        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
-        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-        /* Rx process is completed, restore huart->RxState to Ready */
-        huart->RxState = HAL_UART_STATE_READY;
-        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-        /* Clear RxISR function pointer */
-        huart->RxISR = NULL;
-
-        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx complete callback*/
-        huart->RxEventCallback(huart, nb_rx_data);
-#else
-        /*Call legacy weak Rx Event callback*/
-        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-      }
-      return;
-    }
-  }
-
-  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
-  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
-  {
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
-
-    /* UART Rx state is not reset as a reception process might be ongoing.
-       If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /* Call registered Wakeup Callback */
-    huart->WakeupCallback(huart);
-#else
-    /* Call legacy weak Wakeup Callback */
-    HAL_UARTEx_WakeupCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-    return;
-  }
-
-  /* UART in mode Transmitter ------------------------------------------------*/
-  if (((isrflags & USART_ISR_TXE) != 0U)
-      && ((cr1its & USART_CR1_TXEIE) != 0U))
-  {
-    if (huart->TxISR != NULL)
-    {
-      huart->TxISR(huart);
-    }
-    return;
-  }
-
-  /* UART in mode Transmitter (transmission end) -----------------------------*/
-  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
-  {
-    UART_EndTransmit_IT(huart);
-    return;
-  }
-
-}
-
-/**
-  * @brief Tx Transfer completed callback.
-  * @param huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_TxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_RxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer completed callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  UART error callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_ErrorCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  UART Abort Complete callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_AbortCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  UART Abort Complete callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  UART Abort Receive Complete callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Reception Event Callback (Rx event notification called after use of advanced reception service).
-  * @param  huart UART handle
-  * @param  Size  Number of data available in application reception buffer (indicates a position in
-  *               reception buffer until which, data are available)
-  * @retval None
-  */
-__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  UNUSED(Size);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UARTEx_RxEventCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief   UART control functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the UART.
-     (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
-     (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
-     (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
-     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
-     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
-     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
-     (+) UART_SetConfig() API configures the UART peripheral
-     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
-     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
-     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
-     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
-     (+) HAL_LIN_SendBreak() API transmits the break characters
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Update on the fly the receiver timeout value in RTOR register.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *                    the configuration information for the specified UART module.
-  * @param  TimeoutValue receiver timeout value in number of baud blocks. The timeout
-  *                     value must be less or equal to 0x0FFFFFFFF.
-  * @retval None
-  */
-void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
-{
-  if (!(IS_LPUART_INSTANCE(huart->Instance)))
-  {
-    assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
-    MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
-  }
-}
-
-/**
-  * @brief  Enable the UART receiver timeout feature.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *                    the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
-{
-  if (!(IS_LPUART_INSTANCE(huart->Instance)))
-  {
-    if (huart->gState == HAL_UART_STATE_READY)
-    {
-      /* Process Locked */
-      __HAL_LOCK(huart);
-
-      huart->gState = HAL_UART_STATE_BUSY;
-
-      /* Set the USART RTOEN bit */
-      SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
-
-      huart->gState = HAL_UART_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(huart);
-
-      return HAL_OK;
-    }
-    else
-    {
-      return HAL_BUSY;
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Disable the UART receiver timeout feature.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *                    the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
-{
-  if (!(IS_LPUART_INSTANCE(huart->Instance)))
-  {
-    if (huart->gState == HAL_UART_STATE_READY)
-    {
-      /* Process Locked */
-      __HAL_LOCK(huart);
-
-      huart->gState = HAL_UART_STATE_BUSY;
-
-      /* Clear the USART RTOEN bit */
-      CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
-
-      huart->gState = HAL_UART_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(huart);
-
-      return HAL_OK;
-    }
-    else
-    {
-      return HAL_BUSY;
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Enable UART in mute mode (does not mean UART enters mute mode;
-  *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
-  * @param  huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
-{
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Enable USART mute mode by setting the MME bit in the CR1 register */
-  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
-  *         as it may not have been in mute mode at this very moment).
-  * @param  huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
-{
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable USART mute mode by clearing the MME bit in the CR1 register */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @brief Enter UART mute mode (means UART actually enters mute mode).
-  * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
-  * @param huart UART handle.
-  * @retval None
-  */
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
-{
-  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
-}
-
-/**
-  * @brief  Enable the UART transmitter and disable the UART receiver.
-  * @param  huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
-{
-  __HAL_LOCK(huart);
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Clear TE and RE bits */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
-
-  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
-  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enable the UART receiver and disable the UART transmitter.
-  * @param  huart UART handle.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
-{
-  __HAL_LOCK(huart);
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Clear TE and RE bits */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
-
-  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
-  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Transmit break characters.
-  * @param  huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
-
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Send break characters */
-  __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
-  *  @brief   UART Peripheral State functions
-  *
-@verbatim
-  ==============================================================================
-            ##### Peripheral State and Error functions #####
-  ==============================================================================
-    [..]
-    This subsection provides functions allowing to :
-      (+) Return the UART handle state.
-      (+) Return the UART handle error code
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Return the UART handle state.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART.
-  * @retval HAL state
-  */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
-{
-  uint32_t temp1;
-  uint32_t temp2;
-  temp1 = huart->gState;
-  temp2 = huart->RxState;
-
-  return (HAL_UART_StateTypeDef)(temp1 | temp2);
-}
-
-/**
-  * @brief  Return the UART handle error code.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART.
-  * @retval UART Error Code
-  */
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
-{
-  return huart->ErrorCode;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Private_Functions UART Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Initialize the callbacks to their default values.
-  * @param  huart UART handle.
-  * @retval none
-  */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
-{
-  /* Init the UART Callback settings */
-  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
-  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
-  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
-  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
-  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
-  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
-  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
-  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
-  huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */
-  huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCallback           */
-
-}
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
-  * @brief Configure the UART peripheral.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg;
-  uint16_t brrtemp;
-  UART_ClockSourceTypeDef clocksource;
-  uint32_t usartdiv;
-  HAL_StatusTypeDef ret               = HAL_OK;
-  uint32_t pclk;
-
-  /* Check the parameters */
-  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  if (UART_INSTANCE_LOWPOWER(huart))
-  {
-    assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
-  }
-  else
-  {
-    assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
-    assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
-  }
-
-  assert_param(IS_UART_PARITY(huart->Init.Parity));
-  assert_param(IS_UART_MODE(huart->Init.Mode));
-  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
-  *  the UART Word Length, Parity, Mode and oversampling:
-  *  set the M bits according to huart->Init.WordLength value
-  *  set PCE and PS bits according to huart->Init.Parity value
-  *  set TE and RE bits according to huart->Init.Mode value
-  *  set OVER8 bit according to huart->Init.OverSampling value */
-  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
-  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
-
-  /*-------------------------- USART CR2 Configuration -----------------------*/
-  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
-  * to huart->Init.StopBits value */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/
-  /* Configure
-  * - UART HardWare Flow Control: set CTSE and RTSE bits according
-  *   to huart->Init.HwFlowCtl value
-  * - one-bit sampling method versus three samples' majority rule according
-  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
-  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
-
-  if (!(UART_INSTANCE_LOWPOWER(huart)))
-  {
-    tmpreg |= huart->Init.OneBitSampling;
-  }
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
-
-
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  UART_GETCLOCKSOURCE(huart, clocksource);
-
-  /* Check LPUART instance */
-  if (UART_INSTANCE_LOWPOWER(huart))
-  {
-    /* Retrieve frequency clock */
-    switch (clocksource)
-    {
-      case UART_CLOCKSOURCE_PCLK1:
-        pclk = HAL_RCC_GetPCLK1Freq();
-        break;
-      case UART_CLOCKSOURCE_HSI:
-        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
-        {
-          pclk = (uint32_t)(HSI_VALUE >> 2U);
-        }
-        else
-        {
-          pclk = (uint32_t) HSI_VALUE;
-        }
-        break;
-      case UART_CLOCKSOURCE_SYSCLK:
-        pclk = HAL_RCC_GetSysClockFreq();
-        break;
-      case UART_CLOCKSOURCE_LSE:
-        pclk = (uint32_t) LSE_VALUE;
-        break;
-      default:
-        pclk = 0U;
-        ret = HAL_ERROR;
-        break;
-    }
-
-    /* If proper clock source reported */
-    if (pclk != 0U)
-    {
-      /* No Prescaler applicable */
-      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
-      if ((pclk < (3U * huart->Init.BaudRate)) ||
-          (pclk > (4096U * huart->Init.BaudRate)))
-      {
-        ret = HAL_ERROR;
-      }
-      else
-      {
-        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
-        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
-        {
-          huart->Instance->BRR = usartdiv;
-        }
-        else
-        {
-          ret = HAL_ERROR;
-        }
-      } /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
-    } /* if (pclk != 0) */
-  }
-  /* Check UART Over Sampling to set Baud Rate Register */
-  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
-  {
-    switch (clocksource)
-    {
-      case UART_CLOCKSOURCE_PCLK1:
-        pclk = HAL_RCC_GetPCLK1Freq();
-        break;
-      case UART_CLOCKSOURCE_PCLK2:
-        pclk = HAL_RCC_GetPCLK2Freq();
-        break;
-      case UART_CLOCKSOURCE_HSI:
-        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
-        {
-          pclk = (uint32_t)(HSI_VALUE >> 2U);
-        }
-        else
-        {
-          pclk = (uint32_t) HSI_VALUE;
-        }
-        break;
-      case UART_CLOCKSOURCE_SYSCLK:
-        pclk = HAL_RCC_GetSysClockFreq();
-        break;
-      case UART_CLOCKSOURCE_LSE:
-        pclk = (uint32_t) LSE_VALUE;
-        break;
-      default:
-        pclk = 0U;
-        ret = HAL_ERROR;
-        break;
-    }
-
-    /* USARTDIV must be greater than or equal to 0d16 */
-    if (pclk != 0U)
-    {
-      usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
-      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
-      {
-        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
-        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
-        huart->Instance->BRR = brrtemp;
-      }
-      else
-      {
-        ret = HAL_ERROR;
-      }
-    }
-  }
-  else
-  {
-    switch (clocksource)
-    {
-      case UART_CLOCKSOURCE_PCLK1:
-        pclk = HAL_RCC_GetPCLK1Freq();
-        break;
-      case UART_CLOCKSOURCE_PCLK2:
-        pclk = HAL_RCC_GetPCLK2Freq();
-        break;
-      case UART_CLOCKSOURCE_HSI:
-        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
-        {
-          pclk = (uint32_t)(HSI_VALUE >> 2U);
-        }
-        else
-        {
-          pclk = (uint32_t) HSI_VALUE;
-        }
-        break;
-      case UART_CLOCKSOURCE_SYSCLK:
-        pclk = HAL_RCC_GetSysClockFreq();
-        break;
-      case UART_CLOCKSOURCE_LSE:
-        pclk = (uint32_t) LSE_VALUE;
-        break;
-      default:
-        pclk = 0U;
-        ret = HAL_ERROR;
-        break;
-    }
-
-    if (pclk != 0U)
-    {
-      /* USARTDIV must be greater than or equal to 0d16 */
-      usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
-      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
-      {
-        huart->Instance->BRR = usartdiv;
-      }
-      else
-      {
-        ret = HAL_ERROR;
-      }
-    }
-  }
-
-
-  /* Clear ISR function pointers */
-  huart->RxISR = NULL;
-  huart->TxISR = NULL;
-
-  return ret;
-}
-
-/**
-  * @brief Configure the UART peripheral advanced features.
-  * @param huart UART handle.
-  * @retval None
-  */
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
-{
-  /* Check whether the set of advanced features to configure is properly set */
-  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
-  /* if required, configure TX pin active level inversion */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
-  }
-
-  /* if required, configure RX pin active level inversion */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
-  }
-
-  /* if required, configure data inversion */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
-  }
-
-  /* if required, configure RX/TX pins swap */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
-  }
-
-  /* if required, configure RX overrun detection disabling */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
-  {
-    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
-    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
-  }
-
-  /* if required, configure DMA disabling on reception error */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
-    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
-  }
-
-  /* if required, configure auto Baud rate detection scheme */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
-  {
-    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
-    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
-    /* set auto Baudrate detection parameters if detection is enabled */
-    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
-    {
-      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
-      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
-    }
-  }
-
-  /* if required, configure MSB first on communication line */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
-  }
-}
-
-/**
-  * @brief Check the UART Idle State.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
-{
-  uint32_t tickstart;
-
-  /* Initialize the UART ErrorCode */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-  /* Init tickstart for timeout management */
-  tickstart = HAL_GetTick();
-
-  /* Check if the Transmitter is enabled */
-  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
-  {
-    /* Wait until TEACK flag is set */
-    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
-    {
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Check if the Receiver is enabled */
-  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
-  {
-    /* Wait until REACK flag is set */
-    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
-    {
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Initialize the UART State */
-  huart->gState = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle UART Communication Timeout.
-  * @param huart     UART handle.
-  * @param Flag      Specifies the UART flag to check
-  * @param Status    Flag status (SET or RESET)
-  * @param Tickstart Tick start value
-  * @param Timeout   Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
-                                              uint32_t Tickstart, uint32_t Timeout)
-{
-  /* Wait until flag is set */
-  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-      {
-        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
-           interrupts for the interrupt process */
-        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
-        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-        huart->gState = HAL_UART_STATE_READY;
-        huart->RxState = HAL_UART_STATE_READY;
-
-        __HAL_UNLOCK(huart);
-
-        return HAL_TIMEOUT;
-      }
-
-      if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
-      {
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
-        {
-          /* Clear Receiver Timeout flag*/
-          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
-
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
-             interrupts for the interrupt process */
-          ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
-          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-          huart->gState = HAL_UART_STATE_READY;
-          huart->RxState = HAL_UART_STATE_READY;
-          huart->ErrorCode = HAL_UART_ERROR_RTO;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(huart);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start Receive operation in interrupt mode.
-  * @note   This function could be called by all HAL UART API providing reception in Interrupt mode.
-  * @note   When calling this function, parameters validity is considered as already checked,
-  *         i.e. Rx State, buffer address, ...
-  *         UART Handle is assumed as Locked.
-  * @param  huart UART handle.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  huart->pRxBuffPtr  = pData;
-  huart->RxXferSize  = Size;
-  huart->RxXferCount = Size;
-  huart->RxISR       = NULL;
-
-  /* Computation of UART mask to apply to RDR register */
-  UART_MASK_COMPUTATION(huart);
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->RxState = HAL_UART_STATE_BUSY_RX;
-
-  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* Set the Rx ISR function pointer according to the data word length */
-  if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-  {
-    huart->RxISR = UART_RxISR_16BIT;
-  }
-  else
-  {
-    huart->RxISR = UART_RxISR_8BIT;
-  }
-
-  __HAL_UNLOCK(huart);
-
-  /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
-  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start Receive operation in DMA mode.
-  * @note   This function could be called by all HAL UART API providing reception in DMA mode.
-  * @note   When calling this function, parameters validity is considered as already checked,
-  *         i.e. Rx State, buffer address, ...
-  *         UART Handle is assumed as Locked.
-  * @param  huart UART handle.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  huart->pRxBuffPtr = pData;
-  huart->RxXferSize = Size;
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->RxState = HAL_UART_STATE_BUSY_RX;
-
-  if (huart->hdmarx != NULL)
-  {
-    /* Set the UART DMA transfer complete callback */
-    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
-    /* Set the UART DMA Half transfer complete callback */
-    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
-    /* Set the DMA error callback */
-    huart->hdmarx->XferErrorCallback = UART_DMAError;
-
-    /* Set the DMA abort callback */
-    huart->hdmarx->XferAbortCallback = NULL;
-
-    /* Enable the DMA channel */
-    if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
-    {
-      /* Set error code to DMA */
-      huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-      __HAL_UNLOCK(huart);
-
-      /* Restore huart->RxState to ready */
-      huart->RxState = HAL_UART_STATE_READY;
-
-      return HAL_ERROR;
-    }
-  }
-  __HAL_UNLOCK(huart);
-
-  /* Enable the UART Parity Error Interrupt */
-  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
-  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-  in the UART CR3 register */
-  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
-  * @param  huart UART handle.
-  * @retval None
-  */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* At end of Tx process, restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-}
-
-
-/**
-  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
-  * @param  huart UART handle.
-  * @retval None
-  */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-  }
-
-  /* At end of Rx process, restore huart->RxState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  /* Reset RxIsr function pointer */
-  huart->RxISR = NULL;
-}
-
-
-/**
-  * @brief DMA UART transmit process complete callback.
-  * @param hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
-  /* DMA Normal mode */
-  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
-  {
-    huart->TxXferCount = 0U;
-
-    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
-       in the UART CR3 register */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Enable the UART Transmit Complete Interrupt */
-    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-  }
-  /* DMA Circular mode */
-  else
-  {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Tx complete callback*/
-    huart->TxCpltCallback(huart);
-#else
-    /*Call legacy weak Tx complete callback*/
-    HAL_UART_TxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief DMA UART transmit process half complete callback.
-  * @param hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /*Call registered Tx Half complete callback*/
-  huart->TxHalfCpltCallback(huart);
-#else
-  /*Call legacy weak Tx Half complete callback*/
-  HAL_UART_TxHalfCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief DMA UART receive process complete callback.
-  * @param hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
-  /* DMA Normal mode */
-  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
-  {
-    huart->RxXferCount = 0U;
-
-    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
-       in the UART CR3 register */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-
-    /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
-    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-    {
-      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-    }
-  }
-
-  /* Check current reception Mode :
-     If Reception till IDLE event has been selected : use Rx Event callback */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx Event callback*/
-    huart->RxEventCallback(huart, huart->RxXferSize);
-#else
-    /*Call legacy weak Rx Event callback*/
-    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* In other cases : use Rx Complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx complete callback*/
-    huart->RxCpltCallback(huart);
-#else
-    /*Call legacy weak Rx complete callback*/
-    HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief DMA UART receive process half complete callback.
-  * @param hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
-  /* Check current reception Mode :
-     If Reception till IDLE event has been selected : use Rx Event callback */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx Event callback*/
-    huart->RxEventCallback(huart, huart->RxXferSize / 2U);
-#else
-    /*Call legacy weak Rx Event callback*/
-    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* In other cases : use Rx Half Complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx Half complete callback*/
-    huart->RxHalfCpltCallback(huart);
-#else
-    /*Call legacy weak Rx Half complete callback*/
-    HAL_UART_RxHalfCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief DMA UART communication error callback.
-  * @param hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMAError(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
-  const HAL_UART_StateTypeDef gstate = huart->gState;
-  const HAL_UART_StateTypeDef rxstate = huart->RxState;
-
-  /* Stop UART DMA Tx request if ongoing */
-  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
-      (gstate == HAL_UART_STATE_BUSY_TX))
-  {
-    huart->TxXferCount = 0U;
-    UART_EndTxTransfer(huart);
-  }
-
-  /* Stop UART DMA Rx request if ongoing */
-  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
-      (rxstate == HAL_UART_STATE_BUSY_RX))
-  {
-    huart->RxXferCount = 0U;
-    UART_EndRxTransfer(huart);
-  }
-
-  huart->ErrorCode |= HAL_UART_ERROR_DMA;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /*Call registered error callback*/
-  huart->ErrorCallback(huart);
-#else
-  /*Call legacy weak error callback*/
-  HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-  huart->RxXferCount = 0U;
-  huart->TxXferCount = 0U;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /*Call registered error callback*/
-  huart->ErrorCallback(huart);
-#else
-  /*Call legacy weak error callback*/
-  HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART Tx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Rx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
-  huart->hdmatx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (huart->hdmarx != NULL)
-  {
-    if (huart->hdmarx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  huart->TxXferCount = 0U;
-  huart->RxXferCount = 0U;
-
-  /* Reset errorCode */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
-
-  /* Restore huart->gState and huart->RxState to Ready */
-  huart->gState  = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  huart->AbortCpltCallback(huart);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_UART_AbortCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-
-/**
-  * @brief  DMA UART Rx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Tx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
-  huart->hdmarx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (huart->hdmatx != NULL)
-  {
-    if (huart->hdmatx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  huart->TxXferCount = 0U;
-  huart->RxXferCount = 0U;
-
-  /* Reset errorCode */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
-  /* Discard the received data */
-  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
-  /* Restore huart->gState and huart->RxState to Ready */
-  huart->gState  = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  huart->AbortCpltCallback(huart);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_UART_AbortCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-
-/**
-  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
-  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
-  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
-  *         and leads to user Tx Abort Complete callback execution).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
-  huart->TxXferCount = 0U;
-
-
-  /* Restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Transmit Complete Callback */
-  huart->AbortTransmitCpltCallback(huart);
-#else
-  /* Call legacy weak Abort Transmit Complete Callback */
-  HAL_UART_AbortTransmitCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
-  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
-  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
-  *         and leads to user Rx Abort Complete callback execution).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  huart->RxXferCount = 0U;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
-  /* Discard the received data */
-  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
-  /* Restore huart->RxState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Receive Complete Callback */
-  huart->AbortReceiveCpltCallback(huart);
-#else
-  /* Call legacy weak Abort Receive Complete Callback */
-  HAL_UART_AbortReceiveCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief TX interrupt handler for 7 or 8 bits data word length .
-  * @note   Function is called under interruption only, once
-  *         interruptions have been enabled by HAL_UART_Transmit_IT().
-  * @param huart UART handle.
-  * @retval None
-  */
-static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
-{
-  /* Check that a Tx process is ongoing */
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)
-  {
-    if (huart->TxXferCount == 0U)
-    {
-      /* Disable the UART Transmit Data Register Empty Interrupt */
-      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
-
-      /* Enable the UART Transmit Complete Interrupt */
-      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-    }
-    else
-    {
-      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
-      huart->pTxBuffPtr++;
-      huart->TxXferCount--;
-    }
-  }
-}
-
-/**
-  * @brief TX interrupt handler for 9 bits data word length.
-  * @note   Function is called under interruption only, once
-  *         interruptions have been enabled by HAL_UART_Transmit_IT().
-  * @param huart UART handle.
-  * @retval None
-  */
-static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
-{
-  uint16_t *tmp;
-
-  /* Check that a Tx process is ongoing */
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)
-  {
-    if (huart->TxXferCount == 0U)
-    {
-      /* Disable the UART Transmit Data Register Empty Interrupt */
-      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
-
-      /* Enable the UART Transmit Complete Interrupt */
-      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-    }
-    else
-    {
-      tmp = (uint16_t *) huart->pTxBuffPtr;
-      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
-      huart->pTxBuffPtr += 2U;
-      huart->TxXferCount--;
-    }
-  }
-}
-
-
-/**
-  * @brief  Wrap up transmission in non-blocking mode.
-  * @param  huart pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable the UART Transmit Complete Interrupt */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
-  /* Tx process is ended, restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Cleat TxISR function pointer */
-  huart->TxISR = NULL;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /*Call registered Tx complete callback*/
-  huart->TxCpltCallback(huart);
-#else
-  /*Call legacy weak Tx complete callback*/
-  HAL_UART_TxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief RX interrupt handler for 7 or 8 bits data word length .
-  * @param huart UART handle.
-  * @retval None
-  */
-static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
-{
-  uint16_t uhMask = huart->Mask;
-  uint16_t  uhdata;
-
-  /* Check that a Rx process is ongoing */
-  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
-  {
-    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
-    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
-    huart->pRxBuffPtr++;
-    huart->RxXferCount--;
-
-    if (huart->RxXferCount == 0U)
-    {
-      /* Disable the UART Parity Error Interrupt and RXNE interrupts */
-      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
-      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-      /* Rx process is completed, restore huart->RxState to Ready */
-      huart->RxState = HAL_UART_STATE_READY;
-
-      /* Clear RxISR function pointer */
-      huart->RxISR = NULL;
-
-      /* Check current reception Mode :
-         If Reception till IDLE event has been selected : */
-      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      {
-        /* Set reception type to Standard */
-        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-        /* Disable IDLE interrupt */
-        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
-        {
-          /* Clear IDLE Flag */
-          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
-        }
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx Event callback*/
-        huart->RxEventCallback(huart, huart->RxXferSize);
-#else
-        /*Call legacy weak Rx Event callback*/
-        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-      }
-      else
-      {
-        /* Standard reception API called */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx complete callback*/
-        huart->RxCpltCallback(huart);
-#else
-        /*Call legacy weak Rx complete callback*/
-        HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-      }
-    }
-  }
-  else
-  {
-    /* Clear RXNE interrupt flag */
-    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-  }
-}
-
-/**
-  * @brief RX interrupt handler for 9 bits data word length .
-  * @note   Function is called under interruption only, once
-  *         interruptions have been enabled by HAL_UART_Receive_IT()
-  * @param huart UART handle.
-  * @retval None
-  */
-static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
-{
-  uint16_t *tmp;
-  uint16_t uhMask = huart->Mask;
-  uint16_t  uhdata;
-
-  /* Check that a Rx process is ongoing */
-  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
-  {
-    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
-    tmp = (uint16_t *) huart->pRxBuffPtr ;
-    *tmp = (uint16_t)(uhdata & uhMask);
-    huart->pRxBuffPtr += 2U;
-    huart->RxXferCount--;
-
-    if (huart->RxXferCount == 0U)
-    {
-      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
-      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
-      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-      /* Rx process is completed, restore huart->RxState to Ready */
-      huart->RxState = HAL_UART_STATE_READY;
-
-      /* Clear RxISR function pointer */
-      huart->RxISR = NULL;
-
-      /* Check current reception Mode :
-         If Reception till IDLE event has been selected : */
-      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      {
-        /* Set reception type to Standard */
-        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-        /* Disable IDLE interrupt */
-        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
-        {
-          /* Clear IDLE Flag */
-          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
-        }
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx Event callback*/
-        huart->RxEventCallback(huart, huart->RxXferSize);
-#else
-        /*Call legacy weak Rx Event callback*/
-        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-      }
-      else
-      {
-        /* Standard reception API called */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx complete callback*/
-        huart->RxCpltCallback(huart);
-#else
-        /*Call legacy weak Rx complete callback*/
-        HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-      }
-    }
-  }
-  else
-  {
-    /* Clear RXNE interrupt flag */
-    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-  }
-}
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c
deleted file mode 100644
index fc2e186695..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c
+++ /dev/null
@@ -1,842 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_uart_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended UART HAL module driver.
-  *          This file provides firmware functions to manage the following extended
-  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *
-  *
-  @verbatim
-  ==============================================================================
-               ##### UART peripheral extended features  #####
-  ==============================================================================
-
-    (#) Declare a UART_HandleTypeDef handle structure.
-
-    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
-        by calling the HAL_RS485Ex_Init() API.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup UARTEx UARTEx
-  * @brief UART Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
-  * @{
-  */
-static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
-  * @{
-  */
-
-/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief    Extended Initialization and Configuration Functions
-  *
-@verbatim
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
-    in asynchronous mode.
-      (+) For the asynchronous mode the parameters below can be configured:
-        (++) Baud Rate
-        (++) Word Length
-        (++) Stop Bit
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written
-             in the data register is transmitted but is changed by the parity bit.
-        (++) Hardware flow control
-        (++) Receiver/transmitter modes
-        (++) Over Sampling Method
-        (++) One-Bit Sampling Method
-      (+) For the asynchronous mode, the following advanced features can be configured as well:
-        (++) TX and/or RX pin level inversion
-        (++) data logical level inversion
-        (++) RX and TX pins swap
-        (++) RX overrun detection disabling
-        (++) DMA disabling on RX error
-        (++) MSB first on communication line
-        (++) auto Baud rate detection
-    [..]
-    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
-     procedures (details for the procedures are available in reference manual).
-
-@endverbatim
-
-  Depending on the frame length defined by the M1 and M0 bits (7-bit,
-  8-bit or 9-bit), the possible UART formats are listed in the
-  following table.
-
-    Table 1. UART frame format.
-    +-----------------------------------------------------------------------+
-    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
-    +-----------------------------------------------------------------------+
-
-  * @{
-  */
-
-/**
-  * @brief Initialize the RS485 Driver enable feature according to the specified
-  *         parameters in the UART_InitTypeDef and creates the associated handle.
-  * @param huart            UART handle.
-  * @param Polarity         Select the driver enable polarity.
-  *          This parameter can be one of the following values:
-  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
-  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
-  * @param AssertionTime    Driver Enable assertion time:
-  *       5-bit value defining the time between the activation of the DE (Driver Enable)
-  *       signal and the beginning of the start bit. It is expressed in sample time
-  *       units (1/8 or 1/16 bit time, depending on the oversampling rate)
-  * @param DeassertionTime  Driver Enable deassertion time:
-  *       5-bit value defining the time between the end of the last stop bit, in a
-  *       transmitted message, and the de-activation of the DE (Driver Enable) signal.
-  *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
-  *       oversampling rate).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
-                                   uint32_t DeassertionTime)
-{
-  uint32_t temp;
-
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-  /* Check the Driver Enable UART instance */
-  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
-
-  /* Check the Driver Enable polarity */
-  assert_param(IS_UART_DE_POLARITY(Polarity));
-
-  /* Check the Driver Enable assertion time */
-  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
-
-  /* Check the Driver Enable deassertion time */
-  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
-  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
-
-  /* Set the Driver Enable polarity */
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
-
-  /* Set the Driver Enable assertion and deassertion times */
-  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
-  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
-  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
-  *  @brief Extended functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    This subsection provides a set of Wakeup and FIFO mode related callback functions.
-
-    (#) Wakeup from Stop mode Callback:
-        (+) HAL_UARTEx_WakeupCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief UART wakeup from Stop mode callback.
-  * @param huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
-   */
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
-  * @brief    Extended Peripheral Control functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..] This section provides the following functions:
-     (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode
-     (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
-     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
-         detection length to more than 4 bits for multiprocessor address mark wake up.
-     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
-         trigger: address match, Start Bit detection or RXNE bit status.
-     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
-     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
-
-    [..] This subsection also provides a set of additional functions providing enhanced reception
-    services to user. (For example, these functions allow application to handle use cases
-    where number of data to be received is unknown).
-
-    (#) Compared to standard reception services which only consider number of received
-        data elements as reception completion criteria, these functions also consider additional events
-        as triggers for updating reception status to caller :
-       (+) Detection of inactivity period (RX line has not been active for a given period).
-          (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
-               for 1 frame time, after last received byte.
-          (++) RX inactivity detected by RTO, i.e. line has been in idle state
-               for a programmable time, after last received byte.
-       (+) Detection that a specific character has been received.
-
-    (#) There are two mode of transfer:
-       (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
-           or till IDLE event occurs. Reception is handled only during function execution.
-           When function exits, no data reception could occur. HAL status and number of actually received data elements,
-           are returned by function after finishing transfer.
-       (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
-           These API's return the HAL status.
-           The end of the data processing will be indicated through the
-           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
-           The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
-           The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
-
-    (#) Blocking mode API:
-        (+) HAL_UARTEx_ReceiveToIdle()
-
-    (#) Non-Blocking mode API with Interrupt:
-        (+) HAL_UARTEx_ReceiveToIdle_IT()
-
-    (#) Non-Blocking mode API with DMA:
-        (+) HAL_UARTEx_ReceiveToIdle_DMA()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Keep UART Clock enabled when in Stop Mode.
-  * @note   When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled
-  *         this clock during STOP mode by setting the UCESM bit in USART_CR3 control register.
-  * @note   When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source,
-  *         and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set.
-  * @param  huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  /* Set UCESM bit */
-  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_UCESM);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable UART Clock when in Stop Mode.
-  * @param  huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  /* Clear UCESM bit */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief By default in multiprocessor mode, when the wake up method is set
-  *        to address mark, the UART handles only 4-bit long addresses detection;
-  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
-  *        long).
-  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
-  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
-  * @param huart         UART handle.
-  * @param AddressLength This parameter can be one of the following values:
-  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
-  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the address length parameter */
-  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the address length */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->gState to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @brief Set Wakeup from Stop mode interrupt flag selection.
-  * @note It is the application responsibility to enable the interrupt used as
-  *       usart_wkup interrupt source before entering low-power mode.
-  * @param huart           UART handle.
-  * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
-  *          This parameter can be one of the following values:
-  *          @arg @ref UART_WAKEUP_ON_ADDRESS
-  *          @arg @ref UART_WAKEUP_ON_STARTBIT
-  *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tickstart;
-
-  /* check the wake-up from stop mode UART instance */
-  assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
-  /* check the wake-up selection parameter */
-  assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the wake-up selection scheme */
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
-
-  if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
-  {
-    UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* Init tickstart for timeout management */
-  tickstart = HAL_GetTick();
-
-  /* Wait until REACK flag is set */
-  if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
-  {
-    status = HAL_TIMEOUT;
-  }
-  else
-  {
-    /* Initialize the UART State */
-    huart->gState = HAL_UART_STATE_READY;
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return status;
-}
-
-/**
-  * @brief Enable UART Stop Mode.
-  * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  /* Set UESM bit */
-  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Disable UART Stop Mode.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  /* Clear UESM bit */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode till either the expected number of data
-  *        is received or an IDLE event occurs.
-  * @note  HAL_OK is returned if reception is completed (expected number of data has been received)
-  *        or if reception is stopped after IDLE event (less than the expected number of data has been received)
-  *        In this case, RxLen output parameter indicates number of data available in reception buffer.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
-  *        of uint16_t available through pData.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer for storing data to be received, should be aligned on a half word frontier
-  *         (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required to ensure proper
-  *         alignment for pData.
-  * @param huart   UART handle.
-  * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).
-  * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.
-  * @param RxLen   Number of data elements finally received
-  *                (could be lower than Size, in case reception ends on IDLE event)
-  * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
-                                           uint32_t Timeout)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-  uint16_t uhMask;
-  uint32_t tickstart;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a uint16_t frontier, as data to be received from RDR will be
-       handled through a uint16_t cast. */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->RxState = HAL_UART_STATE_BUSY_RX;
-    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    huart->RxXferSize  = Size;
-    huart->RxXferCount = Size;
-
-    /* Computation of UART mask to apply to RDR register */
-    UART_MASK_COMPUTATION(huart);
-    uhMask = huart->Mask;
-
-    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) pData;
-    }
-    else
-    {
-      pdata8bits  = pData;
-      pdata16bits = NULL;
-    }
-
-    __HAL_UNLOCK(huart);
-
-    /* Initialize output number of received elements */
-    *RxLen = 0U;
-
-    /* as long as data have to be received */
-    while (huart->RxXferCount > 0U)
-    {
-      /* Check if IDLE flag is set */
-      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
-      {
-        /* Clear IDLE flag in ISR */
-        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
-
-        /* If Set, but no data ever received, clear flag without exiting loop */
-        /* If Set, and data has already been received, this means Idle Event is valid : End reception */
-        if (*RxLen > 0U)
-        {
-          huart->RxState = HAL_UART_STATE_READY;
-
-          return HAL_OK;
-        }
-      }
-
-      /* Check if RXNE flag is set */
-      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
-      {
-        if (pdata8bits == NULL)
-        {
-          *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
-          pdata16bits++;
-        }
-        else
-        {
-          *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
-          pdata8bits++;
-        }
-        /* Increment number of received elements */
-        *RxLen += 1U;
-        huart->RxXferCount--;
-      }
-
-      /* Check for the Timeout */
-      if (Timeout != HAL_MAX_DELAY)
-      {
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-        {
-          huart->RxState = HAL_UART_STATE_READY;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Set number of received elements in output parameter : RxLen */
-    *RxLen = huart->RxXferSize - huart->RxXferCount;
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in interrupt mode till either the expected number of data
-  *        is received or an IDLE event occurs.
-  * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
-  *        to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
-  *        number of received data elements.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
-  *        of uint16_t available through pData.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        address of user data buffer for storing data to be received, should be aligned on a half word frontier
-  *        (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
-  *        use of specific alignment compilation directives or pragmas might be required
-  *        to ensure proper alignment for pData.
-  * @param huart UART handle.
-  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
-  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef status;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a uint16_t frontier, as data to be received from RDR will be
-       handled through a uint16_t cast. */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    __HAL_LOCK(huart);
-
-    /* Set Reception type to reception till IDLE Event*/
-    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
-
-    status =  UART_Start_Receive_IT(huart, pData, Size);
-
-    /* Check Rx process has been successfully started */
-    if (status == HAL_OK)
-    {
-      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      {
-        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
-        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-      }
-      else
-      {
-        /* In case of errors already pending when reception is started,
-           Interrupts may have already been raised and lead to reception abortion.
-           (Overrun error for instance).
-           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
-        status = HAL_ERROR;
-      }
-    }
-
-    return status;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in DMA mode till either the expected number
-  *        of data is received or an IDLE event occurs.
-  * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
-  *        to DMA services, transferring automatically received data elements in user reception buffer and
-  *        calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
-  *        reception phase as ended. In all cases, callback execution will indicate number of received data elements.
-  * @note  When the UART parity is enabled (PCE = 1), the received data contain
-  *        the parity bit (MSB position).
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
-  *        of uint16_t available through pData.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        address of user data buffer for storing data to be received, should be aligned on a half word frontier
-  *        (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
-  *        use of specific alignment compilation directives or pragmas might be required
-  *        to ensure proper alignment for pData.
-  * @param huart UART handle.
-  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
-  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef status;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a uint16_t frontier, as data copy from RDR will be
-       handled by DMA from a uint16_t frontier. */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    __HAL_LOCK(huart);
-
-    /* Set Reception type to reception till IDLE Event*/
-    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
-
-    status =  UART_Start_Receive_DMA(huart, pData, Size);
-
-    /* Check Rx process has been successfully started */
-    if (status == HAL_OK)
-    {
-      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      {
-        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
-        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-      }
-      else
-      {
-        /* In case of errors already pending when reception is started,
-           Interrupts may have already been raised and lead to reception abortion.
-           (Overrun error for instance).
-           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
-        status = HAL_ERROR;
-      }
-    }
-
-    return status;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup UARTEx_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
-  * @param huart           UART handle.
-  * @param WakeUpSelection UART wake up from stop mode parameters.
-  * @retval None
-  */
-static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
-{
-  assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
-
-  /* Set the USART address length */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
-
-  /* Set the USART address node */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c
deleted file mode 100644
index bd6ff67255..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c
+++ /dev/null
@@ -1,3249 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_usart.c
-  * @author  MCD Application Team
-  * @brief   USART HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
-  *          Peripheral (USART).
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Error functions
-  *
-  @verbatim
- ===============================================================================
-                        ##### How to use this driver #####
- ===============================================================================
-    [..]
-      The USART HAL driver can be used as follows:
-
-      (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
-      (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
-          (++) Enable the USARTx interface clock.
-          (++) USART pins configuration:
-            (+++) Enable the clock for the USART GPIOs.
-            (+++) Configure these USART pins as alternate function pull-up.
-          (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
-                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-            (++) USART interrupts handling:
-              -@@-   The specific USART interrupts (Transmission complete interrupt,
-                  RXNE interrupt and Error Interrupts) will be managed using the macros
-                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
-          (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
-               HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx channel.
-            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer
-                  complete interrupt on the DMA Tx/Rx channel.
-
-      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
-          (Receiver/Transmitter) in the husart handle Init structure.
-
-      (#) Initialize the USART registers by calling the HAL_USART_Init() API:
-          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-               by calling the customized HAL_USART_MspInit(&husart) API.
-
-    [..]
-     (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
-        HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
-        HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
-
-    ##### Callback registration #####
-    ==================================
-
-    [..]
-    The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
-    allows the user to configure dynamically the driver callbacks.
-
-    [..]
-    Use Function HAL_USART_RegisterCallback() to register a user callback.
-    Function HAL_USART_RegisterCallback() allows to register following callbacks:
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) MspInitCallback           : USART MspInit.
-    (+) MspDeInitCallback         : USART MspDeInit.
-    This function takes as parameters the HAL peripheral handle, the Callback ID
-    and a pointer to the user callback function.
-
-    [..]
-    Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-    and the Callback ID.
-    This function allows to reset following callbacks:
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) MspInitCallback           : USART MspInit.
-    (+) MspDeInitCallback         : USART MspDeInit.
-
-    [..]
-    By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
-    Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the HAL_USART_Init()
-    and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
-    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
-
-    [..]
-    Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
-    Exception done MspInit/MspDeInit that can be registered/unregistered
-    in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
-    MspInit/DeInit callbacks can be used during the Init/DeInit.
-    In that case first register the MspInit/MspDeInit user callbacks
-    using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit()
-    or HAL_USART_Init() function.
-
-    [..]
-    When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
-    not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
-
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup USART USART
-  * @brief HAL USART Synchronous module driver
-  * @{
-  */
-
-#ifdef HAL_USART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup USART_Private_Constants USART Private Constants
-  * @{
-  */
-#define USART_DUMMY_DATA          ((uint16_t) 0xFFFF)           /*!< USART transmitted dummy data                     */
-#define USART_TEACK_REACK_TIMEOUT             1000U             /*!< USART TX or RX enable acknowledge time-out value */
-#define USART_CR1_FIELDS          ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
-                                              USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8))    /*!< USART CR1 fields of parameters set by USART_SetConfig API */
-#define USART_CR2_FIELDS          ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
-                                              USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
-
-#define USART_BRR_MIN    0x10U        /* USART BRR minimum authorized value */
-#define USART_BRR_MAX    0xFFFFU      /* USART BRR maximum authorized value */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup USART_Private_Functions
-  * @{
-  */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-static void USART_EndTransfer(USART_HandleTypeDef *husart);
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAError(DMA_HandleTypeDef *hdma);
-static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
-                                                      uint32_t Tickstart, uint32_t Timeout);
-static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
-static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
-static void USART_TxISR_16BIT(USART_HandleTypeDef *husart);
-static void USART_EndTransmit_IT(USART_HandleTypeDef *husart);
-static void USART_RxISR_8BIT(USART_HandleTypeDef *husart);
-static void USART_RxISR_16BIT(USART_HandleTypeDef *husart);
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup USART_Exported_Functions USART Exported Functions
-  * @{
-  */
-
-/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to initialize the USART
-    in asynchronous and in synchronous modes.
-      (+) For the asynchronous mode only these parameters can be configured:
-        (++) Baud Rate
-        (++) Word Length
-        (++) Stop Bit
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written
-             in the data register is transmitted but is changed by the parity bit.
-        (++) USART polarity
-        (++) USART phase
-        (++) USART LastBit
-        (++) Receiver/transmitter modes
-
-    [..]
-    The HAL_USART_Init() function follows the USART  synchronous configuration
-    procedure (details for the procedure are available in reference manual).
-
-@endverbatim
-
-  Depending on the frame length defined by the M1 and M0 bits (7-bit,
-  8-bit or 9-bit), the possible USART formats are listed in the
-  following table.
-
-    Table 1. USART frame format.
-    +-----------------------------------------------------------------------+
-    |  M1 bit |  M0 bit |  PCE bit  |            USART frame                |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
-    +-----------------------------------------------------------------------+
-
-  * @{
-  */
-
-/**
-  * @brief  Initialize the USART mode according to the specified
-  *         parameters in the USART_InitTypeDef and initialize the associated handle.
-  * @param  husart USART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
-{
-  /* Check the USART handle allocation */
-  if (husart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_USART_INSTANCE(husart->Instance));
-
-  if (husart->State == HAL_USART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    husart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-    USART_InitCallbacksToDefault(husart);
-
-    if (husart->MspInitCallback == NULL)
-    {
-      husart->MspInitCallback = HAL_USART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    husart->MspInitCallback(husart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_USART_MspInit(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-  }
-
-  husart->State = HAL_USART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_USART_DISABLE(husart);
-
-  /* Set the Usart Communication parameters */
-  if (USART_SetConfig(husart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  /* In Synchronous mode, the following bits must be kept cleared:
-  - LINEN bit in the USART_CR2 register
-  - HDSEL, SCEN and IREN bits in the USART_CR3 register.
-  */
-  husart->Instance->CR2 &= ~USART_CR2_LINEN;
-  husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
-
-  /* Enable the Peripheral */
-  __HAL_USART_ENABLE(husart);
-
-  /* TEACK and/or REACK to check before moving husart->State to Ready */
-  return (USART_CheckIdleState(husart));
-}
-
-/**
-  * @brief DeInitialize the USART peripheral.
-  * @param  husart USART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
-{
-  /* Check the USART handle allocation */
-  if (husart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_USART_INSTANCE(husart->Instance));
-
-  husart->State = HAL_USART_STATE_BUSY;
-
-  husart->Instance->CR1 = 0x0U;
-  husart->Instance->CR2 = 0x0U;
-  husart->Instance->CR3 = 0x0U;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  if (husart->MspDeInitCallback == NULL)
-  {
-    husart->MspDeInitCallback = HAL_USART_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  husart->MspDeInitCallback(husart);
-#else
-  /* DeInit the low level hardware */
-  HAL_USART_MspDeInit(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-  husart->ErrorCode = HAL_USART_ERROR_NONE;
-  husart->State = HAL_USART_STATE_RESET;
-
-  /* Process Unlock */
-  __HAL_UNLOCK(husart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Initialize the USART MSP.
-  * @param husart USART handle.
-  * @retval None
-  */
-__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_USART_MspInit can be implemented in the user file
-   */
-}
-
-/**
-  * @brief DeInitialize the USART MSP.
-  * @param husart USART handle.
-  * @retval None
-  */
-__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_USART_MspDeInit can be implemented in the user file
-   */
-}
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User USART Callback
-  *         To be used instead of the weak predefined callback
-  * @param  husart usart handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-+  */
-HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
-                                             pUSART_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(husart);
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_USART_TX_HALFCOMPLETE_CB_ID :
-        husart->TxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_USART_TX_COMPLETE_CB_ID :
-        husart->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_USART_RX_HALFCOMPLETE_CB_ID :
-        husart->RxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_USART_RX_COMPLETE_CB_ID :
-        husart->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_USART_TX_RX_COMPLETE_CB_ID :
-        husart->TxRxCpltCallback = pCallback;
-        break;
-
-      case HAL_USART_ERROR_CB_ID :
-        husart->ErrorCallback = pCallback;
-        break;
-
-      case HAL_USART_ABORT_COMPLETE_CB_ID :
-        husart->AbortCpltCallback = pCallback;
-        break;
-
-
-      case HAL_USART_MSPINIT_CB_ID :
-        husart->MspInitCallback = pCallback;
-        break;
-
-      case HAL_USART_MSPDEINIT_CB_ID :
-        husart->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (husart->State == HAL_USART_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_USART_MSPINIT_CB_ID :
-        husart->MspInitCallback = pCallback;
-        break;
-
-      case HAL_USART_MSPDEINIT_CB_ID :
-        husart->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(husart);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister an USART Callback
-  *         USART callaback is redirected to the weak predefined callback
-  * @param  husart usart handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(husart);
-
-  if (HAL_USART_STATE_READY == husart->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_USART_TX_HALFCOMPLETE_CB_ID :
-        husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback  */
-        break;
-
-      case HAL_USART_TX_COMPLETE_CB_ID :
-        husart->TxCpltCallback = HAL_USART_TxCpltCallback;                       /* Legacy weak TxCpltCallback       */
-        break;
-
-      case HAL_USART_RX_HALFCOMPLETE_CB_ID :
-        husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback   */
-        break;
-
-      case HAL_USART_RX_COMPLETE_CB_ID :
-        husart->RxCpltCallback = HAL_USART_RxCpltCallback;                       /* Legacy weak RxCpltCallback       */
-        break;
-
-      case HAL_USART_TX_RX_COMPLETE_CB_ID :
-        husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback;                   /* Legacy weak TxRxCpltCallback     */
-        break;
-
-      case HAL_USART_ERROR_CB_ID :
-        husart->ErrorCallback = HAL_USART_ErrorCallback;                         /* Legacy weak ErrorCallback        */
-        break;
-
-      case HAL_USART_ABORT_COMPLETE_CB_ID :
-        husart->AbortCpltCallback = HAL_USART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback    */
-        break;
-
-
-      case HAL_USART_MSPINIT_CB_ID :
-        husart->MspInitCallback = HAL_USART_MspInit;                             /* Legacy weak MspInitCallback      */
-        break;
-
-      case HAL_USART_MSPDEINIT_CB_ID :
-        husart->MspDeInitCallback = HAL_USART_MspDeInit;                         /* Legacy weak MspDeInitCallback    */
-        break;
-
-      default :
-        /* Update the error code */
-        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_USART_STATE_RESET == husart->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_USART_MSPINIT_CB_ID :
-        husart->MspInitCallback = HAL_USART_MspInit;
-        break;
-
-      case HAL_USART_MSPDEINIT_CB_ID :
-        husart->MspDeInitCallback = HAL_USART_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(husart);
-
-  return status;
-}
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Exported_Functions_Group2 IO operation functions
-  * @brief   USART Transmit and Receive functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..] This subsection provides a set of functions allowing to manage the USART synchronous
-    data transfers.
-
-    [..] The USART supports master mode only: it cannot receive or send data related to an input
-         clock (SCLK is always an output).
-
-    [..]
-
-    (#) There are two modes of transfer:
-        (++) Blocking mode: The communication is performed in polling mode.
-             The HAL status of all data processing is returned by the same function
-             after finishing transfer.
-        (++) No-Blocking mode: The communication is performed using Interrupts
-             or DMA, These API's return the HAL status.
-             The end of the data processing will be indicated through the
-             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
-             using DMA mode.
-             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
-             will be executed respectively at the end of the transmit or Receive process
-             The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
-
-    (#) Blocking mode API's are :
-        (++) HAL_USART_Transmit() in simplex mode
-        (++) HAL_USART_Receive() in full duplex receive only
-        (++) HAL_USART_TransmitReceive() in full duplex mode
-
-    (#) Non-Blocking mode API's with Interrupt are :
-        (++) HAL_USART_Transmit_IT() in simplex mode
-        (++) HAL_USART_Receive_IT() in full duplex receive only
-        (++) HAL_USART_TransmitReceive_IT() in full duplex mode
-        (++) HAL_USART_IRQHandler()
-
-    (#) No-Blocking mode API's  with DMA are :
-        (++) HAL_USART_Transmit_DMA() in simplex mode
-        (++) HAL_USART_Receive_DMA() in full duplex receive only
-        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
-        (++) HAL_USART_DMAPause()
-        (++) HAL_USART_DMAResume()
-        (++) HAL_USART_DMAStop()
-
-    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
-        (++) HAL_USART_TxCpltCallback()
-        (++) HAL_USART_RxCpltCallback()
-        (++) HAL_USART_TxHalfCpltCallback()
-        (++) HAL_USART_RxHalfCpltCallback()
-        (++) HAL_USART_ErrorCallback()
-        (++) HAL_USART_TxRxCpltCallback()
-
-    (#) Non-Blocking mode transfers could be aborted using Abort API's :
-        (++) HAL_USART_Abort()
-        (++) HAL_USART_Abort_IT()
-
-    (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
-        (++) HAL_USART_AbortCpltCallback()
-
-    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
-        Errors are handled as follows :
-        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
-             to be evaluated by user : this concerns Frame Error,
-             Parity Error or Noise Error in Interrupt mode reception .
-             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
-             error type, and HAL_USART_ErrorCallback() user callback is executed.
-             Transfer is kept ongoing on USART side.
-             If user wants to abort it, Abort services should be called by user.
-        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
-             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
-             Error code is set to allow user to identify error type,
-             and HAL_USART_ErrorCallback() user callback is executed.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Simplex send an amount of data in blocking mode.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pTxData.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
-  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required
-  *         to ensure proper alignment for pTxData.
-  * @param  husart USART handle.
-  * @param  pTxData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size Amount of data elements (u8 or u16) to be sent.
-  * @param  Timeout Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *ptxdata8bits;
-  uint16_t *ptxdata16bits;
-  uint32_t tickstart;
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pTxData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be filled into TDR will be
-       handled through a u16 cast. */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      if ((((uint32_t)pTxData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-
-    /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      ptxdata8bits  = NULL;
-      ptxdata16bits = (uint16_t *) pTxData;
-    }
-    else
-    {
-      ptxdata8bits  = pTxData;
-      ptxdata16bits = NULL;
-    }
-
-    /* Check the remaining data to be sent */
-    while (husart->TxXferCount > 0U)
-    {
-      if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if (ptxdata8bits == NULL)
-      {
-        husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU);
-        ptxdata16bits++;
-      }
-      else
-      {
-        husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU);
-        ptxdata8bits++;
-      }
-
-      husart->TxXferCount--;
-    }
-
-    if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear Transmission Complete Flag */
-    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
-
-    /* Clear overrun flag and discard the received data */
-    __HAL_USART_CLEAR_OREFLAG(husart);
-    __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
-    __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
-
-    /* At end of Tx process, restore husart->State to Ready */
-    husart->State = HAL_USART_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode.
-  * @note   To receive synchronous data, dummy data are simultaneously transmitted.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pRxData.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
-  *         (as received data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
-  * @param husart USART handle.
-  * @param pRxData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size Amount of data elements (u8 or u16) to be received.
-  * @param Timeout Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *prxdata8bits;
-  uint16_t *prxdata16bits;
-  uint16_t uhMask;
-  uint32_t tickstart;
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pRxData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pRxData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be received from RDR will be
-       handled through a u16 cast. */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      if ((((uint32_t)pRxData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_RX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    husart->RxXferSize = Size;
-    husart->RxXferCount = Size;
-
-    /* Computation of USART mask to apply to RDR register */
-    USART_MASK_COMPUTATION(husart);
-    uhMask = husart->Mask;
-
-    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      prxdata8bits  = NULL;
-      prxdata16bits = (uint16_t *) pRxData;
-    }
-    else
-    {
-      prxdata8bits  = pRxData;
-      prxdata16bits = NULL;
-    }
-
-    /* as long as data have to be received */
-    while (husart->RxXferCount > 0U)
-    {
-      {
-        /* Wait until TXE flag is set to send dummy byte in order to generate the
-        * clock for the slave to send data.
-        * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
-        * can be written for all the cases. */
-        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
-      }
-
-      /* Wait for RXNE Flag */
-      if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      if (prxdata8bits == NULL)
-      {
-        *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
-        prxdata16bits++;
-      }
-      else
-      {
-        *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
-        prxdata8bits++;
-      }
-
-      husart->RxXferCount--;
-
-    }
-
-
-    /* At end of Rx process, restore husart->State to Ready */
-    husart->State = HAL_USART_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
-  *         of u16 available through pTxData and through pRxData.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
-  *         (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
-  * @param  husart USART handle.
-  * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
-  * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
-  * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
-  * @param  Timeout Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
-                                            uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *prxdata8bits;
-  uint16_t *prxdata16bits;
-  uint8_t  *ptxdata8bits;
-  uint16_t *ptxdata16bits;
-  uint16_t uhMask;
-  uint16_t rxdatacount;
-  uint32_t tickstart;
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
-       should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
-       handled through a u16 cast. */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_RX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    husart->RxXferSize = Size;
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-    husart->RxXferCount = Size;
-
-    /* Computation of USART mask to apply to RDR register */
-    USART_MASK_COMPUTATION(husart);
-    uhMask = husart->Mask;
-
-    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      prxdata8bits  = NULL;
-      ptxdata8bits  = NULL;
-      ptxdata16bits = (uint16_t *) pTxData;
-      prxdata16bits = (uint16_t *) pRxData;
-    }
-    else
-    {
-      prxdata8bits  = pRxData;
-      ptxdata8bits  = pTxData;
-      ptxdata16bits = NULL;
-      prxdata16bits = NULL;
-    }
-
-    if (husart->TxXferCount == 0x01U)
-    {
-      /* Wait until TXE flag is set to send data */
-      if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if (ptxdata8bits == NULL)
-      {
-        husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
-        ptxdata16bits++;
-      }
-      else
-      {
-        husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
-        ptxdata8bits++;
-      }
-
-      husart->TxXferCount--;
-    }
-
-    /* Check the remain data to be sent */
-    /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
-    rxdatacount = husart->RxXferCount;
-    while ((husart->TxXferCount > 0U) || (rxdatacount > 0U))
-    {
-      if (husart->TxXferCount > 0U)
-      {
-        /* Wait until TXE flag is set to send data */
-        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        if (ptxdata8bits == NULL)
-        {
-          husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
-          ptxdata16bits++;
-        }
-        else
-        {
-          husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
-          ptxdata8bits++;
-        }
-
-        husart->TxXferCount--;
-      }
-
-      if (husart->RxXferCount > 0U)
-      {
-        /* Wait for RXNE Flag */
-        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        if (prxdata8bits == NULL)
-        {
-          *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
-          prxdata16bits++;
-        }
-        else
-        {
-          *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
-          prxdata8bits++;
-        }
-
-        husart->RxXferCount--;
-      }
-      rxdatacount = husart->RxXferCount;
-    }
-
-    /* At end of TxRx process, restore husart->State to Ready */
-    husart->State = HAL_USART_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Send an amount of data in interrupt mode.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pTxData.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
-  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
-  * @param  husart USART handle.
-  * @param  pTxData pointer to data buffer (u8 or u16 data elements).
-  * @param  Size amount of data elements (u8 or u16) to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pTxData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be filled into TDR will be
-       handled through a u16 cast. */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      if ((((uint32_t)pTxData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pTxBuffPtr  = pTxData;
-    husart->TxXferSize  = Size;
-    husart->TxXferCount = Size;
-    husart->TxISR       = NULL;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State     = HAL_USART_STATE_BUSY_TX;
-
-    /* The USART Error Interrupts: (Frame error, noise error, overrun error)
-    are not managed by the USART Transmit Process to avoid the overrun interrupt
-    when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
-    to benefit for the frame error and noise interrupts the usart mode should be
-    configured only for transmit "USART_MODE_TX" */
-
-    {
-      /* Set the Tx ISR function pointer according to the data word length */
-      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-      {
-        husart->TxISR = USART_TxISR_16BIT;
-      }
-      else
-      {
-        husart->TxISR = USART_TxISR_8BIT;
-      }
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(husart);
-
-      /* Enable the USART Transmit Data Register Empty Interrupt */
-      __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in interrupt mode.
-  * @note   To receive synchronous data, dummy data are simultaneously transmitted.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pRxData.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
-  *         (as received data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
-  * @param  husart USART handle.
-  * @param  pRxData pointer to data buffer (u8 or u16 data elements).
-  * @param  Size amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
-{
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pRxData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pRxData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be received from RDR will be
-       handled through a u16 cast. */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      if ((((uint32_t)pRxData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pRxBuffPtr  = pRxData;
-    husart->RxXferSize  = Size;
-    husart->RxXferCount = Size;
-    husart->RxISR       = NULL;
-
-    USART_MASK_COMPUTATION(husart);
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_RX;
-
-    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-    {
-      /* Set the Rx ISR function pointer according to the data word length */
-      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-      {
-        husart->RxISR = USART_RxISR_16BIT;
-      }
-      else
-      {
-        husart->RxISR = USART_RxISR_8BIT;
-      }
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(husart);
-
-      /* Enable the USART Parity Error and Data Register not empty Interrupts */
-      SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-    }
-
-    {
-      /* Send dummy data in order to generate the clock for the Slave to send the next data.
-      */
-      {
-        husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
-      }
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
-  *         of u16 available through pTxData and through pRxData.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
-  *         (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
-  * @param  husart USART handle.
-  * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
-  * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
-  * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
-                                               uint16_t Size)
-{
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
-       should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
-       handled through a u16 cast. */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pRxBuffPtr = pRxData;
-    husart->RxXferSize = Size;
-    husart->RxXferCount = Size;
-    husart->pTxBuffPtr = pTxData;
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-
-    /* Computation of USART mask to apply to RDR register */
-    USART_MASK_COMPUTATION(husart);
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
-    {
-      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-      {
-        husart->TxISR = USART_TxISR_16BIT;
-        husart->RxISR = USART_RxISR_16BIT;
-      }
-      else
-      {
-        husart->TxISR = USART_TxISR_8BIT;
-        husart->RxISR = USART_RxISR_8BIT;
-      }
-
-      /* Process Locked */
-      __HAL_UNLOCK(husart);
-
-      /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-      /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
-      SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-
-      /* Enable the USART Transmit Data Register Empty Interrupt */
-      SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in DMA mode.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pTxData.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
-  *         (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
-  *         use of specific alignment compilation directives or pragmas might be required
-  *         to ensure proper alignment for pTxData.
-  * @param  husart USART handle.
-  * @param  pTxData pointer to data buffer (u8 or u16 data elements).
-  * @param  Size amount of data elements (u8 or u16) to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t *tmp;
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pTxData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data copy into TDR will be
-       handled by DMA from a u16 frontier. */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      if ((((uint32_t)pTxData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pTxBuffPtr = pTxData;
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX;
-
-    if (husart->hdmatx != NULL)
-    {
-      /* Set the USART DMA transfer complete callback */
-      husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
-      /* Set the USART DMA Half transfer complete callback */
-      husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
-      /* Set the DMA error callback */
-      husart->hdmatx->XferErrorCallback = USART_DMAError;
-
-      /* Enable the USART transmit DMA channel */
-      tmp = (uint32_t *)&pTxData;
-      status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
-    }
-
-    if (status == HAL_OK)
-    {
-      /* Clear the TC flag in the ICR register */
-      __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(husart);
-
-      /* Enable the DMA transfer for transmit request by setting the DMAT bit
-         in the USART CR3 register */
-      SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-      return HAL_OK;
-    }
-    else
-    {
-      /* Set error code to DMA */
-      husart->ErrorCode = HAL_USART_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(husart);
-
-      /* Restore husart->State to ready */
-      husart->State = HAL_USART_STATE_READY;
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in DMA mode.
-  * @note   When the USART parity is enabled (PCE = 1), the received data contain
-  *         the parity bit (MSB position).
-  * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pRxData.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffer for storing data to be received, should be aligned on
-  *         a half word frontier (16 bits) (as received data will be handled by DMA from halfword frontier).
-  *         Depending on compilation chain, use of specific alignment compilation directives or pragmas
-  *         might be required to ensure proper alignment for pRxData.
-  * @param  husart USART handle.
-  * @param  pRxData pointer to data buffer (u8 or u16 data elements).
-  * @param  Size amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t *tmp = (uint32_t *)&pRxData;
-
-  /* Check that a Rx process is not already ongoing */
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pRxData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pRxData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data copy from RDR will be
-       handled by DMA from a u16 frontier. */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      if ((((uint32_t)pRxData) & 1U) != 0U)
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pRxBuffPtr = pRxData;
-    husart->RxXferSize = Size;
-    husart->pTxBuffPtr = pRxData;
-    husart->TxXferSize = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_RX;
-
-    if (husart->hdmarx != NULL)
-    {
-      /* Set the USART DMA Rx transfer complete callback */
-      husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
-      /* Set the USART DMA Half transfer complete callback */
-      husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
-      /* Set the USART DMA Rx transfer error callback */
-      husart->hdmarx->XferErrorCallback = USART_DMAError;
-
-      /* Enable the USART receive DMA channel */
-      status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
-    }
-
-    {
-      /* Enable the USART transmit DMA channel: the transmit channel is used in order
-         to generate in the non-blocking mode the clock to the slave device,
-         this mode isn't a simplex receive mode but a full-duplex receive mode */
-
-      /* Set the USART DMA Tx Complete and Error callback to Null */
-      if (husart->hdmatx != NULL)
-      {
-        husart->hdmatx->XferErrorCallback = NULL;
-        husart->hdmatx->XferHalfCpltCallback = NULL;
-        husart->hdmatx->XferCpltCallback = NULL;
-        status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
-      }
-    }
-
-    if (status == HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(husart);
-
-      /* Enable the USART Parity Error Interrupt */
-      SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
-      /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-      /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-         in the USART CR3 register */
-      SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-      /* Enable the DMA transfer for transmit request by setting the DMAT bit
-         in the USART CR3 register */
-      SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-      return HAL_OK;
-    }
-    else
-    {
-      if (husart->hdmarx != NULL)
-      {
-        status = HAL_DMA_Abort(husart->hdmarx);
-      }
-
-      /* No need to check on error code */
-      UNUSED(status);
-
-      /* Set error code to DMA */
-      husart->ErrorCode = HAL_USART_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(husart);
-
-      /* Restore husart->State to ready */
-      husart->State = HAL_USART_STATE_READY;
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
-  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
-  *         of u16 available through pTxData and through pRxData.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         address of user data buffers containing data to be sent/received, should be aligned on a half word frontier
-  *         (16 bits) (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation
-  *         chain, use of specific alignment compilation directives or pragmas might be required
-  *         to ensure proper alignment for pTxData and pRxData.
-  * @param  husart USART handle.
-  * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
-  * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
-  * @param  Size amount of data elements (u8 or u16) to be received/sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
-                                                uint16_t Size)
-{
-  HAL_StatusTypeDef status;
-  uint32_t *tmp;
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
-       should be aligned on a u16 frontier, as data copy to/from TDR/RDR will be
-       handled by DMA from a u16 frontier. */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
-      {
-        return  HAL_ERROR;
-      }
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pRxBuffPtr = pRxData;
-    husart->RxXferSize = Size;
-    husart->pTxBuffPtr = pTxData;
-    husart->TxXferSize = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
-    if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL))
-    {
-      /* Set the USART DMA Rx transfer complete callback */
-      husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
-      /* Set the USART DMA Half transfer complete callback */
-      husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
-      /* Set the USART DMA Tx transfer complete callback */
-      husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
-      /* Set the USART DMA Half transfer complete callback */
-      husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
-      /* Set the USART DMA Tx transfer error callback */
-      husart->hdmatx->XferErrorCallback = USART_DMAError;
-
-      /* Set the USART DMA Rx transfer error callback */
-      husart->hdmarx->XferErrorCallback = USART_DMAError;
-
-      /* Enable the USART receive DMA channel */
-      tmp = (uint32_t *)&pRxData;
-      status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
-
-      /* Enable the USART transmit DMA channel */
-      if (status == HAL_OK)
-      {
-        tmp = (uint32_t *)&pTxData;
-        status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
-      }
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-
-    if (status == HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(husart);
-
-      /* Enable the USART Parity Error Interrupt */
-      SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
-      /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-      /* Clear the TC flag in the ICR register */
-      __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
-
-      /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-         in the USART CR3 register */
-      SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-      /* Enable the DMA transfer for transmit request by setting the DMAT bit
-         in the USART CR3 register */
-      SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-      return HAL_OK;
-    }
-    else
-    {
-      if (husart->hdmarx != NULL)
-      {
-        status = HAL_DMA_Abort(husart->hdmarx);
-      }
-
-      /* No need to check on error code */
-      UNUSED(status);
-
-      /* Set error code to DMA */
-      husart->ErrorCode = HAL_USART_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(husart);
-
-      /* Restore husart->State to ready */
-      husart->State = HAL_USART_STATE_READY;
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pause the DMA Transfer.
-  * @param  husart USART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
-{
-  const HAL_USART_StateTypeDef state = husart->State;
-
-  /* Process Locked */
-  __HAL_LOCK(husart);
-
-  if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) &&
-      (state == HAL_USART_STATE_BUSY_TX))
-  {
-    /* Disable the USART DMA Tx request */
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-  }
-  else if ((state == HAL_USART_STATE_BUSY_RX) ||
-           (state == HAL_USART_STATE_BUSY_TX_RX))
-  {
-    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
-    {
-      /* Disable the USART DMA Tx request */
-      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-    }
-    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
-    {
-      /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-      /* Disable the USART DMA Rx request */
-      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-    }
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(husart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Resume the DMA Transfer.
-  * @param  husart USART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
-{
-  const HAL_USART_StateTypeDef state = husart->State;
-
-  /* Process Locked */
-  __HAL_LOCK(husart);
-
-  if (state == HAL_USART_STATE_BUSY_TX)
-  {
-    /* Enable the USART DMA Tx request */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-  }
-  else if ((state == HAL_USART_STATE_BUSY_RX) ||
-           (state == HAL_USART_STATE_BUSY_TX_RX))
-  {
-    /* Clear the Overrun flag before resuming the Rx transfer*/
-    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
-
-    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the USART DMA Rx request  before the DMA Tx request */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Enable the USART DMA Tx request */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(husart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stop the DMA Transfer.
-  * @param  husart USART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
-{
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
-     HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
-     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
-     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
-     the stream and the corresponding call back is executed. */
-
-  /* Disable the USART Tx/Rx DMA requests */
-  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-  /* Abort the USART DMA tx channel */
-  if (husart->hdmatx != NULL)
-  {
-    if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
-    {
-      if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-      {
-        /* Set error code to DMA */
-        husart->ErrorCode = HAL_USART_ERROR_DMA;
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /* Abort the USART DMA rx channel */
-  if (husart->hdmarx != NULL)
-  {
-    if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
-    {
-      if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-      {
-        /* Set error code to DMA */
-        husart->ErrorCode = HAL_USART_ERROR_DMA;
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  USART_EndTransfer(husart);
-  husart->State = HAL_USART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfers (blocking mode).
-  * @param  husart USART handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable USART Interrupts (Tx and Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
-{
-  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the USART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if (husart->hdmatx != NULL)
-    {
-      /* Set the USART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      husart->hdmatx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          husart->ErrorCode = HAL_USART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Disable the USART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if (husart->hdmarx != NULL)
-    {
-      /* Set the USART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      husart->hdmarx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          husart->ErrorCode = HAL_USART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Tx and Rx transfer counters */
-  husart->TxXferCount = 0U;
-  husart->RxXferCount = 0U;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
-
-
-  /* Discard the received data */
-  __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
-
-  /* Restore husart->State to Ready */
-  husart->State  = HAL_USART_STATE_READY;
-
-  /* Reset Handle ErrorCode to No Error */
-  husart->ErrorCode = HAL_USART_ERROR_NONE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfers (Interrupt mode).
-  * @param  husart USART handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable USART Interrupts (Tx and Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
-{
-  uint32_t abortcplt = 1U;
-
-  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-  /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
-     before any call to DMA Abort functions */
-  /* DMA Tx Handle is valid */
-  if (husart->hdmatx != NULL)
-  {
-    /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
-    {
-      husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
-    }
-    else
-    {
-      husart->hdmatx->XferAbortCallback = NULL;
-    }
-  }
-  /* DMA Rx Handle is valid */
-  if (husart->hdmarx != NULL)
-  {
-    /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
-    {
-      husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
-    }
-    else
-    {
-      husart->hdmarx->XferAbortCallback = NULL;
-    }
-  }
-
-  /* Disable the USART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
-  {
-    /* Disable DMA Tx at USART level */
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
-    if (husart->hdmatx != NULL)
-    {
-      /* USART Tx DMA Abort callback has already been initialised :
-         will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
-      {
-        husart->hdmatx->XferAbortCallback = NULL;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-
-  /* Disable the USART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
-    if (husart->hdmarx != NULL)
-    {
-      /* USART Rx DMA Abort callback has already been initialised :
-         will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
-      {
-        husart->hdmarx->XferAbortCallback = NULL;
-        abortcplt = 1U;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-
-  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
-  if (abortcplt == 1U)
-  {
-    /* Reset Tx and Rx transfer counters */
-    husart->TxXferCount = 0U;
-    husart->RxXferCount = 0U;
-
-    /* Reset errorCode */
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-
-    /* Clear the Error flags in the ICR register */
-    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
-
-
-    /* Discard the received data */
-    __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
-
-    /* Restore husart->State to Ready */
-    husart->State  = HAL_USART_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Complete Callback */
-    husart->AbortCpltCallback(husart);
-#else
-    /* Call legacy weak Abort Complete Callback */
-    HAL_USART_AbortCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle USART interrupt request.
-  * @param  husart USART handle.
-  * @retval None
-  */
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
-{
-  uint32_t isrflags   = READ_REG(husart->Instance->ISR);
-  uint32_t cr1its     = READ_REG(husart->Instance->CR1);
-  uint32_t cr3its     = READ_REG(husart->Instance->CR3);
-
-  uint32_t errorflags;
-  uint32_t errorcode;
-
-  /* If no error occurs */
-  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
-  if (errorflags == 0U)
-  {
-    /* USART in mode Receiver ---------------------------------------------------*/
-    if (((isrflags & USART_ISR_RXNE) != 0U)
-        && ((cr1its & USART_CR1_RXNEIE) != 0U))
-    {
-      if (husart->RxISR != NULL)
-      {
-        husart->RxISR(husart);
-      }
-      return;
-    }
-  }
-
-  /* If some errors occur */
-  if ((errorflags != 0U)
-      && (((cr3its & USART_CR3_EIE) != 0U)
-          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
-  {
-    /* USART parity error interrupt occurred -------------------------------------*/
-    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
-    {
-      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
-
-      husart->ErrorCode |= HAL_USART_ERROR_PE;
-    }
-
-    /* USART frame error interrupt occurred --------------------------------------*/
-    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
-    {
-      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
-
-      husart->ErrorCode |= HAL_USART_ERROR_FE;
-    }
-
-    /* USART noise error interrupt occurred --------------------------------------*/
-    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
-    {
-      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
-
-      husart->ErrorCode |= HAL_USART_ERROR_NE;
-    }
-
-    /* USART Over-Run interrupt occurred -----------------------------------------*/
-    if (((isrflags & USART_ISR_ORE) != 0U)
-        && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
-            ((cr3its & USART_CR3_EIE) != 0U)))
-    {
-      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
-
-      husart->ErrorCode |= HAL_USART_ERROR_ORE;
-    }
-
-    /* USART Receiver Timeout interrupt occurred ---------------------------------*/
-    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
-    {
-      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
-
-      husart->ErrorCode |= HAL_USART_ERROR_RTO;
-    }
-
-
-    /* Call USART Error Call back function if need be --------------------------*/
-    if (husart->ErrorCode != HAL_USART_ERROR_NONE)
-    {
-      /* USART in mode Receiver ---------------------------------------------------*/
-      if (((isrflags & USART_ISR_RXNE) != 0U)
-          && ((cr1its & USART_CR1_RXNEIE) != 0U))
-      {
-        if (husart->RxISR != NULL)
-        {
-          husart->RxISR(husart);
-        }
-      }
-
-      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
-         consider error as blocking */
-      errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE;
-      if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) ||
-          (errorcode != 0U))
-      {
-        /* Blocking error : transfer is aborted
-           Set the USART state ready to be able to start again the process,
-           Disable Interrupts, and disable DMA requests, if ongoing */
-        USART_EndTransfer(husart);
-
-        /* Disable the USART DMA Rx request if enabled */
-        if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
-        {
-          CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
-
-          /* Abort the USART DMA Tx channel */
-          if (husart->hdmatx != NULL)
-          {
-            /* Set the USART Tx DMA Abort callback to NULL : no callback
-               executed at end of DMA abort procedure */
-            husart->hdmatx->XferAbortCallback = NULL;
-
-            /* Abort DMA TX */
-            (void)HAL_DMA_Abort_IT(husart->hdmatx);
-          }
-
-          /* Abort the USART DMA Rx channel */
-          if (husart->hdmarx != NULL)
-          {
-            /* Set the USART Rx DMA Abort callback :
-               will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
-            husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
-
-            /* Abort DMA RX */
-            if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
-            {
-              /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
-              husart->hdmarx->XferAbortCallback(husart->hdmarx);
-            }
-          }
-          else
-          {
-            /* Call user error callback */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-            /* Call registered Error Callback */
-            husart->ErrorCallback(husart);
-#else
-            /* Call legacy weak Error Callback */
-            HAL_USART_ErrorCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-          }
-        }
-        else
-        {
-          /* Call user error callback */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-          /* Call registered Error Callback */
-          husart->ErrorCallback(husart);
-#else
-          /* Call legacy weak Error Callback */
-          HAL_USART_ErrorCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-        }
-      }
-      else
-      {
-        /* Non Blocking error : transfer could go on.
-           Error is notified to user through user error callback */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-        /* Call registered Error Callback */
-        husart->ErrorCallback(husart);
-#else
-        /* Call legacy weak Error Callback */
-        HAL_USART_ErrorCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-        husart->ErrorCode = HAL_USART_ERROR_NONE;
-      }
-    }
-    return;
-
-  } /* End if some error occurs */
-
-
-  /* USART in mode Transmitter ------------------------------------------------*/
-  if (((isrflags & USART_ISR_TXE) != 0U)
-      && ((cr1its & USART_CR1_TXEIE) != 0U))
-  {
-    if (husart->TxISR != NULL)
-    {
-      husart->TxISR(husart);
-    }
-    return;
-  }
-
-  /* USART in mode Transmitter (transmission end) -----------------------------*/
-  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
-  {
-    USART_EndTransmit_IT(husart);
-    return;
-  }
-
-}
-
-/**
-  * @brief Tx Transfer completed callback.
-  * @param husart USART handle.
-  * @retval None
-  */
-__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_USART_TxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callback.
-  * @param husart USART handle.
-  * @retval None
-  */
-__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callback.
-  * @param husart USART handle.
-  * @retval None
-  */
-__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_USART_RxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief Rx Half Transfer completed callback.
-  * @param husart USART handle.
-  * @retval None
-  */
-__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_USART_RxHalfCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief Tx/Rx Transfers completed callback for the non-blocking process.
-  * @param husart USART handle.
-  * @retval None
-  */
-__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_USART_TxRxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief USART error callback.
-  * @param husart USART handle.
-  * @retval None
-  */
-__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_USART_ErrorCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  USART Abort Complete callback.
-  * @param  husart USART handle.
-  * @retval None
-  */
-__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_USART_AbortCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
-  *  @brief   USART Peripheral State and Error functions
-  *
-@verbatim
-  ==============================================================================
-            ##### Peripheral State and Error functions #####
-  ==============================================================================
-    [..]
-    This subsection provides functions allowing to :
-      (+) Return the USART handle state
-      (+) Return the USART handle error code
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief Return the USART handle state.
-  * @param husart pointer to a USART_HandleTypeDef structure that contains
-  *              the configuration information for the specified USART.
-  * @retval USART handle state
-  */
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
-{
-  return husart->State;
-}
-
-/**
-  * @brief Return the USART error code.
-  * @param husart pointer to a USART_HandleTypeDef structure that contains
-  *              the configuration information for the specified USART.
-  * @retval USART handle Error Code
-  */
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
-{
-  return husart->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Functions USART Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Initialize the callbacks to their default values.
-  * @param  husart USART handle.
-  * @retval none
-  */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
-{
-  /* Init the USART Callback settings */
-  husart->TxHalfCpltCallback        = HAL_USART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
-  husart->TxCpltCallback            = HAL_USART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
-  husart->RxHalfCpltCallback        = HAL_USART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
-  husart->RxCpltCallback            = HAL_USART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
-  husart->TxRxCpltCallback          = HAL_USART_TxRxCpltCallback;          /* Legacy weak TxRxCpltCallback          */
-  husart->ErrorCallback             = HAL_USART_ErrorCallback;             /* Legacy weak ErrorCallback             */
-  husart->AbortCpltCallback         = HAL_USART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
-}
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/**
-  * @brief  End ongoing transfer on USART peripheral (following error detection or Transfer completion).
-  * @param  husart USART handle.
-  * @retval None
-  */
-static void USART_EndTransfer(USART_HandleTypeDef *husart)
-{
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-  /* At end of process, restore husart->State to Ready */
-  husart->State = HAL_USART_STATE_READY;
-}
-
-/**
-  * @brief DMA USART transmit process complete callback.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
-
-  /* DMA Normal mode */
-  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
-  {
-    husart->TxXferCount = 0U;
-
-    if (husart->State == HAL_USART_STATE_BUSY_TX)
-    {
-      /* Disable the DMA transfer for transmit request by resetting the DMAT bit
-         in the USART CR3 register */
-      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-      /* Enable the USART Transmit Complete Interrupt */
-      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
-    }
-  }
-  /* DMA Circular mode */
-  else
-  {
-    if (husart->State == HAL_USART_STATE_BUSY_TX)
-    {
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-      /* Call registered Tx Complete Callback */
-      husart->TxCpltCallback(husart);
-#else
-      /* Call legacy weak Tx Complete Callback */
-      HAL_USART_TxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-    }
-  }
-}
-
-/**
-  * @brief DMA USART transmit process half complete callback.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Tx Half Complete Callback */
-  husart->TxHalfCpltCallback(husart);
-#else
-  /* Call legacy weak Tx Half Complete Callback */
-  HAL_USART_TxHalfCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief DMA USART receive process complete callback.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
-
-  /* DMA Normal mode */
-  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
-  {
-    husart->RxXferCount = 0U;
-
-    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
-       in USART CR3 register */
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-    /* similarly, disable the DMA TX transfer that was started to provide the
-       clock to the slave device */
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-    if (husart->State == HAL_USART_STATE_BUSY_RX)
-    {
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-      /* Call registered Rx Complete Callback */
-      husart->RxCpltCallback(husart);
-#else
-      /* Call legacy weak Rx Complete Callback */
-      HAL_USART_RxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-    }
-    /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
-    else
-    {
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-      /* Call registered Tx Rx Complete Callback */
-      husart->TxRxCpltCallback(husart);
-#else
-      /* Call legacy weak Tx Rx Complete Callback */
-      HAL_USART_TxRxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-    }
-    husart->State = HAL_USART_STATE_READY;
-  }
-  /* DMA circular mode */
-  else
-  {
-    if (husart->State == HAL_USART_STATE_BUSY_RX)
-    {
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-      /* Call registered Rx Complete Callback */
-      husart->RxCpltCallback(husart);
-#else
-      /* Call legacy weak Rx Complete Callback */
-      HAL_USART_RxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-    }
-    /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
-    else
-    {
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-      /* Call registered Tx Rx Complete Callback */
-      husart->TxRxCpltCallback(husart);
-#else
-      /* Call legacy weak Tx Rx Complete Callback */
-      HAL_USART_TxRxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-    }
-  }
-}
-
-/**
-  * @brief DMA USART receive process half complete callback.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Rx Half Complete Callback */
-  husart->RxHalfCpltCallback(husart);
-#else
-  /* Call legacy weak Rx Half Complete Callback */
-  HAL_USART_RxHalfCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief DMA USART communication error callback.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void USART_DMAError(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
-
-  husart->RxXferCount = 0U;
-  husart->TxXferCount = 0U;
-  USART_EndTransfer(husart);
-
-  husart->ErrorCode |= HAL_USART_ERROR_DMA;
-  husart->State = HAL_USART_STATE_READY;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Error Callback */
-  husart->ErrorCallback(husart);
-#else
-  /* Call legacy weak Error Callback */
-  HAL_USART_ErrorCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
-  husart->RxXferCount = 0U;
-  husart->TxXferCount = 0U;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Error Callback */
-  husart->ErrorCallback(husart);
-#else
-  /* Call legacy weak Error Callback */
-  HAL_USART_ErrorCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA USART Tx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Rx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
-
-  husart->hdmatx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (husart->hdmarx != NULL)
-  {
-    if (husart->hdmarx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  husart->TxXferCount = 0U;
-  husart->RxXferCount = 0U;
-
-  /* Reset errorCode */
-  husart->ErrorCode = HAL_USART_ERROR_NONE;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
-
-  /* Restore husart->State to Ready */
-  husart->State = HAL_USART_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Complete Callback */
-  husart->AbortCpltCallback(husart);
-#else
-  /* Call legacy weak Abort Complete Callback */
-  HAL_USART_AbortCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-}
-
-
-/**
-  * @brief  DMA USART Rx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Tx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
-
-  husart->hdmarx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (husart->hdmatx != NULL)
-  {
-    if (husart->hdmatx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  husart->TxXferCount = 0U;
-  husart->RxXferCount = 0U;
-
-  /* Reset errorCode */
-  husart->ErrorCode = HAL_USART_ERROR_NONE;
-
-  /* Clear the Error flags in the ICR register */
-  __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
-
-  /* Restore husart->State to Ready */
-  husart->State  = HAL_USART_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Complete Callback */
-  husart->AbortCpltCallback(husart);
-#else
-  /* Call legacy weak Abort Complete Callback */
-  HAL_USART_AbortCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}
-
-
-/**
-  * @brief  Handle USART Communication Timeout.
-  * @param  husart USART handle.
-  * @param  Flag Specifies the USART flag to check.
-  * @param  Status the Flag status (SET or RESET).
-  * @param  Tickstart Tick start value
-  * @param  Timeout timeout duration.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
-                                                      uint32_t Tickstart, uint32_t Timeout)
-{
-  /* Wait until flag is set */
-  while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-      {
-        husart->State = HAL_USART_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(husart);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief Configure the USART peripheral.
-  * @param husart USART handle.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
-{
-  uint32_t tmpreg;
-  USART_ClockSourceTypeDef clocksource;
-  HAL_StatusTypeDef ret                = HAL_OK;
-  uint16_t brrtemp;
-  uint32_t usartdiv                    = 0x00000000;
-  uint32_t pclk;
-
-  /* Check the parameters */
-  assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
-  assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
-  assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
-  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
-  assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
-  assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
-  assert_param(IS_USART_PARITY(husart->Init.Parity));
-  assert_param(IS_USART_MODE(husart->Init.Mode));
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  /* Clear M, PCE, PS, TE and RE bits and configure
-  *  the USART Word Length, Parity and Mode:
-  *  set the M bits according to husart->Init.WordLength value
-  *  set PCE and PS bits according to husart->Init.Parity value
-  *  set TE and RE bits according to husart->Init.Mode value
-  *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
-  tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
-  MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
-
-  /*---------------------------- USART CR2 Configuration ---------------------*/
-  /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
-   * set CPOL bit according to husart->Init.CLKPolarity value
-   * set CPHA bit according to husart->Init.CLKPhase value
-   * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
-   * set STOP[13:12] bits according to husart->Init.StopBits value */
-  tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
-  tmpreg |= (uint32_t)husart->Init.CLKLastBit;
-  tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
-  tmpreg |= (uint32_t)husart->Init.StopBits;
-  MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
-
-
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */
-  USART_GETCLOCKSOURCE(husart, clocksource);
-
-  switch (clocksource)
-  {
-    case USART_CLOCKSOURCE_PCLK1:
-      pclk = HAL_RCC_GetPCLK1Freq();
-      usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate));
-      break;
-    case USART_CLOCKSOURCE_PCLK2:
-      pclk = HAL_RCC_GetPCLK2Freq();
-      usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate));
-      break;
-    case USART_CLOCKSOURCE_HSI:
-      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
-      {
-        usartdiv = (uint32_t)(USART_DIV_SAMPLING8((HSI_VALUE >> 2U), husart->Init.BaudRate));
-      }
-      else
-      {
-        usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate));
-      }
-      break;
-    case USART_CLOCKSOURCE_SYSCLK:
-      pclk = HAL_RCC_GetSysClockFreq();
-      usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate));
-      break;
-    case USART_CLOCKSOURCE_LSE:
-      usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate));
-      break;
-    default:
-      ret = HAL_ERROR;
-      break;
-  }
-
-  /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */
-  if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX))
-  {
-    brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
-    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
-    husart->Instance->BRR = brrtemp;
-  }
-  else
-  {
-    ret = HAL_ERROR;
-  }
-
-
-  /* Clear ISR function pointers */
-  husart->RxISR   = NULL;
-  husart->TxISR   = NULL;
-
-  return ret;
-}
-
-/**
-  * @brief Check the USART Idle State.
-  * @param husart USART handle.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
-{
-  uint32_t tickstart;
-
-  /* Initialize the USART ErrorCode */
-  husart->ErrorCode = HAL_USART_ERROR_NONE;
-
-  /* Init tickstart for timeout management */
-  tickstart = HAL_GetTick();
-
-  /* Check if the Transmitter is enabled */
-  if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
-  {
-    /* Wait until TEACK flag is set */
-    if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
-    {
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
-    }
-  }
-  /* Check if the Receiver is enabled */
-  if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
-  {
-    /* Wait until REACK flag is set */
-    if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
-    {
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Initialize the USART state*/
-  husart->State = HAL_USART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(husart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Simplex send an amount of data in non-blocking mode.
-  * @note   Function called under interruption only, once
-  *         interruptions have been enabled by HAL_USART_Transmit_IT().
-  * @note   The USART errors are not managed to avoid the overrun error.
-  * @note   ISR function executed when data word length is less than 9 bits long.
-  * @param  husart USART handle.
-  * @retval None
-  */
-static void USART_TxISR_8BIT(USART_HandleTypeDef *husart)
-{
-  const HAL_USART_StateTypeDef state = husart->State;
-
-  /* Check that a Tx process is ongoing */
-  if ((state == HAL_USART_STATE_BUSY_TX) ||
-      (state == HAL_USART_STATE_BUSY_TX_RX))
-  {
-    if (husart->TxXferCount == 0U)
-    {
-      /* Disable the USART Transmit data register empty interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-
-      /* Enable the USART Transmit Complete Interrupt */
-      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
-    }
-    else
-    {
-      husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
-      husart->pTxBuffPtr++;
-      husart->TxXferCount--;
-    }
-  }
-}
-
-/**
-  * @brief  Simplex send an amount of data in non-blocking mode.
-  * @note   Function called under interruption only, once
-  *         interruptions have been enabled by HAL_USART_Transmit_IT().
-  * @note   The USART errors are not managed to avoid the overrun error.
-  * @note   ISR function executed when data word length is 9 bits long.
-  * @param  husart USART handle.
-  * @retval None
-  */
-static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
-{
-  const HAL_USART_StateTypeDef state = husart->State;
-  uint16_t *tmp;
-
-  if ((state == HAL_USART_STATE_BUSY_TX) ||
-      (state == HAL_USART_STATE_BUSY_TX_RX))
-  {
-    if (husart->TxXferCount == 0U)
-    {
-      /* Disable the USART Transmit data register empty interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-
-      /* Enable the USART Transmit Complete Interrupt */
-      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
-    }
-    else
-    {
-      tmp = (uint16_t *) husart->pTxBuffPtr;
-      husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
-      husart->pTxBuffPtr += 2U;
-      husart->TxXferCount--;
-    }
-  }
-}
-
-
-/**
-  * @brief  Wraps up transmission in non-blocking mode.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-static void USART_EndTransmit_IT(USART_HandleTypeDef *husart)
-{
-  /* Disable the USART Transmit Complete Interrupt */
-  __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
-
-  /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-  __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
-  /* Clear TxISR function pointer */
-  husart->TxISR = NULL;
-
-  if (husart->State == HAL_USART_STATE_BUSY_TX)
-  {
-    /* Clear overrun flag and discard the received data */
-    __HAL_USART_CLEAR_OREFLAG(husart);
-    __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
-
-    /* Tx process is completed, restore husart->State to Ready */
-    husart->State = HAL_USART_STATE_READY;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-    /* Call registered Tx Complete Callback */
-    husart->TxCpltCallback(husart);
-#else
-    /* Call legacy weak Tx Complete Callback */
-    HAL_USART_TxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-  }
-  else if (husart->RxXferCount == 0U)
-  {
-    /* TxRx process is completed, restore husart->State to Ready */
-    husart->State = HAL_USART_STATE_READY;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-    /* Call registered Tx Rx Complete Callback */
-    husart->TxRxCpltCallback(husart);
-#else
-    /* Call legacy weak Tx Rx Complete Callback */
-    HAL_USART_TxRxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-}
-
-
-/**
-  * @brief  Simplex receive an amount of data in non-blocking mode.
-  * @note   Function called under interruption only, once
-  *         interruptions have been enabled by HAL_USART_Receive_IT().
-  * @note   ISR function executed when data word length is less than 9 bits long.
-  * @param  husart USART handle
-  * @retval None
-  */
-static void USART_RxISR_8BIT(USART_HandleTypeDef *husart)
-{
-  const HAL_USART_StateTypeDef state = husart->State;
-  uint16_t txdatacount;
-  uint16_t uhMask = husart->Mask;
-
-  if ((state == HAL_USART_STATE_BUSY_RX) ||
-      (state == HAL_USART_STATE_BUSY_TX_RX))
-  {
-    *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
-    husart->pRxBuffPtr++;
-    husart->RxXferCount--;
-
-    if (husart->RxXferCount == 0U)
-    {
-      /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
-      CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
-      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-      /* Clear RxISR function pointer */
-      husart->RxISR = NULL;
-
-      /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
-      txdatacount = husart->TxXferCount;
-
-      if (state == HAL_USART_STATE_BUSY_RX)
-      {
-
-        /* Rx process is completed, restore husart->State to Ready */
-        husart->State = HAL_USART_STATE_READY;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-        /* Call registered Rx Complete Callback */
-        husart->RxCpltCallback(husart);
-#else
-        /* Call legacy weak Rx Complete Callback */
-        HAL_USART_RxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-      }
-      else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
-               (txdatacount == 0U))
-      {
-        /* TxRx process is completed, restore husart->State to Ready */
-        husart->State = HAL_USART_STATE_READY;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-        /* Call registered Tx Rx Complete Callback */
-        husart->TxRxCpltCallback(husart);
-#else
-        /* Call legacy weak Tx Rx Complete Callback */
-        HAL_USART_TxRxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-      }
-      else
-      {
-        /* Nothing to do */
-      }
-    }
-    else if (state == HAL_USART_STATE_BUSY_RX)
-    {
-      /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
-      husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-  }
-}
-
-/**
-  * @brief  Simplex receive an amount of data in non-blocking mode.
-  * @note   Function called under interruption only, once
-  *         interruptions have been enabled by HAL_USART_Receive_IT().
-  * @note   ISR function executed when data word length is 9 bits long.
-  * @param  husart USART handle
-  * @retval None
-  */
-static void USART_RxISR_16BIT(USART_HandleTypeDef *husart)
-{
-  const HAL_USART_StateTypeDef state = husart->State;
-  uint16_t txdatacount;
-  uint16_t *tmp;
-  uint16_t uhMask = husart->Mask;
-
-  if ((state == HAL_USART_STATE_BUSY_RX) ||
-      (state == HAL_USART_STATE_BUSY_TX_RX))
-  {
-    tmp = (uint16_t *) husart->pRxBuffPtr;
-    *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
-    husart->pRxBuffPtr += 2U;
-    husart->RxXferCount--;
-
-    if (husart->RxXferCount == 0U)
-    {
-      /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
-      CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
-      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-      /* Clear RxISR function pointer */
-      husart->RxISR = NULL;
-
-      /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
-      txdatacount = husart->TxXferCount;
-
-      if (state == HAL_USART_STATE_BUSY_RX)
-      {
-
-        /* Rx process is completed, restore husart->State to Ready */
-        husart->State = HAL_USART_STATE_READY;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-        /* Call registered Rx Complete Callback */
-        husart->RxCpltCallback(husart);
-#else
-        /* Call legacy weak Rx Complete Callback */
-        HAL_USART_RxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-      }
-      else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
-               (txdatacount == 0U))
-      {
-        /* TxRx process is completed, restore husart->State to Ready */
-        husart->State = HAL_USART_STATE_READY;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-        /* Call registered Tx Rx Complete Callback */
-        husart->TxRxCpltCallback(husart);
-#else
-        /* Call legacy weak Tx Rx Complete Callback */
-        HAL_USART_TxRxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-      }
-      else
-      {
-        /* Nothing to do */
-      }
-    }
-    else if (state == HAL_USART_STATE_BUSY_RX)
-    {
-      /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
-      husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-  }
-}
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_USART_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_wwdg.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_wwdg.c
deleted file mode 100644
index c298bdcc0b..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_wwdg.c
+++ /dev/null
@@ -1,422 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_wwdg.c
-  * @author  MCD Application Team
-  * @brief   WWDG HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Window Watchdog (WWDG) peripheral:
-  *           + Initialization and Configuration functions
-  *           + IO operation functions
-  @verbatim
-  ==============================================================================
-                      ##### WWDG Specific features #####
-  ==============================================================================
-  [..]
-    Once enabled the WWDG generates a system reset on expiry of a programmed
-    time period, unless the program refreshes the counter (T[6;0] downcounter)
-    before reaching 0x3F value (i.e. a reset is generated when the counter
-    value rolls down from 0x40 to 0x3F).
-
-    (+) An MCU reset is also generated if the counter value is refreshed
-        before the counter has reached the refresh window value. This
-        implies that the counter must be refreshed in a limited window.
-    (+) Once enabled the WWDG cannot be disabled except by a system reset.
-    (+) If required by application, an Early Wakeup Interrupt can be triggered
-        in order to be warned before WWDG expiration. The Early Wakeup Interrupt
-        (EWI) can be used if specific safety operations or data logging must
-        be performed before the actual reset is generated. When the downcounter
-        reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
-        line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
-        disabled except by a system reset.
-    (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
-        reset occurs.
-    (+) The WWDG counter input clock is derived from the APB clock divided
-        by a programmable prescaler.
-    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
-    (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
-        where T[5;0] are the lowest 6 bits of Counter.
-    (+) WWDG Counter refresh is allowed between the following limits :
-        (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
-        (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
-    (+) Typical values:
-        (++) Counter min (T[5;0] = 0x00) at 32MHz (PCLK1) with zero prescaler:
-             max timeout before reset: approximately 41.79�s
-        (++) Counter max (T[5;0] = 0x3F) at 32MHz (PCLK1) with prescaler
-             dividing by 8:
-             max timeout before reset: approximately 342.38ms
-
-                     ##### How to use this driver #####
-  ==============================================================================
-
-    *** Common driver usage ***
-    ===========================
-
-  [..]
-    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
-    (+) Configure the WWDG prescaler, refresh window value, counter value and early
-        interrupt status using HAL_WWDG_Init() function. This will automatically
-        enable WWDG and start its downcounter. Time reference can be taken from 
-        function exit. Care must be taken to provide a counter value
-        greater than 0x40 to prevent generation of immediate reset.
-    (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
-        generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
-        triggered by the interrupt service routine, flag will be automatically
-        cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
-        can add his own code by customization of callback HAL_WWDG_WakeupCallback.
-    (+) Then the application program must refresh the WWDG counter at regular
-        intervals during normal operation to prevent an MCU reset, using
-        HAL_WWDG_Refresh() function. This operation must occur only when
-        the counter is lower than the refresh window value already programmed.
-
-    *** Callback registration ***
-    =============================
-
-  [..]
-    The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
-    the user to configure dynamically the driver callbacks. Use Functions
-    HAL_WWDG_RegisterCallback() to register a user callback.
-
-    (+) Function HAL_WWDG_RegisterCallback() allows to register following
-        callbacks:
-        (++) EwiCallback : callback for Early WakeUp Interrupt.
-        (++) MspInitCallback : WWDG MspInit.
-    This function takes as parameters the HAL peripheral handle, the Callback ID
-    and a pointer to the user callback function.
-
-    (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
-    the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
-    takes as parameters the HAL peripheral handle and the Callback ID.
-    This function allows to reset following callbacks:
-        (++) EwiCallback : callback for  Early WakeUp Interrupt.
-        (++) MspInitCallback : WWDG MspInit.
-
-    [..]
-    When calling HAL_WWDG_Init function, callbacks are reset to the
-    corresponding legacy weak (surcharged) functions:
-    HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
-    not been registered before.
-
-    [..]
-    When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
-    not defined, the callback registering feature is not available
-    and weak (surcharged) callbacks are used.
-
-    *** WWDG HAL driver macros list ***
-    ===================================
-    [..]
-      Below the list of available macros in WWDG HAL driver.
-      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
-      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
-      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
-      (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
-/** @defgroup WWDG WWDG
-  * @brief WWDG HAL module driver.
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
-  * @{
-  */
-
-/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
-  *  @brief    Initialization and Configuration functions.
-  *
-@verbatim
-  ==============================================================================
-          ##### Initialization and Configuration functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-      (+) Initialize and start the WWDG according to the specified parameters
-          in the WWDG_InitTypeDef of associated handle.
-      (+) Initialize the WWDG MSP.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the WWDG according to the specified.
-  *         parameters in the WWDG_InitTypeDef of  associated handle.
-  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified WWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Check the WWDG handle allocation */
-  if (hwwdg == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
-  assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
-  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
-  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
-  assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-  /* Reset Callback pointers */
-  if (hwwdg->EwiCallback == NULL)
-  {
-    hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
-  }
-
-  if (hwwdg->MspInitCallback == NULL)
-  {
-    hwwdg->MspInitCallback = HAL_WWDG_MspInit;
-  }
-
-  /* Init the low level hardware */
-  hwwdg->MspInitCallback(hwwdg);
-#else
-  /* Init the low level hardware */
-  HAL_WWDG_MspInit(hwwdg);
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-
-  /* Set WWDG Counter */
-  WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
-
-  /* Set WWDG Prescaler and Window */
-  WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Initialize the WWDG MSP.
-  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified WWDG module.
-  * @note   When rewriting this function in user file, mechanism may be added
-  *         to avoid multiple initialize when HAL_WWDG_Init function is called
-  *         again to change parameters.
-  * @retval None
-  */
-__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hwwdg);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_WWDG_MspInit could be implemented in the user file
-   */
-}
-
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User WWDG Callback
-  *         To be used instead of the weak (surcharged) predefined callback
-  * @param  hwwdg WWDG handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
-  *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
-                                            pWWDG_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    switch (CallbackID)
-    {
-      case HAL_WWDG_EWI_CB_ID:
-        hwwdg->EwiCallback = pCallback;
-        break;
-
-      case HAL_WWDG_MSPINIT_CB_ID:
-        hwwdg->MspInitCallback = pCallback;
-        break;
-
-      default:
-        status = HAL_ERROR;
-        break;
-    }
-  }
-
-  return status;
-}
-
-
-/**
-  * @brief  Unregister a WWDG Callback
-  *         WWDG Callback is redirected to the weak (surcharged) predefined callback
-  * @param  hwwdg WWDG handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
-  *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  switch (CallbackID)
-  {
-    case HAL_WWDG_EWI_CB_ID:
-      hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
-      break;
-
-    case HAL_WWDG_MSPINIT_CB_ID:
-      hwwdg->MspInitCallback = HAL_WWDG_MspInit;
-      break;
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  return status;
-}
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
-  *  @brief    IO operation functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Refresh the WWDG.
-    (+) Handle WWDG interrupt request and associated function callback.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Refresh the WWDG.
-  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified WWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Write to WWDG CR the WWDG Counter value to refresh with */
-  WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle WWDG interrupt request.
-  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
-  *         or data logging must be performed before the actual reset is generated.
-  *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
-  *         EWIMode set to WWDG_EWI_ENABLE.
-  *         When the downcounter reaches the value 0x40, and EWI interrupt is
-  *         generated and the corresponding Interrupt Service Routine (ISR) can
-  *         be used to trigger specific actions (such as communications or data
-  *         logging), before resetting the device.
-  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified WWDG module.
-  * @retval None
-  */
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Check if Early Wakeup Interrupt is enable */
-  if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
-  {
-    /* Check if WWDG Early Wakeup Interrupt occurred */
-    if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
-    {
-      /* Clear the WWDG Early Wakeup flag */
-      __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-      /* Early Wakeup registered callback */
-      hwwdg->EwiCallback(hwwdg);
-#else
-      /* Early Wakeup callback */
-      HAL_WWDG_EarlyWakeupCallback(hwwdg);
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-    }
-  }
-}
-
-
-/**
-  * @brief  WWDG Early Wakeup callback.
-  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified WWDG module.
-  * @retval None
-  */
-__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hwwdg);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_WWDG_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c
deleted file mode 100644
index 3b88320aaf..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c
+++ /dev/null
@@ -1,670 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_adc.c
-  * @author  MCD Application Team
-  * @brief   ADC LL module driver
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_adc.h"
-#include "stm32l0xx_ll_bus.h"
-
-#ifdef  USE_FULL_ASSERT
-  #include "stm32_assert.h"
-#else
-  #define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (ADC1)
-
-/** @addtogroup ADC_LL ADC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup ADC_LL_Private_Constants
-  * @{
-  */
-
-/* Definitions of ADC hardware constraints delays */
-/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
-/*       not timeout values:                                                  */
-/*       Timeout values for ADC operations are dependent to device clock      */
-/*       configuration (system clock versus ADC clock),                       */
-/*       and therefore must be defined in user application.                   */
-/*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
-/*       values definition.                                                   */
-/* Note: ADC timeout values are defined here in CPU cycles to be independent  */
-/*       of device clock setting.                                             */
-/*       In user application, ADC timeout values should be defined with       */
-/*       temporal values, in function of device clock settings.               */
-/*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
-/*        - ADC clock from synchronous clock with AHB prescaler 512,          */
-/*          APB prescaler 16, ADC prescaler 4.                                */
-/*        - ADC clock from asynchronous clock (HSI) with prescaler 1,         */
-/*          with highest ratio CPU clock frequency vs HSI clock frequency:    */
-/*          CPU clock frequency max 32MHz, HSI frequency 16MHz: ratio 2.      */
-/* Unit: CPU cycles.                                                          */
-#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          ((uint32_t) 512U * 16U * 4U)
-#define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
-#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup ADC_LL_Private_Macros
-  * @{
-  */
-
-/* Check of parameters for configuration of ADC hierarchical scope:           */
-/* common to several ADC instances.                                           */
-#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
-  (   ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
-  )
-
-#define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__)                         \
-  (   ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH)                   \
-   || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW)                    \
-  )
-
-/* Check of parameters for configuration of ADC hierarchical scope:           */
-/* ADC instance.                                                              */
-#define IS_LL_ADC_CLOCK(__CLOCK__)                                             \
-  (   ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
-   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
-   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC)                                      \
-  )
-
-#define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
-  (   ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \
-   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
-   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
-   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
-  )
-
-#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
-  (   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
-   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
-  )
-
-#define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
-  (   ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                 \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF)                              \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF)                     \
-  )
-
-/* Check of parameters for configuration of ADC hierarchical scope:           */
-/* ADC group regular                                                          */
-/* ADC group regular external trigger TIM2_CC3 available only on              */
-/* STM32L0 devices categories: Cat.1, Cat.2, Cat.5                            */
-#if defined (STM32L011xx) || defined (STM32L021xx) || \
-    defined (STM32L031xx) || defined (STM32L041xx) || \
-    defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
-    defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
-  (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM21_CH2)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4)                  \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM22_TRGO)                \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)                  \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
-  )
-#else
-#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
-  (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM21_CH2)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4)                  \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM22_TRGO)                \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
-  )
-#endif
-
-#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
-  (   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
-   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
-  )
-
-#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
-  (   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
-   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
-   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
-  )
-
-#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
-  (   ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)           \
-   || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
-  )
-
-#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
-  (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
-   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
-  )
-
-/**
-  * @}
-  */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADC_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize registers of all ADC instances belonging to
-  *         the same ADC common instance to their default reset values.
-  * @note   This function is performing a hard reset, using high level
-  *         clock source RCC ADC reset.
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ADC common registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
-  
-  /* Force reset of ADC clock (core clock) */
-  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1);
-  
-  /* Release reset of ADC clock (core clock) */
-  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
-  
-  return SUCCESS;
-}
-
-/**
-  * @brief  Initialize some features of ADC common parameters
-  *         (all ADC instances belonging to the same ADC common instance)
-  *         and multimode (for devices with several ADC instances available).
-  * @note   The setting of ADC common parameters is conditioned to
-  *         ADC instances state:
-  *         All ADC instances belonging to the same ADC common instance
-  *         must be disabled.
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ADC common registers are initialized
-  *          - ERROR: ADC common registers are not initialized
-  */
-ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
-  assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
-  
-  /* Note: Hardware constraint (refer to description of functions             */
-  /*       "LL_ADC_SetCommonXXX()":                                           */
-  /*       On this STM32 serie, setting of these features is conditioned to   */
-  /*       ADC state:                                                         */
-  /*       All ADC instances of the ADC common group must be disabled.        */
-  if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
-  {
-    /* Configuration of ADC hierarchical scope:                               */
-    /*  - common to several ADC                                               */
-    /*    (all ADC instances belonging to the same ADC common instance)       */
-    /*    - Set ADC clock (conversion clock)                                  */
-    LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
-  }
-  else
-  {
-    /* Initialization error: One or several ADC instances belonging to        */
-    /* the same ADC common instance are not disabled.                         */
-    status = ERROR;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
-  * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
-  *                              whose fields will be set to default values.
-  * @retval None
-  */
-void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
-{
-  /* Set ADC_CommonInitStruct fields to default values */
-  /* Set fields of ADC common */
-  /* (all ADC instances belonging to the same ADC common instance) */
-  ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
-  
-}
-
-/**
-  * @brief  De-initialize registers of the selected ADC instance
-  *         to their default reset values.
-  * @note   To reset all ADC instances quickly (perform a hard reset),
-  *         use function @ref LL_ADC_CommonDeInit().
-  * @note   If this functions returns error status, it means that ADC instance
-  *         is in an unknown state.
-  *         In this case, perform a hard reset using high level
-  *         clock source RCC ADC reset.
-  *         Refer to function @ref LL_ADC_CommonDeInit().
-  * @param  ADCx ADC instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ADC registers are de-initialized
-  *          - ERROR: ADC registers are not de-initialized
-  */
-ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
-{
-  ErrorStatus status = SUCCESS;
-  
-  __IO uint32_t timeout_cpu_cycles = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-  
-  /* Disable ADC instance if not already disabled.                            */
-  if(LL_ADC_IsEnabled(ADCx) == 1U)
-  {
-    /* Set ADC group regular trigger source to SW start to ensure to not      */
-    /* have an external trigger event occurring during the conversion stop    */
-    /* ADC disable process.                                                   */
-    LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
-    
-    /* Stop potential ADC conversion on going on ADC group regular.           */
-    if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
-    {
-      if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
-      {
-        LL_ADC_REG_StopConversion(ADCx);
-      }
-    }
-    
-    /* Wait for ADC conversions are effectively stopped                       */
-    timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
-    while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U)
-    {
-      if(timeout_cpu_cycles-- == 0U)
-      {
-        /* Time-out error */
-        status = ERROR;
-      }
-    }
-    
-    /* Disable the ADC instance */
-    LL_ADC_Disable(ADCx);
-    
-    /* Wait for ADC instance is effectively disabled */
-    timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
-    while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
-    {
-      if(timeout_cpu_cycles-- == 0U)
-      {
-        /* Time-out error */
-        status = ERROR;
-      }
-    }
-  }
-  
-  /* Check whether ADC state is compliant with expected state */
-  if(READ_BIT(ADCx->CR,
-              (  ADC_CR_ADSTP | ADC_CR_ADSTART
-               | ADC_CR_ADDIS | ADC_CR_ADEN   )
-             )
-     == 0U)
-  {
-    /* ========== Reset ADC registers ========== */
-    /* Reset register IER */
-    CLEAR_BIT(ADCx->IER,
-              (  LL_ADC_IT_ADRDY
-               | LL_ADC_IT_EOC
-               | LL_ADC_IT_EOS
-               | LL_ADC_IT_OVR
-               | LL_ADC_IT_EOSMP
-               | LL_ADC_IT_AWD1 )
-             );
-    
-    /* Reset register ISR */
-    SET_BIT(ADCx->ISR,
-            (  LL_ADC_FLAG_ADRDY
-             | LL_ADC_FLAG_EOC
-             | LL_ADC_FLAG_EOS
-             | LL_ADC_FLAG_OVR
-             | LL_ADC_FLAG_EOSMP
-             | LL_ADC_FLAG_AWD1 )
-           );
-    
-    /* Reset register CR */
-    /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode     */
-    /* "read-set": no direct reset applicable.                                */
-    CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
-    
-    /* Reset register CFGR1 */
-    CLEAR_BIT(ADCx->CFGR1,
-              (  ADC_CFGR1_AWDCH   | ADC_CFGR1_AWDEN  | ADC_CFGR1_AWDSGL  | ADC_CFGR1_DISCEN
-               | ADC_CFGR1_AUTOFF  | ADC_CFGR1_WAIT   | ADC_CFGR1_CONT    | ADC_CFGR1_OVRMOD
-               | ADC_CFGR1_EXTEN   | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN   | ADC_CFGR1_RES
-               | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN                     )
-             );
-    
-    /* Reset register CFGR2 */
-    /* Note: Update of ADC clock mode is conditioned to ADC state disabled:   */
-    /*       already done above.                                              */
-    CLEAR_BIT(ADCx->CFGR2,
-              (  ADC_CFGR2_CKMODE
-               | ADC_CFGR2_TOVS   | ADC_CFGR2_OVSS  | ADC_CFGR2_OVSR
-               | ADC_CFGR2_OVSE   | ADC_CFGR2_CKMODE                )
-             );
-    
-    /* Reset register SMPR */
-    CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP);
-
-    /* Reset register TR */
-    MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT);
-    
-    /* Reset register CHSELR */
-#if defined(ADC_CCR_VLCDEN)
-    CLEAR_BIT(ADCx->CHSELR,
-              (  ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
-               | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
-               | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9  | ADC_CHSELR_CHSEL8
-               | ADC_CHSELR_CHSEL7  | ADC_CHSELR_CHSEL6  | ADC_CHSELR_CHSEL5  | ADC_CHSELR_CHSEL4
-               | ADC_CHSELR_CHSEL3  | ADC_CHSELR_CHSEL2  | ADC_CHSELR_CHSEL1  | ADC_CHSELR_CHSEL0 )
-             );
-#else
-    CLEAR_BIT(ADCx->CHSELR,
-              (  ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17
-               | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
-               | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9  | ADC_CHSELR_CHSEL8
-               | ADC_CHSELR_CHSEL7  | ADC_CHSELR_CHSEL6  | ADC_CHSELR_CHSEL5  | ADC_CHSELR_CHSEL4
-               | ADC_CHSELR_CHSEL3  | ADC_CHSELR_CHSEL2  | ADC_CHSELR_CHSEL1  | ADC_CHSELR_CHSEL0 )
-             );
-#endif
-    
-    /* Reset register DR */
-    /* bits in access mode read only, no direct reset applicable */
-    
-    /* Reset register CALFACT */
-    CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
-    
-  }
-  else
-  {
-    /* ADC instance is in an unknown state */
-    /* Need to performing a hard reset of ADC instance, using high level      */
-    /* clock source RCC ADC reset.                                            */
-    /* Caution: On this STM32 serie, if several ADC instances are available   */
-    /*          on the selected device, RCC ADC reset will reset              */
-    /*          all ADC instances belonging to the common ADC instance.       */
-    status = ERROR;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Initialize some features of ADC instance.
-  * @note   These parameters have an impact on ADC scope: ADC instance.
-  *         Refer to corresponding unitary functions into
-  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
-  * @note   The setting of these parameters by function @ref LL_ADC_Init()
-  *         is conditioned to ADC state:
-  *         ADC instance must be disabled.
-  *         This condition is applied to all ADC features, for efficiency
-  *         and compatibility over all STM32 families. However, the different
-  *         features can be set under different ADC state conditions
-  *         (setting possible with ADC enabled without conversion on going,
-  *         ADC enabled with conversion on going, ...)
-  *         Each feature can be updated afterwards with a unitary function
-  *         and potentially with ADC in a different state than disabled,
-  *         refer to description of each function for setting
-  *         conditioned to ADC state.
-  * @note   After using this function, some other features must be configured
-  *         using LL unitary functions.
-  *         The minimum configuration remaining to be done is:
-  *          - Set ADC group regular sequencer:
-  *            map channel on rank corresponding to channel number.
-  *            Refer to function @ref LL_ADC_REG_SetSequencerChannels();
-  *          - Set ADC channel sampling time
-  *            Refer to function LL_ADC_SetChannelSamplingTime();
-  * @param  ADCx ADC instance
-  * @param  ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ADC registers are initialized
-  *          - ERROR: ADC registers are not initialized
-  */
-ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-  
-  assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
-  assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
-  assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
-  assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
-  
-  /* Note: Hardware constraint (refer to description of this function):       */
-  /*       ADC instance must be disabled.                                     */
-  if(LL_ADC_IsEnabled(ADCx) == 0U)
-  {
-    /* Configuration of ADC hierarchical scope:                               */
-    /*  - ADC instance                                                        */
-    /*    - Set ADC data resolution                                           */
-    /*    - Set ADC conversion data alignment                                 */
-    /*    - Set ADC low power mode                                            */
-    MODIFY_REG(ADCx->CFGR1,
-                 ADC_CFGR1_RES
-               | ADC_CFGR1_ALIGN
-               | ADC_CFGR1_WAIT
-               | ADC_CFGR1_AUTOFF
-              ,
-                 ADC_InitStruct->Resolution
-               | ADC_InitStruct->DataAlignment
-               | ADC_InitStruct->LowPowerMode
-              );
-    
-    MODIFY_REG(ADCx->CFGR2,
-               ADC_CFGR2_CKMODE
-              ,
-               ADC_InitStruct->Clock
-              );
-  }
-  else
-  {
-    /* Initialization error: ADC instance is not disabled. */
-    status = ERROR;
-  }
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
-  * @param  ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
-  *                        whose fields will be set to default values.
-  * @retval None
-  */
-void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
-{
-  /* Set ADC_InitStruct fields to default values */
-  /* Set fields of ADC instance */
-  ADC_InitStruct->Clock         = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
-  ADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
-  ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
-  ADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
-  
-}
-
-/**
-  * @brief  Initialize some features of ADC group regular.
-  * @note   These parameters have an impact on ADC scope: ADC group regular.
-  *         Refer to corresponding unitary functions into
-  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
-  *         (functions with prefix "REG").
-  * @note   The setting of these parameters by function @ref LL_ADC_Init()
-  *         is conditioned to ADC state:
-  *         ADC instance must be disabled.
-  *         This condition is applied to all ADC features, for efficiency
-  *         and compatibility over all STM32 families. However, the different
-  *         features can be set under different ADC state conditions
-  *         (setting possible with ADC enabled without conversion on going,
-  *         ADC enabled with conversion on going, ...)
-  *         Each feature can be updated afterwards with a unitary function
-  *         and potentially with ADC in a different state than disabled,
-  *         refer to description of each function for setting
-  *         conditioned to ADC state.
-  * @note   After using this function, other features must be configured
-  *         using LL unitary functions.
-  *         The minimum configuration remaining to be done is:
-  *          - Set ADC group regular sequencer:
-  *            map channel on rank corresponding to channel number.
-  *            Refer to function @ref LL_ADC_REG_SetSequencerChannels();
-  *          - Set ADC channel sampling time
-  *            Refer to function LL_ADC_SetChannelSamplingTime();
-  * @param  ADCx ADC instance
-  * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ADC registers are initialized
-  *          - ERROR: ADC registers are not initialized
-  */
-ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-  assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
-  assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
-  assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
-  assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
-  assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
-
-  /* ADC group regular continuous mode and discontinuous mode                 */
-  /* can not be enabled simultenaeously                                       */
-  assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
-               || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
-
-  /* Note: Hardware constraint (refer to description of this function):       */
-  /*       ADC instance must be disabled.                                     */
-  if(LL_ADC_IsEnabled(ADCx) == 0U)
-  {
-    /* Configuration of ADC hierarchical scope:                               */
-    /*  - ADC group regular                                                   */
-    /*    - Set ADC group regular trigger source                              */
-    /*    - Set ADC group regular sequencer discontinuous mode                */
-    /*    - Set ADC group regular continuous mode                             */
-    /*    - Set ADC group regular conversion data transfer: no transfer or    */
-    /*      transfer by DMA, and DMA requests mode                            */
-    /*    - Set ADC group regular overrun behavior                            */
-    /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
-    /*       setting of trigger source to SW start.                           */
-    MODIFY_REG(ADCx->CFGR1,
-                 ADC_CFGR1_EXTSEL
-               | ADC_CFGR1_EXTEN
-               | ADC_CFGR1_DISCEN
-               | ADC_CFGR1_CONT
-               | ADC_CFGR1_DMAEN
-               | ADC_CFGR1_DMACFG
-               | ADC_CFGR1_OVRMOD
-              ,
-                 ADC_REG_InitStruct->TriggerSource
-               | ADC_REG_InitStruct->SequencerDiscont
-               | ADC_REG_InitStruct->ContinuousMode
-               | ADC_REG_InitStruct->DMATransfer
-               | ADC_REG_InitStruct->Overrun
-              );
-
-  }
-  else
-  {
-    /* Initialization error: ADC instance is not disabled. */
-    status = ERROR;
-  }
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
-  * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
-  *                            whose fields will be set to default values.
-  * @retval None
-  */
-void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
-{
-  /* Set ADC_REG_InitStruct fields to default values */
-  /* Set fields of ADC group regular */
-  /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by       */
-  /*       setting of trigger source to SW start.                             */
-  ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
-  ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
-  ADC_REG_InitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
-  ADC_REG_InitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
-  ADC_REG_InitStruct->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* ADC1 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c
deleted file mode 100644
index 27b64108d6..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_comp.c
-  * @author  MCD Application Team
-  * @brief   COMP LL module driver
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_comp.h"
-
-#ifdef  USE_FULL_ASSERT
-  #include "stm32_assert.h"
-#else
-  #define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (COMP1) || defined (COMP2)
-
-/** @addtogroup COMP_LL COMP
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup COMP_LL_Private_Macros
-  * @{
-  */
-
-/* Check of parameters for configuration of COMP hierarchical scope:          */
-/* COMP instance.                                                             */
-
-#define IS_LL_COMP_POWER_MODE(__POWER_MODE__)                                  \
-  (   ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
-   || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
-  )
-
-#if defined (STM32L011xx) || defined (STM32L021xx)
-#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
-  (((__COMP_INSTANCE__) == COMP1)                                              \
-    ? (                                                                        \
-       (__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1                              \
-      )                                                                        \
-      :                                                                        \
-      (                                                                        \
-          ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO4)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO5)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO6)                         \
-      )                                                                        \
-  )
-#else
-#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
-  (((__COMP_INSTANCE__) == COMP1)                                              \
-    ? (                                                                        \
-       (__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1                              \
-      )                                                                        \
-      :                                                                        \
-      (                                                                        \
-          ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO4)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO5)                         \
-      )                                                                        \
-  )
-#endif
-
-/* Note: On this STM32 serie, comparator input minus parameters are           */
-/*       the different depending on COMP instances.                           */
-#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
-  (((__COMP_INSTANCE__) == COMP1)                                              \
-    ? (                                                                        \
-          ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                   \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                  \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                  \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                       \
-      )                                                                        \
-      :                                                                        \
-      (                                                                        \
-          ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                   \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                  \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                  \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                       \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                       \
-      )                                                                        \
-  )
-
-#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)                               \
-  (   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
-   || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
-  )
-
-/**
-  * @}
-  */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup COMP_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup COMP_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize registers of the selected COMP instance
-  *         to their default reset values.
-  * @note   If comparator is locked, de-initialization by software is
-  *         not possible.
-  *         The only way to unlock the comparator is a device hardware reset.
-  * @param  COMPx COMP instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: COMP registers are de-initialized
-  *          - ERROR: COMP registers are not de-initialized
-  */
-ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_COMP_ALL_INSTANCE(COMPx));
-  
-  /* Note: Hardware constraint (refer to description of this function):       */
-  /*       COMP instance must not be locked.                                  */
-  if(LL_COMP_IsLocked(COMPx) == 0U)
-  {
-    if(COMPx == COMP1)
-    {
-      CLEAR_BIT(COMPx->CSR,
-                (  COMP_CSR_COMP1EN
-                 | COMP_CSR_COMP1INNSEL
-                 | COMP_CSR_COMP1WM
-                 | COMP_CSR_COMP1LPTIM1IN1
-                 | COMP_CSR_COMP1POLARITY
-                 | COMP_CSR_COMP1LOCK
-                ) 
-               );
-    }
-    else
-    {
-      CLEAR_BIT(COMPx->CSR,
-                (  COMP_CSR_COMP2EN
-                 | COMP_CSR_COMP2SPEED
-                 | COMP_CSR_COMP2INNSEL
-                 | COMP_CSR_COMP2INPSEL
-                 | COMP_CSR_COMP2LPTIM1IN2
-                 | COMP_CSR_COMP2LPTIM1IN1
-                 | COMP_CSR_COMP2POLARITY
-                 | COMP_CSR_COMP2LOCK
-                ) 
-               );
-    }
-
-  }
-  else
-  {
-    /* Comparator instance is locked: de-initialization by software is         */
-    /* not possible.                                                           */
-    /* The only way to unlock the comparator is a device hardware reset.       */
-    status = ERROR;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Initialize some features of COMP instance.
-  * @note   This function configures features of the selected COMP instance.
-  *         Some features are also available at scope COMP common instance
-  *         (common to several COMP instances).
-  *         Refer to functions having argument "COMPxy_COMMON" as parameter.
-  * @param  COMPx COMP instance
-  * @param  COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: COMP registers are initialized
-  *          - ERROR: COMP registers are not initialized
-  */
-ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_COMP_ALL_INSTANCE(COMPx));
-  if(COMPx == COMP2)
-  {
-    assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
-    assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
-  }
-  assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
-  assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
-  
-  /* Note: Hardware constraint (refer to description of this function)        */
-  /*       COMP instance must not be locked.                                  */
-  if(LL_COMP_IsLocked(COMPx) == 0U)
-  {
-    /* Configuration of comparator instance :                                 */
-    /*  - PowerMode                                                           */
-    /*  - InputPlus                                                           */
-    /*  - InputMinus                                                          */
-    /*  - OutputPolarity                                                      */
-    /* Note: Connection switch is applicable only to COMP instance COMP1,     */
-    /*       therefore is COMP2 is selected the equivalent bit is             */
-    /*       kept unmodified.                                                 */
-    if(COMPx == COMP1)
-    {
-      MODIFY_REG(COMPx->CSR,
-                 ( COMP_CSR_COMP1INNSEL
-                  | COMP_CSR_COMP1POLARITY
-                 ) 
-                ,
-                 (  COMP_InitStruct->InputMinus
-                  | COMP_InitStruct->OutputPolarity
-                 ) 
-                );
-    }
-    else
-    {
-      MODIFY_REG(COMPx->CSR,
-                 (  COMP_CSR_COMP2SPEED       
-                  | COMP_CSR_COMP2INPSEL      
-                  | COMP_CSR_COMP2INNSEL      
-                  | COMP_CSR_COMP2POLARITY
-                 ) 
-                ,
-                 (  COMP_InitStruct->PowerMode
-                  | COMP_InitStruct->InputPlus
-                  | COMP_InitStruct->InputMinus
-                  | COMP_InitStruct->OutputPolarity
-                 ) 
-                );
-    }
-
-  }
-  else
-  {
-    /* Initialization error: COMP instance is locked.                         */
-    status = ERROR;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
-  * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure
-  *                         whose fields will be set to default values.
-  * @retval None
-  */
-void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
-{
-  /* Set COMP_InitStruct fields to default values */
-  COMP_InitStruct->PowerMode            = LL_COMP_POWERMODE_MEDIUMSPEED;
-  COMP_InitStruct->InputPlus            = LL_COMP_INPUT_PLUS_IO1;
-  COMP_InitStruct->InputMinus           = LL_COMP_INPUT_MINUS_VREFINT;
-  COMP_InitStruct->OutputPolarity       = LL_COMP_OUTPUTPOL_NONINVERTED;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* COMP1 || COMP2 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c
deleted file mode 100644
index 9664148b84..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_crc.c
-  * @author  MCD Application Team
-  * @brief   CRC LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_crc.h"
-#include "stm32l0xx_ll_bus.h"
-
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (CRC)
-
-/** @addtogroup CRC_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRC_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CRC_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize CRC registers (Registers restored to their default values).
-  * @param  CRCx CRC Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: CRC registers are de-initialized
-  *          - ERROR: CRC registers are not de-initialized
-  */
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_CRC_ALL_INSTANCE(CRCx));
-
-  if (CRCx == CRC)
-  {
-    /* Force CRC reset */
-    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
-
-    /* Release CRC reset */
-    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
-  }
-  else
-  {
-    status = ERROR;
-  }
-
-  return (status);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (CRC) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c
deleted file mode 100644
index 78c03a95c1..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_crs.h
-  * @author  MCD Application Team
-  * @brief   CRS LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_crs.h"
-#include "stm32l0xx_ll_bus.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined(CRS)
-
-/** @defgroup CRS_LL CRS
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRS_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CRS_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-Initializes CRS peripheral registers to their default reset values.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: CRS registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_CRS_DeInit(void)
-{
-  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
-  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
-
-  return  SUCCESS;
-}
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(CRS) */
-
-/**
-  * @}
-  */
-  
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c
deleted file mode 100644
index 62f0fc6d7b..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_dac.c
-  * @author  MCD Application Team
-  * @brief   DAC LL module driver
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_dac.h"
-#include "stm32l0xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
-  #include "stm32_assert.h"
-#else
-  #define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (DAC1)
-
-/** @addtogroup DAC_LL DAC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup DAC_LL_Private_Macros
-  * @{
-  */
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)                           \
-  (                                                                            \
-      ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                  \
-   || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)                                  \
-  )
-#else
-#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)                           \
-  (                                                                            \
-   ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                     \
-  )
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
-  (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                      \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_CH3)                       \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM21_TRGO)                     \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
-  )
-
-#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)           \
-  (   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)     \
-   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
-   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
-  )
-
-#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__)      \
-  (   ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)     \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)  \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)  \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)  \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)  \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)  \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)  \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)  \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)  \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)  \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)       \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)       \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)       \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)      \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)      \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)      \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)     \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)     \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)     \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)    \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)    \
-   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)    \
-  )
-
-#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)                             \
-  (   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
-   || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
-  )
-
-/**
-  * @}
-  */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DAC_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DAC_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize registers of the selected DAC instance
-  *         to their default reset values.
-  * @param  DACx DAC instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: DAC registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(DACx));
-  
-  /* Force reset of DAC clock */
-  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
-  
-  /* Release reset of DAC clock */
-  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
-  
-  return SUCCESS;
-}
-
-/**
-  * @brief  Initialize some features of DAC instance.
-  * @note   The setting of these parameters by function @ref LL_DAC_Init()
-  *         is conditioned to DAC state:
-  *         DAC instance must be disabled.
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
-  *         (1) On this STM32 serie, parameter not available on all devices.
-  *             Refer to device datasheet for channels availability.
-  * @param  DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: DAC registers are initialized
-  *          - ERROR: DAC registers are not initialized
-  */
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(DACx));
-  assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
-  assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
-  assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
-  assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
-  if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
-  {
-    assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
-  }
-  
-  /* Note: Hardware constraint (refer to description of this function)        */
-  /*       DAC instance must be disabled.                                     */
-  if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
-  {
-    /* Configuration of DAC channel:                                          */
-    /*  - TriggerSource                                                       */
-    /*  - WaveAutoGeneration                                                  */
-    /*  - OutputBuffer                                                        */
-    if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
-    {
-      MODIFY_REG(DACx->CR,
-                 (  DAC_CR_TSEL1
-                  | DAC_CR_WAVE1
-                  | DAC_CR_MAMP1
-                  | DAC_CR_BOFF1
-                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                ,
-                 (  DAC_InitStruct->TriggerSource
-                  | DAC_InitStruct->WaveAutoGeneration
-                  | DAC_InitStruct->WaveAutoGenerationConfig
-                  | DAC_InitStruct->OutputBuffer
-                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                );
-    }
-    else
-    {
-      MODIFY_REG(DACx->CR,
-                 (  DAC_CR_TSEL1
-                  | DAC_CR_WAVE1
-                  | DAC_CR_BOFF1
-                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                ,
-                 (  DAC_InitStruct->TriggerSource
-                  | LL_DAC_WAVE_AUTO_GENERATION_NONE
-                  | DAC_InitStruct->OutputBuffer
-                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                );
-    }
-  }
-  else
-  {
-    /* Initialization error: DAC instance is not disabled.                    */
-    status = ERROR;
-  }
-  return status;
-}
-
-/**
-  * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
-  * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
-  *                       whose fields will be set to default values.
-  * @retval None
-  */
-void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
-{
-  /* Set DAC_InitStruct fields to default values */
-  DAC_InitStruct->TriggerSource            = LL_DAC_TRIG_SOFTWARE;
-  DAC_InitStruct->WaveAutoGeneration       = LL_DAC_WAVE_AUTO_GENERATION_NONE;
-  /* Note: Parameter discarded if wave auto generation is disabled,           */
-  /*       set anyway to its default value.                                   */
-  DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
-  DAC_InitStruct->OutputBuffer             = LL_DAC_OUTPUT_BUFFER_ENABLE;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DAC1 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c
deleted file mode 100644
index 4b7665d708..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_dma.c
-  * @author  MCD Application Team
-  * @brief   DMA LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_dma.h"
-#include "stm32l0xx_ll_bus.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (DMA1)
-
-/** @defgroup DMA_LL DMA
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup DMA_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
-                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
-                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
-
-#define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
-                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
-
-#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
-                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
-
-#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
-                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
-
-#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
-                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
-                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
-
-#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
-                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
-                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
-
-#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <=  0x0000FFFFU)
-
-#define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      (((__VALUE__) == LL_DMA_REQUEST_0)  || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_1)  || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_2)  || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_3)  || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_4)  || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_5)  || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_6)  || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_7)  || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_8)  || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_9)  || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_10) || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_11) || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_12) || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_13) || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_14) || \
-                                                 ((__VALUE__) == LL_DMA_REQUEST_15))
-
-#define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
-                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
-                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
-                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
-
-#if defined (DMA1_Channel6) && defined (DMA1_Channel7)
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
-                                                            (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_2) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_3) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_4) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_5) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_6) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_7))))
-#elif defined (DMA1_Channel6)
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
-                                                            (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_2) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_3) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_4) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_5) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_6))))
-#else
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
-                                                            (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_2) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_3) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_4) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_5))))
-#endif /* DMA1_Channel6 && DMA1_Channel7 */
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DMA_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the DMA registers to their default reset values.
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6 (*)
-  *         @arg @ref LL_DMA_CHANNEL_7 (*)
-  *         @arg @ref LL_DMA_CHANNEL_ALL
-  *
-  *         (*) value not defined in all devices
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: DMA registers are de-initialized
-  *          - ERROR: DMA registers are not de-initialized
-  */
-ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
-  ErrorStatus status = SUCCESS;
-
-  /* Check the DMA Instance DMAx and Channel parameters*/
-  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
-
-  if (Channel == LL_DMA_CHANNEL_ALL)
-  {
-    if (DMAx == DMA1)
-    {
-      /* Force reset of DMA clock */
-      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
-
-      /* Release reset of DMA clock */
-      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
-    }
-#if defined(DMA2)
-    else if (DMAx == DMA2)
-    {
-      /* Force reset of DMA clock */
-      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
-
-      /* Release reset of DMA clock */
-      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
-    }
-#endif
-    else
-    {
-      status = ERROR;
-    }
-  }
-  else
-  {
-    tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
-
-    /* Disable the selected DMAx_Channely */
-    CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
-
-    /* Reset DMAx_Channely control register */
-    LL_DMA_WriteReg(tmp, CCR, 0U);
-
-    /* Reset DMAx_Channely remaining bytes register */
-    LL_DMA_WriteReg(tmp, CNDTR, 0U);
-
-    /* Reset DMAx_Channely peripheral address register */
-    LL_DMA_WriteReg(tmp, CPAR, 0U);
-
-    /* Reset DMAx_Channely memory address register */
-    LL_DMA_WriteReg(tmp, CMAR, 0U);
-
-    /* Reset Request register field for DMAx Channel */
-    LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
-
-    if (Channel == LL_DMA_CHANNEL_1)
-    {
-      /* Reset interrupt pending bits for DMAx Channel1 */
-      LL_DMA_ClearFlag_GI1(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_2)
-    {
-      /* Reset interrupt pending bits for DMAx Channel2 */
-      LL_DMA_ClearFlag_GI2(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_3)
-    {
-      /* Reset interrupt pending bits for DMAx Channel3 */
-      LL_DMA_ClearFlag_GI3(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_4)
-    {
-      /* Reset interrupt pending bits for DMAx Channel4 */
-      LL_DMA_ClearFlag_GI4(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_5)
-    {
-      /* Reset interrupt pending bits for DMAx Channel5 */
-      LL_DMA_ClearFlag_GI5(DMAx);
-    }
-
-#if defined(DMA1_Channel6)
-    else if (Channel == LL_DMA_CHANNEL_6)
-    {
-      /* Reset interrupt pending bits for DMAx Channel6 */
-      LL_DMA_ClearFlag_GI6(DMAx);
-    }
-#endif
-#if defined(DMA1_Channel7)
-    else if (Channel == LL_DMA_CHANNEL_7)
-    {
-      /* Reset interrupt pending bits for DMAx Channel7 */
-      LL_DMA_ClearFlag_GI7(DMAx);
-    }
-#endif
-    else
-    {
-      status = ERROR;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
-  * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
-  *         @arg @ref __LL_DMA_GET_INSTANCE
-  *         @arg @ref __LL_DMA_GET_CHANNEL
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6 (*)
-  *         @arg @ref LL_DMA_CHANNEL_7 (*)
-  *
-  *         (*) value not defined in all devices
-  * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: DMA registers are initialized
-  *          - ERROR: Not applicable
-  */
-ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
-{
-  /* Check the DMA Instance DMAx and Channel parameters*/
-  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
-
-  /* Check the DMA parameters from DMA_InitStruct */
-  assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
-  assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
-  assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
-  assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
-  assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
-  assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
-  assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
-  assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
-  assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
-
-  /*---------------------------- DMAx CCR Configuration ------------------------
-   * Configure DMAx_Channely: data transfer direction, data transfer mode,
-   *                          peripheral and memory increment mode,
-   *                          data size alignment and  priority level with parameters :
-   * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
-   * - Mode:           DMA_CCR_CIRC bit
-   * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
-   * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
-   * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
-   * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
-   * - Priority:               DMA_CCR_PL[1:0] bits
-   */
-  LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
-                        DMA_InitStruct->Mode                   | \
-                        DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
-                        DMA_InitStruct->MemoryOrM2MDstIncMode  | \
-                        DMA_InitStruct->PeriphOrM2MSrcDataSize | \
-                        DMA_InitStruct->MemoryOrM2MDstDataSize | \
-                        DMA_InitStruct->Priority);
-
-  /*-------------------------- DMAx CMAR Configuration -------------------------
-   * Configure the memory or destination base address with parameter :
-   * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
-   */
-  LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
-
-  /*-------------------------- DMAx CPAR Configuration -------------------------
-   * Configure the peripheral or source base address with parameter :
-   * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
-   */
-  LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
-
-  /*--------------------------- DMAx CNDTR Configuration -----------------------
-   * Configure the peripheral base address with parameter :
-   * - NbData: DMA_CNDTR_NDT[15:0] bits
-   */
-  LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
-
-  /*--------------------------- DMAx CSELR Configuration -----------------------
-   * Configure the DMA request for DMA instance on Channel x with parameter :
-   * - PeriphRequest: DMA_CSELR[31:0] bits
-   */
-  LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
-  * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
-  * @retval None
-  */
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
-{
-  /* Set DMA_InitStruct fields to default values */
-  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
-  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
-  DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
-  DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
-  DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
-  DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
-  DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
-  DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
-  DMA_InitStruct->NbData                 = 0x00000000U;
-  DMA_InitStruct->PeriphRequest          = LL_DMA_REQUEST_0;
-  DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DMA1 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c
deleted file mode 100644
index 82b82f125d..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_exti.c
-  * @author  MCD Application Team
-  * @brief   EXTI LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_exti.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Private_Macros
-  * @{
-  */
-
-#define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
-
-#define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
-                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
-                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
-
-
-#define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
-                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
-                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
-                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup EXTI_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the EXTI registers to their default reset values.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: EXTI registers are de-initialized
-  *          - ERROR: not applicable
-  */
-uint32_t LL_EXTI_DeInit(void)
-{
-  /* Interrupt mask register set to default reset values */
-  LL_EXTI_WriteReg(IMR,   0x3F840000U);
-  /* Event mask register set to default reset values */
-  LL_EXTI_WriteReg(EMR,   0x00000000U);
-  /* Rising Trigger selection register set to default reset values */
-  LL_EXTI_WriteReg(RTSR,  0x00000000U);
-  /* Falling Trigger selection register set to default reset values */
-  LL_EXTI_WriteReg(FTSR,  0x00000000U);
-  /* Software interrupt event register set to default reset values */
-  LL_EXTI_WriteReg(SWIER, 0x00000000U);
-  /* Pending register set to default reset values */
-  LL_EXTI_WriteReg(PR,    0x007BFFFFU);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
-  * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: EXTI registers are initialized
-  *          - ERROR: not applicable
-  */
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  /* Check the parameters */
-  assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
-  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
-  assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
-
-  /* ENABLE LineCommand */
-  if (EXTI_InitStruct->LineCommand != DISABLE)
-  {
-    assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
-
-    /* Configure EXTI Lines in range from 0 to 31 */
-    if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
-    {
-      switch (EXTI_InitStruct->Mode)
-      {
-        case LL_EXTI_MODE_IT:
-          /* First Disable Event on provided Lines */
-          LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
-          /* Then Enable IT on provided Lines */
-          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
-          break;
-        case LL_EXTI_MODE_EVENT:
-          /* First Disable IT on provided Lines */
-          LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
-          /* Then Enable Event on provided Lines */
-          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
-          break;
-        case LL_EXTI_MODE_IT_EVENT:
-          /* Directly Enable IT & Event on provided Lines */
-          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
-          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
-          break;
-        default:
-          status = ERROR;
-          break;
-      }
-      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
-      {
-        switch (EXTI_InitStruct->Trigger)
-        {
-          case LL_EXTI_TRIGGER_RISING:
-            /* First Disable Falling Trigger on provided Lines */
-            LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            /* Then Enable Rising Trigger on provided Lines */
-            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            break;
-          case LL_EXTI_TRIGGER_FALLING:
-            /* First Disable Rising Trigger on provided Lines */
-            LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            /* Then Enable Falling Trigger on provided Lines */
-            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            break;
-          case LL_EXTI_TRIGGER_RISING_FALLING:
-            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            break;
-          default:
-            status = ERROR;
-            break;
-        }
-      }
-    }
-  }
-  /* DISABLE LineCommand */
-  else
-  {
-    /* De-configure EXTI Lines in range from 0 to 31 */
-    LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
-    LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
-  }
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
-  * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
-  * @retval None
-  */
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
-  EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
-  EXTI_InitStruct->LineCommand    = DISABLE;
-  EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
-  EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (EXTI) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c
deleted file mode 100644
index 56bdc191cc..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_gpio.c
-  * @author  MCD Application Team
-  * @brief   GPIO LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_gpio.h"
-#include "stm32l0xx_ll_bus.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH)
-
-/** @addtogroup GPIO_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000UL) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
-
-#define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
-                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
-                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
-                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))
-
-#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
-                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
-
-#define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
-                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
-                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
-                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
-
-#define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
-                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
-                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))
-
-#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_7 ))
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize GPIO registers (Registers restored to their default values).
-  * @param  GPIOx GPIO Port
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: GPIO registers are de-initialized
-  *          - ERROR:   Wrong GPIO Port
-  */
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-
-  /* Force and Release reset on clock of GPIOx Port */
-  if (GPIOx == GPIOA)
-  {
-    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOA);
-    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOA);
-  }
-  else if (GPIOx == GPIOB)
-  {
-    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOB);
-    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOB);
-  }
-  else if (GPIOx == GPIOC)
-  {
-    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOC);
-    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOC);
-  }
-#if defined(GPIOD)
-  else if (GPIOx == GPIOD)
-  {
-    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOD);
-    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOD);
-  }
-#endif /* GPIOD */
-#if defined(GPIOE)
-  else if (GPIOx == GPIOE)
-  {
-    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOE);
-    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOE);
-  }
-#endif /* GPIOE */
-#if defined(GPIOH)
-  else if (GPIOx == GPIOH)
-  {
-    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOH);
-    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOH);
-  }
-#endif /* GPIOH */
-  else
-  {
-    status = ERROR;
-  }
-
-  return (status);
-}
-
-/**
-  * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
-  * @param  GPIOx GPIO Port
-  * @param  GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
-  *         that contains the configuration information for the specified GPIO peripheral.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
-  *          - ERROR:   Not applicable
-  */
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
-  uint32_t pinpos     = 0x00000000U;
-  uint32_t currentpin = 0x00000000U;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
-  assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
-  assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
-
-  /* ------------------------- Configure the port pins ---------------- */
-  /* Initialize  pinpos on first pin set */
-  /* pinpos = 0; useless as already done in default initialization */
-
-  /* Configure the port pins */
-  while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
-  {
-    /* Get current io position */
-    currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
-
-    if (currentpin)
-    {
-      if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
-      {
-        /* Check Speed mode parameters */
-        assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
-
-        /* Speed mode configuration */
-        LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
-
-        /* Check Output mode parameters */
-        assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
-        /* Output mode configuration*/
-        LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
-      }
-
-      /* Pull-up Pull down resistor configuration*/
-      LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
-
-      if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
-      {
-        /* Check Alternate parameter */
-        assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
-
-        /* Speed mode configuration */
-        if (currentpin < LL_GPIO_PIN_8)
-        {
-          LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
-        }
-        else
-        {
-          LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
-        }
-      }
-
-      /* Pin Mode configuration */
-      LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
-    }
-    pinpos++;
-  }
-
-
-  return (SUCCESS);
-}
-
-/**
-  * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
-  * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
-  *                          whose fields will be set to default values.
-  * @retval None
-  */
-
-void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
-  /* Reset GPIO init structure parameters values */
-  GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
-  GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
-  GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
-  GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
-  GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
-  GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c
deleted file mode 100644
index e6be18cdf2..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_i2c.c
-  * @author  MCD Application Team
-  * @brief   I2C LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_i2c.h"
-#include "stm32l0xx_ll_bus.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (I2C1) || defined (I2C2) || defined (I2C3)
-
-/** @defgroup I2C_LL I2C
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup I2C_LL_Private_Macros
-  * @{
-  */
-
-#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
-                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
-                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
-                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
-
-#define IS_LL_I2C_ANALOG_FILTER(__VALUE__)      (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
-                                                 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
-
-#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
-
-#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
-
-#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
-                                                 ((__VALUE__) == LL_I2C_NACK))
-
-#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
-                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2C_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the I2C registers to their default reset values.
-  * @param  I2Cx I2C Instance.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: I2C registers are de-initialized
-  *          - ERROR: I2C registers are not de-initialized
-  */
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the I2C Instance I2Cx */
-  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
-
-  if (I2Cx == I2C1)
-  {
-    /* Force reset of I2C clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
-
-    /* Release reset of I2C clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
-  }
-#if defined(I2C2)
-  else if (I2Cx == I2C2)
-  {
-    /* Force reset of I2C clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
-
-    /* Release reset of I2C clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
-
-  }
-#endif /* I2C2 */
-#if defined(I2C3)
-  else if (I2Cx == I2C3)
-  {
-    /* Force reset of I2C clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
-
-    /* Release reset of I2C clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
-  }
-#endif /* I2C3 */
-  else
-  {
-    status = ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
-  * @param  I2Cx I2C Instance.
-  * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: I2C registers are initialized
-  *          - ERROR: Not applicable
-  */
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
-{
-  /* Check the I2C Instance I2Cx */
-  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
-
-  /* Check the I2C parameters from I2C_InitStruct */
-  assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
-  assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
-  assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
-  assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
-  assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
-  assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
-
-  /* Disable the selected I2Cx Peripheral */
-  LL_I2C_Disable(I2Cx);
-
-  /*---------------------------- I2Cx CR1 Configuration ------------------------
-   * Configure the analog and digital noise filters with parameters :
-   * - AnalogFilter: I2C_CR1_ANFOFF bit
-   * - DigitalFilter: I2C_CR1_DNF[3:0] bits
-   */
-  LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
-
-  /*---------------------------- I2Cx TIMINGR Configuration --------------------
-   * Configure the SDA setup, hold time and the SCL high, low period with parameter :
-   * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
-   *           I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
-   */
-  LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
-
-  /* Enable the selected I2Cx Peripheral */
-  LL_I2C_Enable(I2Cx);
-
-  /*---------------------------- I2Cx OAR1 Configuration -----------------------
-   * Disable, Configure and Enable I2Cx device own address 1 with parameters :
-   * - OwnAddress1:  I2C_OAR1_OA1[9:0] bits
-   * - OwnAddrSize:  I2C_OAR1_OA1MODE bit
-   */
-  LL_I2C_DisableOwnAddress1(I2Cx);
-  LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
-
-  /* OwnAdress1 == 0 is reserved for General Call address */
-  if (I2C_InitStruct->OwnAddress1 != 0U)
-  {
-    LL_I2C_EnableOwnAddress1(I2Cx);
-  }
-
-  /*---------------------------- I2Cx MODE Configuration -----------------------
-  * Configure I2Cx peripheral mode with parameter :
-   * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
-   */
-  LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
-
-  /*---------------------------- I2Cx CR2 Configuration ------------------------
-   * Configure the ACKnowledge or Non ACKnowledge condition
-   * after the address receive match code or next received byte with parameter :
-   * - TypeAcknowledge: I2C_CR2_NACK bit
-   */
-  LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
-  * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
-  * @retval None
-  */
-void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
-{
-  /* Set I2C_InitStruct fields to default values */
-  I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
-  I2C_InitStruct->Timing          = 0U;
-  I2C_InitStruct->AnalogFilter    = LL_I2C_ANALOGFILTER_ENABLE;
-  I2C_InitStruct->DigitalFilter   = 0U;
-  I2C_InitStruct->OwnAddress1     = 0U;
-  I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
-  I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* I2C1 || I2C2 || I2C3 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c
deleted file mode 100644
index 1366e9be35..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_lptim.c
-  * @author  MCD Application Team
-  * @brief   LPTIM LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_lptim.h"
-#include "stm32l0xx_ll_bus.h"
-#include "stm32l0xx_ll_rcc.h"
-
-
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (LPTIM1)
-
-/** @addtogroup LPTIM_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup LPTIM_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
-                                             || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
-
-#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
-                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
-                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
-                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
-                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
-                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
-                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
-                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
-
-#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
-                                         || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
-
-#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
-                                                || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
-/**
-  * @}
-  */
-
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
-  * @{
-  */
-/**
-  * @}
-  */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup LPTIM_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup LPTIM_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  Set LPTIMx registers to their reset values.
-  * @param  LPTIMx LP Timer instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: LPTIMx registers are de-initialized
-  *          - ERROR: invalid LPTIMx instance
-  */
-ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
-{
-  ErrorStatus result = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(LPTIMx));
-
-  if (LPTIMx == LPTIM1)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
-  }
-  else
-  {
-    result = ERROR;
-  }
-
-  return result;
-}
-
-/**
-  * @brief  Set each fields of the LPTIM_InitStruct structure to its default
-  *         value.
-  * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
-  * @retval None
-  */
-void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
-{
-  /* Set the default configuration */
-  LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
-  LPTIM_InitStruct->Prescaler   = LL_LPTIM_PRESCALER_DIV1;
-  LPTIM_InitStruct->Waveform    = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
-  LPTIM_InitStruct->Polarity    = LL_LPTIM_OUTPUT_POLARITY_REGULAR;
-}
-
-/**
-  * @brief  Configure the LPTIMx peripheral according to the specified parameters.
-  * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
-  * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
-  * @param  LPTIMx LP Timer Instance
-  * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: LPTIMx instance has been initialized
-  *          - ERROR: LPTIMx instance hasn't been initialized
-  */
-ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
-{
-  ErrorStatus result = SUCCESS;
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(LPTIMx));
-  assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
-  assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
-  assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
-  assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
-
-  /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
-     (ENABLE bit is reset to 0).
-  */
-  if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL)
-  {
-    result = ERROR;
-  }
-  else
-  {
-    /* Set CKSEL bitfield according to ClockSource value */
-    /* Set PRESC bitfield according to Prescaler value */
-    /* Set WAVE bitfield according to Waveform value */
-    /* Set WAVEPOL bitfield according to Polarity value */
-    MODIFY_REG(LPTIMx->CFGR,
-               (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL),
-               LPTIM_InitStruct->ClockSource | \
-               LPTIM_InitStruct->Prescaler | \
-               LPTIM_InitStruct->Waveform | \
-               LPTIM_InitStruct->Polarity);
-  }
-
-  return result;
-}
-
-/**
-  * @brief  Disable the LPTIM instance
-  * @rmtoll CR           ENABLE        LL_LPTIM_Disable
-  * @param  LPTIMx Low-Power Timer instance
-  * @note   The following sequence is required to solve LPTIM disable HW limitation.
-  *         Please check Errata Sheet ES0335 for more details under "MCU may remain
-  *         stuck in LPTIM interrupt when entering Stop mode" section.
-  * @retval None
-  */
-void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
-{
-  LL_RCC_ClocksTypeDef rcc_clock;
-  uint32_t tmpclksource = 0;
-  uint32_t tmpIER;
-  uint32_t tmpCFGR;
-  uint32_t tmpCMP;
-  uint32_t tmpARR;
-
-  /* Check the parameters */
-  assert_param(IS_LPTIM_INSTANCE(LPTIMx));
-
-  __disable_irq();
-
-  /********** Save LPTIM Config *********/
-  /* Save LPTIM source clock */
-  switch ((uint32_t)LPTIMx)
-  {
-    case LPTIM1_BASE:
-      tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
-      break;
-    default:
-      break;
-  }
-
-  /* Save LPTIM configuration registers */
-  tmpIER = LPTIMx->IER;
-  tmpCFGR = LPTIMx->CFGR;
-  tmpCMP = LPTIMx->CMP;
-  tmpARR = LPTIMx->ARR;
-
-  /************* Reset LPTIM ************/
-  (void)LL_LPTIM_DeInit(LPTIMx);
-
-  /********* Restore LPTIM Config *******/
-  LL_RCC_GetSystemClocksFreq(&rcc_clock);
-
-  if ((tmpCMP != 0UL) || (tmpARR != 0UL))
-  {
-    /* Force LPTIM source kernel clock from APB */
-    switch ((uint32_t)LPTIMx)
-    {
-      case LPTIM1_BASE:
-        LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
-        break;
-      default:
-        break;
-    }
-
-    if (tmpCMP != 0UL)
-    {
-      /* Restore CMP and ARR registers (LPTIM should be enabled first) */
-      LPTIMx->CR |= LPTIM_CR_ENABLE;
-      LPTIMx->CMP = tmpCMP;
-
-      /* Polling on CMP write ok status after above restore operation */
-      do
-      {
-        rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
-      } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
-
-      LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
-    }
-
-    if (tmpARR != 0UL)
-    {
-      LPTIMx->CR |= LPTIM_CR_ENABLE;
-      LPTIMx->ARR = tmpARR;
-
-      LL_RCC_GetSystemClocksFreq(&rcc_clock);
-      /* Polling on ARR write ok status after above restore operation */
-      do
-      {
-        rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
-      }
-      while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
-
-      LL_LPTIM_ClearFlag_ARROK(LPTIMx);
-    }
-
-
-    /* Restore LPTIM source kernel clock */
-    LL_RCC_SetLPTIMClockSource(tmpclksource);
-  }
-
-  /* Restore configuration registers (LPTIM should be disabled first) */
-  LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
-  LPTIMx->IER = tmpIER;
-  LPTIMx->CFGR = tmpCFGR;
-
-  __enable_irq();
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* LPTIM1 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c
deleted file mode 100644
index 28e129888d..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_lpuart.c
-  * @author  MCD Application Team
-  * @brief   LPUART LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_lpuart.h"
-#include "stm32l0xx_ll_rcc.h"
-#include "stm32l0xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (LPUART1)
-
-/** @addtogroup LPUART_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup LPUART_LL_Private_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup LPUART_LL_Private_Macros
-  * @{
-  */
-
-/* Check of parameters for configuration of LPUART registers                  */
-
-/* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register   */
-/*              value :                                                       */
-/*                - fck must be in the range [3 x baudrate, 4096 x baudrate]  */
-/*                - LPUART_BRR register value should be >= 0x300              */
-/*                - LPUART_BRR register value should be <= 0xFFFFF (20 bits)  */
-/*              Baudrate specified by the user should belong to [8, 10600000].*/
-#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 10600000U) && ((__BAUDRATE__) >= 8U))
-
-/* __VALUE__ BRR content must be greater than or equal to 0x300. */
-#define IS_LL_LPUART_BRR_MIN(__VALUE__)   ((__VALUE__) >= 0x300U)
-
-/* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */
-#define IS_LL_LPUART_BRR_MAX(__VALUE__)   ((__VALUE__) <= 0x000FFFFFU)
-
-#define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
-                                           || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
-                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
-                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))
-
-#define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \
-                                        || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
-                                        || ((__VALUE__) == LL_LPUART_PARITY_ODD))
-
-#define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
-                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
-                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))
-
-#define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \
-                                          || ((__VALUE__) == LL_LPUART_STOPBITS_2))
-
-#define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
-                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
-                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
-                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup LPUART_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup LPUART_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize LPUART registers (Registers restored to their default values).
-  * @param  LPUARTx LPUART Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: LPUART registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_LPUART_INSTANCE(LPUARTx));
-
-  if (LPUARTx == LPUART1)
-  {
-    /* Force reset of LPUART peripheral */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPUART1);
-
-    /* Release reset of LPUART peripheral */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART1);
-  }
-  else
-  {
-    status = ERROR;
-  }
-
-  return (status);
-}
-
-/**
-  * @brief  Initialize LPUART registers according to the specified
-  *         parameters in LPUART_InitStruct.
-  * @note   As some bits in LPUART configuration registers can only be written when
-  *         the LPUART is disabled (USART_CR1_UE bit =0),
-  *         LPUART Peripheral should be in disabled state prior calling this function.
-  *         Otherwise, ERROR result will be returned.
-  * @note   Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
-  * @param  LPUARTx LPUART Instance
-  * @param  LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
-  *         that contains the configuration information for the specified LPUART peripheral.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
-  *          - ERROR: Problem occurred during LPUART Registers initialization
-  */
-ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
-{
-  ErrorStatus status = ERROR;
-  uint32_t periphclk;
-
-  /* Check the parameters */
-  assert_param(IS_LPUART_INSTANCE(LPUARTx));
-  assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
-  assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));
-  assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));
-  assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));
-  assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
-  assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
-
-  /* LPUART needs to be in disabled state, in order to be able to configure some bits in
-     CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
-  if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
-  {
-    /*---------------------------- LPUART CR1 Configuration -----------------------
-     * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:
-     * - DataWidth:          USART_CR1_M bits according to LPUART_InitStruct->DataWidth value
-     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value
-     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value
-     */
-    MODIFY_REG(LPUARTx->CR1,
-               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
-               (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));
-
-    /*---------------------------- LPUART CR2 Configuration -----------------------
-     * Configure LPUARTx CR2 (Stop bits) with parameters:
-     * - Stop Bits:          USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.
-     */
-    LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);
-
-    /*---------------------------- LPUART CR3 Configuration -----------------------
-     * Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
-     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according
-     *   to LPUART_InitStruct->HardwareFlowControl value.
-     */
-    LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
-
-    /*---------------------------- LPUART BRR Configuration -----------------------
-     * Retrieve Clock frequency used for LPUART Peripheral
-     */
-    periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
-
-    /* Configure the LPUART Baud Rate :
-       - valid baud rate value (different from 0) is required
-       - Peripheral clock as returned by RCC service, should be valid (different from 0).
-    */
-    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
-        && (LPUART_InitStruct->BaudRate != 0U))
-    {
-      status = SUCCESS;
-      LL_LPUART_SetBaudRate(LPUARTx,
-                            periphclk,
-                            LPUART_InitStruct->BaudRate);
-
-      /* Check BRR is greater than or equal to 0x300 */
-      assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR));
-
-      /* Check BRR is lower than or equal to 0xFFFFF */
-      assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR));
-    }
-
-  }
-
-  return (status);
-}
-
-/**
-  * @brief Set each @ref LL_LPUART_InitTypeDef field to default value.
-  * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
-  *                          whose fields will be set to default values.
-  * @retval None
-  */
-
-void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
-{
-  /* Set LPUART_InitStruct fields to default values */
-  LPUART_InitStruct->BaudRate            = 9600U;
-  LPUART_InitStruct->DataWidth           = LL_LPUART_DATAWIDTH_8B;
-  LPUART_InitStruct->StopBits            = LL_LPUART_STOPBITS_1;
-  LPUART_InitStruct->Parity              = LL_LPUART_PARITY_NONE ;
-  LPUART_InitStruct->TransferDirection   = LL_LPUART_DIRECTION_TX_RX;
-  LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* LPUART1 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c
deleted file mode 100644
index 818f0a567f..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_pwr.c
-  * @author  MCD Application Team
-  * @brief   PWR LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_pwr.h"
-#include "stm32l0xx_ll_bus.h"
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWR_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup PWR_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the PWR registers to their default reset values.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: PWR registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_PWR_DeInit(void)
-{
-  /* Force reset of PWR clock */
-  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
-
-  /* Release reset of PWR clock */
-  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
-
-  return SUCCESS;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined(PWR) */
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c
deleted file mode 100644
index 453301c370..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c
+++ /dev/null
@@ -1,698 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_rcc.c
-  * @author  MCD Application Team
-  * @brief   RCC LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_rcc.h"
-#ifdef  USE_FULL_ASSERT
-  #include "stm32_assert.h"
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_LL_Private_Macros
-  * @{
-  */
-#if defined(RCC_CCIPR_USART1SEL) && defined(RCC_CCIPR_USART2SEL)
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
-                                            || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
-#elif defined(RCC_CCIPR_USART1SEL) && !defined(RCC_CCIPR_USART2SEL)
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
-#else
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
-#endif /* RCC_CCIPR_USART1SEL && RCC_CCIPR_USART2SEL */
-
-#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
-
-#if defined(RCC_CCIPR_I2C3SEL)
-#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
-                                            || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
-#else
-#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)     ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
-#endif /* RCC_CCIPR_I2C3SEL */
-
-#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  ((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)
-
-#if defined(USB)
-#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
-#endif /* USB */
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCC_LL_Private_Functions RCC Private functions
-  * @{
-  */
-static uint32_t RCC_GetSystemClockFreq(void);
-static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
-static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
-static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
-static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCC_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  Reset the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *         - MSI  ON and used as system clock source
-  *         - HSE, HSI and PLL OFF
-  *         - AHB, APB1 and APB2 prescaler set to 1.
-  *         - CSS, MCO OFF
-  *         - All interrupts disabled
-  * @note   This function doesn't modify the configuration of the
-  *         - Peripheral clocks
-  *         - LSI, LSE and RTC clocks
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RCC registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_RCC_DeInit(void)
-{
-  __IO uint32_t vl_mask;
-
-  /* Set MSION bit */
-  LL_RCC_MSI_Enable();
-
-  /* Insure MSIRDY bit is set before writing default MSIRANGE value */
-  while (LL_RCC_MSI_IsReady() == 0U)
-  {
-    __NOP();
-  }
-
-  /* Set MSIRANGE default value */
-  LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5);
-  /* Set MSITRIM bits to the reset value*/
-  LL_RCC_MSI_SetCalibTrimming(0U);
-
-  /* Set HSITRIM bits to the reset value*/
-  LL_RCC_HSI_SetCalibTrimming(0x10U);
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE bits */
-  vl_mask = 0xFFFFFFFFU;
-  CLEAR_BIT(vl_mask, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | \
-                     RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE);
-  LL_RCC_WriteReg(CFGR, vl_mask);
-
-  /* Reset HSI, HSE, PLL */
-  vl_mask = LL_RCC_ReadReg(CR);
-#if defined(RCC_CR_HSIOUTEN)
-  CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
-                     RCC_CR_HSEON | RCC_CR_PLLON);
-#else
-  CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \
-                     RCC_CR_HSEON | RCC_CR_PLLON);
-#endif
-  LL_RCC_WriteReg(CR, vl_mask);
-  /* Delay after an RCC peripheral clock */
-  vl_mask = LL_RCC_ReadReg(CR);
-
-  /* Reset HSEBYP bit */
-  LL_RCC_HSE_DisableBypass();
-
-  /* Set RCC_CR_RTCPRE to 0b00*/
-  CLEAR_BIT(vl_mask, RCC_CR_RTCPRE);
-  LL_RCC_WriteReg(CR, vl_mask);
-
-  /* Insure PLL is disabled before to reset PLLSRC/PLLMUL/PLLDIV in CFGR register */
-  while(LL_RCC_PLL_IsReady() != 0U) {};
-
-  /* Reset CFGR register */
-  LL_RCC_WriteReg(CFGR, 0x00000000U);
-
-#if defined(RCC_HSI48_SUPPORT)
-
-  /* Reset CRRCR register to disable HSI48 */
-#if defined(RCC_CRRCR_HSI48DIV6OUTEN)
-  CLEAR_BIT(RCC->CRRCR, (RCC_CRRCR_HSI48ON | RCC_CRRCR_HSI48DIV6OUTEN));
-#else
-  CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
-#endif
-
-#endif /*RCC_HSI48_SUPPORT*/
-
-  /* Disable all interrupts */
-  LL_RCC_WriteReg(CIER, 0x00000000U);
-
-  /* Disable all interrupt flags */
-  LL_RCC_WriteReg(CICR, 0xFFFFFFFFU);
-
-  /* Clear reset flags */
-  LL_RCC_ClearResetFlags();
-
-  return SUCCESS;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_LL_EF_Get_Freq
-  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
-  *         and different peripheral clocks available on the device.
-  * @note   If SYSCLK source is MSI, function returns values based on MSI clock(*)
-  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
-  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
-  * @note   If SYSCLK source is PLL, function returns values based on
-  *         HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
-  * @note   (*) MSI clock depends on the selected MSI range but the real value
-  *             may vary depending on the variations in voltage and temperature.
-  * @note   (**) HSI_VALUE is a defined constant but the real value may vary
-  *              depending on the variations in voltage and temperature.
-  * @note   (***) HSE_VALUE is a defined constant, user has to ensure that
-  *               HSE_VALUE is same as the real frequency of the crystal used.
-  *               Otherwise, this function may have wrong result.
-  * @note   The result of this function could be incorrect when using fractional
-  *         value for HSE crystal.
-  * @note   This function can be used by the user application to compute the
-  *         baud-rate for the communication peripherals or configure other parameters.
-  * @{
-  */
-
-/**
-  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
-  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
-  *         must be called to update structure fields. Otherwise, any
-  *         configuration based on this function will be incorrect.
-  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
-  * @retval None
-  */
-void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
-{
-  /* Get SYSCLK frequency */
-  RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
-
-  /* HCLK clock frequency */
-  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
-
-  /* PCLK1 clock frequency */
-  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
-
-  /* PCLK2 clock frequency */
-  RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
-}
-
-/**
-  * @brief  Return USARTx clock frequency
-  * @param  USARTxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval USART clock frequency (in Hz)
-  *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
-  */
-uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
-{
-  uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
-#if defined(RCC_CCIPR_USART1SEL)
-  if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
-  {
-    /* USART1CLK clock frequency */
-    switch (LL_RCC_GetUSARTClockSource(USARTxSource))
-    {
-      case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
-        usart_frequency = RCC_GetSystemClockFreq();
-        break;
-
-      case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() != 0U)
-        {
-          if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
-          {
-            usart_frequency = (HSI_VALUE >> 2U);
-          }
-          else
-          {
-            usart_frequency = HSI_VALUE;
-          }
-        }
-        break;
-
-      case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
-        if (LL_RCC_LSE_IsReady() != 0U)
-        {
-          usart_frequency = LSE_VALUE;
-        }
-        break;
-
-      case LL_RCC_USART1_CLKSOURCE_PCLK2:  /* USART1 Clock is PCLK2 */
-      default:
-        usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-#endif /* RCC_CCIPR_USART1SEL  */
-
-#if defined(RCC_CCIPR_USART2SEL)
-  if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
-  {
-    /* USART2CLK clock frequency */
-    switch (LL_RCC_GetUSARTClockSource(USARTxSource))
-    {
-      case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
-        usart_frequency = RCC_GetSystemClockFreq();
-        break;
-
-      case LL_RCC_USART2_CLKSOURCE_HSI:    /* USART2 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() != 0U)
-        {
-          if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
-          {
-            usart_frequency = (HSI_VALUE >> 2U);
-          }
-          else
-          {
-            usart_frequency = HSI_VALUE;
-          }
-        }
-        break;
-
-      case LL_RCC_USART2_CLKSOURCE_LSE:    /* USART2 Clock is LSE Osc. */
-        if (LL_RCC_LSE_IsReady() != 0U)
-        {
-          usart_frequency = LSE_VALUE;
-        }
-        break;
-
-      case LL_RCC_USART2_CLKSOURCE_PCLK1:  /* USART2 Clock is PCLK1 */
-      default:
-        usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-#endif /* RCC_CCIPR_USART2SEL */
-
-  return usart_frequency;
-}
-
-/**
-  * @brief  Return I2Cx clock frequency
-  * @param  I2CxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
-  *         @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval I2C clock frequency (in Hz)
-  *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
-  */
-uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
-{
-  uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
-
-  /* I2C1 CLK clock frequency */
-  if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
-  {
-    switch (LL_RCC_GetI2CClockSource(I2CxSource))
-    {
-      case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
-        i2c_frequency = RCC_GetSystemClockFreq();
-        break;
-
-      case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() != 0U)
-        {
-          if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
-          {
-            i2c_frequency = (HSI_VALUE >> 2U);
-          }
-          else
-          {
-            i2c_frequency = HSI_VALUE;
-          }
-        }
-        break;
-
-      case LL_RCC_I2C1_CLKSOURCE_PCLK1:  /* I2C1 Clock is PCLK1 */
-      default:
-        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-
-#if defined(RCC_CCIPR_I2C3SEL)
-  /* I2C3 CLK clock frequency */
-  if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
-  {
-    switch (LL_RCC_GetI2CClockSource(I2CxSource))
-    {
-      case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
-        i2c_frequency = RCC_GetSystemClockFreq();
-        break;
-
-      case LL_RCC_I2C3_CLKSOURCE_HSI:    /* I2C3 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() != 0U)
-        {
-          if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
-          {
-            i2c_frequency = (HSI_VALUE >> 2U);
-          }
-          else
-          {
-            i2c_frequency = HSI_VALUE;
-          }
-        }
-        break;
-
-      case LL_RCC_I2C3_CLKSOURCE_PCLK1:  /* I2C3 Clock is PCLK1 */
-      default:
-        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-#endif /*RCC_CCIPR_I2C3SEL*/
-
-  return i2c_frequency;
-}
-
-/**
-  * @brief  Return LPUARTx clock frequency
-  * @param  LPUARTxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
-  * @retval LPUART clock frequency (in Hz)
-  *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
-  */
-uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
-{
-  uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
-
-  /* LPUART1CLK clock frequency */
-  switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
-  {
-    case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
-      lpuart_frequency = RCC_GetSystemClockFreq();
-      break;
-
-    case LL_RCC_LPUART1_CLKSOURCE_HSI:    /* LPUART1 Clock is HSI Osc. */
-      if (LL_RCC_HSI_IsReady() != 0U)
-      {
-        if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
-        {
-          lpuart_frequency = (HSI_VALUE >> 2U);
-        }
-        else
-        {
-          lpuart_frequency = HSI_VALUE;
-        }
-      }
-      break;
-
-    case LL_RCC_LPUART1_CLKSOURCE_LSE:    /* LPUART1 Clock is LSE Osc. */
-      if (LL_RCC_LSE_IsReady() != 0U)
-      {
-        lpuart_frequency = LSE_VALUE;
-      }
-      break;
-
-    case LL_RCC_LPUART1_CLKSOURCE_PCLK1:  /* LPUART1 Clock is PCLK1 */
-    default:
-      lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-      break;
-  }
-
-  return lpuart_frequency;
-}
-
-/**
-  * @brief  Return LPTIMx clock frequency
-  * @param  LPTIMxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
-  * @retval LPTIM clock frequency (in Hz)
-  *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
-  */
-uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
-{
-  uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
-
-  if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
-  {
-    /* LPTIM1CLK clock frequency */
-    switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
-    {
-      case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */
-        if (LL_RCC_LSI_IsReady() != 0U)
-        {
-          lptim_frequency = LSI_VALUE;
-        }
-        break;
-
-      case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() != 0U)
-        {
-          if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
-          {
-            lptim_frequency = (HSI_VALUE >> 2U);
-          }
-          else
-          {
-            lptim_frequency = HSI_VALUE;
-          }
-        }
-        break;
-
-      case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */
-        if (LL_RCC_LSE_IsReady() != 0U)
-        {
-          lptim_frequency = LSE_VALUE;
-        }
-        break;
-
-      case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */
-      default:
-        lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-
-  return lptim_frequency;
-}
-
-#if defined(USB)
-/**
-  * @brief  Return USBx clock frequency
-  * @param  USBxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE
-  * @retval USB clock frequency (in Hz)
-  *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
-  *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
-  */
-uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
-{
-  uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
-
-  /* USBCLK clock frequency */
-  switch (LL_RCC_GetUSBClockSource(USBxSource))
-  {
-    case LL_RCC_USB_CLKSOURCE_PLL:        /* PLL clock used as USB clock source */
-      if (LL_RCC_PLL_IsReady() != 0U)
-      {
-        usb_frequency = RCC_PLL_GetFreqDomain_SYS();
-      }
-      break;
-
-    case LL_RCC_USB_CLKSOURCE_HSI48:      /* HSI48 clock used as USB clock source */
-    default:
-      if (LL_RCC_HSI48_IsReady() != 0U)
-      {
-        usb_frequency = HSI48_VALUE;
-      }
-      break;
-  }
-
-  return usb_frequency;
-}
-#endif /* USB */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_LL_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Return SYSTEM clock frequency
-  * @retval SYSTEM clock frequency (in Hz)
-  */
-static uint32_t RCC_GetSystemClockFreq(void)
-{
-  uint32_t frequency;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (LL_RCC_GetSysClkSource())
-  {
-    case LL_RCC_SYS_CLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
-      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
-      break;
-
-    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
-      if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
-      {
-        frequency = (HSI_VALUE >> 2U);
-      }
-      else
-      {
-        frequency = HSI_VALUE;
-      }
-      break;
-
-    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock source */
-      frequency = HSE_VALUE;
-      break;
-
-    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
-      frequency = RCC_PLL_GetFreqDomain_SYS();
-      break;
-
-    default:
-      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
-      break;
-  }
-
-  return frequency;
-}
-
-/**
-  * @brief  Return HCLK clock frequency
-  * @param  SYSCLK_Frequency SYSCLK clock frequency
-  * @retval HCLK clock frequency (in Hz)
-  */
-static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
-{
-  /* HCLK clock frequency */
-  return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
-}
-
-/**
-  * @brief  Return PCLK1 clock frequency
-  * @param  HCLK_Frequency HCLK clock frequency
-  * @retval PCLK1 clock frequency (in Hz)
-  */
-static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
-{
-  /* PCLK1 clock frequency */
-  return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
-}
-
-/**
-  * @brief  Return PCLK2 clock frequency
-  * @param  HCLK_Frequency HCLK clock frequency
-  * @retval PCLK2 clock frequency (in Hz)
-  */
-static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
-{
-  /* PCLK2 clock frequency */
-  return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
-}
-
-/**
-  * @brief  Return PLL clock frequency used for system domain
-  * @retval PLL clock frequency (in Hz)
-  */
-static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
-{
-  uint32_t pllinputfreq, pllsource;
-
-  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
-
-  /* Get PLL source */
-  pllsource = LL_RCC_PLL_GetMainSource();
-
-  switch (pllsource)
-  {
-    case LL_RCC_PLLSOURCE_HSI:       /* HSI used as PLL clock source */
-      if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
-      {
-        pllinputfreq = (HSI_VALUE >> 2U);
-      }
-      else
-      {
-        pllinputfreq = HSI_VALUE;
-      }
-      break;
-
-    default:       /* HSE used as PLL clock source */
-      pllinputfreq = HSE_VALUE;
-      break;
-  }
-  return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider());
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(RCC) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c
deleted file mode 100644
index 67d52e35ee..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_rng.c
-  * @author  MCD Application Team
-  * @brief   RNG LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_rng.h"
-#include "stm32l0xx_ll_bus.h"
-
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (RNG)
-
-/** @addtogroup RNG_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RNG_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RNG_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize RNG registers (Registers restored to their default values).
-  * @param  RNGx RNG Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RNG registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
-{
-  /* Check the parameters */
-  assert_param(IS_RNG_ALL_INSTANCE(RNGx));
-  /* Enable RNG reset state */
-  LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG);
-
-  /* Release RNG from reset state */
-  LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG);
-  return (SUCCESS);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* RNG */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c
deleted file mode 100644
index e7d23cce71..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c
+++ /dev/null
@@ -1,868 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_rtc.c
-  * @author  MCD Application Team
-  * @brief   RTC LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_rtc.h"
-#include "stm32l0xx_ll_cortex.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined(RTC)
-
-/** @addtogroup RTC_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RTC_LL_Private_Constants
-  * @{
-  */
-/* Default values used for prescaler */
-#define RTC_ASYNCH_PRESC_DEFAULT     0x0000007FU
-#define RTC_SYNCH_PRESC_DEFAULT      0x000000FFU
-
-/* Values used for timeout */
-#define RTC_INITMODE_TIMEOUT         1000U /* 1s when tick set to 1ms */
-#define RTC_SYNCHRO_TIMEOUT          1000U /* 1s when tick set to 1ms */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RTC_LL_Private_Macros
-  * @{
-  */
-
-#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
-                                      || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
-
-#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= 0x7FU)
-
-#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= 0x7FFFU)
-
-#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
-                                  || ((__VALUE__) == LL_RTC_FORMAT_BCD))
-
-#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
-                                       || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
-
-#define IS_LL_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
-#define IS_LL_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)
-#define IS_LL_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)
-#define IS_LL_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)
-
-#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
-                                   || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
-                                   || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
-                                   || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
-                                   || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
-                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
-                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
-
-#define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
-
-#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
-
-#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
-
-#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
-                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
-                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
-                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
-                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
-                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
-
-#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
-                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
-                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
-                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
-                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
-                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
-
-
-#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
-                                                  ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
-
-#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
-                                                  ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
-
-
-/**
-  * @}
-  */
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RTC_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-Initializes the RTC registers to their default reset values.
-  * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
-  *         registers.
-  * @param  RTCx RTC Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC registers are de-initialized
-  *          - ERROR: RTC registers are not de-initialized
-  */
-ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameter */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
-  /* Disable the write protection for RTC registers */
-  LL_RTC_DisableWriteProtection(RTCx);
-
-  /* Set Initialization mode */
-  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
-  {
-    /* Reset TR, DR and CR registers */
-    WRITE_REG(RTCx->TR,       0x00000000U);
-#if defined(RTC_WAKEUP_SUPPORT)
-    WRITE_REG(RTCx->WUTR,     RTC_WUTR_WUT);
-#endif /* RTC_WAKEUP_SUPPORT */
-    WRITE_REG(RTCx->DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
-    /* Reset All CR bits except CR[2:0] */
-#if defined(RTC_WAKEUP_SUPPORT)
-    WRITE_REG(RTCx->CR, (READ_REG(RTCx->CR) & RTC_CR_WUCKSEL));
-#else
-    WRITE_REG(RTCx, CR, 0x00000000U);
-#endif /* RTC_WAKEUP_SUPPORT */
-    WRITE_REG(RTCx->PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
-    WRITE_REG(RTCx->ALRMAR,   0x00000000U);
-    WRITE_REG(RTCx->ALRMBR,   0x00000000U);
-    WRITE_REG(RTCx->SHIFTR,   0x00000000U);
-    WRITE_REG(RTCx->CALR,     0x00000000U);
-    WRITE_REG(RTCx->ALRMASSR, 0x00000000U);
-    WRITE_REG(RTCx->ALRMBSSR, 0x00000000U);
-
-    /* Reset ISR register and exit initialization mode */
-    WRITE_REG(RTCx->ISR,      0x00000000U);
-
-    /* Reset Tamper and alternate functions configuration register */
-    WRITE_REG(RTCx->TAMPCR, 0x00000000U);
-
-    /* Reset Option register */
-    WRITE_REG(RTCx->OR, 0x00000000U);
-
-    /* Wait till the RTC RSF flag is set */
-    status = LL_RTC_WaitForSynchro(RTCx);
-  }
-
-  /* Enable the write protection for RTC registers */
-  LL_RTC_EnableWriteProtection(RTCx);
-
-  return status;
-}
-
-/**
-  * @brief  Initializes the RTC registers according to the specified parameters
-  *         in RTC_InitStruct.
-  * @param  RTCx RTC Instance
-  * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
-  *         the configuration information for the RTC peripheral.
-  * @note   The RTC Prescaler register is write protected and can be written in
-  *         initialization mode only.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC registers are initialized
-  *          - ERROR: RTC registers are not initialized
-  */
-ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-  assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
-  assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
-  assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
-
-  /* Disable the write protection for RTC registers */
-  LL_RTC_DisableWriteProtection(RTCx);
-
-  /* Set Initialization mode */
-  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
-  {
-    /* Set Hour Format */
-    LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
-
-    /* Configure Synchronous and Asynchronous prescaler factor */
-    LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
-    LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
-
-    /* Exit Initialization mode */
-    LL_RTC_DisableInitMode(RTCx);
-
-    status = SUCCESS;
-  }
-  /* Enable the write protection for RTC registers */
-  LL_RTC_EnableWriteProtection(RTCx);
-
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_RTC_InitTypeDef field to default value.
-  * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
-  * @retval None
-  */
-void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
-{
-  /* Set RTC_InitStruct fields to default values */
-  RTC_InitStruct->HourFormat      = LL_RTC_HOURFORMAT_24HOUR;
-  RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
-  RTC_InitStruct->SynchPrescaler  = RTC_SYNCH_PRESC_DEFAULT;
-}
-
-/**
-  * @brief  Set the RTC current time.
-  * @param  RTCx RTC Instance
-  * @param  RTC_Format This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_FORMAT_BIN
-  *         @arg @ref LL_RTC_FORMAT_BCD
-  * @param  RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
-  *                        the time configuration information for the RTC.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC Time register is configured
-  *          - ERROR: RTC Time register is not configured
-  */
-ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
-
-  if (RTC_Format == LL_RTC_FORMAT_BIN)
-  {
-    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
-    {
-      assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
-      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
-    }
-    else
-    {
-      RTC_TimeStruct->TimeFormat = 0x00U;
-      assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
-    }
-    assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
-    assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
-  }
-  else
-  {
-    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
-    {
-      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
-      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
-    }
-    else
-    {
-      RTC_TimeStruct->TimeFormat = 0x00U;
-      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
-    }
-    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
-    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
-  }
-
-  /* Disable the write protection for RTC registers */
-  LL_RTC_DisableWriteProtection(RTCx);
-
-  /* Set Initialization mode */
-  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
-  {
-    /* Check the input parameters format */
-    if (RTC_Format != LL_RTC_FORMAT_BIN)
-    {
-      LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
-                         RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
-    }
-    else
-    {
-      LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
-                         __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
-                         __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
-    }
-
-    /* Exit Initialization mode */
-    LL_RTC_DisableInitMode(RTCx);
-
-    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
-    {
-      status = LL_RTC_WaitForSynchro(RTCx);
-    }
-    else
-    {
-      status = SUCCESS;
-    }
-  }
-  /* Enable the write protection for RTC registers */
-  LL_RTC_EnableWriteProtection(RTCx);
-
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
-  * @param  RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
-  * @retval None
-  */
-void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
-{
-  /* Time = 00h:00min:00sec */
-  RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
-  RTC_TimeStruct->Hours      = 0U;
-  RTC_TimeStruct->Minutes    = 0U;
-  RTC_TimeStruct->Seconds    = 0U;
-}
-
-/**
-  * @brief  Set the RTC current date.
-  * @param  RTCx RTC Instance
-  * @param  RTC_Format This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_FORMAT_BIN
-  *         @arg @ref LL_RTC_FORMAT_BCD
-  * @param  RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
-  *                        the date configuration information for the RTC.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC Day register is configured
-  *          - ERROR: RTC Day register is not configured
-  */
-ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
-
-  if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
-  {
-    RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU;
-  }
-  if (RTC_Format == LL_RTC_FORMAT_BIN)
-  {
-    assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
-    assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
-    assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
-  }
-  else
-  {
-    assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
-    assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
-    assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
-  }
-  assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
-
-  /* Disable the write protection for RTC registers */
-  LL_RTC_DisableWriteProtection(RTCx);
-
-  /* Set Initialization mode */
-  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
-  {
-    /* Check the input parameters format */
-    if (RTC_Format != LL_RTC_FORMAT_BIN)
-    {
-      LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
-    }
-    else
-    {
-      LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
-                         __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
-    }
-
-    /* Exit Initialization mode */
-    LL_RTC_DisableInitMode(RTCx);
-
-    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
-    {
-      status = LL_RTC_WaitForSynchro(RTCx);
-    }
-    else
-    {
-      status = SUCCESS;
-    }
-  }
-  /* Enable the write protection for RTC registers */
-  LL_RTC_EnableWriteProtection(RTCx);
-
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
-  * @param  RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
-  * @retval None
-  */
-void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
-{
-  /* Monday, January 01 xx00 */
-  RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
-  RTC_DateStruct->Day     = 1U;
-  RTC_DateStruct->Month   = LL_RTC_MONTH_JANUARY;
-  RTC_DateStruct->Year    = 0U;
-}
-
-/**
-  * @brief  Set the RTC Alarm A.
-  * @note   The Alarm register can only be written when the corresponding Alarm
-  *         is disabled (Use @ref LL_RTC_ALMA_Disable function).
-  * @param  RTCx RTC Instance
-  * @param  RTC_Format This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_FORMAT_BIN
-  *         @arg @ref LL_RTC_FORMAT_BCD
-  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
-  *                         contains the alarm configuration parameters.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ALARMA registers are configured
-  *          - ERROR: ALARMA registers are not configured
-  */
-ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
-  assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
-  assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
-
-  if (RTC_Format == LL_RTC_FORMAT_BIN)
-  {
-    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
-    {
-      assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
-      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
-    }
-    assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
-    assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
-
-    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
-    }
-  }
-  else
-  {
-    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
-    {
-      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
-      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
-    }
-
-    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
-    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
-
-    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
-    }
-    else
-    {
-      assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
-    }
-  }
-
-  /* Disable the write protection for RTC registers */
-  LL_RTC_DisableWriteProtection(RTCx);
-
-  /* Select weekday selection */
-  if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
-  {
-    /* Set the date for ALARM */
-    LL_RTC_ALMA_DisableWeekday(RTCx);
-    if (RTC_Format != LL_RTC_FORMAT_BIN)
-    {
-      LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
-    }
-    else
-    {
-      LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
-    }
-  }
-  else
-  {
-    /* Set the week day for ALARM */
-    LL_RTC_ALMA_EnableWeekday(RTCx);
-    LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
-  }
-
-  /* Configure the Alarm register */
-  if (RTC_Format != LL_RTC_FORMAT_BIN)
-  {
-    LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
-                           RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
-  }
-  else
-  {
-    LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
-                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
-                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
-                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
-  }
-  /* Set ALARM mask */
-  LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
-
-  /* Enable the write protection for RTC registers */
-  LL_RTC_EnableWriteProtection(RTCx);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set the RTC Alarm B.
-  * @note   The Alarm register can only be written when the corresponding Alarm
-  *         is disabled (@ref LL_RTC_ALMB_Disable function).
-  * @param  RTCx RTC Instance
-  * @param  RTC_Format This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_FORMAT_BIN
-  *         @arg @ref LL_RTC_FORMAT_BCD
-  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
-  *                         contains the alarm configuration parameters.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ALARMB registers are configured
-  *          - ERROR: ALARMB registers are not configured
-  */
-ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
-  assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
-  assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
-
-  if (RTC_Format == LL_RTC_FORMAT_BIN)
-  {
-    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
-    {
-      assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
-      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
-    }
-    assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
-    assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
-
-    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
-    }
-  }
-  else
-  {
-    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
-    {
-      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
-      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
-    }
-
-    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
-    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
-
-    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
-    }
-    else
-    {
-      assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
-    }
-  }
-
-  /* Disable the write protection for RTC registers */
-  LL_RTC_DisableWriteProtection(RTCx);
-
-  /* Select weekday selection */
-  if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
-  {
-    /* Set the date for ALARM */
-    LL_RTC_ALMB_DisableWeekday(RTCx);
-    if (RTC_Format != LL_RTC_FORMAT_BIN)
-    {
-      LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
-    }
-    else
-    {
-      LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
-    }
-  }
-  else
-  {
-    /* Set the week day for ALARM */
-    LL_RTC_ALMB_EnableWeekday(RTCx);
-    LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
-  }
-
-  /* Configure the Alarm register */
-  if (RTC_Format != LL_RTC_FORMAT_BIN)
-  {
-    LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
-                           RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
-  }
-  else
-  {
-    LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
-                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
-                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
-                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
-  }
-  /* Set ALARM mask */
-  LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
-
-  /* Enable the write protection for RTC registers */
-  LL_RTC_EnableWriteProtection(RTCx);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
-  *         Day = 1st day of the month/Mask = all fields are masked).
-  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
-  * @retval None
-  */
-void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
-  /* Alarm Time Settings : Time = 00h:00mn:00sec */
-  RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
-  RTC_AlarmStruct->AlarmTime.Hours      = 0U;
-  RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
-  RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
-
-  /* Alarm Day Settings : Day = 1st day of the month */
-  RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
-  RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
-
-  /* Alarm Masks Settings : Mask =  all fields are not masked */
-  RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMA_MASK_NONE;
-}
-
-/**
-  * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
-  *         Day = 1st day of the month/Mask = all fields are masked).
-  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
-  * @retval None
-  */
-void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
-  /* Alarm Time Settings : Time = 00h:00mn:00sec */
-  RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
-  RTC_AlarmStruct->AlarmTime.Hours      = 0U;
-  RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
-  RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
-
-  /* Alarm Day Settings : Day = 1st day of the month */
-  RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
-  RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
-
-  /* Alarm Masks Settings : Mask =  all fields are not masked */
-  RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMB_MASK_NONE;
-}
-
-/**
-  * @brief  Enters the RTC Initialization mode.
-  * @note   The RTC Initialization mode is write protected, use the
-  *         @ref LL_RTC_DisableWriteProtection before calling this function.
-  * @param  RTCx RTC Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC is in Init mode
-  *          - ERROR: RTC is not in Init mode
-  */
-ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
-{
-  __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
-  ErrorStatus status = SUCCESS;
-  uint32_t tmp;
-
-  /* Check the parameter */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
-  /* Check if the Initialization mode is set */
-  if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
-  {
-    /* Set the Initialization mode */
-    LL_RTC_EnableInitMode(RTCx);
-
-    /* Wait till RTC is in INIT state and if Time out is reached exit */
-    tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
-    while ((timeout != 0U) && (tmp != 1U))
-    {
-      if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
-      {
-        timeout --;
-      }
-      tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
-      if (timeout == 0U)
-      {
-        status = ERROR;
-      }
-    }
-  }
-  return status;
-}
-
-/**
-  * @brief  Exit the RTC Initialization mode.
-  * @note   When the initialization sequence is complete, the calendar restarts
-  *         counting after 4 RTCCLK cycles.
-  * @note   The RTC Initialization mode is write protected, use the
-  *         @ref LL_RTC_DisableWriteProtection before calling this function.
-  * @param  RTCx RTC Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC exited from in Init mode
-  *          - ERROR: Not applicable
-  */
-ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
-{
-  /* Check the parameter */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
-  /* Disable initialization mode */
-  LL_RTC_DisableInitMode(RTCx);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
-  *         synchronized with RTC APB clock.
-  * @note   The RTC Resynchronization mode is write protected, use the
-  *         @ref LL_RTC_DisableWriteProtection before calling this function.
-  * @note   To read the calendar through the shadow registers after Calendar
-  *         initialization, calendar update or after wakeup from low power modes
-  *         the software must first clear the RSF flag.
-  *         The software must then wait until it is set again before reading
-  *         the calendar, which means that the calendar registers have been
-  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
-  * @param  RTCx RTC Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC registers are synchronised
-  *          - ERROR: RTC registers are not synchronised
-  */
-ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
-{
-  __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
-  ErrorStatus status = SUCCESS;
-  uint32_t tmp;
-
-  /* Check the parameter */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
-  /* Clear RSF flag */
-  LL_RTC_ClearFlag_RS(RTCx);
-
-  /* Wait the registers to be synchronised */
-  tmp = LL_RTC_IsActiveFlag_RS(RTCx);
-  while ((timeout != 0U) && (tmp != 0U))
-  {
-    if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
-    {
-      timeout--;
-    }
-    tmp = LL_RTC_IsActiveFlag_RS(RTCx);
-    if (timeout == 0U)
-    {
-      status = ERROR;
-    }
-  }
-
-  if (status != ERROR)
-  {
-    timeout = RTC_SYNCHRO_TIMEOUT;
-    tmp = LL_RTC_IsActiveFlag_RS(RTCx);
-    while ((timeout != 0U) && (tmp != 1U))
-    {
-      if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
-      {
-        timeout--;
-      }
-      tmp = LL_RTC_IsActiveFlag_RS(RTCx);
-      if (timeout == 0U)
-      {
-        status = ERROR;
-      }
-    }
-  }
-
-  return (status);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(RTC) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c
deleted file mode 100644
index 5a78c599c6..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c
+++ /dev/null
@@ -1,518 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_spi.c
-  * @author  MCD Application Team
-  * @brief   SPI LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_spi.h"
-#include "stm32l0xx_ll_bus.h"
-#include "stm32l0xx_ll_rcc.h"
-
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (SPI1) || defined (SPI2)
-
-/** @addtogroup SPI_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Constants SPI Private Constants
-  * @{
-  */
-/* SPI registers Masks */
-#define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
-                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
-                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_DFF    | \
-                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
-                                            SPI_CR1_BIDIMODE)
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Macros SPI Private Macros
-  * @{
-  */
-#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
-                                                 || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
-                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
-                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
-
-#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
-                                   || ((__VALUE__) == LL_SPI_MODE_SLAVE))
-
-#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
-
-#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
-                                       || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
-
-#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
-                                    || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
-
-#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT)          \
-                                  || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
-                                  || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
-
-#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
-
-#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
-                                       || ((__VALUE__) == LL_SPI_MSB_FIRST))
-
-#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
-                                             || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
-
-#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SPI_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the SPI registers to their default reset values.
-  * @param  SPIx SPI Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: SPI registers are de-initialized
-  *          - ERROR: SPI registers are not de-initialized
-  */
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
-#if defined(SPI1)
-  if (SPIx == SPI1)
-  {
-    /* Force reset of SPI clock */
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
-
-    /* Release reset of SPI clock */
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
-
-    status = SUCCESS;
-  }
-#endif /* SPI1 */
-#if defined(SPI2)
-  if (SPIx == SPI2)
-  {
-    /* Force reset of SPI clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
-
-    /* Release reset of SPI clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
-
-    status = SUCCESS;
-  }
-#endif /* SPI2 */
-
-  return status;
-}
-
-/**
-  * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
-  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
-  *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
-  * @param  SPIx SPI Instance
-  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
-  */
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the SPI Instance SPIx*/
-  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
-  /* Check the SPI parameters from SPI_InitStruct*/
-  assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
-  assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
-  assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
-  assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
-  assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
-  assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
-  assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
-  assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
-  assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
-
-  if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
-  {
-    /*---------------------------- SPIx CR1 Configuration ------------------------
-     * Configure SPIx CR1 with parameters:
-     * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
-     * - Master/Slave Mode:  SPI_CR1_MSTR bit
-     * - DataWidth:          SPI_CR1_DFF bit
-     * - ClockPolarity:      SPI_CR1_CPOL bit
-     * - ClockPhase:         SPI_CR1_CPHA bit
-     * - NSS management:     SPI_CR1_SSM bit
-     * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
-     * - BitOrder:           SPI_CR1_LSBFIRST bit
-     * - CRCCalculation:     SPI_CR1_CRCEN bit
-     */
-    MODIFY_REG(SPIx->CR1,
-               SPI_CR1_CLEAR_MASK,
-               SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
-               SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
-               SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
-               SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
-
-    /*---------------------------- SPIx CR2 Configuration ------------------------
-     * Configure SPIx CR2 with parameters:
-     * - NSS management:     SSOE bit
-     */
-    MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
-
-    /*---------------------------- SPIx CRCPR Configuration ----------------------
-     * Configure SPIx CRCPR with parameters:
-     * - CRCPoly:            CRCPOLY[15:0] bits
-     */
-    if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
-    {
-      assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
-      LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
-    }
-    status = SUCCESS;
-  }
-
-#if defined (SPI_I2S_SUPPORT)
-  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
-  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2S_SUPPORT */
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
-  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
-  * whose fields will be set to default values.
-  * @retval None
-  */
-void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
-{
-  /* Set SPI_InitStruct fields to default values */
-  SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
-  SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
-  SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
-  SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
-  SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
-  SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
-  SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
-  SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
-  SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
-  SPI_InitStruct->CRCPoly           = 7U;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @addtogroup I2S_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Constants I2S Private Constants
-  * @{
-  */
-/* I2S registers Masks */
-#define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
-                                            SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
-                                            SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
-
-#define I2S_I2SPR_CLEAR_MASK               0x0002U
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Macros I2S Private Macros
-  * @{
-  */
-
-#define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)             \
-                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
-                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
-                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
-
-#define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
-                                          || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
-
-#define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)      \
-                                          || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
-                                          || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
-                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
-                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
-
-#define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)     \
-                                          || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
-                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
-                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
-
-#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
-                                          || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
-
-#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)       \
-                                          && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
-                                         || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
-
-#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
-                                               || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2S_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the SPI/I2S registers to their default reset values.
-  * @param  SPIx SPI Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: SPI registers are de-initialized
-  *          - ERROR: SPI registers are not de-initialized
-  */
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_DeInit(SPIx);
-}
-
-/**
-  * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
-  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
-  *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
-  * @param  SPIx SPI Instance
-  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: SPI registers are Initialized
-  *          - ERROR: SPI registers are not Initialized
-  */
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
-{
-  uint32_t i2sdiv = 2U;
-  uint32_t i2sodd = 0U;
-  uint32_t packetlength = 1U;
-  uint32_t tmp;
-  LL_RCC_ClocksTypeDef rcc_clocks;
-  uint32_t sourceclock;
-  ErrorStatus status = ERROR;
-
-  /* Check the I2S parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
-  assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
-  assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
-  assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
-  assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
-  assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
-  assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
-
-  if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
-  {
-    /*---------------------------- SPIx I2SCFGR Configuration --------------------
-     * Configure SPIx I2SCFGR with parameters:
-     * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
-     * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
-     * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
-     * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
-     */
-
-    /* Write to SPIx I2SCFGR */
-    MODIFY_REG(SPIx->I2SCFGR,
-               I2S_I2SCFGR_CLEAR_MASK,
-               I2S_InitStruct->Mode | I2S_InitStruct->Standard |
-               I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
-               SPI_I2SCFGR_I2SMOD);
-
-    /*---------------------------- SPIx I2SPR Configuration ----------------------
-     * Configure SPIx I2SPR with parameters:
-     * - MCLKOutput:    SPI_I2SPR_MCKOE bit
-     * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
-     */
-
-    /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
-     * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
-     */
-    if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
-    {
-      /* Check the frame length (For the Prescaler computing)
-       * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
-       */
-      if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
-      {
-        /* Packet length is 32 bits */
-        packetlength = 2U;
-      }
-
-      /* I2S Clock source is System clock: Get System Clock frequency */
-      LL_RCC_GetSystemClocksFreq(&rcc_clocks);
-
-      /* Get the source clock value: based on System Clock value */
-      sourceclock = rcc_clocks.SYSCLK_Frequency;
-
-      /* Compute the Real divider depending on the MCLK output state with a floating point */
-      if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
-      {
-        /* MCLK output is enabled */
-        tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
-      }
-      else
-      {
-        /* MCLK output is disabled */
-        tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
-      }
-
-      /* Remove the floating point */
-      tmp = tmp / 10U;
-
-      /* Check the parity of the divider */
-      i2sodd = (tmp & (uint16_t)0x0001U);
-
-      /* Compute the i2sdiv prescaler */
-      i2sdiv = ((tmp - i2sodd) / 2U);
-
-      /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-      i2sodd = (i2sodd << 8U);
-    }
-
-    /* Test if the divider is 1 or 0 or greater than 0xFF */
-    if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
-    {
-      /* Set the default values */
-      i2sdiv = 2U;
-      i2sodd = 0U;
-    }
-
-    /* Write to SPIx I2SPR register the computed value */
-    WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
-
-    status = SUCCESS;
-  }
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
-  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
-  *         whose fields will be set to default values.
-  * @retval None
-  */
-void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
-{
-  /*--------------- Reset I2S init structure parameters values -----------------*/
-  I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
-  I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
-  I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
-  I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
-  I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
-  I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
-}
-
-/**
-  * @brief  Set linear and parity prescaler.
-  * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
-  *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
-  * @param  SPIx SPI Instance
-  * @param  PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
-  * @param  PrescalerParity This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
-  * @retval None
-  */
-void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
-{
-  /* Check the I2S parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
-  assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
-  assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
-
-  /* Write to SPIx I2SPR */
-  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c
deleted file mode 100644
index fd874d510d..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c
+++ /dev/null
@@ -1,854 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_tim.c
-  * @author  MCD Application Team
-  * @brief   TIM LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_tim.h"
-#include "stm32l0xx_ll_bus.h"
-
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (TIM2) || defined (TIM3) || defined (TIM21) || defined (TIM22) || defined (TIM6) || defined (TIM7)
-
-/** @addtogroup TIM_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup TIM_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
-                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
-                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
-                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
-                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
-
-#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
-                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
-                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
-
-#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
-
-#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
-                                      || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
-
-#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
-                                         || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
-
-#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
-                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
-                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
-
-#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
-                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
-                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
-                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
-
-#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
-
-#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
-                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
-                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
-
-#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
-                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
-                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
-
-#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
-                                                  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
-/**
-  * @}
-  */
-
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup TIM_LL_Private_Functions TIM Private Functions
-  * @{
-  */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup TIM_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  Set TIMx registers to their reset values.
-  * @param  TIMx Timer instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: invalid TIMx instance
-  */
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
-{
-  ErrorStatus result = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(TIMx));
-
-  if (TIMx == TIM2)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
-  }
-#if defined(TIM3)
-  else if (TIMx == TIM3)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
-  }
-#endif /* TIM3 */
-#if defined(TIM6)
-  else if (TIMx == TIM6)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
-  }
-#endif /* TIM6 */
-#if defined(TIM7)
-  else if (TIMx == TIM7)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
-  }
-#endif /* TIM7 */
-  else if (TIMx == TIM21)
-  {
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM21);
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM21);
-  }
-#if defined(TIM22)
-  else if (TIMx == TIM22)
-  {
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM22);
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM22);
-  }
-#endif /* TIM22 */
-  else
-  {
-    result = ERROR;
-  }
-
-  return result;
-}
-
-/**
-  * @brief  Set the fields of the time base unit configuration data structure
-  *         to their default values.
-  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
-  * @retval None
-  */
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
-{
-  /* Set the default configuration */
-  TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
-  TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
-  TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
-  TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
-}
-
-/**
-  * @brief  Configure the TIMx time base unit.
-  * @param  TIMx Timer Instance
-  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
-  *         (TIMx time base unit configuration data structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
-{
-  uint32_t tmpcr1;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
-  assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
-
-  tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
-
-  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
-  {
-    /* Select the Counter Mode */
-    MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
-  }
-
-  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
-  {
-    /* Set the clock division */
-    MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
-  }
-
-  /* Write to TIMx CR1 */
-  LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
-
-  /* Set the Autoreload value */
-  LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
-
-  /* Set the Prescaler value */
-  LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
-  /* Generate an update event to reload the Prescaler
-     and the repetition counter value (if applicable) immediately */
-  LL_TIM_GenerateEvent_UPDATE(TIMx);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set the fields of the TIMx output channel configuration data
-  *         structure to their default values.
-  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
-  *         (the output channel configuration data structure)
-  * @retval None
-  */
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
-  /* Set the default configuration */
-  TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
-  TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
-  TIM_OC_InitStruct->CompareValue = 0x00000000U;
-  TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
-}
-
-/**
-  * @brief  Configure the TIMx output channel.
-  * @param  TIMx Timer Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
-  *         data structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx output channel is initialized
-  *          - ERROR: TIMx output channel is not initialized
-  */
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
-  ErrorStatus result = ERROR;
-
-  switch (Channel)
-  {
-    case LL_TIM_CHANNEL_CH1:
-      result = OC1Config(TIMx, TIM_OC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH2:
-      result = OC2Config(TIMx, TIM_OC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH3:
-      result = OC3Config(TIMx, TIM_OC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH4:
-      result = OC4Config(TIMx, TIM_OC_InitStruct);
-      break;
-    default:
-      break;
-  }
-
-  return result;
-}
-
-/**
-  * @brief  Set the fields of the TIMx input channel configuration data
-  *         structure to their default values.
-  * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
-  *         data structure)
-  * @retval None
-  */
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Set the default configuration */
-  TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
-  TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
-  TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
-  TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
-  * @brief  Configure the TIMx input channel.
-  * @param  TIMx Timer Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
-  *         structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx output channel is initialized
-  *          - ERROR: TIMx output channel is not initialized
-  */
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
-{
-  ErrorStatus result = ERROR;
-
-  switch (Channel)
-  {
-    case LL_TIM_CHANNEL_CH1:
-      result = IC1Config(TIMx, TIM_IC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH2:
-      result = IC2Config(TIMx, TIM_IC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH3:
-      result = IC3Config(TIMx, TIM_IC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH4:
-      result = IC4Config(TIMx, TIM_IC_InitStruct);
-      break;
-    default:
-      break;
-  }
-
-  return result;
-}
-
-/**
-  * @brief  Fills each TIM_EncoderInitStruct field with its default value
-  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
-  *         configuration data structure)
-  * @retval None
-  */
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
-  /* Set the default configuration */
-  TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
-  TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
-  TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
-  TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
-  TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
-  TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
-  TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
-  TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
-  TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
-  * @brief  Configure the encoder interface of the timer instance.
-  * @param  TIMx Timer Instance
-  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
-  *         configuration data structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
-  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
-  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
-
-  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
-  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
-  /* Get the TIMx CCER register value */
-  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Configure TI1 */
-  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
-
-  /* Configure TI2 */
-  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
-
-  /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
-  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
-  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
-  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
-  /* Set encoder mode */
-  LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
-
-  /* Write to TIMx CCMR1 */
-  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
-  *  @brief   Private functions
-  * @{
-  */
-/**
-  * @brief  Configure the TIMx output channel 1.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
-  /* Reset Capture/Compare selection Bits */
-  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
-
-  /* Set the Output Compare Mode */
-  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx CCMR1 */
-  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx output channel 2.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
-  /* Reset Capture/Compare selection Bits */
-  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
-
-  /* Select the Output Compare Mode */
-  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx CCMR1 */
-  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx output channel 3.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr2;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
-  /* Reset Capture/Compare selection Bits */
-  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
-
-  /* Select the Output Compare Mode */
-  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx CCMR2 */
-  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx output channel 4.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr2;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
-  /* Reset Capture/Compare selection Bits */
-  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
-
-  /* Select the Output Compare Mode */
-  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx CCMR2 */
-  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-
-/**
-  * @brief  Configure the TIMx input channel 1.
-  * @param  TIMx Timer Instance
-  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
-
-  /* Select the Input and set the filter and the prescaler value */
-  MODIFY_REG(TIMx->CCMR1,
-             (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
-             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
-  /* Select the Polarity and set the CC1E Bit */
-  MODIFY_REG(TIMx->CCER,
-             (TIM_CCER_CC1P | TIM_CCER_CC1NP),
-             (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx input channel 2.
-  * @param  TIMx Timer Instance
-  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
-
-  /* Select the Input and set the filter and the prescaler value */
-  MODIFY_REG(TIMx->CCMR1,
-             (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
-             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
-  /* Select the Polarity and set the CC2E Bit */
-  MODIFY_REG(TIMx->CCER,
-             (TIM_CCER_CC2P | TIM_CCER_CC2NP),
-             ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx input channel 3.
-  * @param  TIMx Timer Instance
-  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
-
-  /* Select the Input and set the filter and the prescaler value */
-  MODIFY_REG(TIMx->CCMR2,
-             (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
-             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
-  /* Select the Polarity and set the CC3E Bit */
-  MODIFY_REG(TIMx->CCER,
-             (TIM_CCER_CC3P | TIM_CCER_CC3NP),
-             ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx input channel 4.
-  * @param  TIMx Timer Instance
-  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
-
-  /* Select the Input and set the filter and the prescaler value */
-  MODIFY_REG(TIMx->CCMR2,
-             (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
-             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
-  /* Select the Polarity and set the CC2E Bit */
-  MODIFY_REG(TIMx->CCER,
-             (TIM_CCER_CC4P | TIM_CCER_CC4NP),
-             ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
-
-  return SUCCESS;
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* TIM1 || TIM3 || TIM21 || TIM22 || TIM6 || TIM7 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c
deleted file mode 100644
index 07e3f96e74..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c
+++ /dev/null
@@ -1,420 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_usart.c
-  * @author  MCD Application Team
-  * @brief   USART LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_usart.h"
-#include "stm32l0xx_ll_rcc.h"
-#include "stm32l0xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-#if defined (USART1) || defined (USART2) || defined (USART4) || defined (USART5)
-
-/** @addtogroup USART_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Macros
-  * @{
-  */
-
-/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
- *              divided by the smallest oversampling used on the USART (i.e. 8)    */
-#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 4000000U)
-
-/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
-#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
-
-#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
-                                          || ((__VALUE__) == LL_USART_DIRECTION_RX) \
-                                          || ((__VALUE__) == LL_USART_DIRECTION_TX) \
-                                          || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
-
-#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
-                                       || ((__VALUE__) == LL_USART_PARITY_EVEN) \
-                                       || ((__VALUE__) == LL_USART_PARITY_ODD))
-
-#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
-                                          || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
-                                          || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
-
-#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
-                                             || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
-
-#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
-                                                 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
-
-#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
-                                           || ((__VALUE__) == LL_USART_PHASE_2EDGE))
-
-#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
-                                              || ((__VALUE__) == LL_USART_POLARITY_HIGH))
-
-#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
-                                            || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
-
-#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
-                                         || ((__VALUE__) == LL_USART_STOPBITS_1) \
-                                         || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
-                                         || ((__VALUE__) == LL_USART_STOPBITS_2))
-
-#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
-                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
-                                          || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
-                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup USART_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize USART registers (Registers restored to their default values).
-  * @param  USARTx USART Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: USART registers are de-initialized
-  *          - ERROR: USART registers are not de-initialized
-  */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(USARTx));
-
-#if defined(USART1)
-  if (USARTx == USART1)
-  {
-    /* Force reset of USART clock */
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
-
-    /* Release reset of USART clock */
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
-  }
-#endif /* USART1 */
-#if defined(USART1)
-  else if (USARTx == USART2)
-#else
-  if (USARTx == USART2)
-#endif /* USART1 */
-  {
-    /* Force reset of USART clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
-
-    /* Release reset of USART clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
-  }
-#if defined(USART4)
-  else if (USARTx == USART4)
-  {
-    /* Force reset of USART clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4);
-
-    /* Release reset of USART clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4);
-  }
-#endif /* USART4 */
-#if defined(USART5)
-  else if (USARTx == USART5)
-  {
-    /* Force reset of USART clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5);
-
-    /* Release reset of USART clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5);
-  }
-#endif /* USART5 */
-  else
-  {
-    status = ERROR;
-  }
-
-  return (status);
-}
-
-/**
-  * @brief  Initialize USART registers according to the specified
-  *         parameters in USART_InitStruct.
-  * @note   As some bits in USART configuration registers can only be written when
-  *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
-  *         this function. Otherwise, ERROR result will be returned.
-  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
-  * @param  USARTx USART Instance
-  * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
-  *         that contains the configuration information for the specified USART peripheral.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
-  *          - ERROR: Problem occurred during USART Registers initialization
-  */
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
-{
-  ErrorStatus status = ERROR;
-  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
-#if defined(USART4) || defined(USART5)
-  LL_RCC_ClocksTypeDef RCC_Clocks;
-#endif /* USART4 || USART5 */
-
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(USARTx));
-  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
-  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
-  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
-  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
-  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
-  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
-  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
-
-  /* USART needs to be in disabled state, in order to be able to configure some bits in
-     CRx registers */
-  if (LL_USART_IsEnabled(USARTx) == 0U)
-  {
-    /*---------------------------- USART CR1 Configuration ---------------------
-     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
-     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
-     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
-     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
-     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
-     */
-    MODIFY_REG(USARTx->CR1,
-               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
-                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
-               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
-                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
-
-    /*---------------------------- USART CR2 Configuration ---------------------
-     * Configure USARTx CR2 (Stop bits) with parameters:
-     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
-     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
-     */
-    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
-
-    /*---------------------------- USART CR3 Configuration ---------------------
-     * Configure USARTx CR3 (Hardware Flow Control) with parameters:
-     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
-     *   USART_InitStruct->HardwareFlowControl value.
-     */
-    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
-
-    /*---------------------------- USART BRR Configuration ---------------------
-     * Retrieve Clock frequency used for USART Peripheral
-     */
-#if defined(USART1)
-    if (USARTx == USART1)
-    {
-      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
-    }
-#endif /* USART1 */
-#if defined(USART1)
-    else if (USARTx == USART2)
-#else
-    if (USARTx == USART2)
-#endif /* USART1 */
-    {
-      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
-    }
-#if defined(USART4)
-    else if (USARTx == USART4)
-    {
-      /* USART4 clock is PCLK1 */
-      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
-      periphclk = RCC_Clocks.PCLK1_Frequency;
-    }
-#endif /* USART4 */
-#if defined(USART5)
-    else if (USARTx == USART5)
-    {
-      /* USART5 clock is PCLK1 */
-      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
-      periphclk = RCC_Clocks.PCLK1_Frequency;
-    }
-#endif /* USART5 */
-    else
-    {
-      /* Nothing to do, as error code is already assigned to ERROR value */
-    }
-
-    /* Configure the USART Baud Rate :
-       - valid baud rate value (different from 0) is required
-       - Peripheral clock as returned by RCC service, should be valid (different from 0).
-    */
-    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
-        && (USART_InitStruct->BaudRate != 0U))
-    {
-      status = SUCCESS;
-      LL_USART_SetBaudRate(USARTx,
-                           periphclk,
-                           USART_InitStruct->OverSampling,
-                           USART_InitStruct->BaudRate);
-
-      /* Check BRR is greater than or equal to 16d */
-      assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
-    }
-  }
-  /* Endif (=> USART not in Disabled state => return ERROR) */
-
-  return (status);
-}
-
-/**
-  * @brief Set each @ref LL_USART_InitTypeDef field to default value.
-  * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
-  *                         whose fields will be set to default values.
-  * @retval None
-  */
-
-void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
-{
-  /* Set USART_InitStruct fields to default values */
-  USART_InitStruct->BaudRate            = 9600U;
-  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
-  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
-  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
-  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
-  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
-  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
-}
-
-/**
-  * @brief  Initialize USART Clock related settings according to the
-  *         specified parameters in the USART_ClockInitStruct.
-  * @note   As some bits in USART configuration registers can only be written when
-  *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
-  *         this function. Otherwise, ERROR result will be returned.
-  * @param  USARTx USART Instance
-  * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
-  *         that contains the Clock configuration information for the specified USART peripheral.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: USART registers related to Clock settings are initialized according
-  *                     to USART_ClockInitStruct content
-  *          - ERROR: Problem occurred during USART Registers initialization
-  */
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check USART Instance and Clock signal output parameters */
-  assert_param(IS_UART_INSTANCE(USARTx));
-  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
-
-  /* USART needs to be in disabled state, in order to be able to configure some bits in
-     CRx registers */
-  if (LL_USART_IsEnabled(USARTx) == 0U)
-  {
-    /* If USART Clock signal is disabled */
-    if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
-    {
-      /* Deactivate Clock signal delivery :
-       * - Disable Clock Output:        USART_CR2_CLKEN cleared
-       */
-      LL_USART_DisableSCLKOutput(USARTx);
-    }
-    else
-    {
-      /* Ensure USART instance is USART capable */
-      assert_param(IS_USART_INSTANCE(USARTx));
-
-      /* Check clock related parameters */
-      assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
-      assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
-      assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
-
-      /*---------------------------- USART CR2 Configuration -----------------------
-       * Configure USARTx CR2 (Clock signal related bits) with parameters:
-       * - Enable Clock Output:         USART_CR2_CLKEN set
-       * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
-       * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
-       * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
-       */
-      MODIFY_REG(USARTx->CR2,
-                 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
-                 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
-                 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
-    }
-  }
-  /* Else (USART not in Disabled state => return ERROR */
-  else
-  {
-    status = ERROR;
-  }
-
-  return (status);
-}
-
-/**
-  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
-  * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
-  *                              whose fields will be set to default values.
-  * @retval None
-  */
-void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
-{
-  /* Set LL_USART_ClockInitStruct fields with default values */
-  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
-  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput =
-                                                                                  LL_USART_CLOCK_DISABLE */
-  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput =
-                                                                                  LL_USART_CLOCK_DISABLE */
-  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput =
-                                                                                  LL_USART_CLOCK_DISABLE */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* USART1 || USART2 || USART4 || USART5 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usb.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usb.c
deleted file mode 100644
index 674c5fe376..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usb.c
+++ /dev/null
@@ -1,808 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_usb.c
-  * @author  MCD Application Team
-  * @brief   USB Low Layer HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the USB Peripheral Controller:
-  *           + Initialization/de-initialization functions
-  *           + I/O operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
-
-      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
-
-      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_hal.h"
-
-/** @addtogroup STM32L0xx_LL_USB_DRIVER
-  * @{
-  */
-
-#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
-#if defined (USB)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-/**
-  * @brief  Initializes the USB Core
-  * @param  USBx USB Instance
-  * @param  cfg pointer to a USB_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(USBx);
-  UNUSED(cfg);
-
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used
-              only by USB OTG FS peripheral.
-            - This function is added to ensure compatibility across platforms.
-   */
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EnableGlobalInt
-  *         Enables the controller's Global Int in the AHB Config reg
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
-{
-  uint32_t winterruptmask;
-
-  /* Clear pending interrupts */
-  USBx->ISTR = 0U;
-
-  /* Set winterruptmask variable */
-  winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM |
-                   USB_CNTR_SUSPM | USB_CNTR_ERRM |
-                   USB_CNTR_SOFM | USB_CNTR_ESOFM |
-                   USB_CNTR_RESETM | USB_CNTR_L1REQM;
-
-  /* Set interrupt mask */
-  USBx->CNTR = (uint16_t)winterruptmask;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DisableGlobalInt
-  *         Disable the controller's Global Int in the AHB Config reg
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
-{
-  uint32_t winterruptmask;
-
-  /* Set winterruptmask variable */
-  winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM |
-                   USB_CNTR_SUSPM | USB_CNTR_ERRM |
-                   USB_CNTR_SOFM | USB_CNTR_ESOFM |
-                   USB_CNTR_RESETM | USB_CNTR_L1REQM;
-
-  /* Clear interrupt mask */
-  USBx->CNTR &= (uint16_t)(~winterruptmask);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_SetCurrentMode Set functional mode
-  * @param  USBx Selected device
-  * @param  mode current core mode
-  *          This parameter can be one of the these values:
-  *            @arg USB_DEVICE_MODE Peripheral mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(USBx);
-  UNUSED(mode);
-
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used
-              only by USB OTG FS peripheral.
-            - This function is added to ensure compatibility across platforms.
-   */
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DevInit Initializes the USB controller registers
-  *         for device mode
-  * @param  USBx Selected device
-  * @param  cfg  pointer to a USB_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(cfg);
-
-  /* Init Device */
-  /* CNTR_FRES = 1 */
-  USBx->CNTR = (uint16_t)USB_CNTR_FRES;
-
-  /* CNTR_FRES = 0 */
-  USBx->CNTR = 0U;
-
-  /* Clear pending interrupts */
-  USBx->ISTR = 0U;
-
-  /*Set Btable Address*/
-  USBx->BTABLE = BTABLE_ADDRESS;
-
-  return HAL_OK;
-}
-
-#if defined (HAL_PCD_MODULE_ENABLED)
-/**
-  * @brief  Activate and configure an endpoint
-  * @param  USBx Selected device
-  * @param  ep pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
-  HAL_StatusTypeDef ret = HAL_OK;
-  uint16_t wEpRegVal;
-
-  wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
-
-  /* initialize Endpoint */
-  switch (ep->type)
-  {
-    case EP_TYPE_CTRL:
-      wEpRegVal |= USB_EP_CONTROL;
-      break;
-
-    case EP_TYPE_BULK:
-      wEpRegVal |= USB_EP_BULK;
-      break;
-
-    case EP_TYPE_INTR:
-      wEpRegVal |= USB_EP_INTERRUPT;
-      break;
-
-    case EP_TYPE_ISOC:
-      wEpRegVal |= USB_EP_ISOCHRONOUS;
-      break;
-
-    default:
-      ret = HAL_ERROR;
-      break;
-  }
-
-  PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
-
-  PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
-
-  if (ep->doublebuffer == 0U)
-  {
-    if (ep->is_in != 0U)
-    {
-      /*Set the endpoint Transmit buffer address */
-      PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
-      if (ep->type != EP_TYPE_ISOC)
-      {
-        /* Configure NAK status for the Endpoint */
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
-      }
-      else
-      {
-        /* Configure TX Endpoint to disabled state */
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
-      }
-    }
-    else
-    {
-      /* Set the endpoint Receive buffer address */
-      PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
-
-      /* Set the endpoint Receive buffer counter */
-      PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-
-      /* Configure VALID status for the Endpoint */
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
-    }
-  }
-  /* Double Buffer */
-  else
-  {
-    if (ep->type == EP_TYPE_BULK)
-    {
-      /* Set bulk endpoint as double buffered */
-      PCD_SET_BULK_EP_DBUF(USBx, ep->num);
-    }
-    else
-    {
-      /* Set the ISOC endpoint in double buffer mode */
-      PCD_CLEAR_EP_KIND(USBx, ep->num);
-    }
-
-    /* Set buffer address for double buffered mode */
-    PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
-
-    if (ep->is_in == 0U)
-    {
-      /* Clear the data toggle bits for the endpoint IN/OUT */
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
-      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
-    }
-    else
-    {
-      /* Clear the data toggle bits for the endpoint IN/OUT */
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
-      if (ep->type != EP_TYPE_ISOC)
-      {
-        /* Configure NAK status for the Endpoint */
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
-      }
-      else
-      {
-        /* Configure TX Endpoint to disabled state */
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
-      }
-
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
-    }
-  }
-
-  return ret;
-}
-
-/**
-  * @brief  De-activate and de-initialize an endpoint
-  * @param  USBx Selected device
-  * @param  ep pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
-  if (ep->doublebuffer == 0U)
-  {
-    if (ep->is_in != 0U)
-    {
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
-      /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
-    }
-    else
-    {
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-
-      /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
-    }
-  }
-  /*Double Buffer*/
-  else
-  {
-    if (ep->is_in == 0U)
-    {
-      /* Clear the data toggle bits for the endpoint IN/OUT*/
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
-      /* Reset value of the data toggle bits for the endpoint out*/
-      PCD_TX_DTOG(USBx, ep->num);
-
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
-      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
-    }
-    else
-    {
-      /* Clear the data toggle bits for the endpoint IN/OUT*/
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-      PCD_RX_DTOG(USBx, ep->num);
-
-      /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EPStartXfer setup and starts a transfer over an EP
-  * @param  USBx Selected device
-  * @param  ep pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
-  uint32_t len;
-  uint16_t pmabuffer;
-  uint16_t wEPVal;
-
-  /* IN endpoint */
-  if (ep->is_in == 1U)
-  {
-    /*Multi packet transfer*/
-    if (ep->xfer_len > ep->maxpacket)
-    {
-      len = ep->maxpacket;
-    }
-    else
-    {
-      len = ep->xfer_len;
-    }
-
-    /* configure and validate Tx endpoint */
-    if (ep->doublebuffer == 0U)
-    {
-      USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
-      PCD_SET_EP_TX_CNT(USBx, ep->num, len);
-    }
-    else
-    {
-      /* double buffer bulk management */
-      if (ep->type == EP_TYPE_BULK)
-      {
-        if (ep->xfer_len_db > ep->maxpacket)
-        {
-          /* enable double buffer */
-          PCD_SET_BULK_EP_DBUF(USBx, ep->num);
-
-          /* each Time to write in PMA xfer_len_db will */
-          ep->xfer_len_db -= len;
-
-          /* Fill the two first buffer in the Buffer0 & Buffer1 */
-          if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
-          {
-            /* Set the Double buffer counter for pmabuffer1 */
-            PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
-            pmabuffer = ep->pmaaddr1;
-
-            /* Write the user buffer to USB PMA */
-            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-            ep->xfer_buff += len;
-
-            if (ep->xfer_len_db > ep->maxpacket)
-            {
-              ep->xfer_len_db -= len;
-            }
-            else
-            {
-              len = ep->xfer_len_db;
-              ep->xfer_len_db = 0U;
-            }
-
-            /* Set the Double buffer counter for pmabuffer0 */
-            PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
-            pmabuffer = ep->pmaaddr0;
-
-            /* Write the user buffer to USB PMA */
-            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-          }
-          else
-          {
-            /* Set the Double buffer counter for pmabuffer0 */
-            PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
-            pmabuffer = ep->pmaaddr0;
-
-            /* Write the user buffer to USB PMA */
-            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-            ep->xfer_buff += len;
-
-            if (ep->xfer_len_db > ep->maxpacket)
-            {
-              ep->xfer_len_db -= len;
-            }
-            else
-            {
-              len = ep->xfer_len_db;
-              ep->xfer_len_db = 0U;
-            }
-
-            /* Set the Double buffer counter for pmabuffer1 */
-            PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
-            pmabuffer = ep->pmaaddr1;
-
-            /* Write the user buffer to USB PMA */
-            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-          }
-        }
-        /* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
-        else
-        {
-          len = ep->xfer_len_db;
-
-          /* disable double buffer mode for Bulk endpoint */
-          PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
-
-          /* Set Tx count with nbre of byte to be transmitted */
-          PCD_SET_EP_TX_CNT(USBx, ep->num, len);
-          pmabuffer = ep->pmaaddr0;
-
-          /* Write the user buffer to USB PMA */
-          USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-        }
-      }
-      else /* manage isochronous double buffer IN mode */
-      {
-        /* each Time to write in PMA xfer_len_db will */
-        ep->xfer_len_db -= len;
-
-        /* Fill the data buffer */
-        if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
-        {
-          /* Set the Double buffer counter for pmabuffer1 */
-          PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
-          pmabuffer = ep->pmaaddr1;
-
-          /* Write the user buffer to USB PMA */
-          USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-        }
-        else
-        {
-          /* Set the Double buffer counter for pmabuffer0 */
-          PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
-          pmabuffer = ep->pmaaddr0;
-
-          /* Write the user buffer to USB PMA */
-          USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-        }
-      }
-    }
-
-    PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
-  }
-  else /* OUT endpoint */
-  {
-    if (ep->doublebuffer == 0U)
-    {
-      /* Multi packet transfer */
-      if (ep->xfer_len > ep->maxpacket)
-      {
-        len = ep->maxpacket;
-        ep->xfer_len -= len;
-      }
-      else
-      {
-        len = ep->xfer_len;
-        ep->xfer_len = 0U;
-      }
-      /* configure and validate Rx endpoint */
-      PCD_SET_EP_RX_CNT(USBx, ep->num, len);
-    }
-    else
-    {
-      /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
-      /* Set the Double buffer counter */
-      if (ep->type == EP_TYPE_BULK)
-      {
-        PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
-
-        /* Coming from ISR */
-        if (ep->xfer_count != 0U)
-        {
-          /* update last value to check if there is blocking state */
-          wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
-
-          /*Blocking State */
-          if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
-              (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
-          {
-            PCD_FreeUserBuffer(USBx, ep->num, 0U);
-          }
-        }
-      }
-      /* iso out double */
-      else if (ep->type == EP_TYPE_ISOC)
-      {
-        /* Multi packet transfer */
-        if (ep->xfer_len > ep->maxpacket)
-        {
-          len = ep->maxpacket;
-          ep->xfer_len -= len;
-        }
-        else
-        {
-          len = ep->xfer_len;
-          ep->xfer_len = 0U;
-        }
-        PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
-      }
-      else
-      {
-        return HAL_ERROR;
-      }
-    }
-
-    PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
-  }
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_EPSetStall set a stall condition over an EP
-  * @param  USBx Selected device
-  * @param  ep pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
-  if (ep->is_in != 0U)
-  {
-    PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
-  }
-  else
-  {
-    PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EPClearStall Clear a stall condition over an EP
-  * @param  USBx Selected device
-  * @param  ep pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
-  if (ep->doublebuffer == 0U)
-  {
-    if (ep->is_in != 0U)
-    {
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
-      if (ep->type != EP_TYPE_ISOC)
-      {
-        /* Configure NAK status for the Endpoint */
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
-      }
-    }
-    else
-    {
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-
-      /* Configure VALID status for the Endpoint */
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
-    }
-  }
-
-  return HAL_OK;
-}
-#endif /* defined (HAL_PCD_MODULE_ENABLED) */
-
-/**
-  * @brief  USB_StopDevice Stop the usb device mode
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
-{
-  /* disable all interrupts and force USB reset */
-  USBx->CNTR = (uint16_t)USB_CNTR_FRES;
-
-  /* clear interrupt status register */
-  USBx->ISTR = 0U;
-
-  /* switch-off device */
-  USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_SetDevAddress Stop the usb device mode
-  * @param  USBx Selected device
-  * @param  address new device address to be assigned
-  *          This parameter can be a value from 0 to 255
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
-{
-  if (address == 0U)
-  {
-    /* set device address and enable function */
-    USBx->DADDR = (uint16_t)USB_DADDR_EF;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_DevConnect(USB_TypeDef *USBx)
-{
-  /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
-  USBx->BCDR |= (uint16_t)USB_BCDR_DPPU;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_DevDisconnect(USB_TypeDef *USBx)
-{
-  /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */
-  USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_ReadInterrupts return the global USB interrupt status
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-uint32_t  USB_ReadInterrupts(USB_TypeDef *USBx)
-{
-  uint32_t tmpreg;
-
-  tmpreg = USBx->ISTR;
-  return tmpreg;
-}
-
-/**
-  * @brief  USB_ActivateRemoteWakeup : active remote wakeup signalling
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
-{
-  USBx->CNTR |= (uint16_t)USB_CNTR_RESUME;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
-{
-  USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Copy a buffer from user memory area to packet memory area (PMA)
-  * @param   USBx USB peripheral instance register address.
-  * @param   pbUsrBuf pointer to user memory area.
-  * @param   wPMABufAddr address into PMA.
-  * @param   wNBytes no. of bytes to be copied.
-  * @retval None
-  */
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
-  uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
-  uint32_t BaseAddr = (uint32_t)USBx;
-  uint32_t i, temp1, temp2;
-  __IO uint16_t *pdwVal;
-  uint8_t *pBuf = pbUsrBuf;
-
-  pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
-
-  for (i = n; i != 0U; i--)
-  {
-    temp1 = *pBuf;
-    pBuf++;
-    temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8));
-    *pdwVal = (uint16_t)temp2;
-    pdwVal++;
-
-#if PMA_ACCESS > 1U
-    pdwVal++;
-#endif
-
-    pBuf++;
-  }
-}
-
-/**
-  * @brief Copy data from packet memory area (PMA) to user memory buffer
-  * @param   USBx USB peripheral instance register address.
-  * @param   pbUsrBuf pointer to user memory area.
-  * @param   wPMABufAddr address into PMA.
-  * @param   wNBytes no. of bytes to be copied.
-  * @retval None
-  */
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
-  uint32_t n = (uint32_t)wNBytes >> 1;
-  uint32_t BaseAddr = (uint32_t)USBx;
-  uint32_t i, temp;
-  __IO uint16_t *pdwVal;
-  uint8_t *pBuf = pbUsrBuf;
-
-  pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
-
-  for (i = n; i != 0U; i--)
-  {
-    temp = *(__IO uint16_t *)pdwVal;
-    pdwVal++;
-    *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
-    pBuf++;
-    *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
-    pBuf++;
-
-#if PMA_ACCESS > 1U
-    pdwVal++;
-#endif
-  }
-
-  if ((wNBytes % 2U) != 0U)
-  {
-    temp = *pdwVal;
-    *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
-  }
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined (USB) */
-#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
-
-/**
-  * @}
-  */
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c
deleted file mode 100644
index facb4c3a70..0000000000
--- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c
+++ /dev/null
@@ -1,591 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_ll_utils.c
-  * @author  MCD Application Team
-  * @brief   UTILS LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l0xx_ll_rcc.h"
-#include "stm32l0xx_ll_utils.h"
-#include "stm32l0xx_ll_system.h"
-#include "stm32l0xx_ll_pwr.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L0xx_LL_Driver
-  * @{
-  */
-
-/** @addtogroup UTILS_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Constants
-  * @{
-  */
-#define UTILS_MAX_FREQUENCY_SCALE1  (32000000U)        /*!< Maximum frequency for system clock at power scale1, in Hz */
-#define UTILS_MAX_FREQUENCY_SCALE2  (16000000U)        /*!< Maximum frequency for system clock at power scale2, in Hz */
-#define UTILS_MAX_FREQUENCY_SCALE3  (4194304U)         /*!< Maximum frequency for system clock at power scale3, in Hz */
-
-/* Defines used for PLL range */
-#define UTILS_PLLVCO_OUTPUT_SCALE1  (96000000U)        /*!< Frequency max for PLLVCO output at power scale1, in Hz  */
-#define UTILS_PLLVCO_OUTPUT_SCALE2  (48000000U)        /*!< Frequency max for PLLVCO output at power scale2, in Hz  */
-#define UTILS_PLLVCO_OUTPUT_SCALE3  (24000000U)        /*!< Frequency max for PLLVCO output at power scale3, in Hz  */
-
-/* Defines used for HSE range */
-#define UTILS_HSE_FREQUENCY_MIN     (1000000U)         /*!< Frequency min for HSE frequency, in Hz   */
-#define UTILS_HSE_FREQUENCY_MAX     (24000000U)        /*!< Frequency max for HSE frequency, in Hz   */
-
-/* Defines used for FLASH latency according to HCLK Frequency */
-#define UTILS_SCALE1_LATENCY1_FREQ  (16000000U)        /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
-#define UTILS_SCALE2_LATENCY1_FREQ  (8000000U)         /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
-#define UTILS_SCALE3_LATENCY1_FREQ  (2000000U)         /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
-
-#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
-                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
-                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
-                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
-                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))
-
-#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
-                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
-                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
-                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
-                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))
-
-#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_3) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_16) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_24) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_32) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_48))
-
-#define IS_LL_UTILS_PLLDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_DIV_2) || ((__VALUE__) == LL_RCC_PLL_DIV_3) || \
-                                             ((__VALUE__) == LL_RCC_PLL_DIV_4))
-
-#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE1) : \
-                                             ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE2) : \
-                                             ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE3)))
-
-#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
-                                             ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
-                                             ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)))
-
-#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
-                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
-
-#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
-/**
-  * @}
-  */
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
-  * @{
-  */
-static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
-                                               LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-static ErrorStatus UTILS_PLL_IsBusy(void);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup UTILS_LL_EF_DELAY
-  * @{
-  */
-
-/**
-  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
-  * @note   When a RTOS is used, it is recommended to avoid changing the Systick
-  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
-  * @param  HCLKFrequency HCLK frequency in Hz
-  * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
-  * @retval None
-  */
-void LL_Init1msTick(uint32_t HCLKFrequency)
-{
-  /* Use frequency provided in argument */
-  LL_InitTick(HCLKFrequency, 1000U);
-}
-
-/**
-  * @brief  This function provides accurate delay (in milliseconds) based
-  *         on SysTick counter flag
-  * @note   When a RTOS is used, it is recommended to avoid using blocking delay
-  *         and use rather osDelay service.
-  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
-  *         will configure Systick to 1ms
-  * @param  Delay specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-void LL_mDelay(uint32_t Delay)
-{
-  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
-  /* Add this code to indicate that local variable is not used */
-  ((void)tmp);
-
-  /* Add a period to guaranty minimum wait */
-  if (Delay < LL_MAX_DELAY)
-  {
-    Delay++;
-  }
-
-  while (Delay)
-  {
-    if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
-    {
-      Delay--;
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup UTILS_EF_SYSTEM
-  *  @brief    System Configuration functions
-  *
-  @verbatim
- ===============================================================================
-           ##### System Configuration functions #####
- ===============================================================================
-    [..]
-         System, AHB and APB buses clocks configuration
-
-         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32000000 Hz.
-  @endverbatim
-  @internal
-             Depending on the device voltage range, the maximum frequency should be
-             adapted accordingly:
-             (++) +----------------------------------------------------------------+
-             (++) |  Wait states  |                HCLK clock frequency (MHz)      |
-             (++) |               |------------------------------------------------|
-             (++) |   (Latency)   |            voltage range       | voltage range |
-             (++) |               |            1.65 V - 3.6 V      | 2.0 V - 3.6 V |
-             (++) |               |----------------|---------------|---------------|
-             (++) |               |  VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
-             (++) |-------------- |----------------|---------------|---------------|
-             (++) |0WS(1CPU cycle)|0 < HCLK <= 2   |0 < HCLK <= 8  |0 < HCLK <= 16 |
-             (++) |---------------|----------------|---------------|---------------|
-             (++) |1WS(2CPU cycle)|2 < HCLK <= 4   |8 < HCLK <= 16 |16 < HCLK <= 32|
-             (++) +----------------------------------------------------------------+
-  @endinternal
-  * @{
-  */
-
-/**
-  * @brief  This function sets directly SystemCoreClock CMSIS variable.
-  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
-  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
-  * @retval None
-  */
-void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
-{
-  /* HCLK clock frequency */
-  SystemCoreClock = HCLKFrequency;
-}
-
-/**
-  * @brief  Update number of Flash wait states in line with new frequency and current
-            voltage range.
-  * @param  Frequency  HCLK frequency
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: Latency has been modified
-  *          - ERROR: Latency cannot be modified
-  */
-ErrorStatus LL_SetFlashLatency(uint32_t Frequency)
-{
-  uint32_t timeout;
-  uint32_t getlatency;
-  uint32_t latency;
-  ErrorStatus status = SUCCESS;
-
-  /* Frequency cannot be equal to 0 */
-  if ((Frequency == 0U) || (Frequency > UTILS_MAX_FREQUENCY_SCALE1))
-  {
-    status = ERROR;
-  }
-  else
-  {
-    if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
-    {
-      if (Frequency > UTILS_SCALE1_LATENCY1_FREQ)
-      {
-        /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
-        latency = LL_FLASH_LATENCY_1;
-      }
-      else
-      {
-        /* else HCLK < 16MHz default LL_FLASH_LATENCY_0 0WS */
-        latency = LL_FLASH_LATENCY_0;
-      }
-    }
-    else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
-    {
-      if (Frequency > UTILS_SCALE2_LATENCY1_FREQ)
-      {
-        /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
-        latency = LL_FLASH_LATENCY_1;
-      }
-      else
-      {
-        /* else HCLK < 8MHz default LL_FLASH_LATENCY_0 0WS */
-        latency = LL_FLASH_LATENCY_0;
-      }
-    }
-    else
-    {
-      if (Frequency > UTILS_SCALE3_LATENCY1_FREQ)
-      {
-        /* 2 < HCLK <= 4 => 1WS (2 CPU cycles) */
-        latency = LL_FLASH_LATENCY_1;
-      }
-      else
-      {
-        /* else HCLK < 2MHz default LL_FLASH_LATENCY_0 0WS */
-        latency = LL_FLASH_LATENCY_0;
-      }
-    }
-
-    if (status != ERROR)
-    {
-      LL_FLASH_SetLatency(latency);
-
-      /* Check that the new number of wait states is taken into account to access the Flash
-           memory by reading the FLASH_ACR register */
-      timeout = 2;
-      do
-      {
-      /* Wait for Flash latency to be updated */
-      getlatency = LL_FLASH_GetLatency();
-      timeout--;
-      } while ((getlatency != latency) && (timeout > 0));
-
-      if(getlatency != latency)
-      {
-        status = ERROR;
-      }
-      else
-      {
-        status = SUCCESS;
-      }
-    }
-  }
-  return status;
-}
-
-/**
-  * @brief  This function configures system clock with HSI as clock source of the PLL
-  * @note   The application need to ensure that PLL is disabled.
-  * @note   Function is based on the following formula:
-  *         - PLL output frequency = ((HSI frequency * PLLMul) / PLLDiv)
-  *         - PLLMul: The application software must set correctly the PLL multiplication factor to ensure
-  *           - PLLVCO does not exceed 96 MHz when the product is in range 1,
-  *           - PLLVCO does not exceed 48 MHz when the product is in range 2,
-  *           - PLLVCO does not exceed 24 MHz when the product is in range 3
-  * @note   FLASH latency can be modified through this function. 
-  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
-  *                             the configuration information for the PLL.
-  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
-  *                             the configuration information for the BUS prescalers.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: Max frequency configuration done
-  *          - ERROR: Max frequency configuration not done
-  */
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
-                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  uint32_t pllfreq = 0U;
-
-  /* Check if one of the PLL is enabled */
-  if (UTILS_PLL_IsBusy() == SUCCESS)
-  {
-    /* Calculate the new PLL output frequency */
-    pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
-
-    /* Enable HSI if not enabled */
-    if (LL_RCC_HSI_IsReady() != 1U)
-    {
-      LL_RCC_HSI_Enable();
-      while (LL_RCC_HSI_IsReady() != 1U)
-      {
-        /* Wait for HSI ready */
-      }
-    }
-
-    /* Configure PLL */
-    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-
-    /* Enable PLL and switch system clock to PLL */
-    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
-  }
-  else
-  {
-    /* Current PLL configuration cannot be modified */
-    status = ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  This function configures system clock with HSE as clock source of the PLL
-  * @note   The application need to ensure that PLL is disabled.
-  * @note   Function is based on the following formula:
-  *         - PLL output frequency = ((HSE frequency * PLLMul) / PLLDiv)
-  *         - PLLMul: The application software must set correctly the PLL multiplication factor to to ensure
-  *           - PLLVCO does not exceed 96 MHz when the product is in range 1,
-  *           - PLLVCO does not exceed 48 MHz when the product is in range 2,
-  *           - PLLVCO does not exceed 24 MHz when the product is in range 3
-  * @note   FLASH latency can be modified through this function. 
-  * @param  HSEFrequency Value between Min_Data = 1000000 and Max_Data = 24000000
-  * @param  HSEBypass This parameter can be one of the following values:
-  *         @arg @ref LL_UTILS_HSEBYPASS_ON
-  *         @arg @ref LL_UTILS_HSEBYPASS_OFF
-  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
-  *                             the configuration information for the PLL.
-  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
-  *                             the configuration information for the BUS prescalers.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: Max frequency configuration done
-  *          - ERROR: Max frequency configuration not done
-  */
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
-                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  uint32_t pllfreq = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
-  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
-
-  /* Check if one of the PLL is enabled */
-  if (UTILS_PLL_IsBusy() == SUCCESS)
-  {
-    /* Calculate the new PLL output frequency */
-    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
-
-    /* Enable HSE if not enabled */
-    if (LL_RCC_HSE_IsReady() != 1U)
-    {
-      /* Check if need to enable HSE bypass feature or not */
-      if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
-      {
-        LL_RCC_HSE_EnableBypass();
-      }
-      else
-      {
-        LL_RCC_HSE_DisableBypass();
-      }
-
-      /* Enable HSE */
-      LL_RCC_HSE_Enable();
-      while (LL_RCC_HSE_IsReady() != 1U)
-      {
-        /* Wait for HSE ready */
-      }
-    }
-
-      /* Configure PLL */
-      LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-
-    /* Enable PLL and switch system clock to PLL */
-    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
-  }
-  else
-  {
-    /* Current PLL configuration cannot be modified */
-    status = ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup UTILS_LL_Private_Functions
-  * @{
-  */
-/**
-  * @brief  Function to check that PLL can be modified
-  * @param  PLL_InputFrequency  PLL input frequency (in Hz)
-  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
-  *                             the configuration information for the PLL.
-  * @retval PLL output frequency (in Hz)
-  */
-static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
-{
-  uint32_t pllfreq = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
-  assert_param(IS_LL_UTILS_PLLDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
-
-  /* Check different PLL parameters according to RM                          */
-  /* The application software must set correctly the PLL multiplication factor to avoid exceeding
-     96 MHz as PLLVCO when the product is in range 1,
-     48 MHz as PLLVCO when the product is in range 2,
-     24 MHz when the product is in range 3. */
-  pllfreq = PLL_InputFrequency * (PLLMulTable[UTILS_PLLInitStruct->PLLMul >> RCC_CFGR_PLLMUL_Pos]);
-  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
-
-  /* The application software must set correctly the PLL multiplication factor to avoid exceeding 
-     maximum frequency 32000000 in range 1 */
-  pllfreq = pllfreq / ((UTILS_PLLInitStruct->PLLDiv >> RCC_CFGR_PLLDIV_Pos)+1U);
-  assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
-
-  return pllfreq;
-}
-
-/**
-  * @brief  Function to check that PLL can be modified
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: PLL modification can be done
-  *          - ERROR: PLL is busy
-  */
-static ErrorStatus UTILS_PLL_IsBusy(void)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check if PLL is busy*/
-  if (LL_RCC_PLL_IsReady() != 0U)
-  {
-    /* PLL configuration cannot be modified */
-    status = ERROR;
-  }
-
-
-  return status;
-}
-
-/**
-  * @brief  Function to enable PLL and switch system clock to PLL
-  * @param  SYSCLK_Frequency SYSCLK frequency
-  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
-  *                             the configuration information for the BUS prescalers.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: No problem to switch system to PLL
-  *          - ERROR: Problem to switch system to PLL
-  */
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  uint32_t hclk_frequency = 0U;
-
-  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
-  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
-  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
-
-  /* Calculate HCLK frequency */
-  hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
-
-  /* Increasing the number of wait states because of higher CPU frequency */
-  if (SystemCoreClock < hclk_frequency)
-  {
-    /* Set FLASH latency to highest latency */
-    status = LL_SetFlashLatency(hclk_frequency);
-  }
-
-  /* Update system clock configuration */
-  if (status == SUCCESS)
-  {
-    /* Enable PLL */
-    LL_RCC_PLL_Enable();
-    while (LL_RCC_PLL_IsReady() != 1U)
-    {
-      /* Wait for PLL ready */
-    }
-
-    /* Sysclk activation on the main PLL */
-    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
-    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
-    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
-    {
-      /* Wait for system clock switch to PLL */
-    }
-
-    /* Set APB1 & APB2 prescaler*/
-    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
-    LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
-  }
-
-  /* Decreasing the number of wait states because of lower CPU frequency */
-  if (SystemCoreClock > hclk_frequency)
-  {
-    /* Set FLASH latency to lowest latency */
-    status = LL_SetFlashLatency(hclk_frequency);
-  }
-
-  /* Update SystemCoreClock variable */
-  if (status == SUCCESS)
-  {
-    LL_SetSystemCoreClock(hclk_frequency);
-  }
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32l010-st-nucleo/.config b/bsp/stm32/stm32l010-st-nucleo/.config
index 6ae2864ad1..7b8228b3a5 100644
--- a/bsp/stm32/stm32l010-st-nucleo/.config
+++ b/bsp/stm32/stm32l010-st-nucleo/.config
@@ -1,17 +1,119 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# RT-Thread Configuration
-#
 CONFIG_SOC_STM32L010RB=y
 CONFIG_BOARD_STM32L010_NUCLEO=y
 
 #
 # RT-Thread Kernel
 #
+
+#
+# klibc options
+#
+
+#
+# rt_vsnprintf options
+#
+# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set
+# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set
+# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set
+# end of rt_vsnprintf options
+
+#
+# rt_vsscanf options
+#
+# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set
+# end of rt_vsscanf options
+
+#
+# rt_memset options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set
+# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set
+# end of rt_memset options
+
+#
+# rt_memcpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set
+# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set
+# end of rt_memcpy options
+
+#
+# rt_memmove options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set
+# end of rt_memmove options
+
+#
+# rt_memcmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set
+# end of rt_memcmp options
+
+#
+# rt_strstr options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set
+# end of rt_strstr options
+
+#
+# rt_strcasecmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set
+# end of rt_strcasecmp options
+
+#
+# rt_strncpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set
+# end of rt_strncpy options
+
+#
+# rt_strcpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set
+# end of rt_strcpy options
+
+#
+# rt_strncmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set
+# end of rt_strncmp options
+
+#
+# rt_strcmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set
+# end of rt_strcmp options
+
+#
+# rt_strlen options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set
+# end of rt_strlen options
+
+#
+# rt_strnlen options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set
+# end of rt_strnlen options
+
+# CONFIG_RT_UTEST_TC_USING_KLIBC is not set
+# end of klibc options
+
 CONFIG_RT_NAME_MAX=8
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
-# CONFIG_RT_USING_SMART is not set
 # CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_SMART is not set
 # CONFIG_RT_USING_AMP is not set
 # CONFIG_RT_USING_SMP is not set
 CONFIG_RT_CPUS_NR=1
@@ -29,18 +131,20 @@ CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
 # CONFIG_RT_USING_TIMER_SOFT is not set
+# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
 
 #
-# kservice optimization
+# kservice options
 #
-# CONFIG_RT_KSERVICE_USING_STDLIB is not set
-# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
 # CONFIG_RT_USING_TINY_FFS is not set
-# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+# end of kservice options
+
 CONFIG_RT_USING_DEBUG=y
+CONFIG_RT_DEBUGING_ASSERT=y
 CONFIG_RT_DEBUGING_COLOR=y
 CONFIG_RT_DEBUGING_CONTEXT=y
 # CONFIG_RT_DEBUGING_AUTO_INIT is not set
+# CONFIG_RT_USING_CI_ACTION is not set
 
 #
 # Inter-Thread communication
@@ -52,6 +156,7 @@ CONFIG_RT_USING_MAILBOX=y
 CONFIG_RT_USING_MESSAGEQUEUE=y
 # CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
 # CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
 
 #
 # Memory Management
@@ -68,22 +173,20 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
 # CONFIG_RT_USING_MEMTRACE is not set
 # CONFIG_RT_USING_HEAP_ISR is not set
 CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
 CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 # CONFIG_RT_USING_THREADSAFE_PRINTF is not set
-# CONFIG_RT_USING_SCHED_THREAD_CTX is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=256
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
-CONFIG_RT_VER_NUM=0x50100
+CONFIG_RT_VER_NUM=0x50201
 # CONFIG_RT_USING_STDC_ATOMIC is not set
 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
-# CONFIG_RT_USING_CACHE is not set
-# CONFIG_RT_USING_HW_ATOMIC is not set
-# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
-# CONFIG_RT_USING_CPU_FFS is not set
+# end of RT-Thread Kernel
+
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_M0=y
@@ -117,12 +220,15 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
 # DFS: device virtual file system
 #
 # CONFIG_RT_USING_DFS is not set
+# end of DFS: device virtual file system
+
 # CONFIG_RT_USING_FAL is not set
 
 #
 # Device Drivers
 #
 # CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_DEV_BUS is not set
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_UNAMED_PIPE_NUMBER=64
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
@@ -131,16 +237,20 @@ CONFIG_RT_USING_SERIAL_V1=y
 # CONFIG_RT_USING_SERIAL_V2 is not set
 CONFIG_RT_SERIAL_USING_DMA=y
 CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_SERIAL_BYPASS is not set
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
 # CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PHY_V2 is not set
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_NULL is not set
 # CONFIG_RT_USING_ZERO is not set
 # CONFIG_RT_USING_RANDOM is not set
 # CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
@@ -153,21 +263,14 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_TOUCH is not set
 # CONFIG_RT_USING_LCD is not set
 # CONFIG_RT_USING_HWCRYPTO is not set
-# CONFIG_RT_USING_PULSE_ENCODER is not set
-# CONFIG_RT_USING_INPUT_CAPTURE is not set
-# CONFIG_RT_USING_DEV_BUS is not set
 # CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_BLK is not set
 # CONFIG_RT_USING_VIRTIO is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_KTIME is not set
 # CONFIG_RT_USING_HWTIMER is not set
-
-#
-# Using USB
-#
-# CONFIG_RT_USING_USB is not set
-# CONFIG_RT_USING_USB_HOST is not set
-# CONFIG_RT_USING_USB_DEVICE is not set
+# CONFIG_RT_USING_CHERRYUSB is not set
+# end of Device Drivers
 
 #
 # C/C++ and POSIX layer
@@ -185,6 +288,8 @@ CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
 CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
 CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
 CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+# end of Timezone and Daylight Saving Time
+# end of ISO-ANSI C layer
 
 #
 # POSIX (Portable Operating System Interface) layer
@@ -206,7 +311,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # Socket is in the 'Network' category
 #
+# end of Interprocess Communication (IPC)
+# end of POSIX (Portable Operating System Interface) layer
+
 # CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C/C++ and POSIX layer
 
 #
 # Network
@@ -215,12 +324,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_RT_USING_NETDEV is not set
 # CONFIG_RT_USING_LWIP is not set
 # CONFIG_RT_USING_AT is not set
+# end of Network
 
 #
 # Memory protection
 #
 # CONFIG_RT_USING_MEM_PROTECTION is not set
 # CONFIG_RT_USING_HW_STACK_GUARD is not set
+# end of Memory protection
 
 #
 # Utilities
@@ -232,12 +343,25 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_RT_USING_RESOURCE_ID is not set
 # CONFIG_RT_USING_ADT is not set
 # CONFIG_RT_USING_RT_LINK is not set
+# end of Utilities
+
 # CONFIG_RT_USING_VBUS is not set
 
+#
+# Using USB legacy version
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB legacy version
+
+# CONFIG_RT_USING_FDT is not set
+# end of RT-Thread Components
+
 #
 # RT-Thread Utestcases
 #
 # CONFIG_RT_USING_UTESTCASES is not set
+# end of RT-Thread Utestcases
 
 #
 # RT-Thread online packages
@@ -246,7 +370,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # IoT - internet of things
 #
-# CONFIG_PKG_USING_LWIP is not set
 # CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
 # CONFIG_PKG_USING_UMQTT is not set
@@ -259,6 +382,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_FREEMODBUS is not set
 # CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
 
 #
 # Wi-Fi
@@ -268,27 +392,35 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Marvell WiFi
 #
 # CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
 
 #
 # Wiced WiFi
 #
 # CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
 # CONFIG_PKG_USING_RW007 is not set
 
 #
 # CYW43012 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43012 is not set
+# end of CYW43012 WiFi
 
 #
 # BL808 WiFi
 #
 # CONFIG_PKG_USING_WLAN_BL808 is not set
+# end of BL808 WiFi
 
 #
 # CYW43439 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# end of CYW43439 WiFi
+# end of Wi-Fi
+
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@@ -311,6 +443,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# end of IoT Cloud
+
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
@@ -353,6 +487,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
 # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
 # CONFIG_PKG_USING_LHC_MODBUS is not set
+# CONFIG_PKG_USING_QMODBUS is not set
+# CONFIG_PKG_USING_PNET is not set
+# CONFIG_PKG_USING_OPENER is not set
+# end of IoT - internet of things
 
 #
 # security packages
@@ -363,6 +501,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_TINYCRYPT is not set
 # CONFIG_PKG_USING_TFM is not set
 # CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
 
 #
 # language packages
@@ -378,18 +517,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_JSMN is not set
 # CONFIG_PKG_USING_AGILE_JSMN is not set
 # CONFIG_PKG_USING_PARSON is not set
+# CONFIG_PKG_USING_RYAN_JSON is not set
+# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
 
 #
 # XML: Extensible Markup Language
 #
 # CONFIG_PKG_USING_SIMPLE_XML is not set
 # CONFIG_PKG_USING_EZXML is not set
+# end of XML: Extensible Markup Language
+
 # CONFIG_PKG_USING_LUATOS_SOC is not set
 # CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
 # CONFIG_PKG_USING_PIKASCRIPT is not set
 # CONFIG_PKG_USING_RTT_RUST is not set
+# end of language packages
 
 #
 # multimedia packages
@@ -401,12 +545,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_LVGL is not set
 # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
 # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+# end of LVGL: powerful and easy-to-use embedded GUI library
 
 #
 # u8g2: a monochrome graphic library
 #
 # CONFIG_PKG_USING_U8G2_OFFICIAL is not set
 # CONFIG_PKG_USING_U8G2 is not set
+# end of u8g2: a monochrome graphic library
+
 # CONFIG_PKG_USING_OPENMV is not set
 # CONFIG_PKG_USING_MUPDF is not set
 # CONFIG_PKG_USING_STEMWIN is not set
@@ -426,6 +573,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
 # CONFIG_PKG_USING_3GPP_AMRNB is not set
+# end of multimedia packages
 
 #
 # tools packages
@@ -475,6 +623,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_VOFA_PLUS is not set
 # CONFIG_PKG_USING_RT_TRACE is not set
 # CONFIG_PKG_USING_ZDEBUG is not set
+# CONFIG_PKG_USING_RVBACKTRACE is not set
+# CONFIG_PKG_USING_HPATCHLITE is not set
+# end of tools packages
 
 #
 # system packages
@@ -485,7 +636,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_RT_MEMCPY_CM is not set
 # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
-# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+# end of enhanced kernel services
+
+# CONFIG_PKG_USING_AUNITY is not set
 
 #
 # acceleration: Assembly language or algorithmic acceleration packages
@@ -493,16 +646,20 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
 # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
 # CONFIG_PKG_USING_QFPLIB_M3 is not set
+# end of acceleration: Assembly language or algorithmic acceleration packages
 
 #
 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 #
 # CONFIG_PKG_USING_CMSIS_5 is not set
-# CONFIG_PKG_USING_CMSIS_CORE is not set
-# CONFIG_PKG_USING_CMSIS_DSP is not set
+CONFIG_PKG_USING_CMSIS_CORE=y
+CONFIG_PKG_CMSIS_CORE_PATH="/packages/system/CMSIS/CMSIS-Core"
+CONFIG_PKG_USING_CMSIS_CORE_LATEST_VERSION=y
+CONFIG_PKG_CMSIS_CORE_VER="latest"
 # CONFIG_PKG_USING_CMSIS_NN is not set
 # CONFIG_PKG_USING_CMSIS_RTOS1 is not set
 # CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 
 #
 # Micrium: Micrium software products porting for RT-Thread
@@ -513,6 +670,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UC_CLK is not set
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
 # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
 # CONFIG_PKG_USING_LITEOS_SDK is not set
 # CONFIG_PKG_USING_TZ_DATABASE is not set
@@ -548,7 +707,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARM_2D is not set
 # CONFIG_PKG_USING_MCUBOOT is not set
 # CONFIG_PKG_USING_TINYUSB is not set
-# CONFIG_PKG_USING_CHERRYUSB is not set
 # CONFIG_PKG_USING_KMULTI_RTIMER is not set
 # CONFIG_PKG_USING_TFDB is not set
 # CONFIG_PKG_USING_QPC is not set
@@ -556,10 +714,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FLASH_BLOB is not set
 # CONFIG_PKG_USING_MLIBC is not set
 # CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_UART_FRAMEWORK is not set
 # CONFIG_PKG_USING_SFDB is not set
 # CONFIG_PKG_USING_RTP is not set
 # CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_RMP is not set
 # CONFIG_PKG_USING_R_RHEALSTONE is not set
+# CONFIG_PKG_USING_HEARTBEAT is not set
+# end of system packages
 
 #
 # peripheral libraries and drivers
@@ -572,9 +734,63 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # STM32 HAL & SDK Drivers
 #
-# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set
+CONFIG_PKG_USING_STM32L0_HAL_DRIVER=y
+CONFIG_PKG_STM32L0_HAL_DRIVER_PATH="/packages/peripherals/hal-sdk/stm32/stm32l0_hal_driver"
+CONFIG_PKG_USING_STM32L0_HAL_DRIVER_LATEST_VERSION=y
+CONFIG_PKG_STM32L0_HAL_DRIVER_VER="latest"
+CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER=y
+CONFIG_PKG_STM32L0_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/stm32/stm32l0_cmsis_driver"
+CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER_LATEST_VERSION=y
+CONFIG_PKG_STM32L0_CMSIS_DRIVER_VER="latest"
+# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set
 # CONFIG_PKG_USING_STM32WB55_SDK is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set
+# end of STM32 HAL & SDK Drivers
+
+#
+# Infineon HAL Packages
+#
+# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
+# CONFIG_PKG_USING_INFINEON_CMSIS is not set
+# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
+# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
+# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
+# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
+# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
+# CONFIG_PKG_USING_INFINEON_USBDEV is not set
+# end of Infineon HAL Packages
+
 # CONFIG_PKG_USING_BLUETRUM_SDK is not set
 # CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_ESP_IDF is not set
@@ -584,9 +800,49 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_K210_SDK is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# end of Kendryte SDK
+
 # CONFIG_PKG_USING_NRF5X_SDK is not set
 # CONFIG_PKG_USING_NRFX is not set
 # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_MM32 is not set
+
+#
+# WCH HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_CH32V20x_SDK is not set
+# CONFIG_PKG_USING_CH32V307_SDK is not set
+# end of WCH HAL & SDK Drivers
+
+#
+# AT32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set
+# end of AT32 HAL & SDK Drivers
+# end of HAL & SDK Drivers
 
 #
 # sensors drivers
@@ -623,14 +879,17 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_BMI088 is not set
 # CONFIG_PKG_USING_HMC5883 is not set
 # CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_MAX31855 is not set
 # CONFIG_PKG_USING_TMP1075 is not set
 # CONFIG_PKG_USING_SR04 is not set
 # CONFIG_PKG_USING_CCS811 is not set
 # CONFIG_PKG_USING_PMSXX is not set
 # CONFIG_PKG_USING_RT3020 is not set
 # CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90382 is not set
 # CONFIG_PKG_USING_MLX90393 is not set
 # CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90394 is not set
 # CONFIG_PKG_USING_MLX90397 is not set
 # CONFIG_PKG_USING_MS5611 is not set
 # CONFIG_PKG_USING_MAX31865 is not set
@@ -656,6 +915,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_PAJ7620 is not set
 # CONFIG_PKG_USING_STHS34PF80 is not set
+# CONFIG_PKG_USING_P3T1755 is not set
+# end of sensors drivers
 
 #
 # touch drivers
@@ -670,6 +931,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_XPT2046_TOUCH is not set
 # CONFIG_PKG_USING_CST816X is not set
 # CONFIG_PKG_USING_CST812T is not set
+# end of touch drivers
+
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
@@ -741,7 +1004,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
 # CONFIG_PKG_USING_BT_MX01 is not set
 # CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_BT_MX02 is not set
+# CONFIG_PKG_USING_GC9A01 is not set
+# CONFIG_PKG_USING_IK485 is not set
+# CONFIG_PKG_USING_SERVO is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
+# end of peripheral libraries and drivers
 
 #
 # AI packages
@@ -756,15 +1024,20 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
 # CONFIG_PKG_USING_R_TINYMAIX is not set
+# CONFIG_PKG_USING_LLMCHAT is not set
+# end of AI packages
 
 #
 # Signal Processing and Control Algorithm Packages
 #
+# CONFIG_PKG_USING_APID is not set
 # CONFIG_PKG_USING_FIRE_PID_CURVE is not set
 # CONFIG_PKG_USING_QPID is not set
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+# end of Signal Processing and Control Algorithm Packages
 
 #
 # miscellaneous packages
@@ -773,6 +1046,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # project laboratory
 #
+# end of project laboratory
 
 #
 # samples: kernel and components samples
@@ -781,6 +1055,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
 # CONFIG_PKG_USING_NETWORK_SAMPLES is not set
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
 
 #
 # entertainment: terminal games and other interesting software packages
@@ -797,6 +1072,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_COWSAY is not set
 # CONFIG_PKG_USING_MORSE is not set
 # CONFIG_PKG_USING_TINYSQUARE is not set
+# end of entertainment: terminal games and other interesting software packages
+
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
@@ -820,6 +1097,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
 # CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LIBCRC is not set
 # CONFIG_PKG_USING_LWGPS is not set
 # CONFIG_PKG_USING_STATE_MACHINE is not set
 # CONFIG_PKG_USING_DESIGN_PATTERN is not set
@@ -831,6 +1109,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QPARAM is not set
 # CONFIG_PKG_USING_CorevMCU_CLI is not set
 # CONFIG_PKG_USING_GET_IRQ_PRIORITY is not set
+# CONFIG_PKG_USING_DRMP is not set
+# end of miscellaneous packages
 
 #
 # Arduino libraries
@@ -843,9 +1123,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+# end of Projects and Demos
 
 #
 # Sensors
@@ -985,6 +1267,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
 # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
+# end of Sensors
 
 #
 # Display
@@ -996,6 +1280,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
 # CONFIG_PKG_USING_SEEED_TM1637 is not set
+# end of Display
 
 #
 # Timing
@@ -1004,6 +1289,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
 # CONFIG_PKG_USING_ARDUINO_TICKER is not set
 # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+# end of Timing
 
 #
 # Data Processing
@@ -1011,6 +1297,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
 # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
 # CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set
+# end of Data Processing
 
 #
 # Data Storage
@@ -1021,6 +1309,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+# end of Communication
 
 #
 # Device Control
@@ -1032,12 +1321,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# end of Device Control
 
 #
 # Other
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# end of Other
 
 #
 # Signal IO
@@ -1050,10 +1341,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+# end of Signal IO
 
 #
 # Uncategorized
 #
+# end of Arduino libraries
+# end of RT-Thread online packages
+
 CONFIG_SOC_FAMILY_STM32=y
 CONFIG_SOC_SERIES_STM32L0=y
 CONFIG_BOARD_SERIES_STM32_NUCLEO_64=y
@@ -1066,16 +1361,20 @@ CONFIG_BOARD_SERIES_STM32_NUCLEO_64=y
 # Onboard Peripheral Drivers
 #
 # CONFIG_BSP_USING_USB_TO_USART is not set
+# end of Onboard Peripheral Drivers
 
 #
 # On-chip Peripheral Drivers
 #
 CONFIG_BSP_USING_GPIO=y
 CONFIG_BSP_USING_UART=y
+CONFIG_BSP_STM32_UART_V1_TX_TIMEOUT=2000
 CONFIG_BSP_USING_UART2=y
 # CONFIG_BSP_UART2_RX_USING_DMA is not set
 # CONFIG_BSP_USING_UDID is not set
+# end of On-chip Peripheral Drivers
 
 #
 # Board extended module Drivers
 #
+# end of Hardware Drivers Config
diff --git a/bsp/stm32/stm32l010-st-nucleo/README_zh.md b/bsp/stm32/stm32l010-st-nucleo/README_zh.md
index c69bbe14fa..84bb870c82 100644
--- a/bsp/stm32/stm32l010-st-nucleo/README_zh.md
+++ b/bsp/stm32/stm32l010-st-nucleo/README_zh.md
@@ -71,6 +71,14 @@ NUCLEO-L010RB 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核
 
 本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
 
+**请注意！！！**
+
+在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的HAL库及CMSIS库，否则无法通过编译）：
+
+```bash
+pkgs --update
+```
+
 #### 硬件连接
 
 使用数据线连接开发板到 PC，打开电源开关。
diff --git a/bsp/stm32/stm32l010-st-nucleo/SConstruct b/bsp/stm32/stm32l010-st-nucleo/SConstruct
index d7ad786f03..7ec774fd90 100644
--- a/bsp/stm32/stm32l010-st-nucleo/SConstruct
+++ b/bsp/stm32/stm32l010-st-nucleo/SConstruct
@@ -42,19 +42,13 @@ if os.path.exists(SDK_ROOT + '/libraries'):
 else:
     libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
 
-SDK_LIB = libraries_path_prefix
-Export('SDK_LIB')
-
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
-stm32_library = 'STM32L0xx_HAL'
-rtconfig.BSP_LIBRARY_TYPE = stm32_library
+rtconfig.BSP_LIBRARY_TYPE = None
 
-# include libraries
-objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'), variant_dir='build/libraries/'+stm32_library, duplicate=0))
 # include drivers
-objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'),variant_dir='build/libraries/'+'HAL_Drivers', duplicate=0))
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'),variant_dir='build/libraries/HAL_Drivers', duplicate=0))
 
 # make a building
 DoBuilding(TARGET, objs)
diff --git a/bsp/stm32/stm32l010-st-nucleo/board/SConscript b/bsp/stm32/stm32l010-st-nucleo/board/SConscript
index 563c041422..1dfb4e3aa2 100644
--- a/bsp/stm32/stm32l010-st-nucleo/board/SConscript
+++ b/bsp/stm32/stm32l010-st-nucleo/board/SConscript
@@ -1,9 +1,6 @@
 import os
-import rtconfig
 from building import *
 
-Import('SDK_LIB')
-
 cwd = GetCurrentDir()
 
 # add general drivers
@@ -13,17 +10,16 @@ CubeMX_Config/Src/stm32l0xx_hal_msp.c
 ''')
 
 path =  [cwd]
-path += [cwd + '/CubeMX_Config/Inc']
+path += [os.path.join(cwd, 'CubeMX_Config', 'Inc')]
 
-startup_path_prefix = SDK_LIB
+CPPDEFINES = ['STM32L053xx']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
 
-if rtconfig.PLATFORM in ['gcc']:
-    src += [startup_path_prefix + '/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l053xx.s']
-elif rtconfig.PLATFORM in ['armcc', 'armclang']:
-    src += [startup_path_prefix + '/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l053xx.s']
-elif rtconfig.PLATFORM in ['iccarm']:
-    src += [startup_path_prefix + '/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l053xx.s']
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+# if os.path.isfile(os.path.join(cwd, "ports", 'SConscript')):
+#     group = group + SConscript(os.path.join("ports", 'SConscript'))
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
 
 Return('group')
diff --git a/bsp/stm32/stm32l010-st-nucleo/rtconfig.h b/bsp/stm32/stm32l010-st-nucleo/rtconfig.h
index 9ca5b3ddd7..ad74346987 100644
--- a/bsp/stm32/stm32l010-st-nucleo/rtconfig.h
+++ b/bsp/stm32/stm32l010-st-nucleo/rtconfig.h
@@ -1,14 +1,69 @@
 #ifndef RT_CONFIG_H__
 #define RT_CONFIG_H__
 
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Configuration */
-
 #define SOC_STM32L010RB
 #define BOARD_STM32L010_NUCLEO
 
 /* RT-Thread Kernel */
 
+/* klibc options */
+
+/* rt_vsnprintf options */
+
+/* end of rt_vsnprintf options */
+
+/* rt_vsscanf options */
+
+/* end of rt_vsscanf options */
+
+/* rt_memset options */
+
+/* end of rt_memset options */
+
+/* rt_memcpy options */
+
+/* end of rt_memcpy options */
+
+/* rt_memmove options */
+
+/* end of rt_memmove options */
+
+/* rt_memcmp options */
+
+/* end of rt_memcmp options */
+
+/* rt_strstr options */
+
+/* end of rt_strstr options */
+
+/* rt_strcasecmp options */
+
+/* end of rt_strcasecmp options */
+
+/* rt_strncpy options */
+
+/* end of rt_strncpy options */
+
+/* rt_strcpy options */
+
+/* end of rt_strcpy options */
+
+/* rt_strncmp options */
+
+/* end of rt_strncmp options */
+
+/* rt_strcmp options */
+
+/* end of rt_strcmp options */
+
+/* rt_strlen options */
+
+/* end of rt_strlen options */
+
+/* rt_strnlen options */
+
+/* end of rt_strnlen options */
+/* end of klibc options */
 #define RT_NAME_MAX 8
 #define RT_CPUS_NR 1
 #define RT_ALIGN_SIZE 8
@@ -22,9 +77,11 @@
 #define RT_IDLE_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 256
 
-/* kservice optimization */
+/* kservice options */
 
+/* end of kservice options */
 #define RT_USING_DEBUG
+#define RT_DEBUGING_ASSERT
 #define RT_DEBUGING_COLOR
 #define RT_DEBUGING_CONTEXT
 
@@ -35,6 +92,7 @@
 #define RT_USING_EVENT
 #define RT_USING_MAILBOX
 #define RT_USING_MESSAGEQUEUE
+/* end of Inter-Thread communication */
 
 /* Memory Management */
 
@@ -42,12 +100,14 @@
 #define RT_USING_SMALL_MEM
 #define RT_USING_SMALL_MEM_AS_HEAP
 #define RT_USING_HEAP
+/* end of Memory Management */
 #define RT_USING_DEVICE
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 256
 #define RT_CONSOLE_DEVICE_NAME "uart2"
-#define RT_VER_NUM 0x50100
+#define RT_VER_NUM 0x50201
 #define RT_BACKTRACE_LEVEL_MAX_NR 32
+/* end of RT-Thread Kernel */
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_M0
@@ -75,6 +135,7 @@
 
 /* DFS: device virtual file system */
 
+/* end of DFS: device virtual file system */
 
 /* Device Drivers */
 
@@ -85,9 +146,7 @@
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
-
-/* Using USB */
-
+/* end of Device Drivers */
 
 /* C/C++ and POSIX layer */
 
@@ -99,6 +158,8 @@
 #define RT_LIBC_TZ_DEFAULT_HOUR 8
 #define RT_LIBC_TZ_DEFAULT_MIN 0
 #define RT_LIBC_TZ_DEFAULT_SEC 0
+/* end of Timezone and Daylight Saving Time */
+/* end of ISO-ANSI C layer */
 
 /* POSIX (Portable Operating System Interface) layer */
 
@@ -108,18 +169,30 @@
 
 /* Socket is in the 'Network' category */
 
+/* end of Interprocess Communication (IPC) */
+/* end of POSIX (Portable Operating System Interface) layer */
+/* end of C/C++ and POSIX layer */
 
 /* Network */
 
+/* end of Network */
 
 /* Memory protection */
 
+/* end of Memory protection */
 
 /* Utilities */
 
+/* end of Utilities */
+
+/* Using USB legacy version */
+
+/* end of Using USB legacy version */
+/* end of RT-Thread Components */
 
 /* RT-Thread Utestcases */
 
+/* end of RT-Thread Utestcases */
 
 /* RT-Thread online packages */
 
@@ -130,57 +203,80 @@
 
 /* Marvell WiFi */
 
+/* end of Marvell WiFi */
 
 /* Wiced WiFi */
 
+/* end of Wiced WiFi */
 
 /* CYW43012 WiFi */
 
+/* end of CYW43012 WiFi */
 
 /* BL808 WiFi */
 
+/* end of BL808 WiFi */
 
 /* CYW43439 WiFi */
 
+/* end of CYW43439 WiFi */
+/* end of Wi-Fi */
 
 /* IoT Cloud */
 
+/* end of IoT Cloud */
+/* end of IoT - internet of things */
 
 /* security packages */
 
+/* end of security packages */
 
 /* language packages */
 
 /* JSON: JavaScript Object Notation, a lightweight data-interchange format */
 
+/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
 
 /* XML: Extensible Markup Language */
 
+/* end of XML: Extensible Markup Language */
+/* end of language packages */
 
 /* multimedia packages */
 
 /* LVGL: powerful and easy-to-use embedded GUI library */
 
+/* end of LVGL: powerful and easy-to-use embedded GUI library */
 
 /* u8g2: a monochrome graphic library */
 
+/* end of u8g2: a monochrome graphic library */
+/* end of multimedia packages */
 
 /* tools packages */
 
+/* end of tools packages */
 
 /* system packages */
 
 /* enhanced kernel services */
 
+/* end of enhanced kernel services */
 
 /* acceleration: Assembly language or algorithmic acceleration packages */
 
+/* end of acceleration: Assembly language or algorithmic acceleration packages */
 
 /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
 
+#define PKG_USING_CMSIS_CORE
+#define PKG_USING_CMSIS_CORE_LATEST_VERSION
+/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
 
 /* Micrium: Micrium software products porting for RT-Thread */
 
+/* end of Micrium: Micrium software products porting for RT-Thread */
+/* end of system packages */
 
 /* peripheral libraries and drivers */
 
@@ -188,66 +284,106 @@
 
 /* STM32 HAL & SDK Drivers */
 
+#define PKG_USING_STM32L0_HAL_DRIVER
+#define PKG_USING_STM32L0_HAL_DRIVER_LATEST_VERSION
+#define PKG_USING_STM32L0_CMSIS_DRIVER
+#define PKG_USING_STM32L0_CMSIS_DRIVER_LATEST_VERSION
+/* end of STM32 HAL & SDK Drivers */
+
+/* Infineon HAL Packages */
+
+/* end of Infineon HAL Packages */
 
 /* Kendryte SDK */
 
+/* end of Kendryte SDK */
+
+/* WCH HAL & SDK Drivers */
+
+/* end of WCH HAL & SDK Drivers */
+
+/* AT32 HAL & SDK Drivers */
+
+/* end of AT32 HAL & SDK Drivers */
+/* end of HAL & SDK Drivers */
 
 /* sensors drivers */
 
+/* end of sensors drivers */
 
 /* touch drivers */
 
+/* end of touch drivers */
+/* end of peripheral libraries and drivers */
 
 /* AI packages */
 
+/* end of AI packages */
 
 /* Signal Processing and Control Algorithm Packages */
 
+/* end of Signal Processing and Control Algorithm Packages */
 
 /* miscellaneous packages */
 
 /* project laboratory */
 
+/* end of project laboratory */
+
 /* samples: kernel and components samples */
 
+/* end of samples: kernel and components samples */
 
 /* entertainment: terminal games and other interesting software packages */
 
+/* end of entertainment: terminal games and other interesting software packages */
+/* end of miscellaneous packages */
 
 /* Arduino libraries */
 
 
 /* Projects and Demos */
 
+/* end of Projects and Demos */
 
 /* Sensors */
 
+/* end of Sensors */
 
 /* Display */
 
+/* end of Display */
 
 /* Timing */
 
+/* end of Timing */
 
 /* Data Processing */
 
+/* end of Data Processing */
 
 /* Data Storage */
 
 /* Communication */
 
+/* end of Communication */
 
 /* Device Control */
 
+/* end of Device Control */
 
 /* Other */
 
+/* end of Other */
 
 /* Signal IO */
 
+/* end of Signal IO */
 
 /* Uncategorized */
 
+/* end of Arduino libraries */
+/* end of RT-Thread online packages */
 #define SOC_FAMILY_STM32
 #define SOC_SERIES_STM32L0
 #define BOARD_SERIES_STM32_NUCLEO_64
@@ -256,14 +392,18 @@
 
 /* Onboard Peripheral Drivers */
 
+/* end of Onboard Peripheral Drivers */
 
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO
 #define BSP_USING_UART
+#define BSP_STM32_UART_V1_TX_TIMEOUT 2000
 #define BSP_USING_UART2
+/* end of On-chip Peripheral Drivers */
 
 /* Board extended module Drivers */
 
+/* end of Hardware Drivers Config */
 
 #endif
diff --git a/bsp/stm32/stm32l053-st-nucleo/.config b/bsp/stm32/stm32l053-st-nucleo/.config
index 216c46fcc4..69e028a48f 100644
--- a/bsp/stm32/stm32l053-st-nucleo/.config
+++ b/bsp/stm32/stm32l053-st-nucleo/.config
@@ -1,17 +1,119 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# RT-Thread Configuration
-#
 CONFIG_SOC_STM32L053R8=y
 CONFIG_BOARD_STM32L053_NUCLEO=y
 
 #
 # RT-Thread Kernel
 #
+
+#
+# klibc options
+#
+
+#
+# rt_vsnprintf options
+#
+# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set
+# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set
+# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set
+# end of rt_vsnprintf options
+
+#
+# rt_vsscanf options
+#
+# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set
+# end of rt_vsscanf options
+
+#
+# rt_memset options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set
+# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set
+# end of rt_memset options
+
+#
+# rt_memcpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set
+# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set
+# end of rt_memcpy options
+
+#
+# rt_memmove options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set
+# end of rt_memmove options
+
+#
+# rt_memcmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set
+# end of rt_memcmp options
+
+#
+# rt_strstr options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set
+# end of rt_strstr options
+
+#
+# rt_strcasecmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set
+# end of rt_strcasecmp options
+
+#
+# rt_strncpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set
+# end of rt_strncpy options
+
+#
+# rt_strcpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set
+# end of rt_strcpy options
+
+#
+# rt_strncmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set
+# end of rt_strncmp options
+
+#
+# rt_strcmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set
+# end of rt_strcmp options
+
+#
+# rt_strlen options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set
+# end of rt_strlen options
+
+#
+# rt_strnlen options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set
+# end of rt_strnlen options
+
+# CONFIG_RT_UTEST_TC_USING_KLIBC is not set
+# end of klibc options
+
 CONFIG_RT_NAME_MAX=8
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
-# CONFIG_RT_USING_SMART is not set
 # CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_SMART is not set
 # CONFIG_RT_USING_AMP is not set
 # CONFIG_RT_USING_SMP is not set
 CONFIG_RT_CPUS_NR=1
@@ -29,18 +131,20 @@ CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
 # CONFIG_RT_USING_TIMER_SOFT is not set
+# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
 
 #
-# kservice optimization
+# kservice options
 #
-# CONFIG_RT_KSERVICE_USING_STDLIB is not set
-# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
 # CONFIG_RT_USING_TINY_FFS is not set
-# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+# end of kservice options
+
 CONFIG_RT_USING_DEBUG=y
+CONFIG_RT_DEBUGING_ASSERT=y
 CONFIG_RT_DEBUGING_COLOR=y
 CONFIG_RT_DEBUGING_CONTEXT=y
 # CONFIG_RT_DEBUGING_AUTO_INIT is not set
+# CONFIG_RT_USING_CI_ACTION is not set
 
 #
 # Inter-Thread communication
@@ -52,6 +156,7 @@ CONFIG_RT_USING_MAILBOX=y
 CONFIG_RT_USING_MESSAGEQUEUE=y
 # CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
 # CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
 
 #
 # Memory Management
@@ -68,22 +173,20 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
 # CONFIG_RT_USING_MEMTRACE is not set
 # CONFIG_RT_USING_HEAP_ISR is not set
 CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
 CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 # CONFIG_RT_USING_THREADSAFE_PRINTF is not set
-# CONFIG_RT_USING_SCHED_THREAD_CTX is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=256
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
-CONFIG_RT_VER_NUM=0x50100
+CONFIG_RT_VER_NUM=0x50201
 # CONFIG_RT_USING_STDC_ATOMIC is not set
 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
-# CONFIG_RT_USING_CACHE is not set
-# CONFIG_RT_USING_HW_ATOMIC is not set
-# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
-# CONFIG_RT_USING_CPU_FFS is not set
+# end of RT-Thread Kernel
+
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_M0=y
@@ -117,12 +220,15 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
 # DFS: device virtual file system
 #
 # CONFIG_RT_USING_DFS is not set
+# end of DFS: device virtual file system
+
 # CONFIG_RT_USING_FAL is not set
 
 #
 # Device Drivers
 #
 # CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_DEV_BUS is not set
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_UNAMED_PIPE_NUMBER=64
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
@@ -131,16 +237,20 @@ CONFIG_RT_USING_SERIAL_V1=y
 # CONFIG_RT_USING_SERIAL_V2 is not set
 CONFIG_RT_SERIAL_USING_DMA=y
 CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_SERIAL_BYPASS is not set
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
 # CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PHY_V2 is not set
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_NULL is not set
 # CONFIG_RT_USING_ZERO is not set
 # CONFIG_RT_USING_RANDOM is not set
 # CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
@@ -153,21 +263,14 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_TOUCH is not set
 # CONFIG_RT_USING_LCD is not set
 # CONFIG_RT_USING_HWCRYPTO is not set
-# CONFIG_RT_USING_PULSE_ENCODER is not set
-# CONFIG_RT_USING_INPUT_CAPTURE is not set
-# CONFIG_RT_USING_DEV_BUS is not set
 # CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_BLK is not set
 # CONFIG_RT_USING_VIRTIO is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_KTIME is not set
 # CONFIG_RT_USING_HWTIMER is not set
-
-#
-# Using USB
-#
-# CONFIG_RT_USING_USB is not set
-# CONFIG_RT_USING_USB_HOST is not set
-# CONFIG_RT_USING_USB_DEVICE is not set
+# CONFIG_RT_USING_CHERRYUSB is not set
+# end of Device Drivers
 
 #
 # C/C++ and POSIX layer
@@ -185,6 +288,8 @@ CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
 CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
 CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
 CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+# end of Timezone and Daylight Saving Time
+# end of ISO-ANSI C layer
 
 #
 # POSIX (Portable Operating System Interface) layer
@@ -206,7 +311,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # Socket is in the 'Network' category
 #
+# end of Interprocess Communication (IPC)
+# end of POSIX (Portable Operating System Interface) layer
+
 # CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C/C++ and POSIX layer
 
 #
 # Network
@@ -215,12 +324,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_RT_USING_NETDEV is not set
 # CONFIG_RT_USING_LWIP is not set
 # CONFIG_RT_USING_AT is not set
+# end of Network
 
 #
 # Memory protection
 #
 # CONFIG_RT_USING_MEM_PROTECTION is not set
 # CONFIG_RT_USING_HW_STACK_GUARD is not set
+# end of Memory protection
 
 #
 # Utilities
@@ -232,12 +343,25 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_RT_USING_RESOURCE_ID is not set
 # CONFIG_RT_USING_ADT is not set
 # CONFIG_RT_USING_RT_LINK is not set
+# end of Utilities
+
 # CONFIG_RT_USING_VBUS is not set
 
+#
+# Using USB legacy version
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB legacy version
+
+# CONFIG_RT_USING_FDT is not set
+# end of RT-Thread Components
+
 #
 # RT-Thread Utestcases
 #
 # CONFIG_RT_USING_UTESTCASES is not set
+# end of RT-Thread Utestcases
 
 #
 # RT-Thread online packages
@@ -246,7 +370,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # IoT - internet of things
 #
-# CONFIG_PKG_USING_LWIP is not set
 # CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
 # CONFIG_PKG_USING_UMQTT is not set
@@ -259,6 +382,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_FREEMODBUS is not set
 # CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
 
 #
 # Wi-Fi
@@ -268,27 +392,35 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Marvell WiFi
 #
 # CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
 
 #
 # Wiced WiFi
 #
 # CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
 # CONFIG_PKG_USING_RW007 is not set
 
 #
 # CYW43012 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43012 is not set
+# end of CYW43012 WiFi
 
 #
 # BL808 WiFi
 #
 # CONFIG_PKG_USING_WLAN_BL808 is not set
+# end of BL808 WiFi
 
 #
 # CYW43439 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# end of CYW43439 WiFi
+# end of Wi-Fi
+
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@@ -311,6 +443,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# end of IoT Cloud
+
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
@@ -353,6 +487,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
 # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
 # CONFIG_PKG_USING_LHC_MODBUS is not set
+# CONFIG_PKG_USING_QMODBUS is not set
+# CONFIG_PKG_USING_PNET is not set
+# CONFIG_PKG_USING_OPENER is not set
+# end of IoT - internet of things
 
 #
 # security packages
@@ -363,6 +501,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_TINYCRYPT is not set
 # CONFIG_PKG_USING_TFM is not set
 # CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
 
 #
 # language packages
@@ -378,18 +517,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_JSMN is not set
 # CONFIG_PKG_USING_AGILE_JSMN is not set
 # CONFIG_PKG_USING_PARSON is not set
+# CONFIG_PKG_USING_RYAN_JSON is not set
+# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
 
 #
 # XML: Extensible Markup Language
 #
 # CONFIG_PKG_USING_SIMPLE_XML is not set
 # CONFIG_PKG_USING_EZXML is not set
+# end of XML: Extensible Markup Language
+
 # CONFIG_PKG_USING_LUATOS_SOC is not set
 # CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
 # CONFIG_PKG_USING_PIKASCRIPT is not set
 # CONFIG_PKG_USING_RTT_RUST is not set
+# end of language packages
 
 #
 # multimedia packages
@@ -401,12 +545,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_LVGL is not set
 # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
 # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+# end of LVGL: powerful and easy-to-use embedded GUI library
 
 #
 # u8g2: a monochrome graphic library
 #
 # CONFIG_PKG_USING_U8G2_OFFICIAL is not set
 # CONFIG_PKG_USING_U8G2 is not set
+# end of u8g2: a monochrome graphic library
+
 # CONFIG_PKG_USING_OPENMV is not set
 # CONFIG_PKG_USING_MUPDF is not set
 # CONFIG_PKG_USING_STEMWIN is not set
@@ -426,6 +573,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
 # CONFIG_PKG_USING_3GPP_AMRNB is not set
+# end of multimedia packages
 
 #
 # tools packages
@@ -475,6 +623,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_VOFA_PLUS is not set
 # CONFIG_PKG_USING_RT_TRACE is not set
 # CONFIG_PKG_USING_ZDEBUG is not set
+# CONFIG_PKG_USING_RVBACKTRACE is not set
+# CONFIG_PKG_USING_HPATCHLITE is not set
+# end of tools packages
 
 #
 # system packages
@@ -485,7 +636,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_RT_MEMCPY_CM is not set
 # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
-# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+# end of enhanced kernel services
+
+# CONFIG_PKG_USING_AUNITY is not set
 
 #
 # acceleration: Assembly language or algorithmic acceleration packages
@@ -493,16 +646,20 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
 # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
 # CONFIG_PKG_USING_QFPLIB_M3 is not set
+# end of acceleration: Assembly language or algorithmic acceleration packages
 
 #
 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 #
 # CONFIG_PKG_USING_CMSIS_5 is not set
-# CONFIG_PKG_USING_CMSIS_CORE is not set
-# CONFIG_PKG_USING_CMSIS_DSP is not set
+CONFIG_PKG_USING_CMSIS_CORE=y
+CONFIG_PKG_CMSIS_CORE_PATH="/packages/system/CMSIS/CMSIS-Core"
+CONFIG_PKG_USING_CMSIS_CORE_LATEST_VERSION=y
+CONFIG_PKG_CMSIS_CORE_VER="latest"
 # CONFIG_PKG_USING_CMSIS_NN is not set
 # CONFIG_PKG_USING_CMSIS_RTOS1 is not set
 # CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 
 #
 # Micrium: Micrium software products porting for RT-Thread
@@ -513,6 +670,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UC_CLK is not set
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
 # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
 # CONFIG_PKG_USING_LITEOS_SDK is not set
 # CONFIG_PKG_USING_TZ_DATABASE is not set
@@ -548,7 +707,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARM_2D is not set
 # CONFIG_PKG_USING_MCUBOOT is not set
 # CONFIG_PKG_USING_TINYUSB is not set
-# CONFIG_PKG_USING_CHERRYUSB is not set
 # CONFIG_PKG_USING_KMULTI_RTIMER is not set
 # CONFIG_PKG_USING_TFDB is not set
 # CONFIG_PKG_USING_QPC is not set
@@ -556,10 +714,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FLASH_BLOB is not set
 # CONFIG_PKG_USING_MLIBC is not set
 # CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_UART_FRAMEWORK is not set
 # CONFIG_PKG_USING_SFDB is not set
 # CONFIG_PKG_USING_RTP is not set
 # CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_RMP is not set
 # CONFIG_PKG_USING_R_RHEALSTONE is not set
+# CONFIG_PKG_USING_HEARTBEAT is not set
+# end of system packages
 
 #
 # peripheral libraries and drivers
@@ -572,9 +734,63 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # STM32 HAL & SDK Drivers
 #
-# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set
+CONFIG_PKG_USING_STM32L0_HAL_DRIVER=y
+CONFIG_PKG_STM32L0_HAL_DRIVER_PATH="/packages/peripherals/hal-sdk/stm32/stm32l0_hal_driver"
+CONFIG_PKG_USING_STM32L0_HAL_DRIVER_LATEST_VERSION=y
+CONFIG_PKG_STM32L0_HAL_DRIVER_VER="latest"
+CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER=y
+CONFIG_PKG_STM32L0_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/stm32/stm32l0_cmsis_driver"
+CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER_LATEST_VERSION=y
+CONFIG_PKG_STM32L0_CMSIS_DRIVER_VER="latest"
+# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set
 # CONFIG_PKG_USING_STM32WB55_SDK is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set
+# end of STM32 HAL & SDK Drivers
+
+#
+# Infineon HAL Packages
+#
+# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
+# CONFIG_PKG_USING_INFINEON_CMSIS is not set
+# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
+# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
+# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
+# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
+# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
+# CONFIG_PKG_USING_INFINEON_USBDEV is not set
+# end of Infineon HAL Packages
+
 # CONFIG_PKG_USING_BLUETRUM_SDK is not set
 # CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_ESP_IDF is not set
@@ -584,9 +800,49 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_K210_SDK is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# end of Kendryte SDK
+
 # CONFIG_PKG_USING_NRF5X_SDK is not set
 # CONFIG_PKG_USING_NRFX is not set
 # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_MM32 is not set
+
+#
+# WCH HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_CH32V20x_SDK is not set
+# CONFIG_PKG_USING_CH32V307_SDK is not set
+# end of WCH HAL & SDK Drivers
+
+#
+# AT32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set
+# end of AT32 HAL & SDK Drivers
+# end of HAL & SDK Drivers
 
 #
 # sensors drivers
@@ -623,14 +879,17 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_BMI088 is not set
 # CONFIG_PKG_USING_HMC5883 is not set
 # CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_MAX31855 is not set
 # CONFIG_PKG_USING_TMP1075 is not set
 # CONFIG_PKG_USING_SR04 is not set
 # CONFIG_PKG_USING_CCS811 is not set
 # CONFIG_PKG_USING_PMSXX is not set
 # CONFIG_PKG_USING_RT3020 is not set
 # CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90382 is not set
 # CONFIG_PKG_USING_MLX90393 is not set
 # CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90394 is not set
 # CONFIG_PKG_USING_MLX90397 is not set
 # CONFIG_PKG_USING_MS5611 is not set
 # CONFIG_PKG_USING_MAX31865 is not set
@@ -656,6 +915,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_PAJ7620 is not set
 # CONFIG_PKG_USING_STHS34PF80 is not set
+# CONFIG_PKG_USING_P3T1755 is not set
+# end of sensors drivers
 
 #
 # touch drivers
@@ -670,6 +931,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_XPT2046_TOUCH is not set
 # CONFIG_PKG_USING_CST816X is not set
 # CONFIG_PKG_USING_CST812T is not set
+# end of touch drivers
+
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
@@ -741,7 +1004,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
 # CONFIG_PKG_USING_BT_MX01 is not set
 # CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_BT_MX02 is not set
+# CONFIG_PKG_USING_GC9A01 is not set
+# CONFIG_PKG_USING_IK485 is not set
+# CONFIG_PKG_USING_SERVO is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
+# end of peripheral libraries and drivers
 
 #
 # AI packages
@@ -756,15 +1024,20 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
 # CONFIG_PKG_USING_R_TINYMAIX is not set
+# CONFIG_PKG_USING_LLMCHAT is not set
+# end of AI packages
 
 #
 # Signal Processing and Control Algorithm Packages
 #
+# CONFIG_PKG_USING_APID is not set
 # CONFIG_PKG_USING_FIRE_PID_CURVE is not set
 # CONFIG_PKG_USING_QPID is not set
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+# end of Signal Processing and Control Algorithm Packages
 
 #
 # miscellaneous packages
@@ -773,6 +1046,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # project laboratory
 #
+# end of project laboratory
 
 #
 # samples: kernel and components samples
@@ -781,6 +1055,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
 # CONFIG_PKG_USING_NETWORK_SAMPLES is not set
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
 
 #
 # entertainment: terminal games and other interesting software packages
@@ -797,6 +1072,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_COWSAY is not set
 # CONFIG_PKG_USING_MORSE is not set
 # CONFIG_PKG_USING_TINYSQUARE is not set
+# end of entertainment: terminal games and other interesting software packages
+
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
@@ -820,6 +1097,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
 # CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LIBCRC is not set
 # CONFIG_PKG_USING_LWGPS is not set
 # CONFIG_PKG_USING_STATE_MACHINE is not set
 # CONFIG_PKG_USING_DESIGN_PATTERN is not set
@@ -831,6 +1109,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QPARAM is not set
 # CONFIG_PKG_USING_CorevMCU_CLI is not set
 # CONFIG_PKG_USING_GET_IRQ_PRIORITY is not set
+# CONFIG_PKG_USING_DRMP is not set
+# end of miscellaneous packages
 
 #
 # Arduino libraries
@@ -843,9 +1123,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+# end of Projects and Demos
 
 #
 # Sensors
@@ -985,6 +1267,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
 # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
+# end of Sensors
 
 #
 # Display
@@ -996,6 +1280,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
 # CONFIG_PKG_USING_SEEED_TM1637 is not set
+# end of Display
 
 #
 # Timing
@@ -1004,6 +1289,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
 # CONFIG_PKG_USING_ARDUINO_TICKER is not set
 # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+# end of Timing
 
 #
 # Data Processing
@@ -1011,6 +1297,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
 # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
 # CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set
+# end of Data Processing
 
 #
 # Data Storage
@@ -1021,6 +1309,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+# end of Communication
 
 #
 # Device Control
@@ -1032,12 +1321,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# end of Device Control
 
 #
 # Other
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# end of Other
 
 #
 # Signal IO
@@ -1050,10 +1341,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+# end of Signal IO
 
 #
 # Uncategorized
 #
+# end of Arduino libraries
+# end of RT-Thread online packages
+
 CONFIG_SOC_FAMILY_STM32=y
 CONFIG_SOC_SERIES_STM32L0=y
 CONFIG_BOARD_SERIES_STM32_NUCLEO_64=y
@@ -1066,16 +1361,20 @@ CONFIG_BOARD_SERIES_STM32_NUCLEO_64=y
 # Onboard Peripheral Drivers
 #
 CONFIG_BSP_USING_USB_TO_USART=y
+# end of Onboard Peripheral Drivers
 
 #
 # On-chip Peripheral Drivers
 #
 CONFIG_BSP_USING_GPIO=y
 CONFIG_BSP_USING_UART=y
+CONFIG_BSP_STM32_UART_V1_TX_TIMEOUT=2000
 CONFIG_BSP_USING_UART2=y
 # CONFIG_BSP_UART2_RX_USING_DMA is not set
 # CONFIG_BSP_USING_UDID is not set
+# end of On-chip Peripheral Drivers
 
 #
 # Board extended module Drivers
 #
+# end of Hardware Drivers Config
diff --git a/bsp/stm32/stm32l053-st-nucleo/README_zh.md b/bsp/stm32/stm32l053-st-nucleo/README_zh.md
index 35799d2715..63c92c3dff 100644
--- a/bsp/stm32/stm32l053-st-nucleo/README_zh.md
+++ b/bsp/stm32/stm32l053-st-nucleo/README_zh.md
@@ -66,6 +66,14 @@ NUCLEO-L053R8 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核
 
 本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
 
+**请注意！！！**
+
+在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的HAL库及CMSIS库，否则无法通过编译）：
+
+```bash
+pkgs --update
+```
+
 #### 硬件连接
 
 使用数据线连接开发板到 PC，打开电源开关。
diff --git a/bsp/stm32/stm32l053-st-nucleo/SConstruct b/bsp/stm32/stm32l053-st-nucleo/SConstruct
index d7ad786f03..7ec774fd90 100644
--- a/bsp/stm32/stm32l053-st-nucleo/SConstruct
+++ b/bsp/stm32/stm32l053-st-nucleo/SConstruct
@@ -42,19 +42,13 @@ if os.path.exists(SDK_ROOT + '/libraries'):
 else:
     libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
 
-SDK_LIB = libraries_path_prefix
-Export('SDK_LIB')
-
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
-stm32_library = 'STM32L0xx_HAL'
-rtconfig.BSP_LIBRARY_TYPE = stm32_library
+rtconfig.BSP_LIBRARY_TYPE = None
 
-# include libraries
-objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'), variant_dir='build/libraries/'+stm32_library, duplicate=0))
 # include drivers
-objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'),variant_dir='build/libraries/'+'HAL_Drivers', duplicate=0))
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'),variant_dir='build/libraries/HAL_Drivers', duplicate=0))
 
 # make a building
 DoBuilding(TARGET, objs)
diff --git a/bsp/stm32/stm32l053-st-nucleo/board/SConscript b/bsp/stm32/stm32l053-st-nucleo/board/SConscript
index 563c041422..1dfb4e3aa2 100644
--- a/bsp/stm32/stm32l053-st-nucleo/board/SConscript
+++ b/bsp/stm32/stm32l053-st-nucleo/board/SConscript
@@ -1,9 +1,6 @@
 import os
-import rtconfig
 from building import *
 
-Import('SDK_LIB')
-
 cwd = GetCurrentDir()
 
 # add general drivers
@@ -13,17 +10,16 @@ CubeMX_Config/Src/stm32l0xx_hal_msp.c
 ''')
 
 path =  [cwd]
-path += [cwd + '/CubeMX_Config/Inc']
+path += [os.path.join(cwd, 'CubeMX_Config', 'Inc')]
 
-startup_path_prefix = SDK_LIB
+CPPDEFINES = ['STM32L053xx']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
 
-if rtconfig.PLATFORM in ['gcc']:
-    src += [startup_path_prefix + '/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l053xx.s']
-elif rtconfig.PLATFORM in ['armcc', 'armclang']:
-    src += [startup_path_prefix + '/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l053xx.s']
-elif rtconfig.PLATFORM in ['iccarm']:
-    src += [startup_path_prefix + '/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l053xx.s']
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+# if os.path.isfile(os.path.join(cwd, "ports", 'SConscript')):
+#     group = group + SConscript(os.path.join("ports", 'SConscript'))
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
 
 Return('group')
diff --git a/bsp/stm32/stm32l053-st-nucleo/rtconfig.h b/bsp/stm32/stm32l053-st-nucleo/rtconfig.h
index 416b9b312d..89fd7d3962 100644
--- a/bsp/stm32/stm32l053-st-nucleo/rtconfig.h
+++ b/bsp/stm32/stm32l053-st-nucleo/rtconfig.h
@@ -1,14 +1,69 @@
 #ifndef RT_CONFIG_H__
 #define RT_CONFIG_H__
 
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Configuration */
-
 #define SOC_STM32L053R8
 #define BOARD_STM32L053_NUCLEO
 
 /* RT-Thread Kernel */
 
+/* klibc options */
+
+/* rt_vsnprintf options */
+
+/* end of rt_vsnprintf options */
+
+/* rt_vsscanf options */
+
+/* end of rt_vsscanf options */
+
+/* rt_memset options */
+
+/* end of rt_memset options */
+
+/* rt_memcpy options */
+
+/* end of rt_memcpy options */
+
+/* rt_memmove options */
+
+/* end of rt_memmove options */
+
+/* rt_memcmp options */
+
+/* end of rt_memcmp options */
+
+/* rt_strstr options */
+
+/* end of rt_strstr options */
+
+/* rt_strcasecmp options */
+
+/* end of rt_strcasecmp options */
+
+/* rt_strncpy options */
+
+/* end of rt_strncpy options */
+
+/* rt_strcpy options */
+
+/* end of rt_strcpy options */
+
+/* rt_strncmp options */
+
+/* end of rt_strncmp options */
+
+/* rt_strcmp options */
+
+/* end of rt_strcmp options */
+
+/* rt_strlen options */
+
+/* end of rt_strlen options */
+
+/* rt_strnlen options */
+
+/* end of rt_strnlen options */
+/* end of klibc options */
 #define RT_NAME_MAX 8
 #define RT_CPUS_NR 1
 #define RT_ALIGN_SIZE 8
@@ -22,9 +77,11 @@
 #define RT_IDLE_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 256
 
-/* kservice optimization */
+/* kservice options */
 
+/* end of kservice options */
 #define RT_USING_DEBUG
+#define RT_DEBUGING_ASSERT
 #define RT_DEBUGING_COLOR
 #define RT_DEBUGING_CONTEXT
 
@@ -35,6 +92,7 @@
 #define RT_USING_EVENT
 #define RT_USING_MAILBOX
 #define RT_USING_MESSAGEQUEUE
+/* end of Inter-Thread communication */
 
 /* Memory Management */
 
@@ -42,12 +100,14 @@
 #define RT_USING_SMALL_MEM
 #define RT_USING_SMALL_MEM_AS_HEAP
 #define RT_USING_HEAP
+/* end of Memory Management */
 #define RT_USING_DEVICE
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 256
 #define RT_CONSOLE_DEVICE_NAME "uart2"
-#define RT_VER_NUM 0x50100
+#define RT_VER_NUM 0x50201
 #define RT_BACKTRACE_LEVEL_MAX_NR 32
+/* end of RT-Thread Kernel */
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_M0
@@ -75,6 +135,7 @@
 
 /* DFS: device virtual file system */
 
+/* end of DFS: device virtual file system */
 
 /* Device Drivers */
 
@@ -85,9 +146,7 @@
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
-
-/* Using USB */
-
+/* end of Device Drivers */
 
 /* C/C++ and POSIX layer */
 
@@ -99,6 +158,8 @@
 #define RT_LIBC_TZ_DEFAULT_HOUR 8
 #define RT_LIBC_TZ_DEFAULT_MIN 0
 #define RT_LIBC_TZ_DEFAULT_SEC 0
+/* end of Timezone and Daylight Saving Time */
+/* end of ISO-ANSI C layer */
 
 /* POSIX (Portable Operating System Interface) layer */
 
@@ -108,18 +169,30 @@
 
 /* Socket is in the 'Network' category */
 
+/* end of Interprocess Communication (IPC) */
+/* end of POSIX (Portable Operating System Interface) layer */
+/* end of C/C++ and POSIX layer */
 
 /* Network */
 
+/* end of Network */
 
 /* Memory protection */
 
+/* end of Memory protection */
 
 /* Utilities */
 
+/* end of Utilities */
+
+/* Using USB legacy version */
+
+/* end of Using USB legacy version */
+/* end of RT-Thread Components */
 
 /* RT-Thread Utestcases */
 
+/* end of RT-Thread Utestcases */
 
 /* RT-Thread online packages */
 
@@ -130,57 +203,80 @@
 
 /* Marvell WiFi */
 
+/* end of Marvell WiFi */
 
 /* Wiced WiFi */
 
+/* end of Wiced WiFi */
 
 /* CYW43012 WiFi */
 
+/* end of CYW43012 WiFi */
 
 /* BL808 WiFi */
 
+/* end of BL808 WiFi */
 
 /* CYW43439 WiFi */
 
+/* end of CYW43439 WiFi */
+/* end of Wi-Fi */
 
 /* IoT Cloud */
 
+/* end of IoT Cloud */
+/* end of IoT - internet of things */
 
 /* security packages */
 
+/* end of security packages */
 
 /* language packages */
 
 /* JSON: JavaScript Object Notation, a lightweight data-interchange format */
 
+/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
 
 /* XML: Extensible Markup Language */
 
+/* end of XML: Extensible Markup Language */
+/* end of language packages */
 
 /* multimedia packages */
 
 /* LVGL: powerful and easy-to-use embedded GUI library */
 
+/* end of LVGL: powerful and easy-to-use embedded GUI library */
 
 /* u8g2: a monochrome graphic library */
 
+/* end of u8g2: a monochrome graphic library */
+/* end of multimedia packages */
 
 /* tools packages */
 
+/* end of tools packages */
 
 /* system packages */
 
 /* enhanced kernel services */
 
+/* end of enhanced kernel services */
 
 /* acceleration: Assembly language or algorithmic acceleration packages */
 
+/* end of acceleration: Assembly language or algorithmic acceleration packages */
 
 /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
 
+#define PKG_USING_CMSIS_CORE
+#define PKG_USING_CMSIS_CORE_LATEST_VERSION
+/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
 
 /* Micrium: Micrium software products porting for RT-Thread */
 
+/* end of Micrium: Micrium software products porting for RT-Thread */
+/* end of system packages */
 
 /* peripheral libraries and drivers */
 
@@ -188,66 +284,106 @@
 
 /* STM32 HAL & SDK Drivers */
 
+#define PKG_USING_STM32L0_HAL_DRIVER
+#define PKG_USING_STM32L0_HAL_DRIVER_LATEST_VERSION
+#define PKG_USING_STM32L0_CMSIS_DRIVER
+#define PKG_USING_STM32L0_CMSIS_DRIVER_LATEST_VERSION
+/* end of STM32 HAL & SDK Drivers */
+
+/* Infineon HAL Packages */
+
+/* end of Infineon HAL Packages */
 
 /* Kendryte SDK */
 
+/* end of Kendryte SDK */
+
+/* WCH HAL & SDK Drivers */
+
+/* end of WCH HAL & SDK Drivers */
+
+/* AT32 HAL & SDK Drivers */
+
+/* end of AT32 HAL & SDK Drivers */
+/* end of HAL & SDK Drivers */
 
 /* sensors drivers */
 
+/* end of sensors drivers */
 
 /* touch drivers */
 
+/* end of touch drivers */
+/* end of peripheral libraries and drivers */
 
 /* AI packages */
 
+/* end of AI packages */
 
 /* Signal Processing and Control Algorithm Packages */
 
+/* end of Signal Processing and Control Algorithm Packages */
 
 /* miscellaneous packages */
 
 /* project laboratory */
 
+/* end of project laboratory */
+
 /* samples: kernel and components samples */
 
+/* end of samples: kernel and components samples */
 
 /* entertainment: terminal games and other interesting software packages */
 
+/* end of entertainment: terminal games and other interesting software packages */
+/* end of miscellaneous packages */
 
 /* Arduino libraries */
 
 
 /* Projects and Demos */
 
+/* end of Projects and Demos */
 
 /* Sensors */
 
+/* end of Sensors */
 
 /* Display */
 
+/* end of Display */
 
 /* Timing */
 
+/* end of Timing */
 
 /* Data Processing */
 
+/* end of Data Processing */
 
 /* Data Storage */
 
 /* Communication */
 
+/* end of Communication */
 
 /* Device Control */
 
+/* end of Device Control */
 
 /* Other */
 
+/* end of Other */
 
 /* Signal IO */
 
+/* end of Signal IO */
 
 /* Uncategorized */
 
+/* end of Arduino libraries */
+/* end of RT-Thread online packages */
 #define SOC_FAMILY_STM32
 #define SOC_SERIES_STM32L0
 #define BOARD_SERIES_STM32_NUCLEO_64
@@ -257,14 +393,18 @@
 /* Onboard Peripheral Drivers */
 
 #define BSP_USING_USB_TO_USART
+/* end of Onboard Peripheral Drivers */
 
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO
 #define BSP_USING_UART
+#define BSP_STM32_UART_V1_TX_TIMEOUT 2000
 #define BSP_USING_UART2
+/* end of On-chip Peripheral Drivers */
 
 /* Board extended module Drivers */
 
+/* end of Hardware Drivers Config */
 
 #endif